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target-microblaze: mmu: Remove unused register state
[qemu/ar7.git] / tests / libqos / ahci.c
blobbc201d762b39456d9267bd1dcaaacfd4dcb29296
1 /*
2 * libqos AHCI functions
3 *
4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26
27 #include "libqtest.h"
28 #include "libqos/ahci.h"
29 #include "libqos/pci-pc.h"
30
31 #include "qemu-common.h"
32 #include "qemu/host-utils.h"
33
34 #include "hw/pci/pci_ids.h"
35 #include "hw/pci/pci_regs.h"
36
37 typedef struct AHCICommandProp {
38 uint8_t cmd; /* Command Code */
39 bool data; /* Data transfer command? */
40 bool pio;
41 bool dma;
42 bool lba28;
43 bool lba48;
44 bool read;
45 bool write;
46 bool atapi;
47 bool ncq;
48 uint64_t size; /* Static transfer size, for commands like IDENTIFY. */
49 uint32_t interrupts; /* Expected interrupts for this command. */
50 } AHCICommandProp;
51
52 AHCICommandProp ahci_command_properties[] = {
53 { .cmd = CMD_READ_PIO, .data = true, .pio = true,
54 .lba28 = true, .read = true },
55 { .cmd = CMD_WRITE_PIO, .data = true, .pio = true,
56 .lba28 = true, .write = true },
57 { .cmd = CMD_READ_PIO_EXT, .data = true, .pio = true,
58 .lba48 = true, .read = true },
59 { .cmd = CMD_WRITE_PIO_EXT, .data = true, .pio = true,
60 .lba48 = true, .write = true },
61 { .cmd = CMD_READ_DMA, .data = true, .dma = true,
62 .lba28 = true, .read = true },
63 { .cmd = CMD_WRITE_DMA, .data = true, .dma = true,
64 .lba28 = true, .write = true },
65 { .cmd = CMD_READ_DMA_EXT, .data = true, .dma = true,
66 .lba48 = true, .read = true },
67 { .cmd = CMD_WRITE_DMA_EXT, .data = true, .dma = true,
68 .lba48 = true, .write = true },
69 { .cmd = CMD_IDENTIFY, .data = true, .pio = true,
70 .size = 512, .read = true },
71 { .cmd = READ_FPDMA_QUEUED, .data = true, .dma = true,
72 .lba48 = true, .read = true, .ncq = true },
73 { .cmd = WRITE_FPDMA_QUEUED, .data = true, .dma = true,
74 .lba48 = true, .write = true, .ncq = true },
75 { .cmd = CMD_READ_MAX, .lba28 = true },
76 { .cmd = CMD_READ_MAX_EXT, .lba48 = true },
77 { .cmd = CMD_FLUSH_CACHE, .data = false },
78 { .cmd = CMD_PACKET, .data = true, .size = 16,
79 .atapi = true, .pio = true },
80 { .cmd = CMD_PACKET_ID, .data = true, .pio = true,
81 .size = 512, .read = true }
82 };
83
84 struct AHCICommand {
85 /* Test Management Data */
86 uint8_t name;
87 uint8_t port;
88 uint8_t slot;
89 uint8_t errors;
90 uint32_t interrupts;
91 uint64_t xbytes;
92 uint32_t prd_size;
93 uint64_t buffer;
94 AHCICommandProp *props;
95 /* Data to be transferred to the guest */
96 AHCICommandHeader header;
97 RegH2DFIS fis;
98 unsigned char *atapi_cmd;
99 };
100
101 /**
102 * Allocate space in the guest using information in the AHCIQState object.
103 */
104 uint64_t ahci_alloc(AHCIQState *ahci, size_t bytes)
105 {
106 g_assert(ahci);
107 g_assert(ahci->parent);
108 return qmalloc(ahci->parent, bytes);
109 }
110
111 void ahci_free(AHCIQState *ahci, uint64_t addr)
112 {
113 g_assert(ahci);
114 g_assert(ahci->parent);
115 qfree(ahci->parent, addr);
116 }
117
118 bool is_atapi(AHCIQState *ahci, uint8_t port)
119 {
120 return ahci_px_rreg(ahci, port, AHCI_PX_SIG) == AHCI_SIGNATURE_CDROM;
121 }
122
123 /**
124 * Locate, verify, and return a handle to the AHCI device.
125 */
126 QPCIDevice *get_ahci_device(QTestState *qts, uint32_t *fingerprint)
127 {
128 QPCIDevice *ahci;
129 uint32_t ahci_fingerprint;
130 QPCIBus *pcibus;
131
132 pcibus = qpci_init_pc(qts, NULL);
133
134 /* Find the AHCI PCI device and verify it's the right one. */
135 ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02));
136 g_assert(ahci != NULL);
137
138 ahci_fingerprint = qpci_config_readl(ahci, PCI_VENDOR_ID);
139
140 switch (ahci_fingerprint) {
141 case AHCI_INTEL_ICH9:
142 break;
143 default:
144 /* Unknown device. */
145 g_assert_not_reached();
146 }
147
148 if (fingerprint) {
149 *fingerprint = ahci_fingerprint;
150 }
151 return ahci;
152 }
153
154 void free_ahci_device(QPCIDevice *dev)
155 {
156 QPCIBus *pcibus = dev ? dev->bus : NULL;
157
158 /* libqos doesn't have a function for this, so free it manually */
159 g_free(dev);
160 qpci_free_pc(pcibus);
161 }
162
163 /* Free all memory in-use by the AHCI device. */
164 void ahci_clean_mem(AHCIQState *ahci)
165 {
166 uint8_t port, slot;
167
168 for (port = 0; port < 32; ++port) {
169 if (ahci->port[port].fb) {
170 ahci_free(ahci, ahci->port[port].fb);
171 ahci->port[port].fb = 0;
172 }
173 if (ahci->port[port].clb) {
174 for (slot = 0; slot < 32; slot++) {
175 ahci_destroy_command(ahci, port, slot);
176 }
177 ahci_free(ahci, ahci->port[port].clb);
178 ahci->port[port].clb = 0;
179 }
180 }
181 }
182
183 /*** Logical Device Initialization ***/
184
185 /**
186 * Start the PCI device and sanity-check default operation.
187 */
188 void ahci_pci_enable(AHCIQState *ahci)
189 {
190 uint8_t reg;
191
192 start_ahci_device(ahci);
193
194 switch (ahci->fingerprint) {
195 case AHCI_INTEL_ICH9:
196 /* ICH9 has a register at PCI 0x92 that
197 * acts as a master port enabler mask. */
198 reg = qpci_config_readb(ahci->dev, 0x92);
199 reg |= 0x3F;
200 qpci_config_writeb(ahci->dev, 0x92, reg);
201 /* 0...0111111b -- bit significant, ports 0-5 enabled. */
202 ASSERT_BIT_SET(qpci_config_readb(ahci->dev, 0x92), 0x3F);
203 break;
204 }
205
206 }
207
208 /**
209 * Map BAR5/ABAR, and engage the PCI device.
210 */
211 void start_ahci_device(AHCIQState *ahci)
212 {
213 /* Map AHCI's ABAR (BAR5) */
214 ahci->hba_bar = qpci_iomap(ahci->dev, 5, &ahci->barsize);
215
216 /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
217 qpci_device_enable(ahci->dev);
218 }
219
220 /**
221 * Test and initialize the AHCI's HBA memory areas.
222 * Initialize and start any ports with devices attached.
223 * Bring the HBA into the idle state.
224 */
225 void ahci_hba_enable(AHCIQState *ahci)
226 {
227 /* Bits of interest in this section:
228 * GHC.AE Global Host Control / AHCI Enable
229 * PxCMD.ST Port Command: Start
230 * PxCMD.SUD "Spin Up Device"
231 * PxCMD.POD "Power On Device"
232 * PxCMD.FRE "FIS Receive Enable"
233 * PxCMD.FR "FIS Receive Running"
234 * PxCMD.CR "Command List Running"
235 */
236 uint32_t reg, ports_impl;
237 uint16_t i;
238 uint8_t num_cmd_slots;
239
240 g_assert(ahci != NULL);
241
242 /* Set GHC.AE to 1 */
243 ahci_set(ahci, AHCI_GHC, AHCI_GHC_AE);
244 reg = ahci_rreg(ahci, AHCI_GHC);
245 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
246
247 /* Cache CAP and CAP2. */
248 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
249 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
250
251 /* Read CAP.NCS, how many command slots do we have? */
252 num_cmd_slots = ((ahci->cap & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1;
253 g_test_message("Number of Command Slots: %u", num_cmd_slots);
254
255 /* Determine which ports are implemented. */
256 ports_impl = ahci_rreg(ahci, AHCI_PI);
257
258 for (i = 0; ports_impl; ports_impl >>= 1, ++i) {
259 if (!(ports_impl & 0x01)) {
260 continue;
261 }
262
263 g_test_message("Initializing port %u", i);
264
265 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
266 if (BITCLR(reg, AHCI_PX_CMD_ST | AHCI_PX_CMD_CR |
267 AHCI_PX_CMD_FRE | AHCI_PX_CMD_FR)) {
268 g_test_message("port is idle");
269 } else {
270 g_test_message("port needs to be idled");
271 ahci_px_clr(ahci, i, AHCI_PX_CMD,
272 (AHCI_PX_CMD_ST | AHCI_PX_CMD_FRE));
273 /* The port has 500ms to disengage. */
274 usleep(500000);
275 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
276 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
277 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
278 g_test_message("port is now idle");
279 /* The spec does allow for possibly needing a PORT RESET
280 * or HBA reset if we fail to idle the port. */
281 }
282
283 /* Allocate Memory for the Command List Buffer & FIS Buffer */
284 /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
285 ahci->port[i].clb = ahci_alloc(ahci, num_cmd_slots * 0x20);
286 qtest_memset(ahci->parent->qts, ahci->port[i].clb, 0x00,
287 num_cmd_slots * 0x20);
288 g_test_message("CLB: 0x%08" PRIx64, ahci->port[i].clb);
289 ahci_px_wreg(ahci, i, AHCI_PX_CLB, ahci->port[i].clb);
290 g_assert_cmphex(ahci->port[i].clb, ==,
291 ahci_px_rreg(ahci, i, AHCI_PX_CLB));
292
293 /* PxFB space ... 0x100, as in 4.2.1 p 35 */
294 ahci->port[i].fb = ahci_alloc(ahci, 0x100);
295 qtest_memset(ahci->parent->qts, ahci->port[i].fb, 0x00, 0x100);
296 g_test_message("FB: 0x%08" PRIx64, ahci->port[i].fb);
297 ahci_px_wreg(ahci, i, AHCI_PX_FB, ahci->port[i].fb);
298 g_assert_cmphex(ahci->port[i].fb, ==,
299 ahci_px_rreg(ahci, i, AHCI_PX_FB));
300
301 /* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */
302 ahci_px_wreg(ahci, i, AHCI_PX_SERR, 0xFFFFFFFF);
303 ahci_px_wreg(ahci, i, AHCI_PX_IS, 0xFFFFFFFF);
304 ahci_wreg(ahci, AHCI_IS, (1 << i));
305
306 /* Verify Interrupts Cleared */
307 reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
308 g_assert_cmphex(reg, ==, 0);
309
310 reg = ahci_px_rreg(ahci, i, AHCI_PX_IS);
311 g_assert_cmphex(reg, ==, 0);
312
313 reg = ahci_rreg(ahci, AHCI_IS);
314 ASSERT_BIT_CLEAR(reg, (1 << i));
315
316 /* Enable All Interrupts: */
317 ahci_px_wreg(ahci, i, AHCI_PX_IE, 0xFFFFFFFF);
318 reg = ahci_px_rreg(ahci, i, AHCI_PX_IE);
319 g_assert_cmphex(reg, ==, ~((uint32_t)AHCI_PX_IE_RESERVED));
320
321 /* Enable the FIS Receive Engine. */
322 ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_FRE);
323 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
324 ASSERT_BIT_SET(reg, AHCI_PX_CMD_FR);
325
326 /* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates
327 * physical presence, a device is present and may be started. However,
328 * PxSERR.DIAG.X /may/ need to be cleared a priori. */
329 reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
330 if (BITSET(reg, AHCI_PX_SERR_DIAG_X)) {
331 ahci_px_set(ahci, i, AHCI_PX_SERR, AHCI_PX_SERR_DIAG_X);
332 }
333
334 reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD);
335 if (BITCLR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ)) {
336 reg = ahci_px_rreg(ahci, i, AHCI_PX_SSTS);
337 if ((reg & AHCI_PX_SSTS_DET) == SSTS_DET_ESTABLISHED) {
338 /* Device Found: set PxCMD.ST := 1 */
339 ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_ST);
340 ASSERT_BIT_SET(ahci_px_rreg(ahci, i, AHCI_PX_CMD),
341 AHCI_PX_CMD_CR);
342 g_test_message("Started Device %u", i);
343 } else if ((reg & AHCI_PX_SSTS_DET)) {
344 /* Device present, but in some unknown state. */
345 g_assert_not_reached();
346 }
347 }
348 }
349
350 /* Enable GHC.IE */
351 ahci_set(ahci, AHCI_GHC, AHCI_GHC_IE);
352 reg = ahci_rreg(ahci, AHCI_GHC);
353 ASSERT_BIT_SET(reg, AHCI_GHC_IE);
354
355 ahci->enabled = true;
356 /* TODO: The device should now be idling and waiting for commands.
357 * In the future, a small test-case to inspect the Register D2H FIS
358 * and clear the initial interrupts might be good. */
359 }
360
361 /**
362 * Pick the first implemented and running port
363 */
364 unsigned ahci_port_select(AHCIQState *ahci)
365 {
366 uint32_t ports, reg;
367 unsigned i;
368
369 ports = ahci_rreg(ahci, AHCI_PI);
370 for (i = 0; i < 32; ports >>= 1, ++i) {
371 if (ports == 0) {
372 i = 32;
373 }
374
375 if (!(ports & 0x01)) {
376 continue;
377 }
378
379 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
380 if (BITSET(reg, AHCI_PX_CMD_ST)) {
381 break;
382 }
383 }
384 g_assert(i < 32);
385 return i;
386 }
387
388 /**
389 * Clear a port's interrupts and status information prior to a test.
390 */
391 void ahci_port_clear(AHCIQState *ahci, uint8_t port)
392 {
393 uint32_t reg;
394
395 /* Clear out this port's interrupts (ignore the init register d2h fis) */
396 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
397 ahci_px_wreg(ahci, port, AHCI_PX_IS, reg);
398 g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
399
400 /* Wipe the FIS-Receive Buffer */
401 qtest_memset(ahci->parent->qts, ahci->port[port].fb, 0x00, 0x100);
402 }
403
404 /**
405 * Check a port for errors.
406 */
407 void ahci_port_check_error(AHCIQState *ahci, uint8_t port,
408 uint32_t imask, uint8_t emask)
409 {
410 uint32_t reg;
411
412 /* The upper 9 bits of the IS register all indicate errors. */
413 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
414 reg &= ~imask;
415 reg >>= 23;
416 g_assert_cmphex(reg, ==, 0);
417
418 /* The Sata Error Register should be empty. */
419 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
420 g_assert_cmphex(reg, ==, 0);
421
422 /* The TFD also has two error sections. */
423 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
424 if (!emask) {
425 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
426 } else {
427 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
428 }
429 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR & (~emask << 8));
430 ASSERT_BIT_SET(reg, AHCI_PX_TFD_ERR & (emask << 8));
431 }
432
433 void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port,
434 uint32_t intr_mask)
435 {
436 uint32_t reg;
437
438 /* Check for expected interrupts */
439 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
440 ASSERT_BIT_SET(reg, intr_mask);
441
442 /* Clear expected interrupts and assert all interrupts now cleared. */
443 ahci_px_wreg(ahci, port, AHCI_PX_IS, intr_mask);
444 g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
445 }
446
447 void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot)
448 {
449 uint32_t reg;
450
451 /* Assert that the command slot is no longer busy (NCQ) */
452 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
453 ASSERT_BIT_CLEAR(reg, (1 << slot));
454
455 /* Non-NCQ */
456 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
457 ASSERT_BIT_CLEAR(reg, (1 << slot));
458
459 /* And assert that we are generally not busy. */
460 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
461 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
462 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_DRQ);
463 }
464
465 void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot)
466 {
467 RegD2HFIS *d2h = g_malloc0(0x20);
468 uint32_t reg;
469
470 qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x40, d2h, 0x20);
471 g_assert_cmphex(d2h->fis_type, ==, 0x34);
472
473 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
474 g_assert_cmphex((reg & AHCI_PX_TFD_ERR) >> 8, ==, d2h->error);
475 g_assert_cmphex((reg & AHCI_PX_TFD_STS), ==, d2h->status);
476
477 g_free(d2h);
478 }
479
480 void ahci_port_check_pio_sanity(AHCIQState *ahci, uint8_t port,
481 uint8_t slot, size_t buffsize)
482 {
483 PIOSetupFIS *pio = g_malloc0(0x20);
484
485 /* We cannot check the Status or E_Status registers, because
486 * the status may have again changed between the PIO Setup FIS
487 * and the conclusion of the command with the D2H Register FIS. */
488 qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x20, pio, 0x20);
489 g_assert_cmphex(pio->fis_type, ==, 0x5f);
490
491 /* BUG: PIO Setup FIS as utilized by QEMU tries to fit the entire
492 * transfer size in a uint16_t field. The maximum transfer size can
493 * eclipse this; the field is meant to convey the size of data per
494 * each Data FIS, not the entire operation as a whole. For now,
495 * we will sanity check the broken case where applicable. */
496 if (buffsize <= UINT16_MAX) {
497 g_assert_cmphex(le16_to_cpu(pio->tx_count), ==, buffsize);
498 }
499
500 g_free(pio);
501 }
502
503 void ahci_port_check_cmd_sanity(AHCIQState *ahci, AHCICommand *cmd)
504 {
505 AHCICommandHeader cmdh;
506
507 ahci_get_command_header(ahci, cmd->port, cmd->slot, &cmdh);
508 /* Physical Region Descriptor Byte Count is not required to work for NCQ. */
509 if (!cmd->props->ncq) {
510 g_assert_cmphex(cmd->xbytes, ==, cmdh.prdbc);
511 }
512 }
513
514 /* Get the command in #slot of port #port. */
515 void ahci_get_command_header(AHCIQState *ahci, uint8_t port,
516 uint8_t slot, AHCICommandHeader *cmd)
517 {
518 uint64_t ba = ahci->port[port].clb;
519 ba += slot * sizeof(AHCICommandHeader);
520 qtest_memread(ahci->parent->qts, ba, cmd, sizeof(AHCICommandHeader));
521
522 cmd->flags = le16_to_cpu(cmd->flags);
523 cmd->prdtl = le16_to_cpu(cmd->prdtl);
524 cmd->prdbc = le32_to_cpu(cmd->prdbc);
525 cmd->ctba = le64_to_cpu(cmd->ctba);
526 }
527
528 /* Set the command in #slot of port #port. */
529 void ahci_set_command_header(AHCIQState *ahci, uint8_t port,
530 uint8_t slot, AHCICommandHeader *cmd)
531 {
532 AHCICommandHeader tmp = { .flags = 0 };
533 uint64_t ba = ahci->port[port].clb;
534 ba += slot * sizeof(AHCICommandHeader);
535
536 tmp.flags = cpu_to_le16(cmd->flags);
537 tmp.prdtl = cpu_to_le16(cmd->prdtl);
538 tmp.prdbc = cpu_to_le32(cmd->prdbc);
539 tmp.ctba = cpu_to_le64(cmd->ctba);
540
541 qtest_memwrite(ahci->parent->qts, ba, &tmp, sizeof(AHCICommandHeader));
542 }
543
544 void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot)
545 {
546 AHCICommandHeader cmd;
547
548 /* Obtain the Nth Command Header */
549 ahci_get_command_header(ahci, port, slot, &cmd);
550 if (cmd.ctba == 0) {
551 /* No address in it, so just return -- it's empty. */
552 goto tidy;
553 }
554
555 /* Free the Table */
556 ahci_free(ahci, cmd.ctba);
557
558 tidy:
559 /* NULL the header. */
560 memset(&cmd, 0x00, sizeof(cmd));
561 ahci_set_command_header(ahci, port, slot, &cmd);
562 ahci->port[port].ctba[slot] = 0;
563 ahci->port[port].prdtl[slot] = 0;
564 }
565
566 void ahci_write_fis(AHCIQState *ahci, AHCICommand *cmd)
567 {
568 RegH2DFIS tmp = cmd->fis;
569 uint64_t addr = cmd->header.ctba;
570
571 /* NCQ commands use exclusively 8 bit fields and needs no adjustment.
572 * Only the count field needs to be adjusted for non-NCQ commands.
573 * The auxiliary FIS fields are defined per-command and are not currently
574 * implemented in libqos/ahci.o, but may or may not need to be flipped. */
575 if (!cmd->props->ncq) {
576 tmp.count = cpu_to_le16(tmp.count);
577 }
578
579 qtest_memwrite(ahci->parent->qts, addr, &tmp, sizeof(tmp));
580 }
581
582 unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port)
583 {
584 unsigned i;
585 unsigned j;
586 uint32_t reg;
587
588 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
589
590 /* Pick the least recently used command slot that's available */
591 for (i = 0; i < 32; ++i) {
592 j = ((ahci->port[port].next + i) % 32);
593 if (reg & (1 << j)) {
594 continue;
595 }
596 ahci_destroy_command(ahci, port, j);
597 ahci->port[port].next = (j + 1) % 32;
598 return j;
599 }
600
601 g_test_message("All command slots were busy.");
602 g_assert_not_reached();
603 }
604
605 inline unsigned size_to_prdtl(unsigned bytes, unsigned bytes_per_prd)
606 {
607 /* Each PRD can describe up to 4MiB */
608 g_assert_cmphex(bytes_per_prd, <=, 4096 * 1024);
609 g_assert_cmphex(bytes_per_prd & 0x01, ==, 0x00);
610 return (bytes + bytes_per_prd - 1) / bytes_per_prd;
611 }
612
613 const AHCIOpts default_opts = { .size = 0 };
614
615 /**
616 * ahci_exec: execute a given command on a specific
617 * AHCI port.
618 *
619 * @ahci: The device to send the command to
620 * @port: The port number of the SATA device we wish
621 * to have execute this command
622 * @op: The S/ATA command to execute, or if opts.atapi
623 * is true, the SCSI command code.
624 * @opts: Optional arguments to modify execution behavior.
625 */
626 void ahci_exec(AHCIQState *ahci, uint8_t port,
627 uint8_t op, const AHCIOpts *opts_in)
628 {
629 AHCICommand *cmd;
630 int rc;
631 AHCIOpts *opts;
632
633 opts = g_memdup((opts_in == NULL ? &default_opts : opts_in),
634 sizeof(AHCIOpts));
635
636 /* No guest buffer provided, create one. */
637 if (opts->size && !opts->buffer) {
638 opts->buffer = ahci_alloc(ahci, opts->size);
639 g_assert(opts->buffer);
640 qtest_memset(ahci->parent->qts, opts->buffer, 0x00, opts->size);
641 }
642
643 /* Command creation */
644 if (opts->atapi) {
645 uint16_t bcl = opts->set_bcl ? opts->bcl : ATAPI_SECTOR_SIZE;
646 cmd = ahci_atapi_command_create(op, bcl);
647 if (opts->atapi_dma) {
648 ahci_command_enable_atapi_dma(cmd);
649 }
650 } else {
651 cmd = ahci_command_create(op);
652 }
653 ahci_command_adjust(cmd, opts->lba, opts->buffer,
654 opts->size, opts->prd_size);
655
656 if (opts->pre_cb) {
657 rc = opts->pre_cb(ahci, cmd, opts);
658 g_assert_cmpint(rc, ==, 0);
659 }
660
661 /* Write command to memory and issue it */
662 ahci_command_commit(ahci, cmd, port);
663 ahci_command_issue_async(ahci, cmd);
664 if (opts->error) {
665 qtest_qmp_eventwait(ahci->parent->qts, "STOP");
666 }
667 if (opts->mid_cb) {
668 rc = opts->mid_cb(ahci, cmd, opts);
669 g_assert_cmpint(rc, ==, 0);
670 }
671 if (opts->error) {
672 qtest_async_qmp(ahci->parent->qts, "{'execute':'cont' }");
673 qtest_qmp_eventwait(ahci->parent->qts, "RESUME");
674 }
675
676 /* Wait for command to complete and verify sanity */
677 ahci_command_wait(ahci, cmd);
678 ahci_command_verify(ahci, cmd);
679 if (opts->post_cb) {
680 rc = opts->post_cb(ahci, cmd, opts);
681 g_assert_cmpint(rc, ==, 0);
682 }
683 ahci_command_free(cmd);
684 if (opts->buffer != opts_in->buffer) {
685 ahci_free(ahci, opts->buffer);
686 }
687 g_free(opts);
688 }
689
690 /* Issue a command, expecting it to fail and STOP the VM */
691 AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port,
692 uint8_t ide_cmd, uint64_t buffer,
693 size_t bufsize, uint64_t sector)
694 {
695 AHCICommand *cmd;
696
697 cmd = ahci_command_create(ide_cmd);
698 ahci_command_adjust(cmd, sector, buffer, bufsize, 0);
699 ahci_command_commit(ahci, cmd, port);
700 ahci_command_issue_async(ahci, cmd);
701 qtest_qmp_eventwait(ahci->parent->qts, "STOP");
702
703 return cmd;
704 }
705
706 /* Resume a previously failed command and verify/finalize */
707 void ahci_guest_io_resume(AHCIQState *ahci, AHCICommand *cmd)
708 {
709 /* Complete the command */
710 qtest_async_qmp(ahci->parent->qts, "{'execute':'cont' }");
711 qtest_qmp_eventwait(ahci->parent->qts, "RESUME");
712 ahci_command_wait(ahci, cmd);
713 ahci_command_verify(ahci, cmd);
714 ahci_command_free(cmd);
715 }
716
717 /* Given a guest buffer address, perform an IO operation */
718 void ahci_guest_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
719 uint64_t buffer, size_t bufsize, uint64_t sector)
720 {
721 AHCICommand *cmd;
722 cmd = ahci_command_create(ide_cmd);
723 ahci_command_set_buffer(cmd, buffer);
724 ahci_command_set_size(cmd, bufsize);
725 if (sector) {
726 ahci_command_set_offset(cmd, sector);
727 }
728 ahci_command_commit(ahci, cmd, port);
729 ahci_command_issue(ahci, cmd);
730 ahci_command_verify(ahci, cmd);
731 ahci_command_free(cmd);
732 }
733
734 static AHCICommandProp *ahci_command_find(uint8_t command_name)
735 {
736 int i;
737
738 for (i = 0; i < ARRAY_SIZE(ahci_command_properties); i++) {
739 if (ahci_command_properties[i].cmd == command_name) {
740 return &ahci_command_properties[i];
741 }
742 }
743
744 return NULL;
745 }
746
747 /* Given a HOST buffer, create a buffer address and perform an IO operation. */
748 void ahci_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
749 void *buffer, size_t bufsize, uint64_t sector)
750 {
751 uint64_t ptr;
752 AHCICommandProp *props;
753
754 props = ahci_command_find(ide_cmd);
755 g_assert(props);
756 ptr = ahci_alloc(ahci, bufsize);
757 g_assert(!bufsize || ptr);
758 qtest_memset(ahci->parent->qts, ptr, 0x00, bufsize);
759
760 if (bufsize && props->write) {
761 qtest_bufwrite(ahci->parent->qts, ptr, buffer, bufsize);
762 }
763
764 ahci_guest_io(ahci, port, ide_cmd, ptr, bufsize, sector);
765
766 if (bufsize && props->read) {
767 qtest_bufread(ahci->parent->qts, ptr, buffer, bufsize);
768 }
769
770 ahci_free(ahci, ptr);
771 }
772
773 /**
774 * Initializes a basic command header in memory.
775 * We assume that this is for an ATA command using RegH2DFIS.
776 */
777 static void command_header_init(AHCICommand *cmd)
778 {
779 AHCICommandHeader *hdr = &cmd->header;
780 AHCICommandProp *props = cmd->props;
781
782 hdr->flags = 5; /* RegH2DFIS is 5 DW long. Must be < 32 */
783 hdr->flags |= CMDH_CLR_BSY; /* Clear the BSY bit when done */
784 if (props->write) {
785 hdr->flags |= CMDH_WRITE;
786 }
787 if (props->atapi) {
788 hdr->flags |= CMDH_ATAPI;
789 }
790 /* Other flags: PREFETCH, RESET, and BIST */
791 hdr->prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
792 hdr->prdbc = 0;
793 hdr->ctba = 0;
794 }
795
796 static void command_table_init(AHCICommand *cmd)
797 {
798 RegH2DFIS *fis = &(cmd->fis);
799 uint16_t sect_count = (cmd->xbytes / AHCI_SECTOR_SIZE);
800
801 fis->fis_type = REG_H2D_FIS;
802 fis->flags = REG_H2D_FIS_CMD; /* "Command" bit */
803 fis->command = cmd->name;
804
805 if (cmd->props->ncq) {
806 NCQFIS *ncqfis = (NCQFIS *)fis;
807 /* NCQ is weird and re-uses FIS frames for unrelated data.
808 * See SATA 3.2, 13.6.4.1 READ FPDMA QUEUED for an example. */
809 ncqfis->sector_low = sect_count & 0xFF;
810 ncqfis->sector_hi = (sect_count >> 8) & 0xFF;
811 ncqfis->device = NCQ_DEVICE_MAGIC;
812 /* Force Unit Access is bit 7 in the device register */
813 ncqfis->tag = 0; /* bits 3-7 are the NCQ tag */
814 ncqfis->prio = 0; /* bits 6,7 are a prio tag */
815 /* RARC bit is bit 0 of TAG field */
816 } else {
817 fis->feature_low = 0x00;
818 fis->feature_high = 0x00;
819 if (cmd->props->lba28 || cmd->props->lba48) {
820 fis->device = ATA_DEVICE_LBA;
821 }
822 fis->count = (cmd->xbytes / AHCI_SECTOR_SIZE);
823 }
824 fis->icc = 0x00;
825 fis->control = 0x00;
826 memset(fis->aux, 0x00, ARRAY_SIZE(fis->aux));
827 }
828
829 void ahci_command_enable_atapi_dma(AHCICommand *cmd)
830 {
831 RegH2DFIS *fis = &(cmd->fis);
832 g_assert(cmd->props->atapi);
833 fis->feature_low |= 0x01;
834 cmd->interrupts &= ~AHCI_PX_IS_PSS;
835 cmd->props->dma = true;
836 cmd->props->pio = false;
837 /* BUG: We expect the DMA Setup interrupt for DMA commands */
838 /* cmd->interrupts |= AHCI_PX_IS_DSS; */
839 }
840
841 AHCICommand *ahci_command_create(uint8_t command_name)
842 {
843 AHCICommandProp *props = ahci_command_find(command_name);
844 AHCICommand *cmd;
845
846 g_assert(props);
847 cmd = g_new0(AHCICommand, 1);
848 g_assert(!(props->dma && props->pio));
849 g_assert(!(props->lba28 && props->lba48));
850 g_assert(!(props->read && props->write));
851 g_assert(!props->size || props->data);
852 g_assert(!props->ncq || props->lba48);
853
854 /* Defaults and book-keeping */
855 cmd->props = g_memdup(props, sizeof(AHCICommandProp));
856 cmd->name = command_name;
857 cmd->xbytes = props->size;
858 cmd->prd_size = 4096;
859 cmd->buffer = 0xabad1dea;
860
861 if (!cmd->props->ncq) {
862 cmd->interrupts = AHCI_PX_IS_DHRS;
863 }
864 /* BUG: We expect the DPS interrupt for data commands */
865 /* cmd->interrupts |= props->data ? AHCI_PX_IS_DPS : 0; */
866 /* BUG: We expect the DMA Setup interrupt for DMA commands */
867 /* cmd->interrupts |= props->dma ? AHCI_PX_IS_DSS : 0; */
868 cmd->interrupts |= props->pio ? AHCI_PX_IS_PSS : 0;
869 cmd->interrupts |= props->ncq ? AHCI_PX_IS_SDBS : 0;
870
871 command_header_init(cmd);
872 command_table_init(cmd);
873
874 return cmd;
875 }
876
877 AHCICommand *ahci_atapi_command_create(uint8_t scsi_cmd, uint16_t bcl)
878 {
879 AHCICommand *cmd = ahci_command_create(CMD_PACKET);
880 cmd->atapi_cmd = g_malloc0(16);
881 cmd->atapi_cmd[0] = scsi_cmd;
882 stw_le_p(&cmd->fis.lba_lo[1], bcl);
883 return cmd;
884 }
885
886 void ahci_atapi_test_ready(AHCIQState *ahci, uint8_t port,
887 bool ready, uint8_t expected_sense)
888 {
889 AHCICommand *cmd = ahci_atapi_command_create(CMD_ATAPI_TEST_UNIT_READY, 0);
890 ahci_command_set_size(cmd, 0);
891 if (!ready) {
892 cmd->interrupts |= AHCI_PX_IS_TFES;
893 cmd->errors |= expected_sense << 4;
894 }
895 ahci_command_commit(ahci, cmd, port);
896 ahci_command_issue(ahci, cmd);
897 ahci_command_verify(ahci, cmd);
898 ahci_command_free(cmd);
899 }
900
901 static int copy_buffer(AHCIQState *ahci, AHCICommand *cmd,
902 const AHCIOpts *opts)
903 {
904 unsigned char *rx = opts->opaque;
905 qtest_bufread(ahci->parent->qts, opts->buffer, rx, opts->size);
906 return 0;
907 }
908
909 void ahci_atapi_get_sense(AHCIQState *ahci, uint8_t port,
910 uint8_t *sense, uint8_t *asc)
911 {
912 unsigned char *rx;
913 AHCIOpts opts = {
914 .size = 18,
915 .atapi = true,
916 .post_cb = copy_buffer,
917 };
918 rx = g_malloc(18);
919 opts.opaque = rx;
920
921 ahci_exec(ahci, port, CMD_ATAPI_REQUEST_SENSE, &opts);
922
923 *sense = rx[2];
924 *asc = rx[12];
925
926 g_free(rx);
927 }
928
929 void ahci_atapi_eject(AHCIQState *ahci, uint8_t port)
930 {
931 AHCICommand *cmd = ahci_atapi_command_create(CMD_ATAPI_START_STOP_UNIT, 0);
932 ahci_command_set_size(cmd, 0);
933
934 cmd->atapi_cmd[4] = 0x02; /* loej = true */
935 ahci_command_commit(ahci, cmd, port);
936 ahci_command_issue(ahci, cmd);
937 ahci_command_verify(ahci, cmd);
938 ahci_command_free(cmd);
939 }
940
941 void ahci_atapi_load(AHCIQState *ahci, uint8_t port)
942 {
943 AHCICommand *cmd = ahci_atapi_command_create(CMD_ATAPI_START_STOP_UNIT, 0);
944 ahci_command_set_size(cmd, 0);
945
946 cmd->atapi_cmd[4] = 0x03; /* loej,start = true */
947 ahci_command_commit(ahci, cmd, port);
948 ahci_command_issue(ahci, cmd);
949 ahci_command_verify(ahci, cmd);
950 ahci_command_free(cmd);
951 }
952
953 void ahci_command_free(AHCICommand *cmd)
954 {
955 g_free(cmd->atapi_cmd);
956 g_free(cmd->props);
957 g_free(cmd);
958 }
959
960 void ahci_command_set_flags(AHCICommand *cmd, uint16_t cmdh_flags)
961 {
962 cmd->header.flags |= cmdh_flags;
963 }
964
965 void ahci_command_clr_flags(AHCICommand *cmd, uint16_t cmdh_flags)
966 {
967 cmd->header.flags &= ~cmdh_flags;
968 }
969
970 static void ahci_atapi_command_set_offset(AHCICommand *cmd, uint64_t lba)
971 {
972 unsigned char *cbd = cmd->atapi_cmd;
973 g_assert(cbd);
974
975 switch (cbd[0]) {
976 case CMD_ATAPI_READ_10:
977 case CMD_ATAPI_READ_CD:
978 g_assert_cmpuint(lba, <=, UINT32_MAX);
979 stl_be_p(&cbd[2], lba);
980 break;
981 case CMD_ATAPI_REQUEST_SENSE:
982 case CMD_ATAPI_TEST_UNIT_READY:
983 case CMD_ATAPI_START_STOP_UNIT:
984 g_assert_cmpuint(lba, ==, 0x00);
985 break;
986 default:
987 /* SCSI doesn't have uniform packet formats,
988 * so you have to add support for it manually. Sorry! */
989 fprintf(stderr, "The Libqos AHCI driver does not support the "
990 "set_offset operation for ATAPI command 0x%02x, "
991 "please add support.\n",
992 cbd[0]);
993 g_assert_not_reached();
994 }
995 }
996
997 void ahci_command_set_offset(AHCICommand *cmd, uint64_t lba_sect)
998 {
999 RegH2DFIS *fis = &(cmd->fis);
1000
1001 if (cmd->props->atapi) {
1002 ahci_atapi_command_set_offset(cmd, lba_sect);
1003 return;
1004 } else if (!cmd->props->data && !lba_sect) {
1005 /* Not meaningful, ignore. */
1006 return;
1007 } else if (cmd->props->lba28) {
1008 g_assert_cmphex(lba_sect, <=, 0xFFFFFFF);
1009 } else if (cmd->props->lba48 || cmd->props->ncq) {
1010 g_assert_cmphex(lba_sect, <=, 0xFFFFFFFFFFFF);
1011 } else {
1012 /* Can't set offset if we don't know the format. */
1013 g_assert_not_reached();
1014 }
1015
1016 /* LBA28 uses the low nibble of the device/control register for LBA24:27 */
1017 fis->lba_lo[0] = (lba_sect & 0xFF);
1018 fis->lba_lo[1] = (lba_sect >> 8) & 0xFF;
1019 fis->lba_lo[2] = (lba_sect >> 16) & 0xFF;
1020 if (cmd->props->lba28) {
1021 fis->device = (fis->device & 0xF0) | ((lba_sect >> 24) & 0x0F);
1022 }
1023 fis->lba_hi[0] = (lba_sect >> 24) & 0xFF;
1024 fis->lba_hi[1] = (lba_sect >> 32) & 0xFF;
1025 fis->lba_hi[2] = (lba_sect >> 40) & 0xFF;
1026 }
1027
1028 void ahci_command_set_buffer(AHCICommand *cmd, uint64_t buffer)
1029 {
1030 cmd->buffer = buffer;
1031 }
1032
1033 static void ahci_atapi_set_size(AHCICommand *cmd, uint64_t xbytes)
1034 {
1035 unsigned char *cbd = cmd->atapi_cmd;
1036 uint64_t nsectors = xbytes / 2048;
1037 uint32_t tmp;
1038 g_assert(cbd);
1039
1040 switch (cbd[0]) {
1041 case CMD_ATAPI_READ_10:
1042 g_assert_cmpuint(nsectors, <=, UINT16_MAX);
1043 stw_be_p(&cbd[7], nsectors);
1044 break;
1045 case CMD_ATAPI_READ_CD:
1046 /* 24bit BE store */
1047 g_assert_cmpuint(nsectors, <, 1ULL << 24);
1048 tmp = nsectors;
1049 cbd[6] = (tmp & 0xFF0000) >> 16;
1050 cbd[7] = (tmp & 0xFF00) >> 8;
1051 cbd[8] = (tmp & 0xFF);
1052 break;
1053 case CMD_ATAPI_REQUEST_SENSE:
1054 g_assert_cmpuint(xbytes, <=, UINT8_MAX);
1055 cbd[4] = (uint8_t)xbytes;
1056 break;
1057 case CMD_ATAPI_TEST_UNIT_READY:
1058 case CMD_ATAPI_START_STOP_UNIT:
1059 g_assert_cmpuint(xbytes, ==, 0);
1060 break;
1061 default:
1062 /* SCSI doesn't have uniform packet formats,
1063 * so you have to add support for it manually. Sorry! */
1064 fprintf(stderr, "The Libqos AHCI driver does not support the set_size "
1065 "operation for ATAPI command 0x%02x, please add support.\n",
1066 cbd[0]);
1067 g_assert_not_reached();
1068 }
1069 }
1070
1071 void ahci_command_set_sizes(AHCICommand *cmd, uint64_t xbytes,
1072 unsigned prd_size)
1073 {
1074 uint16_t sect_count;
1075
1076 /* Each PRD can describe up to 4MiB, and must not be odd. */
1077 g_assert_cmphex(prd_size, <=, 4096 * 1024);
1078 g_assert_cmphex(prd_size & 0x01, ==, 0x00);
1079 if (prd_size) {
1080 cmd->prd_size = prd_size;
1081 }
1082 cmd->xbytes = xbytes;
1083 sect_count = (cmd->xbytes / AHCI_SECTOR_SIZE);
1084
1085 if (cmd->props->ncq) {
1086 NCQFIS *nfis = (NCQFIS *)&(cmd->fis);
1087 nfis->sector_low = sect_count & 0xFF;
1088 nfis->sector_hi = (sect_count >> 8) & 0xFF;
1089 } else if (cmd->props->atapi) {
1090 ahci_atapi_set_size(cmd, xbytes);
1091 } else {
1092 cmd->fis.count = sect_count;
1093 }
1094 cmd->header.prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
1095 }
1096
1097 void ahci_command_set_size(AHCICommand *cmd, uint64_t xbytes)
1098 {
1099 ahci_command_set_sizes(cmd, xbytes, cmd->prd_size);
1100 }
1101
1102 void ahci_command_set_prd_size(AHCICommand *cmd, unsigned prd_size)
1103 {
1104 ahci_command_set_sizes(cmd, cmd->xbytes, prd_size);
1105 }
1106
1107 void ahci_command_adjust(AHCICommand *cmd, uint64_t offset, uint64_t buffer,
1108 uint64_t xbytes, unsigned prd_size)
1109 {
1110 ahci_command_set_sizes(cmd, xbytes, prd_size);
1111 ahci_command_set_buffer(cmd, buffer);
1112 ahci_command_set_offset(cmd, offset);
1113 }
1114
1115 void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port)
1116 {
1117 uint16_t i, prdtl;
1118 uint64_t table_size, table_ptr, remaining;
1119 PRD prd;
1120
1121 /* This command is now tied to this port/command slot */
1122 cmd->port = port;
1123 cmd->slot = ahci_pick_cmd(ahci, port);
1124
1125 if (cmd->props->ncq) {
1126 NCQFIS *nfis = (NCQFIS *)&cmd->fis;
1127 nfis->tag = (cmd->slot << 3) & 0xFC;
1128 }
1129
1130 /* Create a buffer for the command table */
1131 prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
1132 table_size = CMD_TBL_SIZ(prdtl);
1133 table_ptr = ahci_alloc(ahci, table_size);
1134 g_assert(table_ptr);
1135 /* AHCI 1.3: Must be aligned to 0x80 */
1136 g_assert((table_ptr & 0x7F) == 0x00);
1137 cmd->header.ctba = table_ptr;
1138
1139 /* Commit the command header (part of the Command List Buffer) */
1140 ahci_set_command_header(ahci, port, cmd->slot, &(cmd->header));
1141 /* Now, write the command table (FIS, ACMD, and PRDT) -- FIS first, */
1142 ahci_write_fis(ahci, cmd);
1143 /* Then ATAPI CMD, if needed */
1144 if (cmd->props->atapi) {
1145 qtest_memwrite(ahci->parent->qts, table_ptr + 0x40, cmd->atapi_cmd, 16);
1146 }
1147
1148 /* Construct and write the PRDs to the command table */
1149 g_assert_cmphex(prdtl, ==, cmd->header.prdtl);
1150 remaining = cmd->xbytes;
1151 for (i = 0; i < prdtl; ++i) {
1152 prd.dba = cpu_to_le64(cmd->buffer + (cmd->prd_size * i));
1153 prd.res = 0;
1154 if (remaining > cmd->prd_size) {
1155 /* Note that byte count is 0-based. */
1156 prd.dbc = cpu_to_le32(cmd->prd_size - 1);
1157 remaining -= cmd->prd_size;
1158 } else {
1159 /* Again, dbc is 0-based. */
1160 prd.dbc = cpu_to_le32(remaining - 1);
1161 remaining = 0;
1162 }
1163 prd.dbc |= cpu_to_le32(0x80000000); /* Request DPS Interrupt */
1164
1165 /* Commit the PRD entry to the Command Table */
1166 qtest_memwrite(ahci->parent->qts, table_ptr + 0x80 + (i * sizeof(PRD)),
1167 &prd, sizeof(PRD));
1168 }
1169
1170 /* Bookmark the PRDTL and CTBA values */
1171 ahci->port[port].ctba[cmd->slot] = table_ptr;
1172 ahci->port[port].prdtl[cmd->slot] = prdtl;
1173 }
1174
1175 void ahci_command_issue_async(AHCIQState *ahci, AHCICommand *cmd)
1176 {
1177 if (cmd->props->ncq) {
1178 ahci_px_wreg(ahci, cmd->port, AHCI_PX_SACT, (1 << cmd->slot));
1179 }
1180
1181 ahci_px_wreg(ahci, cmd->port, AHCI_PX_CI, (1 << cmd->slot));
1182 }
1183
1184 void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd)
1185 {
1186 /* We can't rely on STS_BSY until the command has started processing.
1187 * Therefore, we also use the Command Issue bit as indication of
1188 * a command in-flight. */
1189
1190 #define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK)))
1191
1192 while (RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_BSY) ||
1193 RSET(AHCI_PX_CI, 1 << cmd->slot) ||
1194 (cmd->props->ncq && RSET(AHCI_PX_SACT, 1 << cmd->slot))) {
1195 usleep(50);
1196 }
1197
1198 }
1199
1200 void ahci_command_issue(AHCIQState *ahci, AHCICommand *cmd)
1201 {
1202 ahci_command_issue_async(ahci, cmd);
1203 ahci_command_wait(ahci, cmd);
1204 }
1205
1206 void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd)
1207 {
1208 uint8_t slot = cmd->slot;
1209 uint8_t port = cmd->port;
1210
1211 ahci_port_check_error(ahci, port, cmd->interrupts, cmd->errors);
1212 ahci_port_check_interrupts(ahci, port, cmd->interrupts);
1213 ahci_port_check_nonbusy(ahci, port, slot);
1214 ahci_port_check_cmd_sanity(ahci, cmd);
1215 if (cmd->interrupts & AHCI_PX_IS_DHRS) {
1216 ahci_port_check_d2h_sanity(ahci, port, slot);
1217 }
1218 if (cmd->props->pio) {
1219 ahci_port_check_pio_sanity(ahci, port, slot, cmd->xbytes);
1220 }
1221 }
1222
1223 uint8_t ahci_command_slot(AHCICommand *cmd)
1224 {
1225 return cmd->slot;
1226 }
AR7 emulation for QEMU