include/hw/ppc/spapr.h

   1 #ifndef HW_SPAPR_H
   2 #define HW_SPAPR_H
   3
   4 #include "qemu/units.h"
   5 #include "sysemu/dma.h"
   6 #include "hw/boards.h"
   7 #include "hw/ppc/spapr_drc.h"
   8 #include "hw/mem/pc-dimm.h"
   9 #include "hw/ppc/spapr_ovec.h"
  10 #include "hw/ppc/spapr_irq.h"
  11 #include "qom/object.h"
  12 #include "hw/ppc/spapr_xive.h"  /* For SpaprXive */
  13 #include "hw/ppc/xics.h"        /* For ICSState */
  14 #include "hw/ppc/spapr_tpm_proxy.h"
  15
  16 struct SpaprVioBus;
  17 struct SpaprPhbState;
  18 struct SpaprNvram;
  19
  20 typedef struct SpaprEventLogEntry SpaprEventLogEntry;
  21 typedef struct SpaprEventSource SpaprEventSource;
  22 typedef struct SpaprPendingHpt SpaprPendingHpt;
  23
  24 #define HPTE64_V_HPTE_DIRTY     0x0000000000000040ULL
  25 #define SPAPR_ENTRY_POINT       0x100
  26
  27 #define SPAPR_TIMEBASE_FREQ     512000000ULL
  28
  29 #define TYPE_SPAPR_RTC "spapr-rtc"
  30
  31 OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC)
  32
  33 struct SpaprRtcState {
  34     /*< private >*/
  35     DeviceState parent_obj;
  36     int64_t ns_offset;
  37 };
  38
  39 typedef struct SpaprDimmState SpaprDimmState;
  40
  41 #define TYPE_SPAPR_MACHINE      "spapr-machine"
  42 OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE)
  43
  44 typedef enum {
  45     SPAPR_RESIZE_HPT_DEFAULT = 0,
  46     SPAPR_RESIZE_HPT_DISABLED,
  47     SPAPR_RESIZE_HPT_ENABLED,
  48     SPAPR_RESIZE_HPT_REQUIRED,
  49 } SpaprResizeHpt;
  50
  51 /**
  52  * Capabilities
  53  */
  54
  55 /* Hardware Transactional Memory */
  56 #define SPAPR_CAP_HTM                   0x00
  57 /* Vector Scalar Extensions */
  58 #define SPAPR_CAP_VSX                   0x01
  59 /* Decimal Floating Point */
  60 #define SPAPR_CAP_DFP                   0x02
  61 /* Cache Flush on Privilege Change */
  62 #define SPAPR_CAP_CFPC                  0x03
  63 /* Speculation Barrier Bounds Checking */
  64 #define SPAPR_CAP_SBBC                  0x04
  65 /* Indirect Branch Serialisation */
  66 #define SPAPR_CAP_IBS                   0x05
  67 /* HPT Maximum Page Size (encoded as a shift) */
  68 #define SPAPR_CAP_HPT_MAXPAGESIZE       0x06
  69 /* Nested KVM-HV */
  70 #define SPAPR_CAP_NESTED_KVM_HV         0x07
  71 /* Large Decrementer */
  72 #define SPAPR_CAP_LARGE_DECREMENTER     0x08
  73 /* Count Cache Flush Assist HW Instruction */
  74 #define SPAPR_CAP_CCF_ASSIST            0x09
  75 /* Implements PAPR FWNMI option */
  76 #define SPAPR_CAP_FWNMI                 0x0A
  77 /* Num Caps */
  78 #define SPAPR_CAP_NUM                   (SPAPR_CAP_FWNMI + 1)
  79
  80 /*
  81  * Capability Values
  82  */
  83 /* Bool Caps */
  84 #define SPAPR_CAP_OFF                   0x00
  85 #define SPAPR_CAP_ON                    0x01
  86
  87 /* Custom Caps */
  88
  89 /* Generic */
  90 #define SPAPR_CAP_BROKEN                0x00
  91 #define SPAPR_CAP_WORKAROUND            0x01
  92 #define SPAPR_CAP_FIXED                 0x02
  93 /* SPAPR_CAP_IBS (cap-ibs) */
  94 #define SPAPR_CAP_FIXED_IBS             0x02
  95 #define SPAPR_CAP_FIXED_CCD             0x03
  96 #define SPAPR_CAP_FIXED_NA              0x10 /* Lets leave a bit of a gap... */
  97
  98 #define FDT_MAX_SIZE                    0x200000
  99
 100 /*
 101  * NUMA related macros. MAX_DISTANCE_REF_POINTS was taken
 102  * from Linux kernel arch/powerpc/mm/numa.h. It represents the
 103  * amount of associativity domains for non-CPU resources.
 104  *
 105  * NUMA_ASSOC_SIZE is the base array size of an ibm,associativity
 106  * array for any non-CPU resource.
 107  *
 108  * VCPU_ASSOC_SIZE represents the size of ibm,associativity array
 109  * for CPUs, which has an extra element (vcpu_id) in the end.
 110  */
 111 #define MAX_DISTANCE_REF_POINTS    4
 112 #define NUMA_ASSOC_SIZE            (MAX_DISTANCE_REF_POINTS + 1)
 113 #define VCPU_ASSOC_SIZE            (NUMA_ASSOC_SIZE + 1)
 114
 115 /* Max number of these GPUsper a physical box */
 116 #define NVGPU_MAX_NUM                6
 117
 118 typedef struct SpaprCapabilities SpaprCapabilities;
 119 struct SpaprCapabilities {
 120     uint8_t caps[SPAPR_CAP_NUM];
 121 };
 122
 123 /**
 124  * SpaprMachineClass:
 125  */
 126 struct SpaprMachineClass {
 127     /*< private >*/
 128     MachineClass parent_class;
 129
 130     /*< public >*/
 131     bool dr_lmb_enabled;       /* enable dynamic-reconfig/hotplug of LMBs */
 132     bool dr_phb_enabled;       /* enable dynamic-reconfig/hotplug of PHBs */
 133     bool update_dt_enabled;    /* enable KVMPPC_H_UPDATE_DT */
 134     bool use_ohci_by_default;  /* use USB-OHCI instead of XHCI */
 135     bool pre_2_10_has_unused_icps;
 136     bool legacy_irq_allocation;
 137     uint32_t nr_xirqs;
 138     bool broken_host_serial_model; /* present real host info to the guest */
 139     bool pre_4_1_migration; /* don't migrate hpt-max-page-size */
 140     bool linux_pci_probe;
 141     bool smp_threads_vsmt; /* set VSMT to smp_threads by default */
 142     hwaddr rma_limit;          /* clamp the RMA to this size */
 143     bool pre_5_1_assoc_refpoints;
 144     bool pre_5_2_numa_associativity;
 145
 146     bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
 147                           uint64_t *buid, hwaddr *pio,
 148                           hwaddr *mmio32, hwaddr *mmio64,
 149                           unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa,
 150                           hwaddr *nv2atsd, Error **errp);
 151     SpaprResizeHpt resize_hpt_default;
 152     SpaprCapabilities default_caps;
 153     SpaprIrq *irq;
 154 };
 155
 156 /**
 157  * SpaprMachineState:
 158  */
 159 struct SpaprMachineState {
 160     /*< private >*/
 161     MachineState parent_obj;
 162
 163     struct SpaprVioBus *vio_bus;
 164     QLIST_HEAD(, SpaprPhbState) phbs;
 165     struct SpaprNvram *nvram;
 166     SpaprRtcState rtc;
 167
 168     SpaprResizeHpt resize_hpt;
 169     void *htab;
 170     uint32_t htab_shift;
 171     uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROC_TBL */
 172     SpaprPendingHpt *pending_hpt; /* in-progress resize */
 173
 174     hwaddr rma_size;
 175     uint32_t fdt_size;
 176     uint32_t fdt_initial_size;
 177     void *fdt_blob;
 178     long kernel_size;
 179     bool kernel_le;
 180     uint64_t kernel_addr;
 181     uint32_t initrd_base;
 182     long initrd_size;
 183     uint64_t rtc_offset; /* Now used only during incoming migration */
 184     struct PPCTimebase tb;
 185     bool has_graphics;
 186     uint32_t vsmt;       /* Virtual SMT mode (KVM's "core stride") */
 187
 188     Notifier epow_notifier;
 189     QTAILQ_HEAD(, SpaprEventLogEntry) pending_events;
 190     bool use_hotplug_event_source;
 191     SpaprEventSource *event_sources;
 192
 193     /* ibm,client-architecture-support option negotiation */
 194     bool cas_pre_isa3_guest;
 195     SpaprOptionVector *ov5;         /* QEMU-supported option vectors */
 196     SpaprOptionVector *ov5_cas;     /* negotiated (via CAS) option vectors */
 197     uint32_t max_compat_pvr;
 198
 199     /* Migration state */
 200     int htab_save_index;
 201     bool htab_first_pass;
 202     int htab_fd;
 203
 204     /* Pending DIMM unplug cache. It is populated when a LMB
 205      * unplug starts. It can be regenerated if a migration
 206      * occurs during the unplug process. */
 207     QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs;
 208
 209     /* State related to FWNMI option */
 210
 211     /* System Reset and Machine Check Notification Routine addresses
 212      * registered by "ibm,nmi-register" RTAS call.
 213      */
 214     target_ulong fwnmi_system_reset_addr;
 215     target_ulong fwnmi_machine_check_addr;
 216
 217     /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is
 218      * set to -1 if a FWNMI machine check is not in progress, else is set to
 219      * the CPU that was delivered the machine check, and is set back to -1
 220      * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used
 221      * to synchronize other CPUs.
 222      */
 223     int fwnmi_machine_check_interlock;
 224     QemuCond fwnmi_machine_check_interlock_cond;
 225
 226     /*< public >*/
 227     char *kvm_type;
 228     char *host_model;
 229     char *host_serial;
 230
 231     int32_t irq_map_nr;
 232     unsigned long *irq_map;
 233     SpaprIrq *irq;
 234     qemu_irq *qirqs;
 235     SpaprInterruptController *active_intc;
 236     ICSState *ics;
 237     SpaprXive *xive;
 238
 239     bool cmd_line_caps[SPAPR_CAP_NUM];
 240     SpaprCapabilities def, eff, mig;
 241
 242     unsigned gpu_numa_id;
 243     SpaprTpmProxy *tpm_proxy;
 244
 245     uint32_t numa_assoc_array[MAX_NODES + NVGPU_MAX_NUM][NUMA_ASSOC_SIZE];
 246
 247     Error *fwnmi_migration_blocker;
 248 };
 249
 250 #define H_SUCCESS         0
 251 #define H_BUSY            1        /* Hardware busy -- retry later */
 252 #define H_CLOSED          2        /* Resource closed */
 253 #define H_NOT_AVAILABLE   3
 254 #define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
 255 #define H_PARTIAL         5
 256 #define H_IN_PROGRESS     14       /* Kind of like busy */
 257 #define H_PAGE_REGISTERED 15
 258 #define H_PARTIAL_STORE   16
 259 #define H_PENDING         17       /* returned from H_POLL_PENDING */
 260 #define H_CONTINUE        18       /* Returned from H_Join on success */
 261 #define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
 262 #define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
 263                                                  is a good time to retry */
 264 #define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
 265                                                  is a good time to retry */
 266 #define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
 267                                                  is a good time to retry */
 268 #define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
 269                                                  is a good time to retry */
 270 #define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
 271                                                  is a good time to retry */
 272 #define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
 273                                                  is a good time to retry */
 274 #define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
 275 #define H_HARDWARE        -1       /* Hardware error */
 276 #define H_FUNCTION        -2       /* Function not supported */
 277 #define H_PRIVILEGE       -3       /* Caller not privileged */
 278 #define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
 279 #define H_BAD_MODE        -5       /* Illegal msr value */
 280 #define H_PTEG_FULL       -6       /* PTEG is full */
 281 #define H_NOT_FOUND       -7       /* PTE was not found" */
 282 #define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
 283 #define H_NO_MEM          -9
 284 #define H_AUTHORITY       -10
 285 #define H_PERMISSION      -11
 286 #define H_DROPPED         -12
 287 #define H_SOURCE_PARM     -13
 288 #define H_DEST_PARM       -14
 289 #define H_REMOTE_PARM     -15
 290 #define H_RESOURCE        -16
 291 #define H_ADAPTER_PARM    -17
 292 #define H_RH_PARM         -18
 293 #define H_RCQ_PARM        -19
 294 #define H_SCQ_PARM        -20
 295 #define H_EQ_PARM         -21
 296 #define H_RT_PARM         -22
 297 #define H_ST_PARM         -23
 298 #define H_SIGT_PARM       -24
 299 #define H_TOKEN_PARM      -25
 300 #define H_MLENGTH_PARM    -27
 301 #define H_MEM_PARM        -28
 302 #define H_MEM_ACCESS_PARM -29
 303 #define H_ATTR_PARM       -30
 304 #define H_PORT_PARM       -31
 305 #define H_MCG_PARM        -32
 306 #define H_VL_PARM         -33
 307 #define H_TSIZE_PARM      -34
 308 #define H_TRACE_PARM      -35
 309
 310 #define H_MASK_PARM       -37
 311 #define H_MCG_FULL        -38
 312 #define H_ALIAS_EXIST     -39
 313 #define H_P_COUNTER       -40
 314 #define H_TABLE_FULL      -41
 315 #define H_ALT_TABLE       -42
 316 #define H_MR_CONDITION    -43
 317 #define H_NOT_ENOUGH_RESOURCES -44
 318 #define H_R_STATE         -45
 319 #define H_RESCINDEND      -46
 320 #define H_P2              -55
 321 #define H_P3              -56
 322 #define H_P4              -57
 323 #define H_P5              -58
 324 #define H_P6              -59
 325 #define H_P7              -60
 326 #define H_P8              -61
 327 #define H_P9              -62
 328 #define H_OVERLAP         -68
 329 #define H_UNSUPPORTED_FLAG -256
 330 #define H_MULTI_THREADS_ACTIVE -9005
 331
 332
 333 /* Long Busy is a condition that can be returned by the firmware
 334  * when a call cannot be completed now, but the identical call
 335  * should be retried later.  This prevents calls blocking in the
 336  * firmware for long periods of time.  Annoyingly the firmware can return
 337  * a range of return codes, hinting at how long we should wait before
 338  * retrying.  If you don't care for the hint, the macro below is a good
 339  * way to check for the long_busy return codes
 340  */
 341 #define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
 342                             && (x <= H_LONG_BUSY_END_RANGE))
 343
 344 /* Flags */
 345 #define H_LARGE_PAGE      (1ULL<<(63-16))
 346 #define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
 347 #define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
 348 #define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
 349 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
 350 #define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
 351 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
 352 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
 353 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
 354 #define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
 355 #define H_ANDCOND         (1ULL<<(63-33))
 356 #define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
 357 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
 358 #define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
 359 #define H_COPY_PAGE       (1ULL<<(63-49))
 360 #define H_N               (1ULL<<(63-61))
 361 #define H_PP1             (1ULL<<(63-62))
 362 #define H_PP2             (1ULL<<(63-63))
 363
 364 /* Values for 2nd argument to H_SET_MODE */
 365 #define H_SET_MODE_RESOURCE_SET_CIABR           1
 366 #define H_SET_MODE_RESOURCE_SET_DAWR0           2
 367 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE     3
 368 #define H_SET_MODE_RESOURCE_LE                  4
 369
 370 /* Flags for H_SET_MODE_RESOURCE_LE */
 371 #define H_SET_MODE_ENDIAN_BIG    0
 372 #define H_SET_MODE_ENDIAN_LITTLE 1
 373
 374 /* VASI States */
 375 #define H_VASI_INVALID    0
 376 #define H_VASI_ENABLED    1
 377 #define H_VASI_ABORTED    2
 378 #define H_VASI_SUSPENDING 3
 379 #define H_VASI_SUSPENDED  4
 380 #define H_VASI_RESUMED    5
 381 #define H_VASI_COMPLETED  6
 382
 383 /* DABRX flags */
 384 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
 385 #define H_DABRX_KERNEL     (1ULL<<(63-62))
 386 #define H_DABRX_USER       (1ULL<<(63-63))
 387
 388 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */
 389 #define H_CPU_CHAR_SPEC_BAR_ORI31               PPC_BIT(0)
 390 #define H_CPU_CHAR_BCCTRL_SERIALISED            PPC_BIT(1)
 391 #define H_CPU_CHAR_L1D_FLUSH_ORI30              PPC_BIT(2)
 392 #define H_CPU_CHAR_L1D_FLUSH_TRIG2              PPC_BIT(3)
 393 #define H_CPU_CHAR_L1D_THREAD_PRIV              PPC_BIT(4)
 394 #define H_CPU_CHAR_HON_BRANCH_HINTS             PPC_BIT(5)
 395 #define H_CPU_CHAR_THR_RECONF_TRIG              PPC_BIT(6)
 396 #define H_CPU_CHAR_CACHE_COUNT_DIS              PPC_BIT(7)
 397 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST           PPC_BIT(9)
 398 #define H_CPU_BEHAV_FAVOUR_SECURITY             PPC_BIT(0)
 399 #define H_CPU_BEHAV_L1D_FLUSH_PR                PPC_BIT(1)
 400 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR           PPC_BIT(2)
 401 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE           PPC_BIT(5)
 402
 403 /* Each control block has to be on a 4K boundary */
 404 #define H_CB_ALIGNMENT     4096
 405
 406 /* pSeries hypervisor opcodes */
 407 #define H_REMOVE                0x04
 408 #define H_ENTER                 0x08
 409 #define H_READ                  0x0c
 410 #define H_CLEAR_MOD             0x10
 411 #define H_CLEAR_REF             0x14
 412 #define H_PROTECT               0x18
 413 #define H_GET_TCE               0x1c
 414 #define H_PUT_TCE               0x20
 415 #define H_SET_SPRG0             0x24
 416 #define H_SET_DABR              0x28
 417 #define H_PAGE_INIT             0x2c
 418 #define H_SET_ASR               0x30
 419 #define H_ASR_ON                0x34
 420 #define H_ASR_OFF               0x38
 421 #define H_LOGICAL_CI_LOAD       0x3c
 422 #define H_LOGICAL_CI_STORE      0x40
 423 #define H_LOGICAL_CACHE_LOAD    0x44
 424 #define H_LOGICAL_CACHE_STORE   0x48
 425 #define H_LOGICAL_ICBI          0x4c
 426 #define H_LOGICAL_DCBF          0x50
 427 #define H_GET_TERM_CHAR         0x54
 428 #define H_PUT_TERM_CHAR         0x58
 429 #define H_REAL_TO_LOGICAL       0x5c
 430 #define H_HYPERVISOR_DATA       0x60
 431 #define H_EOI                   0x64
 432 #define H_CPPR                  0x68
 433 #define H_IPI                   0x6c
 434 #define H_IPOLL                 0x70
 435 #define H_XIRR                  0x74
 436 #define H_PERFMON               0x7c
 437 #define H_MIGRATE_DMA           0x78
 438 #define H_REGISTER_VPA          0xDC
 439 #define H_CEDE                  0xE0
 440 #define H_CONFER                0xE4
 441 #define H_PROD                  0xE8
 442 #define H_GET_PPP               0xEC
 443 #define H_SET_PPP               0xF0
 444 #define H_PURR                  0xF4
 445 #define H_PIC                   0xF8
 446 #define H_REG_CRQ               0xFC
 447 #define H_FREE_CRQ              0x100
 448 #define H_VIO_SIGNAL            0x104
 449 #define H_SEND_CRQ              0x108
 450 #define H_COPY_RDMA             0x110
 451 #define H_REGISTER_LOGICAL_LAN  0x114
 452 #define H_FREE_LOGICAL_LAN      0x118
 453 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
 454 #define H_SEND_LOGICAL_LAN      0x120
 455 #define H_BULK_REMOVE           0x124
 456 #define H_MULTICAST_CTRL        0x130
 457 #define H_SET_XDABR             0x134
 458 #define H_STUFF_TCE             0x138
 459 #define H_PUT_TCE_INDIRECT      0x13C
 460 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
 461 #define H_VTERM_PARTNER_INFO    0x150
 462 #define H_REGISTER_VTERM        0x154
 463 #define H_FREE_VTERM            0x158
 464 #define H_RESET_EVENTS          0x15C
 465 #define H_ALLOC_RESOURCE        0x160
 466 #define H_FREE_RESOURCE         0x164
 467 #define H_MODIFY_QP             0x168
 468 #define H_QUERY_QP              0x16C
 469 #define H_REREGISTER_PMR        0x170
 470 #define H_REGISTER_SMR          0x174
 471 #define H_QUERY_MR              0x178
 472 #define H_QUERY_MW              0x17C
 473 #define H_QUERY_HCA             0x180
 474 #define H_QUERY_PORT            0x184
 475 #define H_MODIFY_PORT           0x188
 476 #define H_DEFINE_AQP1           0x18C
 477 #define H_GET_TRACE_BUFFER      0x190
 478 #define H_DEFINE_AQP0           0x194
 479 #define H_RESIZE_MR             0x198
 480 #define H_ATTACH_MCQP           0x19C
 481 #define H_DETACH_MCQP           0x1A0
 482 #define H_CREATE_RPT            0x1A4
 483 #define H_REMOVE_RPT            0x1A8
 484 #define H_REGISTER_RPAGES       0x1AC
 485 #define H_DISABLE_AND_GETC      0x1B0
 486 #define H_ERROR_DATA            0x1B4
 487 #define H_GET_HCA_INFO          0x1B8
 488 #define H_GET_PERF_COUNT        0x1BC
 489 #define H_MANAGE_TRACE          0x1C0
 490 #define H_GET_CPU_CHARACTERISTICS 0x1C8
 491 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
 492 #define H_QUERY_INT_STATE       0x1E4
 493 #define H_POLL_PENDING          0x1D8
 494 #define H_ILLAN_ATTRIBUTES      0x244
 495 #define H_MODIFY_HEA_QP         0x250
 496 #define H_QUERY_HEA_QP          0x254
 497 #define H_QUERY_HEA             0x258
 498 #define H_QUERY_HEA_PORT        0x25C
 499 #define H_MODIFY_HEA_PORT       0x260
 500 #define H_REG_BCMC              0x264
 501 #define H_DEREG_BCMC            0x268
 502 #define H_REGISTER_HEA_RPAGES   0x26C
 503 #define H_DISABLE_AND_GET_HEA   0x270
 504 #define H_GET_HEA_INFO          0x274
 505 #define H_ALLOC_HEA_RESOURCE    0x278
 506 #define H_ADD_CONN              0x284
 507 #define H_DEL_CONN              0x288
 508 #define H_JOIN                  0x298
 509 #define H_VASI_STATE            0x2A4
 510 #define H_ENABLE_CRQ            0x2B0
 511 #define H_GET_EM_PARMS          0x2B8
 512 #define H_SET_MPP               0x2D0
 513 #define H_GET_MPP               0x2D4
 514 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC
 515 #define H_XIRR_X                0x2FC
 516 #define H_RANDOM                0x300
 517 #define H_SET_MODE              0x31C
 518 #define H_RESIZE_HPT_PREPARE    0x36C
 519 #define H_RESIZE_HPT_COMMIT     0x370
 520 #define H_CLEAN_SLB             0x374
 521 #define H_INVALIDATE_PID        0x378
 522 #define H_REGISTER_PROC_TBL     0x37C
 523 #define H_SIGNAL_SYS_RESET      0x380
 524
 525 #define H_INT_GET_SOURCE_INFO   0x3A8
 526 #define H_INT_SET_SOURCE_CONFIG 0x3AC
 527 #define H_INT_GET_SOURCE_CONFIG 0x3B0
 528 #define H_INT_GET_QUEUE_INFO    0x3B4
 529 #define H_INT_SET_QUEUE_CONFIG  0x3B8
 530 #define H_INT_GET_QUEUE_CONFIG  0x3BC
 531 #define H_INT_SET_OS_REPORTING_LINE 0x3C0
 532 #define H_INT_GET_OS_REPORTING_LINE 0x3C4
 533 #define H_INT_ESB               0x3C8
 534 #define H_INT_SYNC              0x3CC
 535 #define H_INT_RESET             0x3D0
 536 #define H_SCM_READ_METADATA     0x3E4
 537 #define H_SCM_WRITE_METADATA    0x3E8
 538 #define H_SCM_BIND_MEM          0x3EC
 539 #define H_SCM_UNBIND_MEM        0x3F0
 540 #define H_SCM_UNBIND_ALL        0x3FC
 541 #define H_SCM_HEALTH            0x400
 542
 543 #define MAX_HCALL_OPCODE        H_SCM_HEALTH
 544
 545 /* The hcalls above are standardized in PAPR and implemented by pHyp
 546  * as well.
 547  *
 548  * We also need some hcalls which are specific to qemu / KVM-on-POWER.
 549  * We put those into the 0xf000-0xfffc range which is reserved by PAPR
 550  * for "platform-specific" hcalls.
 551  */
 552 #define KVMPPC_HCALL_BASE       0xf000
 553 #define KVMPPC_H_RTAS           (KVMPPC_HCALL_BASE + 0x0)
 554 #define KVMPPC_H_LOGICAL_MEMOP  (KVMPPC_HCALL_BASE + 0x1)
 555 /* Client Architecture support */
 556 #define KVMPPC_H_CAS            (KVMPPC_HCALL_BASE + 0x2)
 557 #define KVMPPC_H_UPDATE_DT      (KVMPPC_HCALL_BASE + 0x3)
 558 #define KVMPPC_HCALL_MAX        KVMPPC_H_UPDATE_DT
 559
 560 /*
 561  * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating
 562  * Secure VM mode via an Ultravisor / Protected Execution Facility
 563  */
 564 #define SVM_HCALL_BASE              0xEF00
 565 #define SVM_H_TPM_COMM              0xEF10
 566 #define SVM_HCALL_MAX               SVM_H_TPM_COMM
 567
 568
 569 typedef struct SpaprDeviceTreeUpdateHeader {
 570     uint32_t version_id;
 571 } SpaprDeviceTreeUpdateHeader;
 572
 573 #define hcall_dprintf(fmt, ...) \
 574     do { \
 575         qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
 576     } while (0)
 577
 578 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
 579                                        target_ulong opcode,
 580                                        target_ulong *args);
 581
 582 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
 583 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
 584                              target_ulong *args);
 585 target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr,
 586                                          target_ulong shift);
 587 target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr,
 588                                         target_ulong flags, target_ulong shift);
 589 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr);
 590 void push_sregs_to_kvm_pr(SpaprMachineState *spapr);
 591
 592 /* Virtual Processor Area structure constants */
 593 #define VPA_MIN_SIZE           640
 594 #define VPA_SIZE_OFFSET        0x4
 595 #define VPA_SHARED_PROC_OFFSET 0x9
 596 #define VPA_SHARED_PROC_VAL    0x2
 597 #define VPA_DISPATCH_COUNTER   0x100
 598
 599 /* ibm,set-eeh-option */
 600 #define RTAS_EEH_DISABLE                 0
 601 #define RTAS_EEH_ENABLE                  1
 602 #define RTAS_EEH_THAW_IO                 2
 603 #define RTAS_EEH_THAW_DMA                3
 604
 605 /* ibm,get-config-addr-info2 */
 606 #define RTAS_GET_PE_ADDR                 0
 607 #define RTAS_GET_PE_MODE                 1
 608 #define RTAS_PE_MODE_NONE                0
 609 #define RTAS_PE_MODE_NOT_SHARED          1
 610 #define RTAS_PE_MODE_SHARED              2
 611
 612 /* ibm,read-slot-reset-state2 */
 613 #define RTAS_EEH_PE_STATE_NORMAL         0
 614 #define RTAS_EEH_PE_STATE_RESET          1
 615 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
 616 #define RTAS_EEH_PE_STATE_STOPPED_DMA    4
 617 #define RTAS_EEH_PE_STATE_UNAVAIL        5
 618 #define RTAS_EEH_NOT_SUPPORT             0
 619 #define RTAS_EEH_SUPPORT                 1
 620 #define RTAS_EEH_PE_UNAVAIL_INFO         1000
 621 #define RTAS_EEH_PE_RECOVER_INFO         0
 622
 623 /* ibm,set-slot-reset */
 624 #define RTAS_SLOT_RESET_DEACTIVATE       0
 625 #define RTAS_SLOT_RESET_HOT              1
 626 #define RTAS_SLOT_RESET_FUNDAMENTAL      3
 627
 628 /* ibm,slot-error-detail */
 629 #define RTAS_SLOT_TEMP_ERR_LOG           1
 630 #define RTAS_SLOT_PERM_ERR_LOG           2
 631
 632 /* RTAS return codes */
 633 #define RTAS_OUT_SUCCESS                        0
 634 #define RTAS_OUT_NO_ERRORS_FOUND                1
 635 #define RTAS_OUT_HW_ERROR                       -1
 636 #define RTAS_OUT_BUSY                           -2
 637 #define RTAS_OUT_PARAM_ERROR                    -3
 638 #define RTAS_OUT_NOT_SUPPORTED                  -3
 639 #define RTAS_OUT_NO_SUCH_INDICATOR              -3
 640 #define RTAS_OUT_NOT_AUTHORIZED                 -9002
 641 #define RTAS_OUT_SYSPARM_PARAM_ERROR            -9999
 642
 643 /* DDW pagesize mask values from ibm,query-pe-dma-window */
 644 #define RTAS_DDW_PGSIZE_4K       0x01
 645 #define RTAS_DDW_PGSIZE_64K      0x02
 646 #define RTAS_DDW_PGSIZE_16M      0x04
 647 #define RTAS_DDW_PGSIZE_32M      0x08
 648 #define RTAS_DDW_PGSIZE_64M      0x10
 649 #define RTAS_DDW_PGSIZE_128M     0x20
 650 #define RTAS_DDW_PGSIZE_256M     0x40
 651 #define RTAS_DDW_PGSIZE_16G      0x80
 652
 653 /* RTAS tokens */
 654 #define RTAS_TOKEN_BASE      0x2000
 655
 656 #define RTAS_DISPLAY_CHARACTER                  (RTAS_TOKEN_BASE + 0x00)
 657 #define RTAS_GET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x01)
 658 #define RTAS_SET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x02)
 659 #define RTAS_POWER_OFF                          (RTAS_TOKEN_BASE + 0x03)
 660 #define RTAS_SYSTEM_REBOOT                      (RTAS_TOKEN_BASE + 0x04)
 661 #define RTAS_QUERY_CPU_STOPPED_STATE            (RTAS_TOKEN_BASE + 0x05)
 662 #define RTAS_START_CPU                          (RTAS_TOKEN_BASE + 0x06)
 663 #define RTAS_STOP_SELF                          (RTAS_TOKEN_BASE + 0x07)
 664 #define RTAS_IBM_GET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x08)
 665 #define RTAS_IBM_SET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x09)
 666 #define RTAS_IBM_SET_XIVE                       (RTAS_TOKEN_BASE + 0x0A)
 667 #define RTAS_IBM_GET_XIVE                       (RTAS_TOKEN_BASE + 0x0B)
 668 #define RTAS_IBM_INT_OFF                        (RTAS_TOKEN_BASE + 0x0C)
 669 #define RTAS_IBM_INT_ON                         (RTAS_TOKEN_BASE + 0x0D)
 670 #define RTAS_CHECK_EXCEPTION                    (RTAS_TOKEN_BASE + 0x0E)
 671 #define RTAS_EVENT_SCAN                         (RTAS_TOKEN_BASE + 0x0F)
 672 #define RTAS_IBM_SET_TCE_BYPASS                 (RTAS_TOKEN_BASE + 0x10)
 673 #define RTAS_QUIESCE                            (RTAS_TOKEN_BASE + 0x11)
 674 #define RTAS_NVRAM_FETCH                        (RTAS_TOKEN_BASE + 0x12)
 675 #define RTAS_NVRAM_STORE                        (RTAS_TOKEN_BASE + 0x13)
 676 #define RTAS_READ_PCI_CONFIG                    (RTAS_TOKEN_BASE + 0x14)
 677 #define RTAS_WRITE_PCI_CONFIG                   (RTAS_TOKEN_BASE + 0x15)
 678 #define RTAS_IBM_READ_PCI_CONFIG                (RTAS_TOKEN_BASE + 0x16)
 679 #define RTAS_IBM_WRITE_PCI_CONFIG               (RTAS_TOKEN_BASE + 0x17)
 680 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER  (RTAS_TOKEN_BASE + 0x18)
 681 #define RTAS_IBM_CHANGE_MSI                     (RTAS_TOKEN_BASE + 0x19)
 682 #define RTAS_SET_INDICATOR                      (RTAS_TOKEN_BASE + 0x1A)
 683 #define RTAS_SET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1B)
 684 #define RTAS_GET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1C)
 685 #define RTAS_GET_SENSOR_STATE                   (RTAS_TOKEN_BASE + 0x1D)
 686 #define RTAS_IBM_CONFIGURE_CONNECTOR            (RTAS_TOKEN_BASE + 0x1E)
 687 #define RTAS_IBM_OS_TERM                        (RTAS_TOKEN_BASE + 0x1F)
 688 #define RTAS_IBM_SET_EEH_OPTION                 (RTAS_TOKEN_BASE + 0x20)
 689 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2          (RTAS_TOKEN_BASE + 0x21)
 690 #define RTAS_IBM_READ_SLOT_RESET_STATE2         (RTAS_TOKEN_BASE + 0x22)
 691 #define RTAS_IBM_SET_SLOT_RESET                 (RTAS_TOKEN_BASE + 0x23)
 692 #define RTAS_IBM_CONFIGURE_PE                   (RTAS_TOKEN_BASE + 0x24)
 693 #define RTAS_IBM_SLOT_ERROR_DETAIL              (RTAS_TOKEN_BASE + 0x25)
 694 #define RTAS_IBM_QUERY_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x26)
 695 #define RTAS_IBM_CREATE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x27)
 696 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x28)
 697 #define RTAS_IBM_RESET_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x29)
 698 #define RTAS_IBM_SUSPEND_ME                     (RTAS_TOKEN_BASE + 0x2A)
 699 #define RTAS_IBM_NMI_REGISTER                   (RTAS_TOKEN_BASE + 0x2B)
 700 #define RTAS_IBM_NMI_INTERLOCK                  (RTAS_TOKEN_BASE + 0x2C)
 701
 702 #define RTAS_TOKEN_MAX                          (RTAS_TOKEN_BASE + 0x2D)
 703
 704 /* RTAS ibm,get-system-parameter token values */
 705 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS      20
 706 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE        42
 707 #define RTAS_SYSPARM_UUID                        48
 708
 709 /* RTAS indicator/sensor types
 710  *
 711  * as defined by PAPR+ 2.7 7.3.5.4, Table 41
 712  *
 713  * NOTE: currently only DR-related sensors are implemented here
 714  */
 715 #define RTAS_SENSOR_TYPE_ISOLATION_STATE        9001
 716 #define RTAS_SENSOR_TYPE_DR                     9002
 717 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE       9003
 718 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
 719
 720 /* Possible values for the platform-processor-diagnostics-run-mode parameter
 721  * of the RTAS ibm,get-system-parameter call.
 722  */
 723 #define DIAGNOSTICS_RUN_MODE_DISABLED  0
 724 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
 725 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
 726 #define DIAGNOSTICS_RUN_MODE_PERIODIC  3
 727
 728 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
 729 {
 730     return addr & ~0xF000000000000000ULL;
 731 }
 732
 733 static inline uint32_t rtas_ld(target_ulong phys, int n)
 734 {
 735     return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
 736 }
 737
 738 static inline uint64_t rtas_ldq(target_ulong phys, int n)
 739 {
 740     return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
 741 }
 742
 743 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
 744 {
 745     stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
 746 }
 747
 748 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
 749                               uint32_t token,
 750                               uint32_t nargs, target_ulong args,
 751                               uint32_t nret, target_ulong rets);
 752 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
 753 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm,
 754                              uint32_t token, uint32_t nargs, target_ulong args,
 755                              uint32_t nret, target_ulong rets);
 756 void spapr_dt_rtas_tokens(void *fdt, int rtas);
 757 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr);
 758
 759 #define SPAPR_TCE_PAGE_SHIFT   12
 760 #define SPAPR_TCE_PAGE_SIZE    (1ULL << SPAPR_TCE_PAGE_SHIFT)
 761 #define SPAPR_TCE_PAGE_MASK    (SPAPR_TCE_PAGE_SIZE - 1)
 762
 763 #define SPAPR_VIO_BASE_LIOBN    0x00000000
 764 #define SPAPR_VIO_LIOBN(reg)    (0x00000000 | (reg))
 765 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
 766     (0x80000000 | ((phb_index) << 8) | (window_num))
 767 #define SPAPR_IS_PCI_LIOBN(liobn)   (!!((liobn) & 0x80000000))
 768 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
 769
 770 #define RTAS_SIZE               2048
 771 #define RTAS_ERROR_LOG_MAX      2048
 772
 773 /* Offset from rtas-base where error log is placed */
 774 #define RTAS_ERROR_LOG_OFFSET       0x30
 775
 776 #define RTAS_EVENT_SCAN_RATE    1
 777
 778 /* This helper should be used to encode interrupt specifiers when the related
 779  * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
 780  * VIO devices, RTAS event sources and PHBs).
 781  */
 782 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi)
 783 {
 784     intspec[0] = cpu_to_be32(irq);
 785     intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
 786 }
 787
 788
 789 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
 790 OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE)
 791
 792 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
 793 DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION,
 794                          TYPE_SPAPR_IOMMU_MEMORY_REGION)
 795
 796 struct SpaprTceTable {
 797     DeviceState parent;
 798     uint32_t liobn;
 799     uint32_t nb_table;
 800     uint64_t bus_offset;
 801     uint32_t page_shift;
 802     uint64_t *table;
 803     uint32_t mig_nb_table;
 804     uint64_t *mig_table;
 805     bool bypass;
 806     bool need_vfio;
 807     bool skipping_replay;
 808     int fd;
 809     MemoryRegion root;
 810     IOMMUMemoryRegion iommu;
 811     struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */
 812     QLIST_ENTRY(SpaprTceTable) list;
 813 };
 814
 815 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn);
 816
 817 struct SpaprEventLogEntry {
 818     uint32_t summary;
 819     uint32_t extended_length;
 820     void *extended_log;
 821     QTAILQ_ENTRY(SpaprEventLogEntry) next;
 822 };
 823
 824 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space);
 825 void spapr_events_init(SpaprMachineState *sm);
 826 void spapr_dt_events(SpaprMachineState *sm, void *fdt);
 827 void close_htab_fd(SpaprMachineState *spapr);
 828 void spapr_setup_hpt(SpaprMachineState *spapr);
 829 void spapr_free_hpt(SpaprMachineState *spapr);
 830 void spapr_check_mmu_mode(bool guest_radix);
 831 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
 832 void spapr_tce_table_enable(SpaprTceTable *tcet,
 833                             uint32_t page_shift, uint64_t bus_offset,
 834                             uint32_t nb_table);
 835 void spapr_tce_table_disable(SpaprTceTable *tcet);
 836 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio);
 837
 838 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet);
 839 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
 840                  uint32_t liobn, uint64_t window, uint32_t size);
 841 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
 842                       SpaprTceTable *tcet);
 843 void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian);
 844 void spapr_hotplug_req_add_by_index(SpaprDrc *drc);
 845 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc);
 846 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type,
 847                                        uint32_t count);
 848 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type,
 849                                           uint32_t count);
 850 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type,
 851                                             uint32_t count, uint32_t index);
 852 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
 853                                                uint32_t count, uint32_t index);
 854 int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
 855 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp);
 856 void spapr_clear_pending_events(SpaprMachineState *spapr);
 857 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr);
 858 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev);
 859 int spapr_max_server_number(SpaprMachineState *spapr);
 860 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
 861                       uint64_t pte0, uint64_t pte1);
 862 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered);
 863
 864 /* DRC callbacks. */
 865 void spapr_core_release(DeviceState *dev);
 866 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
 867                            void *fdt, int *fdt_start_offset, Error **errp);
 868 void spapr_lmb_release(DeviceState *dev);
 869 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
 870                           void *fdt, int *fdt_start_offset, Error **errp);
 871 void spapr_phb_release(DeviceState *dev);
 872 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
 873                           void *fdt, int *fdt_start_offset, Error **errp);
 874
 875 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns);
 876 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset);
 877
 878 #define TYPE_SPAPR_RNG "spapr-rng"
 879
 880 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */
 881
 882 /*
 883  * This defines the maximum number of DIMM slots we can have for sPAPR
 884  * guest. This is not defined by sPAPR but we are defining it to 32 slots
 885  * based on default number of slots provided by PowerPC kernel.
 886  */
 887 #define SPAPR_MAX_RAM_SLOTS     32
 888
 889 /* 1GB alignment for hotplug memory region */
 890 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB)
 891
 892 /*
 893  * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
 894  * property under ibm,dynamic-reconfiguration-memory node.
 895  */
 896 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
 897
 898 /*
 899  * Defines for flag value in ibm,dynamic-memory property under
 900  * ibm,dynamic-reconfiguration-memory node.
 901  */
 902 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
 903 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
 904 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
 905 #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100
 906
 907 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
 908
 909 #define HTAB_SIZE(spapr)        (1ULL << ((spapr)->htab_shift))
 910
 911 int spapr_get_vcpu_id(PowerPCCPU *cpu);
 912 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
 913 PowerPCCPU *spapr_find_cpu(int vcpu_id);
 914
 915 int spapr_caps_pre_load(void *opaque);
 916 int spapr_caps_pre_save(void *opaque);
 917
 918 /*
 919  * Handling of optional capabilities
 920  */
 921 extern const VMStateDescription vmstate_spapr_cap_htm;
 922 extern const VMStateDescription vmstate_spapr_cap_vsx;
 923 extern const VMStateDescription vmstate_spapr_cap_dfp;
 924 extern const VMStateDescription vmstate_spapr_cap_cfpc;
 925 extern const VMStateDescription vmstate_spapr_cap_sbbc;
 926 extern const VMStateDescription vmstate_spapr_cap_ibs;
 927 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize;
 928 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
 929 extern const VMStateDescription vmstate_spapr_cap_large_decr;
 930 extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
 931 extern const VMStateDescription vmstate_spapr_cap_fwnmi;
 932
 933 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap)
 934 {
 935     return spapr->eff.caps[cap];
 936 }
 937
 938 void spapr_caps_init(SpaprMachineState *spapr);
 939 void spapr_caps_apply(SpaprMachineState *spapr);
 940 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu);
 941 void spapr_caps_add_properties(SpaprMachineClass *smc);
 942 int spapr_caps_post_migration(SpaprMachineState *spapr);
 943
 944 bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
 945                           Error **errp);
 946 /*
 947  * XIVE definitions
 948  */
 949 #define SPAPR_OV5_XIVE_LEGACY   0x0
 950 #define SPAPR_OV5_XIVE_EXPLOIT  0x40
 951 #define SPAPR_OV5_XIVE_BOTH     0x80 /* Only to advertise on the platform */
 952
 953 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask);
 954 hwaddr spapr_get_rtas_addr(void);
 955 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr);
 956 #endif /* HW_SPAPR_H */