target-xtensa/op_helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "helper.h"
  30 #include "qemu/host-utils.h"
  31
  32 static void do_unaligned_access(CPUXtensaState *env,
  33         target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
  34
  35 #define ALIGNED_ONLY
  36 #define MMUSUFFIX _mmu
  37
  38 #define SHIFT 0
  39 #include "exec/softmmu_template.h"
  40
  41 #define SHIFT 1
  42 #include "exec/softmmu_template.h"
  43
  44 #define SHIFT 2
  45 #include "exec/softmmu_template.h"
  46
  47 #define SHIFT 3
  48 #include "exec/softmmu_template.h"
  49
  50 static void do_unaligned_access(CPUXtensaState *env,
  51         target_ulong addr, int is_write, int is_user, uintptr_t retaddr)
  52 {
  53     if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
  54             !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
  55         cpu_restore_state(env, retaddr);
  56         HELPER(exception_cause_vaddr)(env,
  57                 env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
  58     }
  59 }
  60
  61 void tlb_fill(CPUXtensaState *env,
  62         target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
  63 {
  64     uint32_t paddr;
  65     uint32_t page_size;
  66     unsigned access;
  67     int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx,
  68             &paddr, &page_size, &access);
  69
  70     qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__,
  71             vaddr, is_write, mmu_idx, paddr, ret);
  72
  73     if (ret == 0) {
  74         tlb_set_page(env,
  75                 vaddr & TARGET_PAGE_MASK,
  76                 paddr & TARGET_PAGE_MASK,
  77                 access, mmu_idx, page_size);
  78     } else {
  79         cpu_restore_state(env, retaddr);
  80         HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
  81     }
  82 }
  83
  84 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
  85 {
  86     uint32_t paddr;
  87     uint32_t page_size;
  88     unsigned access;
  89     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
  90             &paddr, &page_size, &access);
  91     if (ret == 0) {
  92         tb_invalidate_phys_addr(paddr);
  93     }
  94 }
  95
  96 void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
  97 {
  98     env->exception_index = excp;
  99     if (excp == EXCP_DEBUG) {
 100         env->exception_taken = 0;
 101     }
 102     cpu_loop_exit(env);
 103 }
 104
 105 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
 106 {
 107     uint32_t vector;
 108
 109     env->pc = pc;
 110     if (env->sregs[PS] & PS_EXCM) {
 111         if (env->config->ndepc) {
 112             env->sregs[DEPC] = pc;
 113         } else {
 114             env->sregs[EPC1] = pc;
 115         }
 116         vector = EXC_DOUBLE;
 117     } else {
 118         env->sregs[EPC1] = pc;
 119         vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 120     }
 121
 122     env->sregs[EXCCAUSE] = cause;
 123     env->sregs[PS] |= PS_EXCM;
 124
 125     HELPER(exception)(env, vector);
 126 }
 127
 128 void HELPER(exception_cause_vaddr)(CPUXtensaState *env,
 129         uint32_t pc, uint32_t cause, uint32_t vaddr)
 130 {
 131     env->sregs[EXCVADDR] = vaddr;
 132     HELPER(exception_cause)(env, pc, cause);
 133 }
 134
 135 void debug_exception_env(CPUXtensaState *env, uint32_t cause)
 136 {
 137     if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 138         HELPER(debug_exception)(env, env->pc, cause);
 139     }
 140 }
 141
 142 void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
 143 {
 144     unsigned level = env->config->debug_level;
 145
 146     env->pc = pc;
 147     env->sregs[DEBUGCAUSE] = cause;
 148     env->sregs[EPC1 + level - 1] = pc;
 149     env->sregs[EPS2 + level - 2] = env->sregs[PS];
 150     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |
 151         (level << PS_INTLEVEL_SHIFT);
 152     HELPER(exception)(env, EXC_DEBUG);
 153 }
 154
 155 uint32_t HELPER(nsa)(uint32_t v)
 156 {
 157     if (v & 0x80000000) {
 158         v = ~v;
 159     }
 160     return v ? clz32(v) - 1 : 31;
 161 }
 162
 163 uint32_t HELPER(nsau)(uint32_t v)
 164 {
 165     return v ? clz32(v) : 32;
 166 }
 167
 168 static void copy_window_from_phys(CPUXtensaState *env,
 169         uint32_t window, uint32_t phys, uint32_t n)
 170 {
 171     assert(phys < env->config->nareg);
 172     if (phys + n <= env->config->nareg) {
 173         memcpy(env->regs + window, env->phys_regs + phys,
 174                 n * sizeof(uint32_t));
 175     } else {
 176         uint32_t n1 = env->config->nareg - phys;
 177         memcpy(env->regs + window, env->phys_regs + phys,
 178                 n1 * sizeof(uint32_t));
 179         memcpy(env->regs + window + n1, env->phys_regs,
 180                 (n - n1) * sizeof(uint32_t));
 181     }
 182 }
 183
 184 static void copy_phys_from_window(CPUXtensaState *env,
 185         uint32_t phys, uint32_t window, uint32_t n)
 186 {
 187     assert(phys < env->config->nareg);
 188     if (phys + n <= env->config->nareg) {
 189         memcpy(env->phys_regs + phys, env->regs + window,
 190                 n * sizeof(uint32_t));
 191     } else {
 192         uint32_t n1 = env->config->nareg - phys;
 193         memcpy(env->phys_regs + phys, env->regs + window,
 194                 n1 * sizeof(uint32_t));
 195         memcpy(env->phys_regs, env->regs + window + n1,
 196                 (n - n1) * sizeof(uint32_t));
 197     }
 198 }
 199
 200
 201 static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env)
 202 {
 203     return a & (env->config->nareg / 4 - 1);
 204 }
 205
 206 static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env)
 207 {
 208     return 1 << windowbase_bound(a, env);
 209 }
 210
 211 void xtensa_sync_window_from_phys(CPUXtensaState *env)
 212 {
 213     copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
 214 }
 215
 216 void xtensa_sync_phys_from_window(CPUXtensaState *env)
 217 {
 218     copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
 219 }
 220
 221 static void rotate_window_abs(CPUXtensaState *env, uint32_t position)
 222 {
 223     xtensa_sync_phys_from_window(env);
 224     env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
 225     xtensa_sync_window_from_phys(env);
 226 }
 227
 228 static void rotate_window(CPUXtensaState *env, uint32_t delta)
 229 {
 230     rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta);
 231 }
 232
 233 void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
 234 {
 235     rotate_window_abs(env, v);
 236 }
 237
 238 void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
 239 {
 240     int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
 241     if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 242         qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
 243                 pc, env->sregs[PS]);
 244         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 245     } else {
 246         env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
 247         rotate_window(env, callinc);
 248         env->sregs[WINDOW_START] |=
 249             windowstart_bit(env->sregs[WINDOW_BASE], env);
 250     }
 251 }
 252
 253 void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
 254 {
 255     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 256     uint32_t windowstart = env->sregs[WINDOW_START];
 257     uint32_t m, n;
 258
 259     if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) {
 260         return;
 261     }
 262
 263     for (n = 1; ; ++n) {
 264         if (n > w) {
 265             return;
 266         }
 267         if (windowstart & windowstart_bit(windowbase + n, env)) {
 268             break;
 269         }
 270     }
 271
 272     m = windowbase_bound(windowbase + n, env);
 273     rotate_window(env, n);
 274     env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 275         (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 276     env->sregs[EPC1] = env->pc = pc;
 277
 278     if (windowstart & windowstart_bit(m + 1, env)) {
 279         HELPER(exception)(env, EXC_WINDOW_OVERFLOW4);
 280     } else if (windowstart & windowstart_bit(m + 2, env)) {
 281         HELPER(exception)(env, EXC_WINDOW_OVERFLOW8);
 282     } else {
 283         HELPER(exception)(env, EXC_WINDOW_OVERFLOW12);
 284     }
 285 }
 286
 287 uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
 288 {
 289     int n = (env->regs[0] >> 30) & 0x3;
 290     int m = 0;
 291     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 292     uint32_t windowstart = env->sregs[WINDOW_START];
 293     uint32_t ret_pc = 0;
 294
 295     if (windowstart & windowstart_bit(windowbase - 1, env)) {
 296         m = 1;
 297     } else if (windowstart & windowstart_bit(windowbase - 2, env)) {
 298         m = 2;
 299     } else if (windowstart & windowstart_bit(windowbase - 3, env)) {
 300         m = 3;
 301     }
 302
 303     if (n == 0 || (m != 0 && m != n) ||
 304             ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 305         qemu_log("Illegal retw instruction(pc = %08x), "
 306                 "PS = %08x, m = %d, n = %d\n",
 307                 pc, env->sregs[PS], m, n);
 308         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 309     } else {
 310         int owb = windowbase;
 311
 312         ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
 313
 314         rotate_window(env, -n);
 315         if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
 316             env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
 317         } else {
 318             /* window underflow */
 319             env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 320                 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 321             env->sregs[EPC1] = env->pc = pc;
 322
 323             if (n == 1) {
 324                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4);
 325             } else if (n == 2) {
 326                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8);
 327             } else if (n == 3) {
 328                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12);
 329             }
 330         }
 331     }
 332     return ret_pc;
 333 }
 334
 335 void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4)
 336 {
 337     rotate_window(env, imm4);
 338 }
 339
 340 void HELPER(restore_owb)(CPUXtensaState *env)
 341 {
 342     rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
 343 }
 344
 345 void HELPER(movsp)(CPUXtensaState *env, uint32_t pc)
 346 {
 347     if ((env->sregs[WINDOW_START] &
 348             (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
 349              windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
 350              windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
 351         HELPER(exception_cause)(env, pc, ALLOCA_CAUSE);
 352     }
 353 }
 354
 355 void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v)
 356 {
 357     if (env->sregs[LBEG] != v) {
 358         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 359         env->sregs[LBEG] = v;
 360     }
 361 }
 362
 363 void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v)
 364 {
 365     if (env->sregs[LEND] != v) {
 366         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 367         env->sregs[LEND] = v;
 368         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 369     }
 370 }
 371
 372 void HELPER(dump_state)(CPUXtensaState *env)
 373 {
 374     XtensaCPU *cpu = xtensa_env_get_cpu(env);
 375
 376     cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
 377 }
 378
 379 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
 380 {
 381     CPUState *cpu;
 382
 383     env->pc = pc;
 384     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
 385         (intlevel << PS_INTLEVEL_SHIFT);
 386     check_interrupts(env);
 387     if (env->pending_irq_level) {
 388         cpu_loop_exit(env);
 389         return;
 390     }
 391
 392     cpu = CPU(xtensa_env_get_cpu(env));
 393     env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 394     cpu->halted = 1;
 395     if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
 396         xtensa_rearm_ccompare_timer(env);
 397     }
 398     HELPER(exception)(env, EXCP_HLT);
 399 }
 400
 401 void HELPER(timer_irq)(CPUXtensaState *env, uint32_t id, uint32_t active)
 402 {
 403     xtensa_timer_irq(env, id, active);
 404 }
 405
 406 void HELPER(advance_ccount)(CPUXtensaState *env, uint32_t d)
 407 {
 408     xtensa_advance_ccount(env, d);
 409 }
 410
 411 void HELPER(check_interrupts)(CPUXtensaState *env)
 412 {
 413     check_interrupts(env);
 414 }
 415
 416 /*!
 417  * Check vaddr accessibility/cache attributes and raise an exception if
 418  * specified by the ATOMCTL SR.
 419  *
 420  * Note: local memory exclusion is not implemented
 421  */
 422 void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
 423 {
 424     uint32_t paddr, page_size, access;
 425     uint32_t atomctl = env->sregs[ATOMCTL];
 426     int rc = xtensa_get_physical_addr(env, true, vaddr, 1,
 427             xtensa_get_cring(env), &paddr, &page_size, &access);
 428
 429     /*
 430      * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
 431      * see opcode description in the ISA
 432      */
 433     if (rc == 0 &&
 434             (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) {
 435         rc = STORE_PROHIBITED_CAUSE;
 436     }
 437
 438     if (rc) {
 439         HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
 440     }
 441
 442     /*
 443      * When data cache is not configured use ATOMCTL bypass field.
 444      * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
 445      * under the Conditional Store Option.
 446      */
 447     if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
 448         access = PAGE_CACHE_BYPASS;
 449     }
 450
 451     switch (access & PAGE_CACHE_MASK) {
 452     case PAGE_CACHE_WB:
 453         atomctl >>= 2;
 454         /* fall through */
 455     case PAGE_CACHE_WT:
 456         atomctl >>= 2;
 457         /* fall through */
 458     case PAGE_CACHE_BYPASS:
 459         if ((atomctl & 0x3) == 0) {
 460             HELPER(exception_cause_vaddr)(env, pc,
 461                     LOAD_STORE_ERROR_CAUSE, vaddr);
 462         }
 463         break;
 464
 465     case PAGE_CACHE_ISOLATE:
 466         HELPER(exception_cause_vaddr)(env, pc,
 467                 LOAD_STORE_ERROR_CAUSE, vaddr);
 468         break;
 469
 470     default:
 471         break;
 472     }
 473 }
 474
 475 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
 476 {
 477     v = (v & 0xffffff00) | 0x1;
 478     if (v != env->sregs[RASID]) {
 479         env->sregs[RASID] = v;
 480         tlb_flush(env, 1);
 481     }
 482 }
 483
 484 static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way)
 485 {
 486     uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
 487
 488     switch (way) {
 489     case 4:
 490         return (tlbcfg >> 16) & 0x3;
 491
 492     case 5:
 493         return (tlbcfg >> 20) & 0x1;
 494
 495     case 6:
 496         return (tlbcfg >> 24) & 0x1;
 497
 498     default:
 499         return 0;
 500     }
 501 }
 502
 503 /*!
 504  * Get bit mask for the virtual address bits translated by the TLB way
 505  */
 506 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 507 {
 508     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 509         bool varway56 = dtlb ?
 510             env->config->dtlb.varway56 :
 511             env->config->itlb.varway56;
 512
 513         switch (way) {
 514         case 4:
 515             return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
 516
 517         case 5:
 518             if (varway56) {
 519                 return 0xf8000000 << get_page_size(env, dtlb, way);
 520             } else {
 521                 return 0xf8000000;
 522             }
 523
 524         case 6:
 525             if (varway56) {
 526                 return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
 527             } else {
 528                 return 0xf0000000;
 529             }
 530
 531         default:
 532             return 0xfffff000;
 533         }
 534     } else {
 535         return REGION_PAGE_MASK;
 536     }
 537 }
 538
 539 /*!
 540  * Get bit mask for the 'VPN without index' field.
 541  * See ISA, 4.6.5.6, data format for RxTLB0
 542  */
 543 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 544 {
 545     if (way < 4) {
 546         bool is32 = (dtlb ?
 547                 env->config->dtlb.nrefillentries :
 548                 env->config->itlb.nrefillentries) == 32;
 549         return is32 ? 0xffff8000 : 0xffffc000;
 550     } else if (way == 4) {
 551         return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
 552     } else if (way <= 6) {
 553         uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
 554         bool varway56 = dtlb ?
 555             env->config->dtlb.varway56 :
 556             env->config->itlb.varway56;
 557
 558         if (varway56) {
 559             return mask << (way == 5 ? 2 : 3);
 560         } else {
 561             return mask << 1;
 562         }
 563     } else {
 564         return 0xfffff000;
 565     }
 566 }
 567
 568 /*!
 569  * Split virtual address into VPN (with index) and entry index
 570  * for the given TLB way
 571  */
 572 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
 573         uint32_t *vpn, uint32_t wi, uint32_t *ei)
 574 {
 575     bool varway56 = dtlb ?
 576         env->config->dtlb.varway56 :
 577         env->config->itlb.varway56;
 578
 579     if (!dtlb) {
 580         wi &= 7;
 581     }
 582
 583     if (wi < 4) {
 584         bool is32 = (dtlb ?
 585                 env->config->dtlb.nrefillentries :
 586                 env->config->itlb.nrefillentries) == 32;
 587         *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
 588     } else {
 589         switch (wi) {
 590         case 4:
 591             {
 592                 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
 593                 *ei = (v >> eibase) & 0x3;
 594             }
 595             break;
 596
 597         case 5:
 598             if (varway56) {
 599                 uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
 600                 *ei = (v >> eibase) & 0x3;
 601             } else {
 602                 *ei = (v >> 27) & 0x1;
 603             }
 604             break;
 605
 606         case 6:
 607             if (varway56) {
 608                 uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
 609                 *ei = (v >> eibase) & 0x7;
 610             } else {
 611                 *ei = (v >> 28) & 0x1;
 612             }
 613             break;
 614
 615         default:
 616             *ei = 0;
 617             break;
 618         }
 619     }
 620     *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 621 }
 622
 623 /*!
 624  * Split TLB address into TLB way, entry index and VPN (with index).
 625  * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
 626  */
 627 static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
 628         uint32_t *vpn, uint32_t *wi, uint32_t *ei)
 629 {
 630     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 631         *wi = v & (dtlb ? 0xf : 0x7);
 632         split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
 633     } else {
 634         *vpn = v & REGION_PAGE_MASK;
 635         *wi = 0;
 636         *ei = (v >> 29) & 0x7;
 637     }
 638 }
 639
 640 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
 641         uint32_t v, bool dtlb, uint32_t *pwi)
 642 {
 643     uint32_t vpn;
 644     uint32_t wi;
 645     uint32_t ei;
 646
 647     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 648     if (pwi) {
 649         *pwi = wi;
 650     }
 651     return xtensa_tlb_get_entry(env, dtlb, wi, ei);
 652 }
 653
 654 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 655 {
 656     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 657         uint32_t wi;
 658         const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 659         return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
 660     } else {
 661         return v & REGION_PAGE_MASK;
 662     }
 663 }
 664
 665 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 666 {
 667     const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
 668     return entry->paddr | entry->attr;
 669 }
 670
 671 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 672 {
 673     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 674         uint32_t wi;
 675         xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 676         if (entry->variable && entry->asid) {
 677             tlb_flush_page(env, entry->vaddr);
 678             entry->asid = 0;
 679         }
 680     }
 681 }
 682
 683 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 684 {
 685     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 686         uint32_t wi;
 687         uint32_t ei;
 688         uint8_t ring;
 689         int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
 690
 691         switch (res) {
 692         case 0:
 693             if (ring >= xtensa_get_ring(env)) {
 694                 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
 695             }
 696             break;
 697
 698         case INST_TLB_MULTI_HIT_CAUSE:
 699         case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
 700             HELPER(exception_cause_vaddr)(env, env->pc, res, v);
 701             break;
 702         }
 703         return 0;
 704     } else {
 705         return (v & REGION_PAGE_MASK) | 0x1;
 706     }
 707 }
 708
 709 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
 710         xtensa_tlb_entry *entry, bool dtlb,
 711         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 712 {
 713     entry->vaddr = vpn;
 714     entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 715     entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
 716     entry->attr = pte & 0xf;
 717 }
 718
 719 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
 720         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 721 {
 722     xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
 723
 724     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 725         if (entry->variable) {
 726             if (entry->asid) {
 727                 tlb_flush_page(env, entry->vaddr);
 728             }
 729             xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
 730             tlb_flush_page(env, entry->vaddr);
 731         } else {
 732             qemu_log("%s %d, %d, %d trying to set immutable entry\n",
 733                     __func__, dtlb, wi, ei);
 734         }
 735     } else {
 736         tlb_flush_page(env, entry->vaddr);
 737         if (xtensa_option_enabled(env->config,
 738                     XTENSA_OPTION_REGION_TRANSLATION)) {
 739             entry->paddr = pte & REGION_PAGE_MASK;
 740         }
 741         entry->attr = pte & 0xf;
 742     }
 743 }
 744
 745 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
 746 {
 747     uint32_t vpn;
 748     uint32_t wi;
 749     uint32_t ei;
 750     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 751     xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
 752 }
 753
 754
 755 void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
 756 {
 757     uint32_t change = v ^ env->sregs[IBREAKENABLE];
 758     unsigned i;
 759
 760     for (i = 0; i < env->config->nibreak; ++i) {
 761         if (change & (1 << i)) {
 762             tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 763         }
 764     }
 765     env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
 766 }
 767
 768 void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 769 {
 770     if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
 771         tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 772         tb_invalidate_virtual_addr(env, v);
 773     }
 774     env->sregs[IBREAKA + i] = v;
 775 }
 776
 777 static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
 778         uint32_t dbreakc)
 779 {
 780     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
 781     uint32_t mask = dbreakc | ~DBREAKC_MASK;
 782
 783     if (env->cpu_watchpoint[i]) {
 784         cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]);
 785     }
 786     if (dbreakc & DBREAKC_SB) {
 787         flags |= BP_MEM_WRITE;
 788     }
 789     if (dbreakc & DBREAKC_LB) {
 790         flags |= BP_MEM_READ;
 791     }
 792     /* contiguous mask after inversion is one less than some power of 2 */
 793     if ((~mask + 1) & ~mask) {
 794         qemu_log("DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
 795         /* cut mask after the first zero bit */
 796         mask = 0xffffffff << (32 - clo32(mask));
 797     }
 798     if (cpu_watchpoint_insert(env, dbreaka & mask, ~mask + 1,
 799             flags, &env->cpu_watchpoint[i])) {
 800         env->cpu_watchpoint[i] = NULL;
 801         qemu_log("Failed to set data breakpoint at 0x%08x/%d\n",
 802                 dbreaka & mask, ~mask + 1);
 803     }
 804 }
 805
 806 void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 807 {
 808     uint32_t dbreakc = env->sregs[DBREAKC + i];
 809
 810     if ((dbreakc & DBREAKC_SB_LB) &&
 811             env->sregs[DBREAKA + i] != v) {
 812         set_dbreak(env, i, v, dbreakc);
 813     }
 814     env->sregs[DBREAKA + i] = v;
 815 }
 816
 817 void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
 818 {
 819     if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {
 820         if (v & DBREAKC_SB_LB) {
 821             set_dbreak(env, i, env->sregs[DBREAKA + i], v);
 822         } else {
 823             if (env->cpu_watchpoint[i]) {
 824                 cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]);
 825                 env->cpu_watchpoint[i] = NULL;
 826             }
 827         }
 828     }
 829     env->sregs[DBREAKC + i] = v;
 830 }
 831
 832 void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
 833 {
 834     static const int rounding_mode[] = {
 835         float_round_nearest_even,
 836         float_round_to_zero,
 837         float_round_up,
 838         float_round_down,
 839     };
 840
 841     env->uregs[FCR] = v & 0xfffff07f;
 842     set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);
 843 }
 844
 845 float32 HELPER(abs_s)(float32 v)
 846 {
 847     return float32_abs(v);
 848 }
 849
 850 float32 HELPER(neg_s)(float32 v)
 851 {
 852     return float32_chs(v);
 853 }
 854
 855 float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
 856 {
 857     return float32_add(a, b, &env->fp_status);
 858 }
 859
 860 float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)
 861 {
 862     return float32_sub(a, b, &env->fp_status);
 863 }
 864
 865 float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)
 866 {
 867     return float32_mul(a, b, &env->fp_status);
 868 }
 869
 870 float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 871 {
 872     return float32_muladd(b, c, a, 0,
 873             &env->fp_status);
 874 }
 875
 876 float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 877 {
 878     return float32_muladd(b, c, a, float_muladd_negate_product,
 879             &env->fp_status);
 880 }
 881
 882 uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
 883 {
 884     float_status fp_status = {0};
 885
 886     set_float_rounding_mode(rounding_mode, &fp_status);
 887     return float32_to_int32(
 888             float32_scalbn(v, scale, &fp_status), &fp_status);
 889 }
 890
 891 uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)
 892 {
 893     float_status fp_status = {0};
 894     float32 res;
 895
 896     set_float_rounding_mode(rounding_mode, &fp_status);
 897
 898     res = float32_scalbn(v, scale, &fp_status);
 899
 900     if (float32_is_neg(v) && !float32_is_any_nan(v)) {
 901         return float32_to_int32(res, &fp_status);
 902     } else {
 903         return float32_to_uint32(res, &fp_status);
 904     }
 905 }
 906
 907 float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 908 {
 909     return float32_scalbn(int32_to_float32(v, &env->fp_status),
 910             (int32_t)scale, &env->fp_status);
 911 }
 912
 913 float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 914 {
 915     return float32_scalbn(uint32_to_float32(v, &env->fp_status),
 916             (int32_t)scale, &env->fp_status);
 917 }
 918
 919 static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)
 920 {
 921     if (v) {
 922         env->sregs[BR] |= br;
 923     } else {
 924         env->sregs[BR] &= ~br;
 925     }
 926 }
 927
 928 void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 929 {
 930     set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);
 931 }
 932
 933 void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 934 {
 935     set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);
 936 }
 937
 938 void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 939 {
 940     int v = float32_compare_quiet(a, b, &env->fp_status);
 941     set_br(env, v == float_relation_equal || v == float_relation_unordered, br);
 942 }
 943
 944 void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 945 {
 946     set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);
 947 }
 948
 949 void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 950 {
 951     int v = float32_compare_quiet(a, b, &env->fp_status);
 952     set_br(env, v == float_relation_less || v == float_relation_unordered, br);
 953 }
 954
 955 void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 956 {
 957     set_br(env, float32_le_quiet(a, b, &env->fp_status), br);
 958 }
 959
 960 void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 961 {
 962     int v = float32_compare_quiet(a, b, &env->fp_status);
 963     set_br(env, v != float_relation_greater, br);
 964 }