target-ppc/mmu-hash64.c

   1 /*
   2  *  PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *  Copyright (c) 2013 David Gibson, IBM Corporation
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "exec/exec-all.h"
  24 #include "exec/helper-proto.h"
  25 #include "qemu/error-report.h"
  26 #include "sysemu/kvm.h"
  27 #include "qemu/error-report.h"
  28 #include "kvm_ppc.h"
  29 #include "mmu-hash64.h"
  30 #include "exec/log.h"
  31
  32 //#define DEBUG_SLB
  33
  34 #ifdef DEBUG_SLB
  35 #  define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
  36 #else
  37 #  define LOG_SLB(...) do { } while (0)
  38 #endif
  39
  40 /*
  41  * Used to indicate that a CPU has its hash page table (HPT) managed
  42  * within the host kernel
  43  */
  44 #define MMU_HASH64_KVM_MANAGED_HPT      ((void *)-1)
  45
  46 /*
  47  * SLB handling
  48  */
  49
  50 static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr)
  51 {
  52     CPUPPCState *env = &cpu->env;
  53     uint64_t esid_256M, esid_1T;
  54     int n;
  55
  56     LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
  57
  58     esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
  59     esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
  60
  61     for (n = 0; n < env->slb_nr; n++) {
  62         ppc_slb_t *slb = &env->slb[n];
  63
  64         LOG_SLB("%s: slot %d %016" PRIx64 " %016"
  65                     PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
  66         /* We check for 1T matches on all MMUs here - if the MMU
  67          * doesn't have 1T segment support, we will have prevented 1T
  68          * entries from being inserted in the slbmte code. */
  69         if (((slb->esid == esid_256M) &&
  70              ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
  71             || ((slb->esid == esid_1T) &&
  72                 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
  73             return slb;
  74         }
  75     }
  76
  77     return NULL;
  78 }
  79
  80 void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu)
  81 {
  82     CPUPPCState *env = &cpu->env;
  83     int i;
  84     uint64_t slbe, slbv;
  85
  86     cpu_synchronize_state(CPU(cpu));
  87
  88     cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
  89     for (i = 0; i < env->slb_nr; i++) {
  90         slbe = env->slb[i].esid;
  91         slbv = env->slb[i].vsid;
  92         if (slbe == 0 && slbv == 0) {
  93             continue;
  94         }
  95         cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
  96                     i, slbe, slbv);
  97     }
  98 }
  99
 100 void helper_slbia(CPUPPCState *env)
 101 {
 102     int n;
 103
 104     /* XXX: Warning: slbia never invalidates the first segment */
 105     for (n = 1; n < env->slb_nr; n++) {
 106         ppc_slb_t *slb = &env->slb[n];
 107
 108         if (slb->esid & SLB_ESID_V) {
 109             slb->esid &= ~SLB_ESID_V;
 110             /* XXX: given the fact that segment size is 256 MB or 1TB,
 111              *      and we still don't have a tlb_flush_mask(env, n, mask)
 112              *      in QEMU, we just invalidate all TLBs
 113              */
 114             env->tlb_need_flush = 1;
 115         }
 116     }
 117 }
 118
 119 void helper_slbie(CPUPPCState *env, target_ulong addr)
 120 {
 121     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 122     ppc_slb_t *slb;
 123
 124     slb = slb_lookup(cpu, addr);
 125     if (!slb) {
 126         return;
 127     }
 128
 129     if (slb->esid & SLB_ESID_V) {
 130         slb->esid &= ~SLB_ESID_V;
 131
 132         /* XXX: given the fact that segment size is 256 MB or 1TB,
 133          *      and we still don't have a tlb_flush_mask(env, n, mask)
 134          *      in QEMU, we just invalidate all TLBs
 135          */
 136         env->tlb_need_flush = 1;
 137     }
 138 }
 139
 140 int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
 141                   target_ulong esid, target_ulong vsid)
 142 {
 143     CPUPPCState *env = &cpu->env;
 144     ppc_slb_t *slb = &env->slb[slot];
 145     const struct ppc_one_seg_page_size *sps = NULL;
 146     int i;
 147
 148     if (slot >= env->slb_nr) {
 149         return -1; /* Bad slot number */
 150     }
 151     if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) {
 152         return -1; /* Reserved bits set */
 153     }
 154     if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
 155         return -1; /* Bad segment size */
 156     }
 157     if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
 158         return -1; /* 1T segment on MMU that doesn't support it */
 159     }
 160
 161     for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
 162         const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
 163
 164         if (!sps1->page_shift) {
 165             break;
 166         }
 167
 168         if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
 169             sps = sps1;
 170             break;
 171         }
 172     }
 173
 174     if (!sps) {
 175         error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu
 176                      " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx,
 177                      slot, esid, vsid);
 178         return -1;
 179     }
 180
 181     slb->esid = esid;
 182     slb->vsid = vsid;
 183     slb->sps = sps;
 184
 185     LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
 186             " %016" PRIx64 "\n", __func__, slot, esid, vsid,
 187             slb->esid, slb->vsid);
 188
 189     return 0;
 190 }
 191
 192 static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb,
 193                              target_ulong *rt)
 194 {
 195     CPUPPCState *env = &cpu->env;
 196     int slot = rb & 0xfff;
 197     ppc_slb_t *slb = &env->slb[slot];
 198
 199     if (slot >= env->slb_nr) {
 200         return -1;
 201     }
 202
 203     *rt = slb->esid;
 204     return 0;
 205 }
 206
 207 static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
 208                              target_ulong *rt)
 209 {
 210     CPUPPCState *env = &cpu->env;
 211     int slot = rb & 0xfff;
 212     ppc_slb_t *slb = &env->slb[slot];
 213
 214     if (slot >= env->slb_nr) {
 215         return -1;
 216     }
 217
 218     *rt = slb->vsid;
 219     return 0;
 220 }
 221
 222 static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
 223                              target_ulong *rt)
 224 {
 225     CPUPPCState *env = &cpu->env;
 226     ppc_slb_t *slb;
 227
 228     if (!msr_is_64bit(env, env->msr)) {
 229         rb &= 0xffffffff;
 230     }
 231     slb = slb_lookup(cpu, rb);
 232     if (slb == NULL) {
 233         *rt = (target_ulong)-1ul;
 234     } else {
 235         *rt = slb->vsid;
 236     }
 237     return 0;
 238 }
 239
 240 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 241 {
 242     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 243
 244     if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) {
 245         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 246                                    POWERPC_EXCP_INVAL);
 247     }
 248 }
 249
 250 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
 251 {
 252     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 253     target_ulong rt = 0;
 254
 255     if (ppc_load_slb_esid(cpu, rb, &rt) < 0) {
 256         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 257                                    POWERPC_EXCP_INVAL);
 258     }
 259     return rt;
 260 }
 261
 262 target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
 263 {
 264     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 265     target_ulong rt = 0;
 266
 267     if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) {
 268         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 269                                    POWERPC_EXCP_INVAL);
 270     }
 271     return rt;
 272 }
 273
 274 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
 275 {
 276     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 277     target_ulong rt = 0;
 278
 279     if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) {
 280         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 281                                    POWERPC_EXCP_INVAL);
 282     }
 283     return rt;
 284 }
 285
 286 /*
 287  * 64-bit hash table MMU handling
 288  */
 289 void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value,
 290                          Error **errp)
 291 {
 292     CPUPPCState *env = &cpu->env;
 293     target_ulong htabsize = value & SDR_64_HTABSIZE;
 294
 295     env->spr[SPR_SDR1] = value;
 296     if (htabsize > 28) {
 297         error_setg(errp,
 298                    "Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1",
 299                    htabsize);
 300         htabsize = 28;
 301     }
 302     env->htab_mask = (1ULL << (htabsize + 18 - 7)) - 1;
 303     env->htab_base = value & SDR_64_HTABORG;
 304 }
 305
 306 void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift,
 307                                  Error **errp)
 308 {
 309     CPUPPCState *env = &cpu->env;
 310     Error *local_err = NULL;
 311
 312     if (hpt) {
 313         env->external_htab = hpt;
 314     } else {
 315         env->external_htab = MMU_HASH64_KVM_MANAGED_HPT;
 316     }
 317     ppc_hash64_set_sdr1(cpu, (target_ulong)(uintptr_t)hpt | (shift - 18),
 318                         &local_err);
 319     if (local_err) {
 320         error_propagate(errp, local_err);
 321         return;
 322     }
 323
 324     /* Not strictly necessary, but makes it clearer that an external
 325      * htab is in use when debugging */
 326     env->htab_base = -1;
 327
 328     if (kvm_enabled()) {
 329         if (kvmppc_put_books_sregs(cpu) < 0) {
 330             error_setg(errp, "Unable to update SDR1 in KVM");
 331         }
 332     }
 333 }
 334
 335 static int ppc_hash64_pte_prot(PowerPCCPU *cpu,
 336                                ppc_slb_t *slb, ppc_hash_pte64_t pte)
 337 {
 338     CPUPPCState *env = &cpu->env;
 339     unsigned pp, key;
 340     /* Some pp bit combinations have undefined behaviour, so default
 341      * to no access in those cases */
 342     int prot = 0;
 343
 344     key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
 345              : (slb->vsid & SLB_VSID_KS));
 346     pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
 347
 348     if (key == 0) {
 349         switch (pp) {
 350         case 0x0:
 351         case 0x1:
 352         case 0x2:
 353             prot = PAGE_READ | PAGE_WRITE;
 354             break;
 355
 356         case 0x3:
 357         case 0x6:
 358             prot = PAGE_READ;
 359             break;
 360         }
 361     } else {
 362         switch (pp) {
 363         case 0x0:
 364         case 0x6:
 365             prot = 0;
 366             break;
 367
 368         case 0x1:
 369         case 0x3:
 370             prot = PAGE_READ;
 371             break;
 372
 373         case 0x2:
 374             prot = PAGE_READ | PAGE_WRITE;
 375             break;
 376         }
 377     }
 378
 379     /* No execute if either noexec or guarded bits set */
 380     if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G)
 381         || (slb->vsid & SLB_VSID_N)) {
 382         prot |= PAGE_EXEC;
 383     }
 384
 385     return prot;
 386 }
 387
 388 static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
 389 {
 390     CPUPPCState *env = &cpu->env;
 391     int key, amrbits;
 392     int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 393
 394     /* Only recent MMUs implement Virtual Page Class Key Protection */
 395     if (!(env->mmu_model & POWERPC_MMU_AMR)) {
 396         return prot;
 397     }
 398
 399     key = HPTE64_R_KEY(pte.pte1);
 400     amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3;
 401
 402     /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
 403     /*         env->spr[SPR_AMR]); */
 404
 405     /*
 406      * A store is permitted if the AMR bit is 0. Remove write
 407      * protection if it is set.
 408      */
 409     if (amrbits & 0x2) {
 410         prot &= ~PAGE_WRITE;
 411     }
 412     /*
 413      * A load is permitted if the AMR bit is 0. Remove read
 414      * protection if it is set.
 415      */
 416     if (amrbits & 0x1) {
 417         prot &= ~PAGE_READ;
 418     }
 419
 420     return prot;
 421 }
 422
 423 uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index)
 424 {
 425     uint64_t token = 0;
 426     hwaddr pte_offset;
 427
 428     pte_offset = pte_index * HASH_PTE_SIZE_64;
 429     if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
 430         /*
 431          * HTAB is controlled by KVM. Fetch the PTEG into a new buffer.
 432          */
 433         token = kvmppc_hash64_read_pteg(cpu, pte_index);
 434     } else if (cpu->env.external_htab) {
 435         /*
 436          * HTAB is controlled by QEMU. Just point to the internally
 437          * accessible PTEG.
 438          */
 439         token = (uint64_t)(uintptr_t) cpu->env.external_htab + pte_offset;
 440     } else if (cpu->env.htab_base) {
 441         token = cpu->env.htab_base + pte_offset;
 442     }
 443     return token;
 444 }
 445
 446 void ppc_hash64_stop_access(PowerPCCPU *cpu, uint64_t token)
 447 {
 448     if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
 449         kvmppc_hash64_free_pteg(token);
 450     }
 451 }
 452
 453 static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
 454     uint64_t pte0, uint64_t pte1)
 455 {
 456     int i;
 457
 458     if (!(pte0 & HPTE64_V_LARGE)) {
 459         if (sps->page_shift != 12) {
 460             /* 4kiB page in a non 4kiB segment */
 461             return 0;
 462         }
 463         /* Normal 4kiB page */
 464         return 12;
 465     }
 466
 467     for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
 468         const struct ppc_one_page_size *ps = &sps->enc[i];
 469         uint64_t mask;
 470
 471         if (!ps->page_shift) {
 472             break;
 473         }
 474
 475         if (ps->page_shift == 12) {
 476             /* L bit is set so this can't be a 4kiB page */
 477             continue;
 478         }
 479
 480         mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
 481
 482         if ((pte1 & mask) == (ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
 483             return ps->page_shift;
 484         }
 485     }
 486
 487     return 0; /* Bad page size encoding */
 488 }
 489
 490 static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
 491                                      const struct ppc_one_seg_page_size *sps,
 492                                      target_ulong ptem,
 493                                      ppc_hash_pte64_t *pte, unsigned *pshift)
 494 {
 495     CPUPPCState *env = &cpu->env;
 496     int i;
 497     uint64_t token;
 498     target_ulong pte0, pte1;
 499     target_ulong pte_index;
 500
 501     pte_index = (hash & env->htab_mask) * HPTES_PER_GROUP;
 502     token = ppc_hash64_start_access(cpu, pte_index);
 503     if (!token) {
 504         return -1;
 505     }
 506     for (i = 0; i < HPTES_PER_GROUP; i++) {
 507         pte0 = ppc_hash64_load_hpte0(cpu, token, i);
 508         pte1 = ppc_hash64_load_hpte1(cpu, token, i);
 509
 510         /* This compares V, B, H (secondary) and the AVPN */
 511         if (HPTE64_V_COMPARE(pte0, ptem)) {
 512             *pshift = hpte_page_shift(sps, pte0, pte1);
 513             /*
 514              * If there is no match, ignore the PTE, it could simply
 515              * be for a different segment size encoding and the
 516              * architecture specifies we should not match. Linux will
 517              * potentially leave behind PTEs for the wrong base page
 518              * size when demoting segments.
 519              */
 520             if (*pshift == 0) {
 521                 continue;
 522             }
 523             /* We don't do anything with pshift yet as qemu TLB only deals
 524              * with 4K pages anyway
 525              */
 526             pte->pte0 = pte0;
 527             pte->pte1 = pte1;
 528             ppc_hash64_stop_access(cpu, token);
 529             return (pte_index + i) * HASH_PTE_SIZE_64;
 530         }
 531     }
 532     ppc_hash64_stop_access(cpu, token);
 533     /*
 534      * We didn't find a valid entry.
 535      */
 536     return -1;
 537 }
 538
 539 static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
 540                                      ppc_slb_t *slb, target_ulong eaddr,
 541                                      ppc_hash_pte64_t *pte, unsigned *pshift)
 542 {
 543     CPUPPCState *env = &cpu->env;
 544     hwaddr pte_offset;
 545     hwaddr hash;
 546     uint64_t vsid, epnmask, epn, ptem;
 547     const struct ppc_one_seg_page_size *sps = slb->sps;
 548
 549     /* The SLB store path should prevent any bad page size encodings
 550      * getting in there, so: */
 551     assert(sps);
 552
 553     /* If ISL is set in LPCR we need to clamp the page size to 4K */
 554     if (env->spr[SPR_LPCR] & LPCR_ISL) {
 555         /* We assume that when using TCG, 4k is first entry of SPS */
 556         sps = &env->sps.sps[0];
 557         assert(sps->page_shift == 12);
 558     }
 559
 560     epnmask = ~((1ULL << sps->page_shift) - 1);
 561
 562     if (slb->vsid & SLB_VSID_B) {
 563         /* 1TB segment */
 564         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
 565         epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
 566         hash = vsid ^ (vsid << 25) ^ (epn >> sps->page_shift);
 567     } else {
 568         /* 256M segment */
 569         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
 570         epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
 571         hash = vsid ^ (epn >> sps->page_shift);
 572     }
 573     ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
 574     ptem |= HPTE64_V_VALID;
 575
 576     /* Page address translation */
 577     qemu_log_mask(CPU_LOG_MMU,
 578             "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
 579             " hash " TARGET_FMT_plx "\n",
 580             env->htab_base, env->htab_mask, hash);
 581
 582     /* Primary PTEG lookup */
 583     qemu_log_mask(CPU_LOG_MMU,
 584             "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 585             " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
 586             " hash=" TARGET_FMT_plx "\n",
 587             env->htab_base, env->htab_mask, vsid, ptem,  hash);
 588     pte_offset = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift);
 589
 590     if (pte_offset == -1) {
 591         /* Secondary PTEG lookup */
 592         ptem |= HPTE64_V_SECONDARY;
 593         qemu_log_mask(CPU_LOG_MMU,
 594                 "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 595                 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
 596                 " hash=" TARGET_FMT_plx "\n", env->htab_base,
 597                 env->htab_mask, vsid, ptem, ~hash);
 598
 599         pte_offset = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift);
 600     }
 601
 602     return pte_offset;
 603 }
 604
 605 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
 606                                           uint64_t pte0, uint64_t pte1)
 607 {
 608     CPUPPCState *env = &cpu->env;
 609     int i;
 610
 611     if (!(pte0 & HPTE64_V_LARGE)) {
 612         return 12;
 613     }
 614
 615     /*
 616      * The encodings in env->sps need to be carefully chosen so that
 617      * this gives an unambiguous result.
 618      */
 619     for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
 620         const struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
 621         unsigned shift;
 622
 623         if (!sps->page_shift) {
 624             break;
 625         }
 626
 627         shift = hpte_page_shift(sps, pte0, pte1);
 628         if (shift) {
 629             return shift;
 630         }
 631     }
 632
 633     return 0;
 634 }
 635
 636 static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
 637                                uint64_t error_code)
 638 {
 639     bool vpm;
 640
 641     if (msr_ir) {
 642         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
 643     } else {
 644         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
 645     }
 646     if (vpm && !msr_hv) {
 647         cs->exception_index = POWERPC_EXCP_HISI;
 648     } else {
 649         cs->exception_index = POWERPC_EXCP_ISI;
 650     }
 651     env->error_code = error_code;
 652 }
 653
 654 static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t dar,
 655                                uint64_t dsisr)
 656 {
 657     bool vpm;
 658
 659     if (msr_dr) {
 660         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
 661     } else {
 662         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
 663     }
 664     if (vpm && !msr_hv) {
 665         cs->exception_index = POWERPC_EXCP_HDSI;
 666         env->spr[SPR_HDAR] = dar;
 667         env->spr[SPR_HDSISR] = dsisr;
 668     } else {
 669         cs->exception_index = POWERPC_EXCP_DSI;
 670         env->spr[SPR_DAR] = dar;
 671         env->spr[SPR_DSISR] = dsisr;
 672    }
 673     env->error_code = 0;
 674 }
 675
 676
 677 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
 678                                 int rwx, int mmu_idx)
 679 {
 680     CPUState *cs = CPU(cpu);
 681     CPUPPCState *env = &cpu->env;
 682     ppc_slb_t *slb;
 683     unsigned apshift;
 684     hwaddr pte_offset;
 685     ppc_hash_pte64_t pte;
 686     int pp_prot, amr_prot, prot;
 687     uint64_t new_pte1, dsisr;
 688     const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
 689     hwaddr raddr;
 690
 691     assert((rwx == 0) || (rwx == 1) || (rwx == 2));
 692
 693     /* Note on LPCR usage: 970 uses HID4, but our special variant
 694      * of store_spr copies relevant fields into env->spr[SPR_LPCR].
 695      * Similarily we filter unimplemented bits when storing into
 696      * LPCR depending on the MMU version. This code can thus just
 697      * use the LPCR "as-is".
 698      */
 699
 700     /* 1. Handle real mode accesses */
 701     if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
 702         /* Translation is supposedly "off"  */
 703         /* In real mode the top 4 effective address bits are (mostly) ignored */
 704         raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
 705
 706         /* In HV mode, add HRMOR if top EA bit is clear */
 707         if (msr_hv || !env->has_hv_mode) {
 708             if (!(eaddr >> 63)) {
 709                 raddr |= env->spr[SPR_HRMOR];
 710             }
 711         } else {
 712             /* Otherwise, check VPM for RMA vs VRMA */
 713             if (env->spr[SPR_LPCR] & LPCR_VPM0) {
 714                 slb = &env->vrma_slb;
 715                 if (slb->sps) {
 716                     goto skip_slb_search;
 717                 }
 718                 /* Not much else to do here */
 719                 cs->exception_index = POWERPC_EXCP_MCHECK;
 720                 env->error_code = 0;
 721                 return 1;
 722             } else if (raddr < env->rmls) {
 723                 /* RMA. Check bounds in RMLS */
 724                 raddr |= env->spr[SPR_RMOR];
 725             } else {
 726                 /* The access failed, generate the approriate interrupt */
 727                 if (rwx == 2) {
 728                     ppc_hash64_set_isi(cs, env, 0x08000000);
 729                 } else {
 730                     dsisr = 0x08000000;
 731                     if (rwx == 1) {
 732                         dsisr |= 0x02000000;
 733                     }
 734                     ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
 735                 }
 736                 return 1;
 737             }
 738         }
 739         tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 740                      PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
 741                      TARGET_PAGE_SIZE);
 742         return 0;
 743     }
 744
 745     /* 2. Translation is on, so look up the SLB */
 746     slb = slb_lookup(cpu, eaddr);
 747     if (!slb) {
 748         if (rwx == 2) {
 749             cs->exception_index = POWERPC_EXCP_ISEG;
 750             env->error_code = 0;
 751         } else {
 752             cs->exception_index = POWERPC_EXCP_DSEG;
 753             env->error_code = 0;
 754             env->spr[SPR_DAR] = eaddr;
 755         }
 756         return 1;
 757     }
 758
 759 skip_slb_search:
 760
 761     /* 3. Check for segment level no-execute violation */
 762     if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
 763         ppc_hash64_set_isi(cs, env, 0x10000000);
 764         return 1;
 765     }
 766
 767     /* 4. Locate the PTE in the hash table */
 768     pte_offset = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
 769     if (pte_offset == -1) {
 770         dsisr = 0x40000000;
 771         if (rwx == 2) {
 772             ppc_hash64_set_isi(cs, env, dsisr);
 773         } else {
 774             if (rwx == 1) {
 775                 dsisr |= 0x02000000;
 776             }
 777             ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
 778         }
 779         return 1;
 780     }
 781     qemu_log_mask(CPU_LOG_MMU,
 782                 "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
 783
 784     /* 5. Check access permissions */
 785
 786     pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
 787     amr_prot = ppc_hash64_amr_prot(cpu, pte);
 788     prot = pp_prot & amr_prot;
 789
 790     if ((need_prot[rwx] & ~prot) != 0) {
 791         /* Access right violation */
 792         qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
 793         if (rwx == 2) {
 794             ppc_hash64_set_isi(cs, env, 0x08000000);
 795         } else {
 796             dsisr = 0;
 797             if (need_prot[rwx] & ~pp_prot) {
 798                 dsisr |= 0x08000000;
 799             }
 800             if (rwx == 1) {
 801                 dsisr |= 0x02000000;
 802             }
 803             if (need_prot[rwx] & ~amr_prot) {
 804                 dsisr |= 0x00200000;
 805             }
 806             ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
 807         }
 808         return 1;
 809     }
 810
 811     qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
 812
 813     /* 6. Update PTE referenced and changed bits if necessary */
 814
 815     new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */
 816     if (rwx == 1) {
 817         new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */
 818     } else {
 819         /* Treat the page as read-only for now, so that a later write
 820          * will pass through this function again to set the C bit */
 821         prot &= ~PAGE_WRITE;
 822     }
 823
 824     if (new_pte1 != pte.pte1) {
 825         ppc_hash64_store_hpte(cpu, pte_offset / HASH_PTE_SIZE_64,
 826                               pte.pte0, new_pte1);
 827     }
 828
 829     /* 7. Determine the real address from the PTE */
 830
 831     raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
 832
 833     tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 834                  prot, mmu_idx, 1ULL << apshift);
 835
 836     return 0;
 837 }
 838
 839 hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
 840 {
 841     CPUPPCState *env = &cpu->env;
 842     ppc_slb_t *slb;
 843     hwaddr pte_offset, raddr;
 844     ppc_hash_pte64_t pte;
 845     unsigned apshift;
 846
 847     /* Handle real mode */
 848     if (msr_dr == 0) {
 849         /* In real mode the top 4 effective address bits are ignored */
 850         raddr = addr & 0x0FFFFFFFFFFFFFFFULL;
 851
 852         /* In HV mode, add HRMOR if top EA bit is clear */
 853         if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) {
 854             return raddr | env->spr[SPR_HRMOR];
 855         }
 856
 857         /* Otherwise, check VPM for RMA vs VRMA */
 858         if (env->spr[SPR_LPCR] & LPCR_VPM0) {
 859             slb = &env->vrma_slb;
 860             if (!slb->sps) {
 861                 return -1;
 862             }
 863         } else if (raddr < env->rmls) {
 864             /* RMA. Check bounds in RMLS */
 865             return raddr | env->spr[SPR_RMOR];
 866         } else {
 867             return -1;
 868         }
 869     } else {
 870         slb = slb_lookup(cpu, addr);
 871         if (!slb) {
 872             return -1;
 873         }
 874     }
 875
 876     pte_offset = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift);
 877     if (pte_offset == -1) {
 878         return -1;
 879     }
 880
 881     return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
 882         & TARGET_PAGE_MASK;
 883 }
 884
 885 void ppc_hash64_store_hpte(PowerPCCPU *cpu,
 886                            target_ulong pte_index,
 887                            target_ulong pte0, target_ulong pte1)
 888 {
 889     CPUPPCState *env = &cpu->env;
 890
 891     if (env->external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
 892         kvmppc_hash64_write_pte(env, pte_index, pte0, pte1);
 893         return;
 894     }
 895
 896     pte_index *= HASH_PTE_SIZE_64;
 897     if (env->external_htab) {
 898         stq_p(env->external_htab + pte_index, pte0);
 899         stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
 900     } else {
 901         stq_phys(CPU(cpu)->as, env->htab_base + pte_index, pte0);
 902         stq_phys(CPU(cpu)->as,
 903                  env->htab_base + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
 904     }
 905 }
 906
 907 void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
 908                                target_ulong pte_index,
 909                                target_ulong pte0, target_ulong pte1)
 910 {
 911     /*
 912      * XXX: given the fact that there are too many segments to
 913      * invalidate, and we still don't have a tlb_flush_mask(env, n,
 914      * mask) in QEMU, we just invalidate all TLBs
 915      */
 916     tlb_flush(CPU(cpu), 1);
 917 }
 918
 919 void ppc_hash64_update_rmls(CPUPPCState *env)
 920 {
 921     uint64_t lpcr = env->spr[SPR_LPCR];
 922
 923     /*
 924      * This is the full 4 bits encoding of POWER8. Previous
 925      * CPUs only support a subset of these but the filtering
 926      * is done when writing LPCR
 927      */
 928     switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) {
 929     case 0x8: /* 32MB */
 930         env->rmls = 0x2000000ull;
 931         break;
 932     case 0x3: /* 64MB */
 933         env->rmls = 0x4000000ull;
 934         break;
 935     case 0x7: /* 128MB */
 936         env->rmls = 0x8000000ull;
 937         break;
 938     case 0x4: /* 256MB */
 939         env->rmls = 0x10000000ull;
 940         break;
 941     case 0x2: /* 1GB */
 942         env->rmls = 0x40000000ull;
 943         break;
 944     case 0x1: /* 16GB */
 945         env->rmls = 0x400000000ull;
 946         break;
 947     default:
 948         /* What to do here ??? */
 949         env->rmls = 0;
 950     }
 951 }
 952
 953 void ppc_hash64_update_vrma(CPUPPCState *env)
 954 {
 955     const struct ppc_one_seg_page_size *sps = NULL;
 956     target_ulong esid, vsid, lpcr;
 957     ppc_slb_t *slb = &env->vrma_slb;
 958     uint32_t vrmasd;
 959     int i;
 960
 961     /* First clear it */
 962     slb->esid = slb->vsid = 0;
 963     slb->sps = NULL;
 964
 965     /* Is VRMA enabled ? */
 966     lpcr = env->spr[SPR_LPCR];
 967     if (!(lpcr & LPCR_VPM0)) {
 968         return;
 969     }
 970
 971     /* Make one up. Mostly ignore the ESID which will not be
 972      * needed for translation
 973      */
 974     vsid = SLB_VSID_VRMA;
 975     vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
 976     vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP);
 977     esid = SLB_ESID_V;
 978
 979    for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
 980         const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
 981
 982         if (!sps1->page_shift) {
 983             break;
 984         }
 985
 986         if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
 987             sps = sps1;
 988             break;
 989         }
 990     }
 991
 992     if (!sps) {
 993         error_report("Bad page size encoding esid 0x"TARGET_FMT_lx
 994                      " vsid 0x"TARGET_FMT_lx, esid, vsid);
 995         return;
 996     }
 997
 998     slb->vsid = vsid;
 999     slb->esid = esid;
1000     slb->sps = sps;
1001 }
1002
1003 void helper_store_lpcr(CPUPPCState *env, target_ulong val)
1004 {
1005     uint64_t lpcr = 0;
1006
1007     /* Filter out bits */
1008     switch (env->mmu_model) {
1009     case POWERPC_MMU_64B: /* 970 */
1010         if (val & 0x40) {
1011             lpcr |= LPCR_LPES0;
1012         }
1013         if (val & 0x8000000000000000ull) {
1014             lpcr |= LPCR_LPES1;
1015         }
1016         if (val & 0x20) {
1017             lpcr |= (0x4ull << LPCR_RMLS_SHIFT);
1018         }
1019         if (val & 0x4000000000000000ull) {
1020             lpcr |= (0x2ull << LPCR_RMLS_SHIFT);
1021         }
1022         if (val & 0x2000000000000000ull) {
1023             lpcr |= (0x1ull << LPCR_RMLS_SHIFT);
1024         }
1025         env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26;
1026
1027         /* XXX We could also write LPID from HID4 here
1028          * but since we don't tag any translation on it
1029          * it doesn't actually matter
1030          */
1031         /* XXX For proper emulation of 970 we also need
1032          * to dig HRMOR out of HID5
1033          */
1034         break;
1035     case POWERPC_MMU_2_03: /* P5p */
1036         lpcr = val & (LPCR_RMLS | LPCR_ILE |
1037                       LPCR_LPES0 | LPCR_LPES1 |
1038                       LPCR_RMI | LPCR_HDICE);
1039         break;
1040     case POWERPC_MMU_2_06: /* P7 */
1041         lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
1042                       LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
1043                       LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
1044                       LPCR_MER | LPCR_TC |
1045                       LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
1046         break;
1047     case POWERPC_MMU_2_07: /* P8 */
1048         lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
1049                       LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
1050                       LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
1051                       LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
1052                       LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
1053         break;
1054     default:
1055         ;
1056     }
1057     env->spr[SPR_LPCR] = lpcr;
1058     ppc_hash64_update_rmls(env);
1059     ppc_hash64_update_vrma(env);
1060 }