2 * ARM implementation of KVM hooks, 32 bit specific code.
4 * Copyright Christoffer Dall 2009-2010
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
11 #include "qemu/osdep.h"
12 #include <sys/ioctl.h>
14 #include <linux/kvm.h>
16 #include "qemu-common.h"
18 #include "qemu/timer.h"
19 #include "sysemu/sysemu.h"
20 #include "sysemu/kvm.h"
22 #include "internals.h"
23 #include "hw/arm/arm.h"
26 static inline void set_feature(uint64_t *features
, int feature
)
28 *features
|= 1ULL << feature
;
31 static int read_sys_reg32(int fd
, uint32_t *pret
, uint64_t id
)
33 struct kvm_one_reg idreg
= { .id
= id
, .addr
= (uintptr_t)pret
};
35 assert((id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U32
);
36 return ioctl(fd
, KVM_GET_ONE_REG
, &idreg
);
39 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures
*ahcf
)
41 /* Identify the feature bits corresponding to the host CPU, and
42 * fill out the ARMHostCPUClass fields accordingly. To do this
43 * we have to create a scratch VM, create a single CPU inside it,
44 * and then query that CPU for the relevant ID registers.
46 int err
= 0, fdarray
[3];
47 uint32_t midr
, id_pfr0
;
48 uint64_t features
= 0;
50 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
51 * we know these will only support creating one kind of guest CPU,
52 * which is its preferred CPU type.
54 static const uint32_t cpus_to_try
[] = {
55 QEMU_KVM_ARM_TARGET_CORTEX_A15
,
56 QEMU_KVM_ARM_TARGET_NONE
58 struct kvm_vcpu_init init
;
60 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try
, fdarray
, &init
)) {
64 ahcf
->target
= init
.target
;
66 /* This is not strictly blessed by the device tree binding docs yet,
67 * but in practice the kernel does not care about this string so
68 * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
70 ahcf
->dtb_compatible
= "arm,arm-v7";
72 err
|= read_sys_reg32(fdarray
[2], &midr
, ARM_CP15_REG32(0, 0, 0, 0));
73 err
|= read_sys_reg32(fdarray
[2], &id_pfr0
, ARM_CP15_REG32(0, 0, 1, 0));
75 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar0
,
76 ARM_CP15_REG32(0, 0, 2, 0));
77 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar1
,
78 ARM_CP15_REG32(0, 0, 2, 1));
79 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar2
,
80 ARM_CP15_REG32(0, 0, 2, 2));
81 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar3
,
82 ARM_CP15_REG32(0, 0, 2, 3));
83 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar4
,
84 ARM_CP15_REG32(0, 0, 2, 4));
85 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar5
,
86 ARM_CP15_REG32(0, 0, 2, 5));
87 if (read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar6
,
88 ARM_CP15_REG32(0, 0, 2, 7))) {
90 * Older kernels don't support reading ID_ISAR6. This register was
91 * only introduced in ARMv8, so we can assume that it is zero on a
92 * CPU that a kernel this old is running on.
94 ahcf
->isar
.id_isar6
= 0;
97 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.mvfr0
,
98 KVM_REG_ARM
| KVM_REG_SIZE_U32
|
99 KVM_REG_ARM_VFP
| KVM_REG_ARM_VFP_MVFR0
);
100 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.mvfr1
,
101 KVM_REG_ARM
| KVM_REG_SIZE_U32
|
102 KVM_REG_ARM_VFP
| KVM_REG_ARM_VFP_MVFR1
);
104 * FIXME: There is not yet a way to read MVFR2.
105 * Fortunately there is not yet anything in there that affects migration.
108 kvm_arm_destroy_scratch_host_vcpu(fdarray
);
114 /* Now we've retrieved all the register information we can
115 * set the feature bits based on the ID register fields.
116 * We can assume any KVM supporting CPU is at least a v7
117 * with VFPv3, virtualization extensions, and the generic
118 * timers; this in turn implies most of the other feature
119 * bits, but a few must be tested.
121 set_feature(&features
, ARM_FEATURE_V7VE
);
122 set_feature(&features
, ARM_FEATURE_VFP3
);
123 set_feature(&features
, ARM_FEATURE_GENERIC_TIMER
);
125 if (extract32(id_pfr0
, 12, 4) == 1) {
126 set_feature(&features
, ARM_FEATURE_THUMB2EE
);
128 if (extract32(ahcf
->isar
.mvfr1
, 12, 4) == 1) {
129 set_feature(&features
, ARM_FEATURE_NEON
);
131 if (extract32(ahcf
->isar
.mvfr1
, 28, 4) == 1) {
132 /* FMAC support implies VFPv4 */
133 set_feature(&features
, ARM_FEATURE_VFP4
);
136 ahcf
->features
= features
;
141 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx
)
143 /* Return true if the regidx is a register we should synchronize
144 * via the cpreg_tuples array (ie is not a core reg we sync by
145 * hand in kvm_arch_get/put_registers())
147 switch (regidx
& KVM_REG_ARM_COPROC_MASK
) {
148 case KVM_REG_ARM_CORE
:
149 case KVM_REG_ARM_VFP
:
156 typedef struct CPRegStateLevel
{
161 /* All coprocessor registers not listed in the following table are assumed to
162 * be of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
163 * often, you must add it to this table with a state of either
164 * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
166 static const CPRegStateLevel non_runtime_cpregs
[] = {
167 { KVM_REG_ARM_TIMER_CNT
, KVM_PUT_FULL_STATE
},
170 int kvm_arm_cpreg_level(uint64_t regidx
)
174 for (i
= 0; i
< ARRAY_SIZE(non_runtime_cpregs
); i
++) {
175 const CPRegStateLevel
*l
= &non_runtime_cpregs
[i
];
176 if (l
->regidx
== regidx
) {
181 return KVM_PUT_RUNTIME_STATE
;
184 #define ARM_CPU_ID_MPIDR 0, 0, 0, 5
186 int kvm_arch_init_vcpu(CPUState
*cs
)
191 struct kvm_one_reg r
;
192 ARMCPU
*cpu
= ARM_CPU(cs
);
194 if (cpu
->kvm_target
== QEMU_KVM_ARM_TARGET_NONE
) {
195 fprintf(stderr
, "KVM is not supported for this guest CPU type\n");
199 /* Determine init features for this CPU */
200 memset(cpu
->kvm_init_features
, 0, sizeof(cpu
->kvm_init_features
));
201 if (cpu
->start_powered_off
) {
202 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_POWER_OFF
;
204 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_ARM_PSCI_0_2
)) {
205 cpu
->psci_version
= 2;
206 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2
;
209 /* Do KVM_ARM_VCPU_INIT ioctl */
210 ret
= kvm_arm_vcpu_init(cs
);
215 /* Query the kernel to make sure it supports 32 VFP
216 * registers: QEMU's "cortex-a15" CPU is always a
217 * VFP-D32 core. The simplest way to do this is just
218 * to attempt to read register d31.
220 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U64
| KVM_REG_ARM_VFP
| 31;
221 r
.addr
= (uintptr_t)(&v
);
222 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &r
);
223 if (ret
== -ENOENT
) {
228 * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
229 * Currently KVM has its own idea about MPIDR assignment, so we
230 * override our defaults with what we get from KVM.
232 ret
= kvm_get_one_reg(cs
, ARM_CP15_REG32(ARM_CPU_ID_MPIDR
), &mpidr
);
236 cpu
->mp_affinity
= mpidr
& ARM32_AFFINITY_MASK
;
238 /* Check whether userspace can specify guest syndrome value */
239 kvm_arm_init_serror_injection(cs
);
241 return kvm_arm_init_cpreg_list(cpu
);
249 #define COREREG(KERNELNAME, QEMUFIELD) \
251 KVM_REG_ARM | KVM_REG_SIZE_U32 | \
252 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
253 offsetof(CPUARMState, QEMUFIELD) \
256 #define VFPSYSREG(R) \
258 KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
259 KVM_REG_ARM_VFP_##R, \
260 offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R]) \
263 /* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
264 #define COREREG64(KERNELNAME, QEMUFIELD) \
266 KVM_REG_ARM | KVM_REG_SIZE_U32 | \
267 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
268 offsetoflow32(CPUARMState, QEMUFIELD) \
271 static const Reg regs
[] = {
272 /* R0_usr .. R14_usr */
273 COREREG(usr_regs
.uregs
[0], regs
[0]),
274 COREREG(usr_regs
.uregs
[1], regs
[1]),
275 COREREG(usr_regs
.uregs
[2], regs
[2]),
276 COREREG(usr_regs
.uregs
[3], regs
[3]),
277 COREREG(usr_regs
.uregs
[4], regs
[4]),
278 COREREG(usr_regs
.uregs
[5], regs
[5]),
279 COREREG(usr_regs
.uregs
[6], regs
[6]),
280 COREREG(usr_regs
.uregs
[7], regs
[7]),
281 COREREG(usr_regs
.uregs
[8], usr_regs
[0]),
282 COREREG(usr_regs
.uregs
[9], usr_regs
[1]),
283 COREREG(usr_regs
.uregs
[10], usr_regs
[2]),
284 COREREG(usr_regs
.uregs
[11], usr_regs
[3]),
285 COREREG(usr_regs
.uregs
[12], usr_regs
[4]),
286 COREREG(usr_regs
.uregs
[13], banked_r13
[BANK_USRSYS
]),
287 COREREG(usr_regs
.uregs
[14], banked_r14
[BANK_USRSYS
]),
288 /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
289 COREREG(svc_regs
[0], banked_r13
[BANK_SVC
]),
290 COREREG(svc_regs
[1], banked_r14
[BANK_SVC
]),
291 COREREG64(svc_regs
[2], banked_spsr
[BANK_SVC
]),
292 COREREG(abt_regs
[0], banked_r13
[BANK_ABT
]),
293 COREREG(abt_regs
[1], banked_r14
[BANK_ABT
]),
294 COREREG64(abt_regs
[2], banked_spsr
[BANK_ABT
]),
295 COREREG(und_regs
[0], banked_r13
[BANK_UND
]),
296 COREREG(und_regs
[1], banked_r14
[BANK_UND
]),
297 COREREG64(und_regs
[2], banked_spsr
[BANK_UND
]),
298 COREREG(irq_regs
[0], banked_r13
[BANK_IRQ
]),
299 COREREG(irq_regs
[1], banked_r14
[BANK_IRQ
]),
300 COREREG64(irq_regs
[2], banked_spsr
[BANK_IRQ
]),
301 /* R8_fiq .. R14_fiq and SPSR_fiq */
302 COREREG(fiq_regs
[0], fiq_regs
[0]),
303 COREREG(fiq_regs
[1], fiq_regs
[1]),
304 COREREG(fiq_regs
[2], fiq_regs
[2]),
305 COREREG(fiq_regs
[3], fiq_regs
[3]),
306 COREREG(fiq_regs
[4], fiq_regs
[4]),
307 COREREG(fiq_regs
[5], banked_r13
[BANK_FIQ
]),
308 COREREG(fiq_regs
[6], banked_r14
[BANK_FIQ
]),
309 COREREG64(fiq_regs
[7], banked_spsr
[BANK_FIQ
]),
311 COREREG(usr_regs
.uregs
[15], regs
[15]),
312 /* VFP system registers */
321 int kvm_arch_put_registers(CPUState
*cs
, int level
)
323 ARMCPU
*cpu
= ARM_CPU(cs
);
324 CPUARMState
*env
= &cpu
->env
;
325 struct kvm_one_reg r
;
328 uint32_t cpsr
, fpscr
;
330 /* Make sure the banked regs are properly set */
331 mode
= env
->uncached_cpsr
& CPSR_M
;
332 bn
= bank_number(mode
);
333 if (mode
== ARM_CPU_MODE_FIQ
) {
334 memcpy(env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
336 memcpy(env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
338 env
->banked_r13
[bn
] = env
->regs
[13];
339 env
->banked_spsr
[bn
] = env
->spsr
;
340 env
->banked_r14
[r14_bank_number(mode
)] = env
->regs
[14];
342 /* Now we can safely copy stuff down to the kernel */
343 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
345 r
.addr
= (uintptr_t)(env
) + regs
[i
].offset
;
346 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &r
);
352 /* Special cases which aren't a single CPUARMState field */
353 cpsr
= cpsr_read(env
);
354 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U32
|
355 KVM_REG_ARM_CORE
| KVM_REG_ARM_CORE_REG(usr_regs
.ARM_cpsr
);
356 r
.addr
= (uintptr_t)(&cpsr
);
357 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &r
);
363 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U64
| KVM_REG_ARM_VFP
;
364 for (i
= 0; i
< 32; i
++) {
365 r
.addr
= (uintptr_t)aa32_vfp_dreg(env
, i
);
366 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &r
);
373 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U32
| KVM_REG_ARM_VFP
|
374 KVM_REG_ARM_VFP_FPSCR
;
375 fpscr
= vfp_get_fpscr(env
);
376 r
.addr
= (uintptr_t)&fpscr
;
377 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &r
);
382 ret
= kvm_put_vcpu_events(cpu
);
387 write_cpustate_to_list(cpu
, true);
389 if (!write_list_to_kvmstate(cpu
, level
)) {
393 kvm_arm_sync_mpstate_to_kvm(cpu
);
398 int kvm_arch_get_registers(CPUState
*cs
)
400 ARMCPU
*cpu
= ARM_CPU(cs
);
401 CPUARMState
*env
= &cpu
->env
;
402 struct kvm_one_reg r
;
405 uint32_t cpsr
, fpscr
;
407 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
409 r
.addr
= (uintptr_t)(env
) + regs
[i
].offset
;
410 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &r
);
416 /* Special cases which aren't a single CPUARMState field */
417 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U32
|
418 KVM_REG_ARM_CORE
| KVM_REG_ARM_CORE_REG(usr_regs
.ARM_cpsr
);
419 r
.addr
= (uintptr_t)(&cpsr
);
420 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &r
);
424 cpsr_write(env
, cpsr
, 0xffffffff, CPSRWriteRaw
);
426 /* Make sure the current mode regs are properly set */
427 mode
= env
->uncached_cpsr
& CPSR_M
;
428 bn
= bank_number(mode
);
429 if (mode
== ARM_CPU_MODE_FIQ
) {
430 memcpy(env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
432 memcpy(env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
434 env
->regs
[13] = env
->banked_r13
[bn
];
435 env
->spsr
= env
->banked_spsr
[bn
];
436 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
439 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U64
| KVM_REG_ARM_VFP
;
440 for (i
= 0; i
< 32; i
++) {
441 r
.addr
= (uintptr_t)aa32_vfp_dreg(env
, i
);
442 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &r
);
449 r
.id
= KVM_REG_ARM
| KVM_REG_SIZE_U32
| KVM_REG_ARM_VFP
|
450 KVM_REG_ARM_VFP_FPSCR
;
451 r
.addr
= (uintptr_t)&fpscr
;
452 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &r
);
456 vfp_set_fpscr(env
, fpscr
);
458 ret
= kvm_get_vcpu_events(cpu
);
463 if (!write_kvmstate_to_list(cpu
)) {
466 /* Note that it's OK to have registers which aren't in CPUState,
467 * so we can ignore a failure return here.
469 write_list_to_cpustate(cpu
);
471 kvm_arm_sync_mpstate_to_qemu(cpu
);
476 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
478 qemu_log_mask(LOG_UNIMP
, "%s: guest debug not yet implemented\n", __func__
);
482 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
484 qemu_log_mask(LOG_UNIMP
, "%s: guest debug not yet implemented\n", __func__
);
488 bool kvm_arm_handle_debug(CPUState
*cs
, struct kvm_debug_exit_arch
*debug_exit
)
490 qemu_log_mask(LOG_UNIMP
, "%s: guest debug not yet implemented\n", __func__
);
494 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
495 target_ulong len
, int type
)
497 qemu_log_mask(LOG_UNIMP
, "%s: not implemented\n", __func__
);
501 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
502 target_ulong len
, int type
)
504 qemu_log_mask(LOG_UNIMP
, "%s: not implemented\n", __func__
);
508 void kvm_arch_remove_all_hw_breakpoints(void)
510 qemu_log_mask(LOG_UNIMP
, "%s: not implemented\n", __func__
);
513 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch
*ptr
)
515 qemu_log_mask(LOG_UNIMP
, "%s: not implemented\n", __func__
);
518 bool kvm_arm_hw_debug_active(CPUState
*cs
)
523 void kvm_arm_pmu_set_irq(CPUState
*cs
, int irq
)
525 qemu_log_mask(LOG_UNIMP
, "%s: not implemented\n", __func__
);
528 void kvm_arm_pmu_init(CPUState
*cs
)
530 qemu_log_mask(LOG_UNIMP
, "%s: not implemented\n", __func__
);