2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include "qemu/osdep.h"
30 #include "exec/exec-all.h"
31 #include "exec/gdbstub.h"
32 #include "exec/helper-proto.h"
33 #include "qemu/host-utils.h"
35 static struct XtensaConfigList
*xtensa_cores
;
37 static void xtensa_core_class_init(ObjectClass
*oc
, void *data
)
39 CPUClass
*cc
= CPU_CLASS(oc
);
40 XtensaCPUClass
*xcc
= XTENSA_CPU_CLASS(oc
);
41 const XtensaConfig
*config
= data
;
45 /* Use num_core_regs to see only non-privileged registers in an unmodified
46 * gdb. Use num_regs to see all registers. gdb modification is required
47 * for that: reset bit 0 in the 'flags' field of the registers definitions
48 * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
50 cc
->gdb_num_core_regs
= config
->gdb_regmap
.num_regs
;
53 static void init_libisa(XtensaConfig
*config
)
59 config
->isa
= xtensa_isa_init(config
->isa_internal
, NULL
, NULL
);
60 assert(xtensa_isa_maxlength(config
->isa
) <= MAX_INSN_LENGTH
);
61 opcodes
= xtensa_isa_num_opcodes(config
->isa
);
62 formats
= xtensa_isa_num_formats(config
->isa
);
63 config
->opcode_ops
= g_new(XtensaOpcodeOps
*, opcodes
);
65 for (i
= 0; i
< formats
; ++i
) {
66 assert(xtensa_format_num_slots(config
->isa
, i
) <= MAX_INSN_SLOTS
);
69 for (i
= 0; i
< opcodes
; ++i
) {
70 const char *opc_name
= xtensa_opcode_name(config
->isa
, i
);
71 XtensaOpcodeOps
*ops
= NULL
;
73 assert(xtensa_opcode_num_operands(config
->isa
, i
) <= MAX_OPCODE_ARGS
);
74 if (!config
->opcode_translators
) {
75 ops
= xtensa_find_opcode_ops(&xtensa_core_opcodes
, opc_name
);
77 for (j
= 0; !ops
&& config
->opcode_translators
[j
]; ++j
) {
78 ops
= xtensa_find_opcode_ops(config
->opcode_translators
[j
],
85 "opcode translator not found for %s's opcode '%s'\n",
86 config
->name
, opc_name
);
89 config
->opcode_ops
[i
] = ops
;
93 void xtensa_finalize_config(XtensaConfig
*config
)
95 if (config
->isa_internal
) {
99 if (config
->gdb_regmap
.num_regs
== 0 ||
100 config
->gdb_regmap
.num_core_regs
== 0) {
102 unsigned n_core_regs
= 0;
104 xtensa_count_regs(config
, &n_regs
, &n_core_regs
);
105 if (config
->gdb_regmap
.num_regs
== 0) {
106 config
->gdb_regmap
.num_regs
= n_regs
;
108 if (config
->gdb_regmap
.num_core_regs
== 0) {
109 config
->gdb_regmap
.num_core_regs
= n_core_regs
;
114 void xtensa_register_core(XtensaConfigList
*node
)
117 .parent
= TYPE_XTENSA_CPU
,
118 .class_init
= xtensa_core_class_init
,
119 .class_data
= (void *)node
->config
,
122 node
->next
= xtensa_cores
;
124 type
.name
= g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), node
->config
->name
);
125 type_register(&type
);
126 g_free((gpointer
)type
.name
);
129 static uint32_t check_hw_breakpoints(CPUXtensaState
*env
)
133 for (i
= 0; i
< env
->config
->ndbreak
; ++i
) {
134 if (env
->cpu_watchpoint
[i
] &&
135 env
->cpu_watchpoint
[i
]->flags
& BP_WATCHPOINT_HIT
) {
136 return DEBUGCAUSE_DB
| (i
<< DEBUGCAUSE_DBNUM_SHIFT
);
142 void xtensa_breakpoint_handler(CPUState
*cs
)
144 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
145 CPUXtensaState
*env
= &cpu
->env
;
147 if (cs
->watchpoint_hit
) {
148 if (cs
->watchpoint_hit
->flags
& BP_CPU
) {
151 cs
->watchpoint_hit
= NULL
;
152 cause
= check_hw_breakpoints(env
);
154 debug_exception_env(env
, cause
);
156 cpu_loop_exit_noexc(cs
);
161 void xtensa_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
163 XtensaConfigList
*core
= xtensa_cores
;
164 cpu_fprintf(f
, "Available CPUs:\n");
165 for (; core
; core
= core
->next
) {
166 cpu_fprintf(f
, " %s\n", core
->config
->name
);
170 #ifdef CONFIG_USER_ONLY
172 int xtensa_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int size
, int rw
,
175 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
176 CPUXtensaState
*env
= &cpu
->env
;
178 qemu_log_mask(CPU_LOG_INT
,
179 "%s: rw = %d, address = 0x%08" VADDR_PRIx
", size = %d\n",
180 __func__
, rw
, address
, size
);
181 env
->sregs
[EXCVADDR
] = address
;
182 env
->sregs
[EXCCAUSE
] = rw
? STORE_PROHIBITED_CAUSE
: LOAD_PROHIBITED_CAUSE
;
183 cs
->exception_index
= EXC_USER
;
189 void xtensa_cpu_do_unaligned_access(CPUState
*cs
,
190 vaddr addr
, MMUAccessType access_type
,
191 int mmu_idx
, uintptr_t retaddr
)
193 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
194 CPUXtensaState
*env
= &cpu
->env
;
196 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_UNALIGNED_EXCEPTION
) &&
197 !xtensa_option_enabled(env
->config
, XTENSA_OPTION_HW_ALIGNMENT
)) {
198 cpu_restore_state(CPU(cpu
), retaddr
, true);
199 HELPER(exception_cause_vaddr
)(env
,
200 env
->pc
, LOAD_STORE_ALIGNMENT_CAUSE
,
205 void tlb_fill(CPUState
*cs
, target_ulong vaddr
, int size
,
206 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
208 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
209 CPUXtensaState
*env
= &cpu
->env
;
213 int ret
= xtensa_get_physical_addr(env
, true, vaddr
, access_type
, mmu_idx
,
214 &paddr
, &page_size
, &access
);
216 qemu_log_mask(CPU_LOG_MMU
, "%s(%08x, %d, %d) -> %08x, ret = %d\n",
217 __func__
, vaddr
, access_type
, mmu_idx
, paddr
, ret
);
221 vaddr
& TARGET_PAGE_MASK
,
222 paddr
& TARGET_PAGE_MASK
,
223 access
, mmu_idx
, page_size
);
225 cpu_restore_state(cs
, retaddr
, true);
226 HELPER(exception_cause_vaddr
)(env
, env
->pc
, ret
, vaddr
);
230 void xtensa_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
, vaddr addr
,
231 unsigned size
, MMUAccessType access_type
,
232 int mmu_idx
, MemTxAttrs attrs
,
233 MemTxResult response
, uintptr_t retaddr
)
235 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
236 CPUXtensaState
*env
= &cpu
->env
;
238 cpu_restore_state(cs
, retaddr
, true);
239 HELPER(exception_cause_vaddr
)(env
, env
->pc
,
240 access_type
== MMU_INST_FETCH
?
241 INSTR_PIF_ADDR_ERROR_CAUSE
:
242 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
246 void xtensa_runstall(CPUXtensaState
*env
, bool runstall
)
248 CPUState
*cpu
= CPU(xtensa_env_get_cpu(env
));
250 env
->runstall
= runstall
;
251 cpu
->halted
= runstall
;
253 cpu_interrupt(cpu
, CPU_INTERRUPT_HALT
);
255 cpu_reset_interrupt(cpu
, CPU_INTERRUPT_HALT
);