hw/misc/imx7_gpr.c

   1 /*
   2  * Copyright (c) 2018, Impinj, Inc.
   3  *
   4  * i.MX7 GPR IP block emulation code
   5  *
   6  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
   7  *
   8  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   9  * See the COPYING file in the top-level directory.
  10  *
  11  * Bare minimum emulation code needed to support being able to shut
  12  * down linux guest gracefully.
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "hw/misc/imx7_gpr.h"
  17 #include "qemu/log.h"
  18 #include "qemu/module.h"
  19 #include "sysemu/sysemu.h"
  20
  21 #include "trace.h"
  22
  23 enum IMX7GPRRegisters {
  24     IOMUXC_GPR0  = 0x00,
  25     IOMUXC_GPR1  = 0x04,
  26     IOMUXC_GPR2  = 0x08,
  27     IOMUXC_GPR3  = 0x0c,
  28     IOMUXC_GPR4  = 0x10,
  29     IOMUXC_GPR5  = 0x14,
  30     IOMUXC_GPR6  = 0x18,
  31     IOMUXC_GPR7  = 0x1c,
  32     IOMUXC_GPR8  = 0x20,
  33     IOMUXC_GPR9  = 0x24,
  34     IOMUXC_GPR10 = 0x28,
  35     IOMUXC_GPR11 = 0x2c,
  36     IOMUXC_GPR12 = 0x30,
  37     IOMUXC_GPR13 = 0x34,
  38     IOMUXC_GPR14 = 0x38,
  39     IOMUXC_GPR15 = 0x3c,
  40     IOMUXC_GPR16 = 0x40,
  41     IOMUXC_GPR17 = 0x44,
  42     IOMUXC_GPR18 = 0x48,
  43     IOMUXC_GPR19 = 0x4c,
  44     IOMUXC_GPR20 = 0x50,
  45     IOMUXC_GPR21 = 0x54,
  46     IOMUXC_GPR22 = 0x58,
  47 };
  48
  49 #define IMX7D_GPR1_IRQ_MASK                 BIT(12)
  50 #define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK    BIT(13)
  51 #define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK    BIT(14)
  52 #define IMX7D_GPR1_ENET_TX_CLK_SEL_MASK     (0x3 << 13)
  53 #define IMX7D_GPR1_ENET1_CLK_DIR_MASK       BIT(17)
  54 #define IMX7D_GPR1_ENET2_CLK_DIR_MASK       BIT(18)
  55 #define IMX7D_GPR1_ENET_CLK_DIR_MASK        (0x3 << 17)
  56
  57 #define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI     BIT(4)
  58 #define IMX7D_GPR12_PCIE_PHY_REFCLK_SEL     BIT(5)
  59 #define IMX7D_GPR22_PCIE_PHY_PLL_LOCKED     BIT(31)
  60
  61
  62 static uint64_t imx7_gpr_read(void *opaque, hwaddr offset, unsigned size)
  63 {
  64     trace_imx7_gpr_read(offset);
  65
  66     if (offset == IOMUXC_GPR22) {
  67         return IMX7D_GPR22_PCIE_PHY_PLL_LOCKED;
  68     }
  69
  70     return 0;
  71 }
  72
  73 static void imx7_gpr_write(void *opaque, hwaddr offset,
  74                            uint64_t v, unsigned size)
  75 {
  76     trace_imx7_gpr_write(offset, v);
  77 }
  78
  79 static const struct MemoryRegionOps imx7_gpr_ops = {
  80     .read = imx7_gpr_read,
  81     .write = imx7_gpr_write,
  82     .endianness = DEVICE_NATIVE_ENDIAN,
  83     .impl = {
  84         /*
  85          * Our device would not work correctly if the guest was doing
  86          * unaligned access. This might not be a limitation on the
  87          * real device but in practice there is no reason for a guest
  88          * to access this device unaligned.
  89          */
  90         .min_access_size = 4,
  91         .max_access_size = 4,
  92         .unaligned = false,
  93     },
  94 };
  95
  96 static void imx7_gpr_init(Object *obj)
  97 {
  98     SysBusDevice *sd = SYS_BUS_DEVICE(obj);
  99     IMX7GPRState *s = IMX7_GPR(obj);
 100
 101     memory_region_init_io(&s->mmio, obj, &imx7_gpr_ops, s,
 102                           TYPE_IMX7_GPR, 64 * 1024);
 103     sysbus_init_mmio(sd, &s->mmio);
 104 }
 105
 106 static void imx7_gpr_class_init(ObjectClass *klass, void *data)
 107 {
 108     DeviceClass *dc = DEVICE_CLASS(klass);
 109
 110     dc->desc  = "i.MX7 General Purpose Registers Module";
 111 }
 112
 113 static const TypeInfo imx7_gpr_info = {
 114     .name          = TYPE_IMX7_GPR,
 115     .parent        = TYPE_SYS_BUS_DEVICE,
 116     .instance_size = sizeof(IMX7GPRState),
 117     .instance_init = imx7_gpr_init,
 118     .class_init    = imx7_gpr_class_init,
 119 };
 120
 121 static void imx7_gpr_register_type(void)
 122 {
 123     type_register_static(&imx7_gpr_info);
 124 }
 125 type_init(imx7_gpr_register_type)