4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "internals.h"
25 #include "disas/disas.h"
26 #include "exec/exec-all.h"
27 #include "tcg/tcg-op.h"
28 #include "tcg/tcg-op-gvec.h"
30 #include "qemu/bitops.h"
32 #include "hw/semihosting/semihost.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
41 #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T)
42 #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5)
43 /* currently all emulated v5 cores are also v5TE, so don't bother */
44 #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5)
45 #define ENABLE_ARCH_5J dc_isar_feature(aa32_jazelle, s)
46 #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6)
47 #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K)
48 #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)
49 #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7)
50 #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8)
52 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
54 #include "translate.h"
56 #if defined(CONFIG_USER_ONLY)
59 #define IS_USER(s) (s->user)
62 /* We reuse the same 64-bit temporaries for efficiency. */
63 static TCGv_i64 cpu_V0
, cpu_V1
, cpu_M0
;
64 static TCGv_i32 cpu_R
[16];
65 TCGv_i32 cpu_CF
, cpu_NF
, cpu_VF
, cpu_ZF
;
66 TCGv_i64 cpu_exclusive_addr
;
67 TCGv_i64 cpu_exclusive_val
;
69 #include "exec/gen-icount.h"
71 static const char * const regnames
[] =
72 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
73 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
75 /* Function prototypes for gen_ functions calling Neon helpers. */
76 typedef void NeonGenThreeOpEnvFn(TCGv_i32
, TCGv_env
, TCGv_i32
,
78 /* Function prototypes for gen_ functions for fix point conversions */
79 typedef void VFPGenFixPointFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
81 /* initialize TCG globals. */
82 void arm_translate_init(void)
86 for (i
= 0; i
< 16; i
++) {
87 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
88 offsetof(CPUARMState
, regs
[i
]),
91 cpu_CF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, CF
), "CF");
92 cpu_NF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, NF
), "NF");
93 cpu_VF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, VF
), "VF");
94 cpu_ZF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, ZF
), "ZF");
96 cpu_exclusive_addr
= tcg_global_mem_new_i64(cpu_env
,
97 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
98 cpu_exclusive_val
= tcg_global_mem_new_i64(cpu_env
,
99 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
101 a64_translate_init();
104 /* Flags for the disas_set_da_iss info argument:
105 * lower bits hold the Rt register number, higher bits are flags.
107 typedef enum ISSInfo
{
110 ISSInvalid
= (1 << 5),
111 ISSIsAcqRel
= (1 << 6),
112 ISSIsWrite
= (1 << 7),
113 ISSIs16Bit
= (1 << 8),
116 /* Save the syndrome information for a Data Abort */
117 static void disas_set_da_iss(DisasContext
*s
, MemOp memop
, ISSInfo issinfo
)
120 int sas
= memop
& MO_SIZE
;
121 bool sse
= memop
& MO_SIGN
;
122 bool is_acqrel
= issinfo
& ISSIsAcqRel
;
123 bool is_write
= issinfo
& ISSIsWrite
;
124 bool is_16bit
= issinfo
& ISSIs16Bit
;
125 int srt
= issinfo
& ISSRegMask
;
127 if (issinfo
& ISSInvalid
) {
128 /* Some callsites want to conditionally provide ISS info,
129 * eg "only if this was not a writeback"
135 /* For AArch32, insns where the src/dest is R15 never generate
136 * ISS information. Catching that here saves checking at all
142 syn
= syn_data_abort_with_iss(0, sas
, sse
, srt
, 0, is_acqrel
,
143 0, 0, 0, is_write
, 0, is_16bit
);
144 disas_set_insn_syndrome(s
, syn
);
147 static inline int get_a32_user_mem_index(DisasContext
*s
)
149 /* Return the core mmu_idx to use for A32/T32 "unprivileged load/store"
151 * if PL2, UNPREDICTABLE (we choose to implement as if PL0)
152 * otherwise, access as if at PL0.
154 switch (s
->mmu_idx
) {
155 case ARMMMUIdx_E2
: /* this one is UNPREDICTABLE */
156 case ARMMMUIdx_E10_0
:
157 case ARMMMUIdx_E10_1
:
158 case ARMMMUIdx_E10_1_PAN
:
159 return arm_to_core_mmu_idx(ARMMMUIdx_E10_0
);
161 case ARMMMUIdx_SE10_0
:
162 case ARMMMUIdx_SE10_1
:
163 case ARMMMUIdx_SE10_1_PAN
:
164 return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0
);
165 case ARMMMUIdx_MUser
:
166 case ARMMMUIdx_MPriv
:
167 return arm_to_core_mmu_idx(ARMMMUIdx_MUser
);
168 case ARMMMUIdx_MUserNegPri
:
169 case ARMMMUIdx_MPrivNegPri
:
170 return arm_to_core_mmu_idx(ARMMMUIdx_MUserNegPri
);
171 case ARMMMUIdx_MSUser
:
172 case ARMMMUIdx_MSPriv
:
173 return arm_to_core_mmu_idx(ARMMMUIdx_MSUser
);
174 case ARMMMUIdx_MSUserNegPri
:
175 case ARMMMUIdx_MSPrivNegPri
:
176 return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri
);
178 g_assert_not_reached();
182 static inline TCGv_i32
load_cpu_offset(int offset
)
184 TCGv_i32 tmp
= tcg_temp_new_i32();
185 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
189 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
191 static inline void store_cpu_offset(TCGv_i32 var
, int offset
)
193 tcg_gen_st_i32(var
, cpu_env
, offset
);
194 tcg_temp_free_i32(var
);
197 #define store_cpu_field(var, name) \
198 store_cpu_offset(var, offsetof(CPUARMState, name))
200 /* The architectural value of PC. */
201 static uint32_t read_pc(DisasContext
*s
)
203 return s
->pc_curr
+ (s
->thumb
? 4 : 8);
206 /* Set a variable to the value of a CPU register. */
207 static void load_reg_var(DisasContext
*s
, TCGv_i32 var
, int reg
)
210 tcg_gen_movi_i32(var
, read_pc(s
));
212 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
216 /* Create a new temporary and set it to the value of a CPU register. */
217 static inline TCGv_i32
load_reg(DisasContext
*s
, int reg
)
219 TCGv_i32 tmp
= tcg_temp_new_i32();
220 load_reg_var(s
, tmp
, reg
);
225 * Create a new temp, REG + OFS, except PC is ALIGN(PC, 4).
226 * This is used for load/store for which use of PC implies (literal),
227 * or ADD that implies ADR.
229 static TCGv_i32
add_reg_for_lit(DisasContext
*s
, int reg
, int ofs
)
231 TCGv_i32 tmp
= tcg_temp_new_i32();
234 tcg_gen_movi_i32(tmp
, (read_pc(s
) & ~3) + ofs
);
236 tcg_gen_addi_i32(tmp
, cpu_R
[reg
], ofs
);
241 /* Set a CPU register. The source must be a temporary and will be
243 static void store_reg(DisasContext
*s
, int reg
, TCGv_i32 var
)
246 /* In Thumb mode, we must ignore bit 0.
247 * In ARM mode, for ARMv4 and ARMv5, it is UNPREDICTABLE if bits [1:0]
248 * are not 0b00, but for ARMv6 and above, we must ignore bits [1:0].
249 * We choose to ignore [1:0] in ARM mode for all architecture versions.
251 tcg_gen_andi_i32(var
, var
, s
->thumb
? ~1 : ~3);
252 s
->base
.is_jmp
= DISAS_JUMP
;
254 tcg_gen_mov_i32(cpu_R
[reg
], var
);
255 tcg_temp_free_i32(var
);
259 * Variant of store_reg which applies v8M stack-limit checks before updating
260 * SP. If the check fails this will result in an exception being taken.
261 * We disable the stack checks for CONFIG_USER_ONLY because we have
262 * no idea what the stack limits should be in that case.
263 * If stack checking is not being done this just acts like store_reg().
265 static void store_sp_checked(DisasContext
*s
, TCGv_i32 var
)
267 #ifndef CONFIG_USER_ONLY
268 if (s
->v8m_stackcheck
) {
269 gen_helper_v8m_stackcheck(cpu_env
, var
);
272 store_reg(s
, 13, var
);
275 /* Value extensions. */
276 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
277 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
278 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
279 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
281 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
282 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
285 static inline void gen_set_cpsr(TCGv_i32 var
, uint32_t mask
)
287 TCGv_i32 tmp_mask
= tcg_const_i32(mask
);
288 gen_helper_cpsr_write(cpu_env
, var
, tmp_mask
);
289 tcg_temp_free_i32(tmp_mask
);
291 /* Set NZCV flags from the high 4 bits of var. */
292 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
294 static void gen_exception_internal(int excp
)
296 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
298 assert(excp_is_internal(excp
));
299 gen_helper_exception_internal(cpu_env
, tcg_excp
);
300 tcg_temp_free_i32(tcg_excp
);
303 static void gen_step_complete_exception(DisasContext
*s
)
305 /* We just completed step of an insn. Move from Active-not-pending
306 * to Active-pending, and then also take the swstep exception.
307 * This corresponds to making the (IMPDEF) choice to prioritize
308 * swstep exceptions over asynchronous exceptions taken to an exception
309 * level where debug is disabled. This choice has the advantage that
310 * we do not need to maintain internal state corresponding to the
311 * ISV/EX syndrome bits between completion of the step and generation
312 * of the exception, and our syndrome information is always correct.
315 gen_swstep_exception(s
, 1, s
->is_ldex
);
316 s
->base
.is_jmp
= DISAS_NORETURN
;
319 static void gen_singlestep_exception(DisasContext
*s
)
321 /* Generate the right kind of exception for singlestep, which is
322 * either the architectural singlestep or EXCP_DEBUG for QEMU's
323 * gdb singlestepping.
326 gen_step_complete_exception(s
);
328 gen_exception_internal(EXCP_DEBUG
);
332 static inline bool is_singlestepping(DisasContext
*s
)
334 /* Return true if we are singlestepping either because of
335 * architectural singlestep or QEMU gdbstub singlestep. This does
336 * not include the command line '-singlestep' mode which is rather
337 * misnamed as it only means "one instruction per TB" and doesn't
338 * affect the code we generate.
340 return s
->base
.singlestep_enabled
|| s
->ss_active
;
343 static void gen_smul_dual(TCGv_i32 a
, TCGv_i32 b
)
345 TCGv_i32 tmp1
= tcg_temp_new_i32();
346 TCGv_i32 tmp2
= tcg_temp_new_i32();
347 tcg_gen_ext16s_i32(tmp1
, a
);
348 tcg_gen_ext16s_i32(tmp2
, b
);
349 tcg_gen_mul_i32(tmp1
, tmp1
, tmp2
);
350 tcg_temp_free_i32(tmp2
);
351 tcg_gen_sari_i32(a
, a
, 16);
352 tcg_gen_sari_i32(b
, b
, 16);
353 tcg_gen_mul_i32(b
, b
, a
);
354 tcg_gen_mov_i32(a
, tmp1
);
355 tcg_temp_free_i32(tmp1
);
358 /* Byteswap each halfword. */
359 static void gen_rev16(TCGv_i32 dest
, TCGv_i32 var
)
361 TCGv_i32 tmp
= tcg_temp_new_i32();
362 TCGv_i32 mask
= tcg_const_i32(0x00ff00ff);
363 tcg_gen_shri_i32(tmp
, var
, 8);
364 tcg_gen_and_i32(tmp
, tmp
, mask
);
365 tcg_gen_and_i32(var
, var
, mask
);
366 tcg_gen_shli_i32(var
, var
, 8);
367 tcg_gen_or_i32(dest
, var
, tmp
);
368 tcg_temp_free_i32(mask
);
369 tcg_temp_free_i32(tmp
);
372 /* Byteswap low halfword and sign extend. */
373 static void gen_revsh(TCGv_i32 dest
, TCGv_i32 var
)
375 tcg_gen_ext16u_i32(var
, var
);
376 tcg_gen_bswap16_i32(var
, var
);
377 tcg_gen_ext16s_i32(dest
, var
);
380 /* 32x32->64 multiply. Marks inputs as dead. */
381 static TCGv_i64
gen_mulu_i64_i32(TCGv_i32 a
, TCGv_i32 b
)
383 TCGv_i32 lo
= tcg_temp_new_i32();
384 TCGv_i32 hi
= tcg_temp_new_i32();
387 tcg_gen_mulu2_i32(lo
, hi
, a
, b
);
388 tcg_temp_free_i32(a
);
389 tcg_temp_free_i32(b
);
391 ret
= tcg_temp_new_i64();
392 tcg_gen_concat_i32_i64(ret
, lo
, hi
);
393 tcg_temp_free_i32(lo
);
394 tcg_temp_free_i32(hi
);
399 static TCGv_i64
gen_muls_i64_i32(TCGv_i32 a
, TCGv_i32 b
)
401 TCGv_i32 lo
= tcg_temp_new_i32();
402 TCGv_i32 hi
= tcg_temp_new_i32();
405 tcg_gen_muls2_i32(lo
, hi
, a
, b
);
406 tcg_temp_free_i32(a
);
407 tcg_temp_free_i32(b
);
409 ret
= tcg_temp_new_i64();
410 tcg_gen_concat_i32_i64(ret
, lo
, hi
);
411 tcg_temp_free_i32(lo
);
412 tcg_temp_free_i32(hi
);
417 /* Swap low and high halfwords. */
418 static void gen_swap_half(TCGv_i32 var
)
420 tcg_gen_rotri_i32(var
, var
, 16);
423 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
424 tmp = (t0 ^ t1) & 0x8000;
427 t0 = (t0 + t1) ^ tmp;
430 static void gen_add16(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
432 TCGv_i32 tmp
= tcg_temp_new_i32();
433 tcg_gen_xor_i32(tmp
, t0
, t1
);
434 tcg_gen_andi_i32(tmp
, tmp
, 0x8000);
435 tcg_gen_andi_i32(t0
, t0
, ~0x8000);
436 tcg_gen_andi_i32(t1
, t1
, ~0x8000);
437 tcg_gen_add_i32(t0
, t0
, t1
);
438 tcg_gen_xor_i32(dest
, t0
, tmp
);
439 tcg_temp_free_i32(tmp
);
442 /* Set N and Z flags from var. */
443 static inline void gen_logic_CC(TCGv_i32 var
)
445 tcg_gen_mov_i32(cpu_NF
, var
);
446 tcg_gen_mov_i32(cpu_ZF
, var
);
449 /* dest = T0 + T1 + CF. */
450 static void gen_add_carry(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
452 tcg_gen_add_i32(dest
, t0
, t1
);
453 tcg_gen_add_i32(dest
, dest
, cpu_CF
);
456 /* dest = T0 - T1 + CF - 1. */
457 static void gen_sub_carry(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
459 tcg_gen_sub_i32(dest
, t0
, t1
);
460 tcg_gen_add_i32(dest
, dest
, cpu_CF
);
461 tcg_gen_subi_i32(dest
, dest
, 1);
464 /* dest = T0 + T1. Compute C, N, V and Z flags */
465 static void gen_add_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
467 TCGv_i32 tmp
= tcg_temp_new_i32();
468 tcg_gen_movi_i32(tmp
, 0);
469 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0
, tmp
, t1
, tmp
);
470 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
471 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
472 tcg_gen_xor_i32(tmp
, t0
, t1
);
473 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
474 tcg_temp_free_i32(tmp
);
475 tcg_gen_mov_i32(dest
, cpu_NF
);
478 /* dest = T0 + T1 + CF. Compute C, N, V and Z flags */
479 static void gen_adc_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
481 TCGv_i32 tmp
= tcg_temp_new_i32();
482 if (TCG_TARGET_HAS_add2_i32
) {
483 tcg_gen_movi_i32(tmp
, 0);
484 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0
, tmp
, cpu_CF
, tmp
);
485 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1
, tmp
);
487 TCGv_i64 q0
= tcg_temp_new_i64();
488 TCGv_i64 q1
= tcg_temp_new_i64();
489 tcg_gen_extu_i32_i64(q0
, t0
);
490 tcg_gen_extu_i32_i64(q1
, t1
);
491 tcg_gen_add_i64(q0
, q0
, q1
);
492 tcg_gen_extu_i32_i64(q1
, cpu_CF
);
493 tcg_gen_add_i64(q0
, q0
, q1
);
494 tcg_gen_extr_i64_i32(cpu_NF
, cpu_CF
, q0
);
495 tcg_temp_free_i64(q0
);
496 tcg_temp_free_i64(q1
);
498 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
499 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
500 tcg_gen_xor_i32(tmp
, t0
, t1
);
501 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
502 tcg_temp_free_i32(tmp
);
503 tcg_gen_mov_i32(dest
, cpu_NF
);
506 /* dest = T0 - T1. Compute C, N, V and Z flags */
507 static void gen_sub_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
510 tcg_gen_sub_i32(cpu_NF
, t0
, t1
);
511 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
512 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0
, t1
);
513 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
514 tmp
= tcg_temp_new_i32();
515 tcg_gen_xor_i32(tmp
, t0
, t1
);
516 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
517 tcg_temp_free_i32(tmp
);
518 tcg_gen_mov_i32(dest
, cpu_NF
);
521 /* dest = T0 + ~T1 + CF. Compute C, N, V and Z flags */
522 static void gen_sbc_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
524 TCGv_i32 tmp
= tcg_temp_new_i32();
525 tcg_gen_not_i32(tmp
, t1
);
526 gen_adc_CC(dest
, t0
, tmp
);
527 tcg_temp_free_i32(tmp
);
530 #define GEN_SHIFT(name) \
531 static void gen_##name(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) \
533 TCGv_i32 tmp1, tmp2, tmp3; \
534 tmp1 = tcg_temp_new_i32(); \
535 tcg_gen_andi_i32(tmp1, t1, 0xff); \
536 tmp2 = tcg_const_i32(0); \
537 tmp3 = tcg_const_i32(0x1f); \
538 tcg_gen_movcond_i32(TCG_COND_GTU, tmp2, tmp1, tmp3, tmp2, t0); \
539 tcg_temp_free_i32(tmp3); \
540 tcg_gen_andi_i32(tmp1, tmp1, 0x1f); \
541 tcg_gen_##name##_i32(dest, tmp2, tmp1); \
542 tcg_temp_free_i32(tmp2); \
543 tcg_temp_free_i32(tmp1); \
549 static void gen_sar(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
552 tmp1
= tcg_temp_new_i32();
553 tcg_gen_andi_i32(tmp1
, t1
, 0xff);
554 tmp2
= tcg_const_i32(0x1f);
555 tcg_gen_movcond_i32(TCG_COND_GTU
, tmp1
, tmp1
, tmp2
, tmp2
, tmp1
);
556 tcg_temp_free_i32(tmp2
);
557 tcg_gen_sar_i32(dest
, t0
, tmp1
);
558 tcg_temp_free_i32(tmp1
);
561 static void shifter_out_im(TCGv_i32 var
, int shift
)
563 tcg_gen_extract_i32(cpu_CF
, var
, shift
, 1);
566 /* Shift by immediate. Includes special handling for shift == 0. */
567 static inline void gen_arm_shift_im(TCGv_i32 var
, int shiftop
,
568 int shift
, int flags
)
574 shifter_out_im(var
, 32 - shift
);
575 tcg_gen_shli_i32(var
, var
, shift
);
581 tcg_gen_shri_i32(cpu_CF
, var
, 31);
583 tcg_gen_movi_i32(var
, 0);
586 shifter_out_im(var
, shift
- 1);
587 tcg_gen_shri_i32(var
, var
, shift
);
594 shifter_out_im(var
, shift
- 1);
597 tcg_gen_sari_i32(var
, var
, shift
);
599 case 3: /* ROR/RRX */
602 shifter_out_im(var
, shift
- 1);
603 tcg_gen_rotri_i32(var
, var
, shift
); break;
605 TCGv_i32 tmp
= tcg_temp_new_i32();
606 tcg_gen_shli_i32(tmp
, cpu_CF
, 31);
608 shifter_out_im(var
, 0);
609 tcg_gen_shri_i32(var
, var
, 1);
610 tcg_gen_or_i32(var
, var
, tmp
);
611 tcg_temp_free_i32(tmp
);
616 static inline void gen_arm_shift_reg(TCGv_i32 var
, int shiftop
,
617 TCGv_i32 shift
, int flags
)
621 case 0: gen_helper_shl_cc(var
, cpu_env
, var
, shift
); break;
622 case 1: gen_helper_shr_cc(var
, cpu_env
, var
, shift
); break;
623 case 2: gen_helper_sar_cc(var
, cpu_env
, var
, shift
); break;
624 case 3: gen_helper_ror_cc(var
, cpu_env
, var
, shift
); break;
629 gen_shl(var
, var
, shift
);
632 gen_shr(var
, var
, shift
);
635 gen_sar(var
, var
, shift
);
637 case 3: tcg_gen_andi_i32(shift
, shift
, 0x1f);
638 tcg_gen_rotr_i32(var
, var
, shift
); break;
641 tcg_temp_free_i32(shift
);
645 * Generate a conditional based on ARM condition code cc.
646 * This is common between ARM and Aarch64 targets.
648 void arm_test_cc(DisasCompare
*cmp
, int cc
)
679 case 8: /* hi: C && !Z */
680 case 9: /* ls: !C || Z -> !(C && !Z) */
682 value
= tcg_temp_new_i32();
684 /* CF is 1 for C, so -CF is an all-bits-set mask for C;
685 ZF is non-zero for !Z; so AND the two subexpressions. */
686 tcg_gen_neg_i32(value
, cpu_CF
);
687 tcg_gen_and_i32(value
, value
, cpu_ZF
);
690 case 10: /* ge: N == V -> N ^ V == 0 */
691 case 11: /* lt: N != V -> N ^ V != 0 */
692 /* Since we're only interested in the sign bit, == 0 is >= 0. */
694 value
= tcg_temp_new_i32();
696 tcg_gen_xor_i32(value
, cpu_VF
, cpu_NF
);
699 case 12: /* gt: !Z && N == V */
700 case 13: /* le: Z || N != V */
702 value
= tcg_temp_new_i32();
704 /* (N == V) is equal to the sign bit of ~(NF ^ VF). Propagate
705 * the sign bit then AND with ZF to yield the result. */
706 tcg_gen_xor_i32(value
, cpu_VF
, cpu_NF
);
707 tcg_gen_sari_i32(value
, value
, 31);
708 tcg_gen_andc_i32(value
, cpu_ZF
, value
);
711 case 14: /* always */
712 case 15: /* always */
713 /* Use the ALWAYS condition, which will fold early.
714 * It doesn't matter what we use for the value. */
715 cond
= TCG_COND_ALWAYS
;
720 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
725 cond
= tcg_invert_cond(cond
);
731 cmp
->value_global
= global
;
734 void arm_free_cc(DisasCompare
*cmp
)
736 if (!cmp
->value_global
) {
737 tcg_temp_free_i32(cmp
->value
);
741 void arm_jump_cc(DisasCompare
*cmp
, TCGLabel
*label
)
743 tcg_gen_brcondi_i32(cmp
->cond
, cmp
->value
, 0, label
);
746 void arm_gen_test_cc(int cc
, TCGLabel
*label
)
749 arm_test_cc(&cmp
, cc
);
750 arm_jump_cc(&cmp
, label
);
754 static inline void gen_set_condexec(DisasContext
*s
)
756 if (s
->condexec_mask
) {
757 uint32_t val
= (s
->condexec_cond
<< 4) | (s
->condexec_mask
>> 1);
758 TCGv_i32 tmp
= tcg_temp_new_i32();
759 tcg_gen_movi_i32(tmp
, val
);
760 store_cpu_field(tmp
, condexec_bits
);
764 static inline void gen_set_pc_im(DisasContext
*s
, target_ulong val
)
766 tcg_gen_movi_i32(cpu_R
[15], val
);
769 /* Set PC and Thumb state from var. var is marked as dead. */
770 static inline void gen_bx(DisasContext
*s
, TCGv_i32 var
)
772 s
->base
.is_jmp
= DISAS_JUMP
;
773 tcg_gen_andi_i32(cpu_R
[15], var
, ~1);
774 tcg_gen_andi_i32(var
, var
, 1);
775 store_cpu_field(var
, thumb
);
779 * Set PC and Thumb state from var. var is marked as dead.
780 * For M-profile CPUs, include logic to detect exception-return
781 * branches and handle them. This is needed for Thumb POP/LDM to PC, LDR to PC,
782 * and BX reg, and no others, and happens only for code in Handler mode.
783 * The Security Extension also requires us to check for the FNC_RETURN
784 * which signals a function return from non-secure state; this can happen
785 * in both Handler and Thread mode.
786 * To avoid having to do multiple comparisons in inline generated code,
787 * we make the check we do here loose, so it will match for EXC_RETURN
788 * in Thread mode. For system emulation do_v7m_exception_exit() checks
789 * for these spurious cases and returns without doing anything (giving
790 * the same behaviour as for a branch to a non-magic address).
792 * In linux-user mode it is unclear what the right behaviour for an
793 * attempted FNC_RETURN should be, because in real hardware this will go
794 * directly to Secure code (ie not the Linux kernel) which will then treat
795 * the error in any way it chooses. For QEMU we opt to make the FNC_RETURN
796 * attempt behave the way it would on a CPU without the security extension,
797 * which is to say "like a normal branch". That means we can simply treat
798 * all branches as normal with no magic address behaviour.
800 static inline void gen_bx_excret(DisasContext
*s
, TCGv_i32 var
)
802 /* Generate the same code here as for a simple bx, but flag via
803 * s->base.is_jmp that we need to do the rest of the work later.
806 #ifndef CONFIG_USER_ONLY
807 if (arm_dc_feature(s
, ARM_FEATURE_M_SECURITY
) ||
808 (s
->v7m_handler_mode
&& arm_dc_feature(s
, ARM_FEATURE_M
))) {
809 s
->base
.is_jmp
= DISAS_BX_EXCRET
;
814 static inline void gen_bx_excret_final_code(DisasContext
*s
)
816 /* Generate the code to finish possible exception return and end the TB */
817 TCGLabel
*excret_label
= gen_new_label();
820 if (arm_dc_feature(s
, ARM_FEATURE_M_SECURITY
)) {
821 /* Covers FNC_RETURN and EXC_RETURN magic */
822 min_magic
= FNC_RETURN_MIN_MAGIC
;
824 /* EXC_RETURN magic only */
825 min_magic
= EXC_RETURN_MIN_MAGIC
;
828 /* Is the new PC value in the magic range indicating exception return? */
829 tcg_gen_brcondi_i32(TCG_COND_GEU
, cpu_R
[15], min_magic
, excret_label
);
830 /* No: end the TB as we would for a DISAS_JMP */
831 if (is_singlestepping(s
)) {
832 gen_singlestep_exception(s
);
834 tcg_gen_exit_tb(NULL
, 0);
836 gen_set_label(excret_label
);
837 /* Yes: this is an exception return.
838 * At this point in runtime env->regs[15] and env->thumb will hold
839 * the exception-return magic number, which do_v7m_exception_exit()
840 * will read. Nothing else will be able to see those values because
841 * the cpu-exec main loop guarantees that we will always go straight
842 * from raising the exception to the exception-handling code.
844 * gen_ss_advance(s) does nothing on M profile currently but
845 * calling it is conceptually the right thing as we have executed
846 * this instruction (compare SWI, HVC, SMC handling).
849 gen_exception_internal(EXCP_EXCEPTION_EXIT
);
852 static inline void gen_bxns(DisasContext
*s
, int rm
)
854 TCGv_i32 var
= load_reg(s
, rm
);
856 /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory
857 * we need to sync state before calling it, but:
858 * - we don't need to do gen_set_pc_im() because the bxns helper will
859 * always set the PC itself
860 * - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE
861 * unless it's outside an IT block or the last insn in an IT block,
862 * so we know that condexec == 0 (already set at the top of the TB)
863 * is correct in the non-UNPREDICTABLE cases, and we can choose
864 * "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise.
866 gen_helper_v7m_bxns(cpu_env
, var
);
867 tcg_temp_free_i32(var
);
868 s
->base
.is_jmp
= DISAS_EXIT
;
871 static inline void gen_blxns(DisasContext
*s
, int rm
)
873 TCGv_i32 var
= load_reg(s
, rm
);
875 /* We don't need to sync condexec state, for the same reason as bxns.
876 * We do however need to set the PC, because the blxns helper reads it.
877 * The blxns helper may throw an exception.
879 gen_set_pc_im(s
, s
->base
.pc_next
);
880 gen_helper_v7m_blxns(cpu_env
, var
);
881 tcg_temp_free_i32(var
);
882 s
->base
.is_jmp
= DISAS_EXIT
;
885 /* Variant of store_reg which uses branch&exchange logic when storing
886 to r15 in ARM architecture v7 and above. The source must be a temporary
887 and will be marked as dead. */
888 static inline void store_reg_bx(DisasContext
*s
, int reg
, TCGv_i32 var
)
890 if (reg
== 15 && ENABLE_ARCH_7
) {
893 store_reg(s
, reg
, var
);
897 /* Variant of store_reg which uses branch&exchange logic when storing
898 * to r15 in ARM architecture v5T and above. This is used for storing
899 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
900 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
901 static inline void store_reg_from_load(DisasContext
*s
, int reg
, TCGv_i32 var
)
903 if (reg
== 15 && ENABLE_ARCH_5
) {
904 gen_bx_excret(s
, var
);
906 store_reg(s
, reg
, var
);
910 #ifdef CONFIG_USER_ONLY
911 #define IS_USER_ONLY 1
913 #define IS_USER_ONLY 0
916 /* Abstractions of "generate code to do a guest load/store for
917 * AArch32", where a vaddr is always 32 bits (and is zero
918 * extended if we're a 64 bit core) and data is also
919 * 32 bits unless specifically doing a 64 bit access.
920 * These functions work like tcg_gen_qemu_{ld,st}* except
921 * that the address argument is TCGv_i32 rather than TCGv.
924 static inline TCGv
gen_aa32_addr(DisasContext
*s
, TCGv_i32 a32
, MemOp op
)
926 TCGv addr
= tcg_temp_new();
927 tcg_gen_extu_i32_tl(addr
, a32
);
929 /* Not needed for user-mode BE32, where we use MO_BE instead. */
930 if (!IS_USER_ONLY
&& s
->sctlr_b
&& (op
& MO_SIZE
) < MO_32
) {
931 tcg_gen_xori_tl(addr
, addr
, 4 - (1 << (op
& MO_SIZE
)));
936 static void gen_aa32_ld_i32(DisasContext
*s
, TCGv_i32 val
, TCGv_i32 a32
,
937 int index
, MemOp opc
)
941 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
942 !arm_dc_feature(s
, ARM_FEATURE_M_MAIN
)) {
946 addr
= gen_aa32_addr(s
, a32
, opc
);
947 tcg_gen_qemu_ld_i32(val
, addr
, index
, opc
);
951 static void gen_aa32_st_i32(DisasContext
*s
, TCGv_i32 val
, TCGv_i32 a32
,
952 int index
, MemOp opc
)
956 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
957 !arm_dc_feature(s
, ARM_FEATURE_M_MAIN
)) {
961 addr
= gen_aa32_addr(s
, a32
, opc
);
962 tcg_gen_qemu_st_i32(val
, addr
, index
, opc
);
966 #define DO_GEN_LD(SUFF, OPC) \
967 static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
968 TCGv_i32 a32, int index) \
970 gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
973 #define DO_GEN_ST(SUFF, OPC) \
974 static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
975 TCGv_i32 a32, int index) \
977 gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
980 static inline void gen_aa32_frob64(DisasContext
*s
, TCGv_i64 val
)
982 /* Not needed for user-mode BE32, where we use MO_BE instead. */
983 if (!IS_USER_ONLY
&& s
->sctlr_b
) {
984 tcg_gen_rotri_i64(val
, val
, 32);
988 static void gen_aa32_ld_i64(DisasContext
*s
, TCGv_i64 val
, TCGv_i32 a32
,
989 int index
, MemOp opc
)
991 TCGv addr
= gen_aa32_addr(s
, a32
, opc
);
992 tcg_gen_qemu_ld_i64(val
, addr
, index
, opc
);
993 gen_aa32_frob64(s
, val
);
997 static inline void gen_aa32_ld64(DisasContext
*s
, TCGv_i64 val
,
998 TCGv_i32 a32
, int index
)
1000 gen_aa32_ld_i64(s
, val
, a32
, index
, MO_Q
| s
->be_data
);
1003 static void gen_aa32_st_i64(DisasContext
*s
, TCGv_i64 val
, TCGv_i32 a32
,
1004 int index
, MemOp opc
)
1006 TCGv addr
= gen_aa32_addr(s
, a32
, opc
);
1008 /* Not needed for user-mode BE32, where we use MO_BE instead. */
1009 if (!IS_USER_ONLY
&& s
->sctlr_b
) {
1010 TCGv_i64 tmp
= tcg_temp_new_i64();
1011 tcg_gen_rotri_i64(tmp
, val
, 32);
1012 tcg_gen_qemu_st_i64(tmp
, addr
, index
, opc
);
1013 tcg_temp_free_i64(tmp
);
1015 tcg_gen_qemu_st_i64(val
, addr
, index
, opc
);
1017 tcg_temp_free(addr
);
1020 static inline void gen_aa32_st64(DisasContext
*s
, TCGv_i64 val
,
1021 TCGv_i32 a32
, int index
)
1023 gen_aa32_st_i64(s
, val
, a32
, index
, MO_Q
| s
->be_data
);
1026 DO_GEN_LD(8u, MO_UB
)
1027 DO_GEN_LD(16u, MO_UW
)
1028 DO_GEN_LD(32u, MO_UL
)
1030 DO_GEN_ST(16, MO_UW
)
1031 DO_GEN_ST(32, MO_UL
)
1033 static inline void gen_hvc(DisasContext
*s
, int imm16
)
1035 /* The pre HVC helper handles cases when HVC gets trapped
1036 * as an undefined insn by runtime configuration (ie before
1037 * the insn really executes).
1039 gen_set_pc_im(s
, s
->pc_curr
);
1040 gen_helper_pre_hvc(cpu_env
);
1041 /* Otherwise we will treat this as a real exception which
1042 * happens after execution of the insn. (The distinction matters
1043 * for the PC value reported to the exception handler and also
1044 * for single stepping.)
1047 gen_set_pc_im(s
, s
->base
.pc_next
);
1048 s
->base
.is_jmp
= DISAS_HVC
;
1051 static inline void gen_smc(DisasContext
*s
)
1053 /* As with HVC, we may take an exception either before or after
1054 * the insn executes.
1058 gen_set_pc_im(s
, s
->pc_curr
);
1059 tmp
= tcg_const_i32(syn_aa32_smc());
1060 gen_helper_pre_smc(cpu_env
, tmp
);
1061 tcg_temp_free_i32(tmp
);
1062 gen_set_pc_im(s
, s
->base
.pc_next
);
1063 s
->base
.is_jmp
= DISAS_SMC
;
1066 static void gen_exception_internal_insn(DisasContext
*s
, uint32_t pc
, int excp
)
1068 gen_set_condexec(s
);
1069 gen_set_pc_im(s
, pc
);
1070 gen_exception_internal(excp
);
1071 s
->base
.is_jmp
= DISAS_NORETURN
;
1074 static void gen_exception_insn(DisasContext
*s
, uint32_t pc
, int excp
,
1075 int syn
, uint32_t target_el
)
1077 gen_set_condexec(s
);
1078 gen_set_pc_im(s
, pc
);
1079 gen_exception(excp
, syn
, target_el
);
1080 s
->base
.is_jmp
= DISAS_NORETURN
;
1083 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syn
)
1087 gen_set_condexec(s
);
1088 gen_set_pc_im(s
, s
->pc_curr
);
1089 tcg_syn
= tcg_const_i32(syn
);
1090 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
1091 tcg_temp_free_i32(tcg_syn
);
1092 s
->base
.is_jmp
= DISAS_NORETURN
;
1095 static void unallocated_encoding(DisasContext
*s
)
1097 /* Unallocated and reserved encodings are uncategorized */
1098 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
1099 default_exception_el(s
));
1102 /* Force a TB lookup after an instruction that changes the CPU state. */
1103 static inline void gen_lookup_tb(DisasContext
*s
)
1105 tcg_gen_movi_i32(cpu_R
[15], s
->base
.pc_next
);
1106 s
->base
.is_jmp
= DISAS_EXIT
;
1109 static inline void gen_hlt(DisasContext
*s
, int imm
)
1111 /* HLT. This has two purposes.
1112 * Architecturally, it is an external halting debug instruction.
1113 * Since QEMU doesn't implement external debug, we treat this as
1114 * it is required for halting debug disabled: it will UNDEF.
1115 * Secondly, "HLT 0x3C" is a T32 semihosting trap instruction,
1116 * and "HLT 0xF000" is an A32 semihosting syscall. These traps
1117 * must trigger semihosting even for ARMv7 and earlier, where
1118 * HLT was an undefined encoding.
1119 * In system mode, we don't allow userspace access to
1120 * semihosting, to provide some semblance of security
1121 * (and for consistency with our 32-bit semihosting).
1123 if (semihosting_enabled() &&
1124 #ifndef CONFIG_USER_ONLY
1125 s
->current_el
!= 0 &&
1127 (imm
== (s
->thumb
? 0x3c : 0xf000))) {
1128 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
1132 unallocated_encoding(s
);
1135 static TCGv_ptr
get_fpstatus_ptr(int neon
)
1137 TCGv_ptr statusptr
= tcg_temp_new_ptr();
1140 offset
= offsetof(CPUARMState
, vfp
.standard_fp_status
);
1142 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
1144 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
1148 static inline long vfp_reg_offset(bool dp
, unsigned reg
)
1151 return offsetof(CPUARMState
, vfp
.zregs
[reg
>> 1].d
[reg
& 1]);
1153 long ofs
= offsetof(CPUARMState
, vfp
.zregs
[reg
>> 2].d
[(reg
>> 1) & 1]);
1155 ofs
+= offsetof(CPU_DoubleU
, l
.upper
);
1157 ofs
+= offsetof(CPU_DoubleU
, l
.lower
);
1163 /* Return the offset of a 32-bit piece of a NEON register.
1164 zero is the least significant end of the register. */
1166 neon_reg_offset (int reg
, int n
)
1170 return vfp_reg_offset(0, sreg
);
1173 /* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
1174 * where 0 is the least significant end of the register.
1177 neon_element_offset(int reg
, int element
, MemOp size
)
1179 int element_size
= 1 << size
;
1180 int ofs
= element
* element_size
;
1181 #ifdef HOST_WORDS_BIGENDIAN
1182 /* Calculate the offset assuming fully little-endian,
1183 * then XOR to account for the order of the 8-byte units.
1185 if (element_size
< 8) {
1186 ofs
^= 8 - element_size
;
1189 return neon_reg_offset(reg
, 0) + ofs
;
1192 static TCGv_i32
neon_load_reg(int reg
, int pass
)
1194 TCGv_i32 tmp
= tcg_temp_new_i32();
1195 tcg_gen_ld_i32(tmp
, cpu_env
, neon_reg_offset(reg
, pass
));
1199 static void neon_load_element(TCGv_i32 var
, int reg
, int ele
, MemOp mop
)
1201 long offset
= neon_element_offset(reg
, ele
, mop
& MO_SIZE
);
1205 tcg_gen_ld8u_i32(var
, cpu_env
, offset
);
1208 tcg_gen_ld16u_i32(var
, cpu_env
, offset
);
1211 tcg_gen_ld_i32(var
, cpu_env
, offset
);
1214 g_assert_not_reached();
1218 static void neon_load_element64(TCGv_i64 var
, int reg
, int ele
, MemOp mop
)
1220 long offset
= neon_element_offset(reg
, ele
, mop
& MO_SIZE
);
1224 tcg_gen_ld8u_i64(var
, cpu_env
, offset
);
1227 tcg_gen_ld16u_i64(var
, cpu_env
, offset
);
1230 tcg_gen_ld32u_i64(var
, cpu_env
, offset
);
1233 tcg_gen_ld_i64(var
, cpu_env
, offset
);
1236 g_assert_not_reached();
1240 static void neon_store_reg(int reg
, int pass
, TCGv_i32 var
)
1242 tcg_gen_st_i32(var
, cpu_env
, neon_reg_offset(reg
, pass
));
1243 tcg_temp_free_i32(var
);
1246 static void neon_store_element(int reg
, int ele
, MemOp size
, TCGv_i32 var
)
1248 long offset
= neon_element_offset(reg
, ele
, size
);
1252 tcg_gen_st8_i32(var
, cpu_env
, offset
);
1255 tcg_gen_st16_i32(var
, cpu_env
, offset
);
1258 tcg_gen_st_i32(var
, cpu_env
, offset
);
1261 g_assert_not_reached();
1265 static void neon_store_element64(int reg
, int ele
, MemOp size
, TCGv_i64 var
)
1267 long offset
= neon_element_offset(reg
, ele
, size
);
1271 tcg_gen_st8_i64(var
, cpu_env
, offset
);
1274 tcg_gen_st16_i64(var
, cpu_env
, offset
);
1277 tcg_gen_st32_i64(var
, cpu_env
, offset
);
1280 tcg_gen_st_i64(var
, cpu_env
, offset
);
1283 g_assert_not_reached();
1287 static inline void neon_load_reg64(TCGv_i64 var
, int reg
)
1289 tcg_gen_ld_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1292 static inline void neon_store_reg64(TCGv_i64 var
, int reg
)
1294 tcg_gen_st_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1297 static inline void neon_load_reg32(TCGv_i32 var
, int reg
)
1299 tcg_gen_ld_i32(var
, cpu_env
, vfp_reg_offset(false, reg
));
1302 static inline void neon_store_reg32(TCGv_i32 var
, int reg
)
1304 tcg_gen_st_i32(var
, cpu_env
, vfp_reg_offset(false, reg
));
1307 static TCGv_ptr
vfp_reg_ptr(bool dp
, int reg
)
1309 TCGv_ptr ret
= tcg_temp_new_ptr();
1310 tcg_gen_addi_ptr(ret
, cpu_env
, vfp_reg_offset(dp
, reg
));
1314 #define ARM_CP_RW_BIT (1 << 20)
1316 /* Include the VFP and Neon decoders */
1317 #include "translate-vfp.inc.c"
1318 #include "translate-neon.inc.c"
1320 static inline void iwmmxt_load_reg(TCGv_i64 var
, int reg
)
1322 tcg_gen_ld_i64(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.regs
[reg
]));
1325 static inline void iwmmxt_store_reg(TCGv_i64 var
, int reg
)
1327 tcg_gen_st_i64(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.regs
[reg
]));
1330 static inline TCGv_i32
iwmmxt_load_creg(int reg
)
1332 TCGv_i32 var
= tcg_temp_new_i32();
1333 tcg_gen_ld_i32(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.cregs
[reg
]));
1337 static inline void iwmmxt_store_creg(int reg
, TCGv_i32 var
)
1339 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.cregs
[reg
]));
1340 tcg_temp_free_i32(var
);
1343 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn
)
1345 iwmmxt_store_reg(cpu_M0
, rn
);
1348 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn
)
1350 iwmmxt_load_reg(cpu_M0
, rn
);
1353 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn
)
1355 iwmmxt_load_reg(cpu_V1
, rn
);
1356 tcg_gen_or_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1359 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn
)
1361 iwmmxt_load_reg(cpu_V1
, rn
);
1362 tcg_gen_and_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1365 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn
)
1367 iwmmxt_load_reg(cpu_V1
, rn
);
1368 tcg_gen_xor_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1371 #define IWMMXT_OP(name) \
1372 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1374 iwmmxt_load_reg(cpu_V1, rn); \
1375 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1378 #define IWMMXT_OP_ENV(name) \
1379 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1381 iwmmxt_load_reg(cpu_V1, rn); \
1382 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1385 #define IWMMXT_OP_ENV_SIZE(name) \
1386 IWMMXT_OP_ENV(name##b) \
1387 IWMMXT_OP_ENV(name##w) \
1388 IWMMXT_OP_ENV(name##l)
1390 #define IWMMXT_OP_ENV1(name) \
1391 static inline void gen_op_iwmmxt_##name##_M0(void) \
1393 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1407 IWMMXT_OP_ENV_SIZE(unpackl
)
1408 IWMMXT_OP_ENV_SIZE(unpackh
)
1410 IWMMXT_OP_ENV1(unpacklub
)
1411 IWMMXT_OP_ENV1(unpackluw
)
1412 IWMMXT_OP_ENV1(unpacklul
)
1413 IWMMXT_OP_ENV1(unpackhub
)
1414 IWMMXT_OP_ENV1(unpackhuw
)
1415 IWMMXT_OP_ENV1(unpackhul
)
1416 IWMMXT_OP_ENV1(unpacklsb
)
1417 IWMMXT_OP_ENV1(unpacklsw
)
1418 IWMMXT_OP_ENV1(unpacklsl
)
1419 IWMMXT_OP_ENV1(unpackhsb
)
1420 IWMMXT_OP_ENV1(unpackhsw
)
1421 IWMMXT_OP_ENV1(unpackhsl
)
1423 IWMMXT_OP_ENV_SIZE(cmpeq
)
1424 IWMMXT_OP_ENV_SIZE(cmpgtu
)
1425 IWMMXT_OP_ENV_SIZE(cmpgts
)
1427 IWMMXT_OP_ENV_SIZE(mins
)
1428 IWMMXT_OP_ENV_SIZE(minu
)
1429 IWMMXT_OP_ENV_SIZE(maxs
)
1430 IWMMXT_OP_ENV_SIZE(maxu
)
1432 IWMMXT_OP_ENV_SIZE(subn
)
1433 IWMMXT_OP_ENV_SIZE(addn
)
1434 IWMMXT_OP_ENV_SIZE(subu
)
1435 IWMMXT_OP_ENV_SIZE(addu
)
1436 IWMMXT_OP_ENV_SIZE(subs
)
1437 IWMMXT_OP_ENV_SIZE(adds
)
1439 IWMMXT_OP_ENV(avgb0
)
1440 IWMMXT_OP_ENV(avgb1
)
1441 IWMMXT_OP_ENV(avgw0
)
1442 IWMMXT_OP_ENV(avgw1
)
1444 IWMMXT_OP_ENV(packuw
)
1445 IWMMXT_OP_ENV(packul
)
1446 IWMMXT_OP_ENV(packuq
)
1447 IWMMXT_OP_ENV(packsw
)
1448 IWMMXT_OP_ENV(packsl
)
1449 IWMMXT_OP_ENV(packsq
)
1451 static void gen_op_iwmmxt_set_mup(void)
1454 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1455 tcg_gen_ori_i32(tmp
, tmp
, 2);
1456 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1459 static void gen_op_iwmmxt_set_cup(void)
1462 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1463 tcg_gen_ori_i32(tmp
, tmp
, 1);
1464 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1467 static void gen_op_iwmmxt_setpsr_nz(void)
1469 TCGv_i32 tmp
= tcg_temp_new_i32();
1470 gen_helper_iwmmxt_setpsr_nz(tmp
, cpu_M0
);
1471 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCASF
]);
1474 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn
)
1476 iwmmxt_load_reg(cpu_V1
, rn
);
1477 tcg_gen_ext32u_i64(cpu_V1
, cpu_V1
);
1478 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1481 static inline int gen_iwmmxt_address(DisasContext
*s
, uint32_t insn
,
1488 rd
= (insn
>> 16) & 0xf;
1489 tmp
= load_reg(s
, rd
);
1491 offset
= (insn
& 0xff) << ((insn
>> 7) & 2);
1492 if (insn
& (1 << 24)) {
1494 if (insn
& (1 << 23))
1495 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1497 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1498 tcg_gen_mov_i32(dest
, tmp
);
1499 if (insn
& (1 << 21))
1500 store_reg(s
, rd
, tmp
);
1502 tcg_temp_free_i32(tmp
);
1503 } else if (insn
& (1 << 21)) {
1505 tcg_gen_mov_i32(dest
, tmp
);
1506 if (insn
& (1 << 23))
1507 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1509 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1510 store_reg(s
, rd
, tmp
);
1511 } else if (!(insn
& (1 << 23)))
1516 static inline int gen_iwmmxt_shift(uint32_t insn
, uint32_t mask
, TCGv_i32 dest
)
1518 int rd
= (insn
>> 0) & 0xf;
1521 if (insn
& (1 << 8)) {
1522 if (rd
< ARM_IWMMXT_wCGR0
|| rd
> ARM_IWMMXT_wCGR3
) {
1525 tmp
= iwmmxt_load_creg(rd
);
1528 tmp
= tcg_temp_new_i32();
1529 iwmmxt_load_reg(cpu_V0
, rd
);
1530 tcg_gen_extrl_i64_i32(tmp
, cpu_V0
);
1532 tcg_gen_andi_i32(tmp
, tmp
, mask
);
1533 tcg_gen_mov_i32(dest
, tmp
);
1534 tcg_temp_free_i32(tmp
);
1538 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred
1539 (ie. an undefined instruction). */
1540 static int disas_iwmmxt_insn(DisasContext
*s
, uint32_t insn
)
1543 int rdhi
, rdlo
, rd0
, rd1
, i
;
1545 TCGv_i32 tmp
, tmp2
, tmp3
;
1547 if ((insn
& 0x0e000e00) == 0x0c000000) {
1548 if ((insn
& 0x0fe00ff0) == 0x0c400000) {
1550 rdlo
= (insn
>> 12) & 0xf;
1551 rdhi
= (insn
>> 16) & 0xf;
1552 if (insn
& ARM_CP_RW_BIT
) { /* TMRRC */
1553 iwmmxt_load_reg(cpu_V0
, wrd
);
1554 tcg_gen_extrl_i64_i32(cpu_R
[rdlo
], cpu_V0
);
1555 tcg_gen_extrh_i64_i32(cpu_R
[rdhi
], cpu_V0
);
1556 } else { /* TMCRR */
1557 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
1558 iwmmxt_store_reg(cpu_V0
, wrd
);
1559 gen_op_iwmmxt_set_mup();
1564 wrd
= (insn
>> 12) & 0xf;
1565 addr
= tcg_temp_new_i32();
1566 if (gen_iwmmxt_address(s
, insn
, addr
)) {
1567 tcg_temp_free_i32(addr
);
1570 if (insn
& ARM_CP_RW_BIT
) {
1571 if ((insn
>> 28) == 0xf) { /* WLDRW wCx */
1572 tmp
= tcg_temp_new_i32();
1573 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
1574 iwmmxt_store_creg(wrd
, tmp
);
1577 if (insn
& (1 << 8)) {
1578 if (insn
& (1 << 22)) { /* WLDRD */
1579 gen_aa32_ld64(s
, cpu_M0
, addr
, get_mem_index(s
));
1581 } else { /* WLDRW wRd */
1582 tmp
= tcg_temp_new_i32();
1583 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
1586 tmp
= tcg_temp_new_i32();
1587 if (insn
& (1 << 22)) { /* WLDRH */
1588 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
1589 } else { /* WLDRB */
1590 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
1594 tcg_gen_extu_i32_i64(cpu_M0
, tmp
);
1595 tcg_temp_free_i32(tmp
);
1597 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1600 if ((insn
>> 28) == 0xf) { /* WSTRW wCx */
1601 tmp
= iwmmxt_load_creg(wrd
);
1602 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
1604 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1605 tmp
= tcg_temp_new_i32();
1606 if (insn
& (1 << 8)) {
1607 if (insn
& (1 << 22)) { /* WSTRD */
1608 gen_aa32_st64(s
, cpu_M0
, addr
, get_mem_index(s
));
1609 } else { /* WSTRW wRd */
1610 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1611 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
1614 if (insn
& (1 << 22)) { /* WSTRH */
1615 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1616 gen_aa32_st16(s
, tmp
, addr
, get_mem_index(s
));
1617 } else { /* WSTRB */
1618 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1619 gen_aa32_st8(s
, tmp
, addr
, get_mem_index(s
));
1623 tcg_temp_free_i32(tmp
);
1625 tcg_temp_free_i32(addr
);
1629 if ((insn
& 0x0f000000) != 0x0e000000)
1632 switch (((insn
>> 12) & 0xf00) | ((insn
>> 4) & 0xff)) {
1633 case 0x000: /* WOR */
1634 wrd
= (insn
>> 12) & 0xf;
1635 rd0
= (insn
>> 0) & 0xf;
1636 rd1
= (insn
>> 16) & 0xf;
1637 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1638 gen_op_iwmmxt_orq_M0_wRn(rd1
);
1639 gen_op_iwmmxt_setpsr_nz();
1640 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1641 gen_op_iwmmxt_set_mup();
1642 gen_op_iwmmxt_set_cup();
1644 case 0x011: /* TMCR */
1647 rd
= (insn
>> 12) & 0xf;
1648 wrd
= (insn
>> 16) & 0xf;
1650 case ARM_IWMMXT_wCID
:
1651 case ARM_IWMMXT_wCASF
:
1653 case ARM_IWMMXT_wCon
:
1654 gen_op_iwmmxt_set_cup();
1656 case ARM_IWMMXT_wCSSF
:
1657 tmp
= iwmmxt_load_creg(wrd
);
1658 tmp2
= load_reg(s
, rd
);
1659 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
1660 tcg_temp_free_i32(tmp2
);
1661 iwmmxt_store_creg(wrd
, tmp
);
1663 case ARM_IWMMXT_wCGR0
:
1664 case ARM_IWMMXT_wCGR1
:
1665 case ARM_IWMMXT_wCGR2
:
1666 case ARM_IWMMXT_wCGR3
:
1667 gen_op_iwmmxt_set_cup();
1668 tmp
= load_reg(s
, rd
);
1669 iwmmxt_store_creg(wrd
, tmp
);
1675 case 0x100: /* WXOR */
1676 wrd
= (insn
>> 12) & 0xf;
1677 rd0
= (insn
>> 0) & 0xf;
1678 rd1
= (insn
>> 16) & 0xf;
1679 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1680 gen_op_iwmmxt_xorq_M0_wRn(rd1
);
1681 gen_op_iwmmxt_setpsr_nz();
1682 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1683 gen_op_iwmmxt_set_mup();
1684 gen_op_iwmmxt_set_cup();
1686 case 0x111: /* TMRC */
1689 rd
= (insn
>> 12) & 0xf;
1690 wrd
= (insn
>> 16) & 0xf;
1691 tmp
= iwmmxt_load_creg(wrd
);
1692 store_reg(s
, rd
, tmp
);
1694 case 0x300: /* WANDN */
1695 wrd
= (insn
>> 12) & 0xf;
1696 rd0
= (insn
>> 0) & 0xf;
1697 rd1
= (insn
>> 16) & 0xf;
1698 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1699 tcg_gen_neg_i64(cpu_M0
, cpu_M0
);
1700 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1701 gen_op_iwmmxt_setpsr_nz();
1702 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1703 gen_op_iwmmxt_set_mup();
1704 gen_op_iwmmxt_set_cup();
1706 case 0x200: /* WAND */
1707 wrd
= (insn
>> 12) & 0xf;
1708 rd0
= (insn
>> 0) & 0xf;
1709 rd1
= (insn
>> 16) & 0xf;
1710 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1711 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1712 gen_op_iwmmxt_setpsr_nz();
1713 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1714 gen_op_iwmmxt_set_mup();
1715 gen_op_iwmmxt_set_cup();
1717 case 0x810: case 0xa10: /* WMADD */
1718 wrd
= (insn
>> 12) & 0xf;
1719 rd0
= (insn
>> 0) & 0xf;
1720 rd1
= (insn
>> 16) & 0xf;
1721 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1722 if (insn
& (1 << 21))
1723 gen_op_iwmmxt_maddsq_M0_wRn(rd1
);
1725 gen_op_iwmmxt_madduq_M0_wRn(rd1
);
1726 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1727 gen_op_iwmmxt_set_mup();
1729 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1730 wrd
= (insn
>> 12) & 0xf;
1731 rd0
= (insn
>> 16) & 0xf;
1732 rd1
= (insn
>> 0) & 0xf;
1733 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1734 switch ((insn
>> 22) & 3) {
1736 gen_op_iwmmxt_unpacklb_M0_wRn(rd1
);
1739 gen_op_iwmmxt_unpacklw_M0_wRn(rd1
);
1742 gen_op_iwmmxt_unpackll_M0_wRn(rd1
);
1747 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1748 gen_op_iwmmxt_set_mup();
1749 gen_op_iwmmxt_set_cup();
1751 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1752 wrd
= (insn
>> 12) & 0xf;
1753 rd0
= (insn
>> 16) & 0xf;
1754 rd1
= (insn
>> 0) & 0xf;
1755 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1756 switch ((insn
>> 22) & 3) {
1758 gen_op_iwmmxt_unpackhb_M0_wRn(rd1
);
1761 gen_op_iwmmxt_unpackhw_M0_wRn(rd1
);
1764 gen_op_iwmmxt_unpackhl_M0_wRn(rd1
);
1769 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1770 gen_op_iwmmxt_set_mup();
1771 gen_op_iwmmxt_set_cup();
1773 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1774 wrd
= (insn
>> 12) & 0xf;
1775 rd0
= (insn
>> 16) & 0xf;
1776 rd1
= (insn
>> 0) & 0xf;
1777 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1778 if (insn
& (1 << 22))
1779 gen_op_iwmmxt_sadw_M0_wRn(rd1
);
1781 gen_op_iwmmxt_sadb_M0_wRn(rd1
);
1782 if (!(insn
& (1 << 20)))
1783 gen_op_iwmmxt_addl_M0_wRn(wrd
);
1784 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1785 gen_op_iwmmxt_set_mup();
1787 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1788 wrd
= (insn
>> 12) & 0xf;
1789 rd0
= (insn
>> 16) & 0xf;
1790 rd1
= (insn
>> 0) & 0xf;
1791 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1792 if (insn
& (1 << 21)) {
1793 if (insn
& (1 << 20))
1794 gen_op_iwmmxt_mulshw_M0_wRn(rd1
);
1796 gen_op_iwmmxt_mulslw_M0_wRn(rd1
);
1798 if (insn
& (1 << 20))
1799 gen_op_iwmmxt_muluhw_M0_wRn(rd1
);
1801 gen_op_iwmmxt_mululw_M0_wRn(rd1
);
1803 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1804 gen_op_iwmmxt_set_mup();
1806 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1807 wrd
= (insn
>> 12) & 0xf;
1808 rd0
= (insn
>> 16) & 0xf;
1809 rd1
= (insn
>> 0) & 0xf;
1810 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1811 if (insn
& (1 << 21))
1812 gen_op_iwmmxt_macsw_M0_wRn(rd1
);
1814 gen_op_iwmmxt_macuw_M0_wRn(rd1
);
1815 if (!(insn
& (1 << 20))) {
1816 iwmmxt_load_reg(cpu_V1
, wrd
);
1817 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1819 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1820 gen_op_iwmmxt_set_mup();
1822 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1823 wrd
= (insn
>> 12) & 0xf;
1824 rd0
= (insn
>> 16) & 0xf;
1825 rd1
= (insn
>> 0) & 0xf;
1826 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1827 switch ((insn
>> 22) & 3) {
1829 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1
);
1832 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1
);
1835 gen_op_iwmmxt_cmpeql_M0_wRn(rd1
);
1840 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1841 gen_op_iwmmxt_set_mup();
1842 gen_op_iwmmxt_set_cup();
1844 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1845 wrd
= (insn
>> 12) & 0xf;
1846 rd0
= (insn
>> 16) & 0xf;
1847 rd1
= (insn
>> 0) & 0xf;
1848 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1849 if (insn
& (1 << 22)) {
1850 if (insn
& (1 << 20))
1851 gen_op_iwmmxt_avgw1_M0_wRn(rd1
);
1853 gen_op_iwmmxt_avgw0_M0_wRn(rd1
);
1855 if (insn
& (1 << 20))
1856 gen_op_iwmmxt_avgb1_M0_wRn(rd1
);
1858 gen_op_iwmmxt_avgb0_M0_wRn(rd1
);
1860 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1861 gen_op_iwmmxt_set_mup();
1862 gen_op_iwmmxt_set_cup();
1864 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1865 wrd
= (insn
>> 12) & 0xf;
1866 rd0
= (insn
>> 16) & 0xf;
1867 rd1
= (insn
>> 0) & 0xf;
1868 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1869 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCGR0
+ ((insn
>> 20) & 3));
1870 tcg_gen_andi_i32(tmp
, tmp
, 7);
1871 iwmmxt_load_reg(cpu_V1
, rd1
);
1872 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
1873 tcg_temp_free_i32(tmp
);
1874 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1875 gen_op_iwmmxt_set_mup();
1877 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1878 if (((insn
>> 6) & 3) == 3)
1880 rd
= (insn
>> 12) & 0xf;
1881 wrd
= (insn
>> 16) & 0xf;
1882 tmp
= load_reg(s
, rd
);
1883 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1884 switch ((insn
>> 6) & 3) {
1886 tmp2
= tcg_const_i32(0xff);
1887 tmp3
= tcg_const_i32((insn
& 7) << 3);
1890 tmp2
= tcg_const_i32(0xffff);
1891 tmp3
= tcg_const_i32((insn
& 3) << 4);
1894 tmp2
= tcg_const_i32(0xffffffff);
1895 tmp3
= tcg_const_i32((insn
& 1) << 5);
1901 gen_helper_iwmmxt_insr(cpu_M0
, cpu_M0
, tmp
, tmp2
, tmp3
);
1902 tcg_temp_free_i32(tmp3
);
1903 tcg_temp_free_i32(tmp2
);
1904 tcg_temp_free_i32(tmp
);
1905 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1906 gen_op_iwmmxt_set_mup();
1908 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1909 rd
= (insn
>> 12) & 0xf;
1910 wrd
= (insn
>> 16) & 0xf;
1911 if (rd
== 15 || ((insn
>> 22) & 3) == 3)
1913 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1914 tmp
= tcg_temp_new_i32();
1915 switch ((insn
>> 22) & 3) {
1917 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 7) << 3);
1918 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1920 tcg_gen_ext8s_i32(tmp
, tmp
);
1922 tcg_gen_andi_i32(tmp
, tmp
, 0xff);
1926 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 3) << 4);
1927 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1929 tcg_gen_ext16s_i32(tmp
, tmp
);
1931 tcg_gen_andi_i32(tmp
, tmp
, 0xffff);
1935 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 1) << 5);
1936 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1939 store_reg(s
, rd
, tmp
);
1941 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1942 if ((insn
& 0x000ff008) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1944 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1945 switch ((insn
>> 22) & 3) {
1947 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 7) << 2) + 0);
1950 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 3) << 3) + 4);
1953 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 1) << 4) + 12);
1956 tcg_gen_shli_i32(tmp
, tmp
, 28);
1958 tcg_temp_free_i32(tmp
);
1960 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1961 if (((insn
>> 6) & 3) == 3)
1963 rd
= (insn
>> 12) & 0xf;
1964 wrd
= (insn
>> 16) & 0xf;
1965 tmp
= load_reg(s
, rd
);
1966 switch ((insn
>> 6) & 3) {
1968 gen_helper_iwmmxt_bcstb(cpu_M0
, tmp
);
1971 gen_helper_iwmmxt_bcstw(cpu_M0
, tmp
);
1974 gen_helper_iwmmxt_bcstl(cpu_M0
, tmp
);
1977 tcg_temp_free_i32(tmp
);
1978 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1979 gen_op_iwmmxt_set_mup();
1981 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1982 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1984 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1985 tmp2
= tcg_temp_new_i32();
1986 tcg_gen_mov_i32(tmp2
, tmp
);
1987 switch ((insn
>> 22) & 3) {
1989 for (i
= 0; i
< 7; i
++) {
1990 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
1991 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1995 for (i
= 0; i
< 3; i
++) {
1996 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
1997 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
2001 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
2002 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
2006 tcg_temp_free_i32(tmp2
);
2007 tcg_temp_free_i32(tmp
);
2009 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
2010 wrd
= (insn
>> 12) & 0xf;
2011 rd0
= (insn
>> 16) & 0xf;
2012 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2013 switch ((insn
>> 22) & 3) {
2015 gen_helper_iwmmxt_addcb(cpu_M0
, cpu_M0
);
2018 gen_helper_iwmmxt_addcw(cpu_M0
, cpu_M0
);
2021 gen_helper_iwmmxt_addcl(cpu_M0
, cpu_M0
);
2026 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2027 gen_op_iwmmxt_set_mup();
2029 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
2030 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
2032 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
2033 tmp2
= tcg_temp_new_i32();
2034 tcg_gen_mov_i32(tmp2
, tmp
);
2035 switch ((insn
>> 22) & 3) {
2037 for (i
= 0; i
< 7; i
++) {
2038 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
2039 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2043 for (i
= 0; i
< 3; i
++) {
2044 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
2045 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2049 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
2050 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2054 tcg_temp_free_i32(tmp2
);
2055 tcg_temp_free_i32(tmp
);
2057 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
2058 rd
= (insn
>> 12) & 0xf;
2059 rd0
= (insn
>> 16) & 0xf;
2060 if ((insn
& 0xf) != 0 || ((insn
>> 22) & 3) == 3)
2062 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2063 tmp
= tcg_temp_new_i32();
2064 switch ((insn
>> 22) & 3) {
2066 gen_helper_iwmmxt_msbb(tmp
, cpu_M0
);
2069 gen_helper_iwmmxt_msbw(tmp
, cpu_M0
);
2072 gen_helper_iwmmxt_msbl(tmp
, cpu_M0
);
2075 store_reg(s
, rd
, tmp
);
2077 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
2078 case 0x906: case 0xb06: case 0xd06: case 0xf06:
2079 wrd
= (insn
>> 12) & 0xf;
2080 rd0
= (insn
>> 16) & 0xf;
2081 rd1
= (insn
>> 0) & 0xf;
2082 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2083 switch ((insn
>> 22) & 3) {
2085 if (insn
& (1 << 21))
2086 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1
);
2088 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1
);
2091 if (insn
& (1 << 21))
2092 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1
);
2094 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1
);
2097 if (insn
& (1 << 21))
2098 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1
);
2100 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1
);
2105 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2106 gen_op_iwmmxt_set_mup();
2107 gen_op_iwmmxt_set_cup();
2109 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
2110 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
2111 wrd
= (insn
>> 12) & 0xf;
2112 rd0
= (insn
>> 16) & 0xf;
2113 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2114 switch ((insn
>> 22) & 3) {
2116 if (insn
& (1 << 21))
2117 gen_op_iwmmxt_unpacklsb_M0();
2119 gen_op_iwmmxt_unpacklub_M0();
2122 if (insn
& (1 << 21))
2123 gen_op_iwmmxt_unpacklsw_M0();
2125 gen_op_iwmmxt_unpackluw_M0();
2128 if (insn
& (1 << 21))
2129 gen_op_iwmmxt_unpacklsl_M0();
2131 gen_op_iwmmxt_unpacklul_M0();
2136 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2137 gen_op_iwmmxt_set_mup();
2138 gen_op_iwmmxt_set_cup();
2140 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
2141 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
2142 wrd
= (insn
>> 12) & 0xf;
2143 rd0
= (insn
>> 16) & 0xf;
2144 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2145 switch ((insn
>> 22) & 3) {
2147 if (insn
& (1 << 21))
2148 gen_op_iwmmxt_unpackhsb_M0();
2150 gen_op_iwmmxt_unpackhub_M0();
2153 if (insn
& (1 << 21))
2154 gen_op_iwmmxt_unpackhsw_M0();
2156 gen_op_iwmmxt_unpackhuw_M0();
2159 if (insn
& (1 << 21))
2160 gen_op_iwmmxt_unpackhsl_M0();
2162 gen_op_iwmmxt_unpackhul_M0();
2167 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2168 gen_op_iwmmxt_set_mup();
2169 gen_op_iwmmxt_set_cup();
2171 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
2172 case 0x214: case 0x614: case 0xa14: case 0xe14:
2173 if (((insn
>> 22) & 3) == 0)
2175 wrd
= (insn
>> 12) & 0xf;
2176 rd0
= (insn
>> 16) & 0xf;
2177 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2178 tmp
= tcg_temp_new_i32();
2179 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2180 tcg_temp_free_i32(tmp
);
2183 switch ((insn
>> 22) & 3) {
2185 gen_helper_iwmmxt_srlw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2188 gen_helper_iwmmxt_srll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2191 gen_helper_iwmmxt_srlq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2194 tcg_temp_free_i32(tmp
);
2195 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2196 gen_op_iwmmxt_set_mup();
2197 gen_op_iwmmxt_set_cup();
2199 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2200 case 0x014: case 0x414: case 0x814: case 0xc14:
2201 if (((insn
>> 22) & 3) == 0)
2203 wrd
= (insn
>> 12) & 0xf;
2204 rd0
= (insn
>> 16) & 0xf;
2205 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2206 tmp
= tcg_temp_new_i32();
2207 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2208 tcg_temp_free_i32(tmp
);
2211 switch ((insn
>> 22) & 3) {
2213 gen_helper_iwmmxt_sraw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2216 gen_helper_iwmmxt_sral(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2219 gen_helper_iwmmxt_sraq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2222 tcg_temp_free_i32(tmp
);
2223 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2224 gen_op_iwmmxt_set_mup();
2225 gen_op_iwmmxt_set_cup();
2227 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2228 case 0x114: case 0x514: case 0x914: case 0xd14:
2229 if (((insn
>> 22) & 3) == 0)
2231 wrd
= (insn
>> 12) & 0xf;
2232 rd0
= (insn
>> 16) & 0xf;
2233 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2234 tmp
= tcg_temp_new_i32();
2235 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2236 tcg_temp_free_i32(tmp
);
2239 switch ((insn
>> 22) & 3) {
2241 gen_helper_iwmmxt_sllw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2244 gen_helper_iwmmxt_slll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2247 gen_helper_iwmmxt_sllq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2250 tcg_temp_free_i32(tmp
);
2251 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2252 gen_op_iwmmxt_set_mup();
2253 gen_op_iwmmxt_set_cup();
2255 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2256 case 0x314: case 0x714: case 0xb14: case 0xf14:
2257 if (((insn
>> 22) & 3) == 0)
2259 wrd
= (insn
>> 12) & 0xf;
2260 rd0
= (insn
>> 16) & 0xf;
2261 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2262 tmp
= tcg_temp_new_i32();
2263 switch ((insn
>> 22) & 3) {
2265 if (gen_iwmmxt_shift(insn
, 0xf, tmp
)) {
2266 tcg_temp_free_i32(tmp
);
2269 gen_helper_iwmmxt_rorw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2272 if (gen_iwmmxt_shift(insn
, 0x1f, tmp
)) {
2273 tcg_temp_free_i32(tmp
);
2276 gen_helper_iwmmxt_rorl(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2279 if (gen_iwmmxt_shift(insn
, 0x3f, tmp
)) {
2280 tcg_temp_free_i32(tmp
);
2283 gen_helper_iwmmxt_rorq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2286 tcg_temp_free_i32(tmp
);
2287 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2288 gen_op_iwmmxt_set_mup();
2289 gen_op_iwmmxt_set_cup();
2291 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2292 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2293 wrd
= (insn
>> 12) & 0xf;
2294 rd0
= (insn
>> 16) & 0xf;
2295 rd1
= (insn
>> 0) & 0xf;
2296 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2297 switch ((insn
>> 22) & 3) {
2299 if (insn
& (1 << 21))
2300 gen_op_iwmmxt_minsb_M0_wRn(rd1
);
2302 gen_op_iwmmxt_minub_M0_wRn(rd1
);
2305 if (insn
& (1 << 21))
2306 gen_op_iwmmxt_minsw_M0_wRn(rd1
);
2308 gen_op_iwmmxt_minuw_M0_wRn(rd1
);
2311 if (insn
& (1 << 21))
2312 gen_op_iwmmxt_minsl_M0_wRn(rd1
);
2314 gen_op_iwmmxt_minul_M0_wRn(rd1
);
2319 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2320 gen_op_iwmmxt_set_mup();
2322 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2323 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2324 wrd
= (insn
>> 12) & 0xf;
2325 rd0
= (insn
>> 16) & 0xf;
2326 rd1
= (insn
>> 0) & 0xf;
2327 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2328 switch ((insn
>> 22) & 3) {
2330 if (insn
& (1 << 21))
2331 gen_op_iwmmxt_maxsb_M0_wRn(rd1
);
2333 gen_op_iwmmxt_maxub_M0_wRn(rd1
);
2336 if (insn
& (1 << 21))
2337 gen_op_iwmmxt_maxsw_M0_wRn(rd1
);
2339 gen_op_iwmmxt_maxuw_M0_wRn(rd1
);
2342 if (insn
& (1 << 21))
2343 gen_op_iwmmxt_maxsl_M0_wRn(rd1
);
2345 gen_op_iwmmxt_maxul_M0_wRn(rd1
);
2350 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2351 gen_op_iwmmxt_set_mup();
2353 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2354 case 0x402: case 0x502: case 0x602: case 0x702:
2355 wrd
= (insn
>> 12) & 0xf;
2356 rd0
= (insn
>> 16) & 0xf;
2357 rd1
= (insn
>> 0) & 0xf;
2358 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2359 tmp
= tcg_const_i32((insn
>> 20) & 3);
2360 iwmmxt_load_reg(cpu_V1
, rd1
);
2361 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
2362 tcg_temp_free_i32(tmp
);
2363 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2364 gen_op_iwmmxt_set_mup();
2366 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2367 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2368 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2369 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2370 wrd
= (insn
>> 12) & 0xf;
2371 rd0
= (insn
>> 16) & 0xf;
2372 rd1
= (insn
>> 0) & 0xf;
2373 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2374 switch ((insn
>> 20) & 0xf) {
2376 gen_op_iwmmxt_subnb_M0_wRn(rd1
);
2379 gen_op_iwmmxt_subub_M0_wRn(rd1
);
2382 gen_op_iwmmxt_subsb_M0_wRn(rd1
);
2385 gen_op_iwmmxt_subnw_M0_wRn(rd1
);
2388 gen_op_iwmmxt_subuw_M0_wRn(rd1
);
2391 gen_op_iwmmxt_subsw_M0_wRn(rd1
);
2394 gen_op_iwmmxt_subnl_M0_wRn(rd1
);
2397 gen_op_iwmmxt_subul_M0_wRn(rd1
);
2400 gen_op_iwmmxt_subsl_M0_wRn(rd1
);
2405 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2406 gen_op_iwmmxt_set_mup();
2407 gen_op_iwmmxt_set_cup();
2409 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2410 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2411 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2412 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2413 wrd
= (insn
>> 12) & 0xf;
2414 rd0
= (insn
>> 16) & 0xf;
2415 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2416 tmp
= tcg_const_i32(((insn
>> 16) & 0xf0) | (insn
& 0x0f));
2417 gen_helper_iwmmxt_shufh(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2418 tcg_temp_free_i32(tmp
);
2419 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2420 gen_op_iwmmxt_set_mup();
2421 gen_op_iwmmxt_set_cup();
2423 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2424 case 0x418: case 0x518: case 0x618: case 0x718:
2425 case 0x818: case 0x918: case 0xa18: case 0xb18:
2426 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2427 wrd
= (insn
>> 12) & 0xf;
2428 rd0
= (insn
>> 16) & 0xf;
2429 rd1
= (insn
>> 0) & 0xf;
2430 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2431 switch ((insn
>> 20) & 0xf) {
2433 gen_op_iwmmxt_addnb_M0_wRn(rd1
);
2436 gen_op_iwmmxt_addub_M0_wRn(rd1
);
2439 gen_op_iwmmxt_addsb_M0_wRn(rd1
);
2442 gen_op_iwmmxt_addnw_M0_wRn(rd1
);
2445 gen_op_iwmmxt_adduw_M0_wRn(rd1
);
2448 gen_op_iwmmxt_addsw_M0_wRn(rd1
);
2451 gen_op_iwmmxt_addnl_M0_wRn(rd1
);
2454 gen_op_iwmmxt_addul_M0_wRn(rd1
);
2457 gen_op_iwmmxt_addsl_M0_wRn(rd1
);
2462 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2463 gen_op_iwmmxt_set_mup();
2464 gen_op_iwmmxt_set_cup();
2466 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2467 case 0x408: case 0x508: case 0x608: case 0x708:
2468 case 0x808: case 0x908: case 0xa08: case 0xb08:
2469 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2470 if (!(insn
& (1 << 20)) || ((insn
>> 22) & 3) == 0)
2472 wrd
= (insn
>> 12) & 0xf;
2473 rd0
= (insn
>> 16) & 0xf;
2474 rd1
= (insn
>> 0) & 0xf;
2475 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2476 switch ((insn
>> 22) & 3) {
2478 if (insn
& (1 << 21))
2479 gen_op_iwmmxt_packsw_M0_wRn(rd1
);
2481 gen_op_iwmmxt_packuw_M0_wRn(rd1
);
2484 if (insn
& (1 << 21))
2485 gen_op_iwmmxt_packsl_M0_wRn(rd1
);
2487 gen_op_iwmmxt_packul_M0_wRn(rd1
);
2490 if (insn
& (1 << 21))
2491 gen_op_iwmmxt_packsq_M0_wRn(rd1
);
2493 gen_op_iwmmxt_packuq_M0_wRn(rd1
);
2496 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2497 gen_op_iwmmxt_set_mup();
2498 gen_op_iwmmxt_set_cup();
2500 case 0x201: case 0x203: case 0x205: case 0x207:
2501 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2502 case 0x211: case 0x213: case 0x215: case 0x217:
2503 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2504 wrd
= (insn
>> 5) & 0xf;
2505 rd0
= (insn
>> 12) & 0xf;
2506 rd1
= (insn
>> 0) & 0xf;
2507 if (rd0
== 0xf || rd1
== 0xf)
2509 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2510 tmp
= load_reg(s
, rd0
);
2511 tmp2
= load_reg(s
, rd1
);
2512 switch ((insn
>> 16) & 0xf) {
2513 case 0x0: /* TMIA */
2514 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2516 case 0x8: /* TMIAPH */
2517 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2519 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2520 if (insn
& (1 << 16))
2521 tcg_gen_shri_i32(tmp
, tmp
, 16);
2522 if (insn
& (1 << 17))
2523 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2524 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2527 tcg_temp_free_i32(tmp2
);
2528 tcg_temp_free_i32(tmp
);
2531 tcg_temp_free_i32(tmp2
);
2532 tcg_temp_free_i32(tmp
);
2533 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2534 gen_op_iwmmxt_set_mup();
2543 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred
2544 (ie. an undefined instruction). */
2545 static int disas_dsp_insn(DisasContext
*s
, uint32_t insn
)
2547 int acc
, rd0
, rd1
, rdhi
, rdlo
;
2550 if ((insn
& 0x0ff00f10) == 0x0e200010) {
2551 /* Multiply with Internal Accumulate Format */
2552 rd0
= (insn
>> 12) & 0xf;
2554 acc
= (insn
>> 5) & 7;
2559 tmp
= load_reg(s
, rd0
);
2560 tmp2
= load_reg(s
, rd1
);
2561 switch ((insn
>> 16) & 0xf) {
2563 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2565 case 0x8: /* MIAPH */
2566 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2568 case 0xc: /* MIABB */
2569 case 0xd: /* MIABT */
2570 case 0xe: /* MIATB */
2571 case 0xf: /* MIATT */
2572 if (insn
& (1 << 16))
2573 tcg_gen_shri_i32(tmp
, tmp
, 16);
2574 if (insn
& (1 << 17))
2575 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2576 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2581 tcg_temp_free_i32(tmp2
);
2582 tcg_temp_free_i32(tmp
);
2584 gen_op_iwmmxt_movq_wRn_M0(acc
);
2588 if ((insn
& 0x0fe00ff8) == 0x0c400000) {
2589 /* Internal Accumulator Access Format */
2590 rdhi
= (insn
>> 16) & 0xf;
2591 rdlo
= (insn
>> 12) & 0xf;
2597 if (insn
& ARM_CP_RW_BIT
) { /* MRA */
2598 iwmmxt_load_reg(cpu_V0
, acc
);
2599 tcg_gen_extrl_i64_i32(cpu_R
[rdlo
], cpu_V0
);
2600 tcg_gen_extrh_i64_i32(cpu_R
[rdhi
], cpu_V0
);
2601 tcg_gen_andi_i32(cpu_R
[rdhi
], cpu_R
[rdhi
], (1 << (40 - 32)) - 1);
2603 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
2604 iwmmxt_store_reg(cpu_V0
, acc
);
2612 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2613 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2614 if (dc_isar_feature(aa32_simd_r32, s)) { \
2615 reg = (((insn) >> (bigbit)) & 0x0f) \
2616 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2618 if (insn & (1 << (smallbit))) \
2620 reg = ((insn) >> (bigbit)) & 0x0f; \
2623 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2624 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2625 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2627 static void gen_neon_dup_low16(TCGv_i32 var
)
2629 TCGv_i32 tmp
= tcg_temp_new_i32();
2630 tcg_gen_ext16u_i32(var
, var
);
2631 tcg_gen_shli_i32(tmp
, var
, 16);
2632 tcg_gen_or_i32(var
, var
, tmp
);
2633 tcg_temp_free_i32(tmp
);
2636 static void gen_neon_dup_high16(TCGv_i32 var
)
2638 TCGv_i32 tmp
= tcg_temp_new_i32();
2639 tcg_gen_andi_i32(var
, var
, 0xffff0000);
2640 tcg_gen_shri_i32(tmp
, var
, 16);
2641 tcg_gen_or_i32(var
, var
, tmp
);
2642 tcg_temp_free_i32(tmp
);
2645 static inline bool use_goto_tb(DisasContext
*s
, target_ulong dest
)
2647 #ifndef CONFIG_USER_ONLY
2648 return (s
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
2649 ((s
->base
.pc_next
- 1) & TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
2655 static void gen_goto_ptr(void)
2657 tcg_gen_lookup_and_goto_ptr();
2660 /* This will end the TB but doesn't guarantee we'll return to
2661 * cpu_loop_exec. Any live exit_requests will be processed as we
2662 * enter the next TB.
2664 static void gen_goto_tb(DisasContext
*s
, int n
, target_ulong dest
)
2666 if (use_goto_tb(s
, dest
)) {
2668 gen_set_pc_im(s
, dest
);
2669 tcg_gen_exit_tb(s
->base
.tb
, n
);
2671 gen_set_pc_im(s
, dest
);
2674 s
->base
.is_jmp
= DISAS_NORETURN
;
2677 static inline void gen_jmp (DisasContext
*s
, uint32_t dest
)
2679 if (unlikely(is_singlestepping(s
))) {
2680 /* An indirect jump so that we still trigger the debug exception. */
2681 gen_set_pc_im(s
, dest
);
2682 s
->base
.is_jmp
= DISAS_JUMP
;
2684 gen_goto_tb(s
, 0, dest
);
2688 static inline void gen_mulxy(TCGv_i32 t0
, TCGv_i32 t1
, int x
, int y
)
2691 tcg_gen_sari_i32(t0
, t0
, 16);
2695 tcg_gen_sari_i32(t1
, t1
, 16);
2698 tcg_gen_mul_i32(t0
, t0
, t1
);
2701 /* Return the mask of PSR bits set by a MSR instruction. */
2702 static uint32_t msr_mask(DisasContext
*s
, int flags
, int spsr
)
2706 if (flags
& (1 << 0)) {
2709 if (flags
& (1 << 1)) {
2712 if (flags
& (1 << 2)) {
2715 if (flags
& (1 << 3)) {
2719 /* Mask out undefined and reserved bits. */
2720 mask
&= aarch32_cpsr_valid_mask(s
->features
, s
->isar
);
2722 /* Mask out execution state. */
2727 /* Mask out privileged bits. */
2734 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
2735 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int spsr
, TCGv_i32 t0
)
2739 /* ??? This is also undefined in system mode. */
2743 tmp
= load_cpu_field(spsr
);
2744 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
2745 tcg_gen_andi_i32(t0
, t0
, mask
);
2746 tcg_gen_or_i32(tmp
, tmp
, t0
);
2747 store_cpu_field(tmp
, spsr
);
2749 gen_set_cpsr(t0
, mask
);
2751 tcg_temp_free_i32(t0
);
2756 /* Returns nonzero if access to the PSR is not permitted. */
2757 static int gen_set_psr_im(DisasContext
*s
, uint32_t mask
, int spsr
, uint32_t val
)
2760 tmp
= tcg_temp_new_i32();
2761 tcg_gen_movi_i32(tmp
, val
);
2762 return gen_set_psr(s
, mask
, spsr
, tmp
);
2765 static bool msr_banked_access_decode(DisasContext
*s
, int r
, int sysm
, int rn
,
2766 int *tgtmode
, int *regno
)
2768 /* Decode the r and sysm fields of MSR/MRS banked accesses into
2769 * the target mode and register number, and identify the various
2770 * unpredictable cases.
2771 * MSR (banked) and MRS (banked) are CONSTRAINED UNPREDICTABLE if:
2772 * + executed in user mode
2773 * + using R15 as the src/dest register
2774 * + accessing an unimplemented register
2775 * + accessing a register that's inaccessible at current PL/security state*
2776 * + accessing a register that you could access with a different insn
2777 * We choose to UNDEF in all these cases.
2778 * Since we don't know which of the various AArch32 modes we are in
2779 * we have to defer some checks to runtime.
2780 * Accesses to Monitor mode registers from Secure EL1 (which implies
2781 * that EL3 is AArch64) must trap to EL3.
2783 * If the access checks fail this function will emit code to take
2784 * an exception and return false. Otherwise it will return true,
2785 * and set *tgtmode and *regno appropriately.
2787 int exc_target
= default_exception_el(s
);
2789 /* These instructions are present only in ARMv8, or in ARMv7 with the
2790 * Virtualization Extensions.
2792 if (!arm_dc_feature(s
, ARM_FEATURE_V8
) &&
2793 !arm_dc_feature(s
, ARM_FEATURE_EL2
)) {
2797 if (IS_USER(s
) || rn
== 15) {
2801 /* The table in the v8 ARM ARM section F5.2.3 describes the encoding
2802 * of registers into (r, sysm).
2805 /* SPSRs for other modes */
2807 case 0xe: /* SPSR_fiq */
2808 *tgtmode
= ARM_CPU_MODE_FIQ
;
2810 case 0x10: /* SPSR_irq */
2811 *tgtmode
= ARM_CPU_MODE_IRQ
;
2813 case 0x12: /* SPSR_svc */
2814 *tgtmode
= ARM_CPU_MODE_SVC
;
2816 case 0x14: /* SPSR_abt */
2817 *tgtmode
= ARM_CPU_MODE_ABT
;
2819 case 0x16: /* SPSR_und */
2820 *tgtmode
= ARM_CPU_MODE_UND
;
2822 case 0x1c: /* SPSR_mon */
2823 *tgtmode
= ARM_CPU_MODE_MON
;
2825 case 0x1e: /* SPSR_hyp */
2826 *tgtmode
= ARM_CPU_MODE_HYP
;
2828 default: /* unallocated */
2831 /* We arbitrarily assign SPSR a register number of 16. */
2834 /* general purpose registers for other modes */
2836 case 0x0 ... 0x6: /* 0b00xxx : r8_usr ... r14_usr */
2837 *tgtmode
= ARM_CPU_MODE_USR
;
2840 case 0x8 ... 0xe: /* 0b01xxx : r8_fiq ... r14_fiq */
2841 *tgtmode
= ARM_CPU_MODE_FIQ
;
2844 case 0x10 ... 0x11: /* 0b1000x : r14_irq, r13_irq */
2845 *tgtmode
= ARM_CPU_MODE_IRQ
;
2846 *regno
= sysm
& 1 ? 13 : 14;
2848 case 0x12 ... 0x13: /* 0b1001x : r14_svc, r13_svc */
2849 *tgtmode
= ARM_CPU_MODE_SVC
;
2850 *regno
= sysm
& 1 ? 13 : 14;
2852 case 0x14 ... 0x15: /* 0b1010x : r14_abt, r13_abt */
2853 *tgtmode
= ARM_CPU_MODE_ABT
;
2854 *regno
= sysm
& 1 ? 13 : 14;
2856 case 0x16 ... 0x17: /* 0b1011x : r14_und, r13_und */
2857 *tgtmode
= ARM_CPU_MODE_UND
;
2858 *regno
= sysm
& 1 ? 13 : 14;
2860 case 0x1c ... 0x1d: /* 0b1110x : r14_mon, r13_mon */
2861 *tgtmode
= ARM_CPU_MODE_MON
;
2862 *regno
= sysm
& 1 ? 13 : 14;
2864 case 0x1e ... 0x1f: /* 0b1111x : elr_hyp, r13_hyp */
2865 *tgtmode
= ARM_CPU_MODE_HYP
;
2866 /* Arbitrarily pick 17 for ELR_Hyp (which is not a banked LR!) */
2867 *regno
= sysm
& 1 ? 13 : 17;
2869 default: /* unallocated */
2874 /* Catch the 'accessing inaccessible register' cases we can detect
2875 * at translate time.
2878 case ARM_CPU_MODE_MON
:
2879 if (!arm_dc_feature(s
, ARM_FEATURE_EL3
) || s
->ns
) {
2882 if (s
->current_el
== 1) {
2883 /* If we're in Secure EL1 (which implies that EL3 is AArch64)
2884 * then accesses to Mon registers trap to EL3
2890 case ARM_CPU_MODE_HYP
:
2892 * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
2893 * (and so we can forbid accesses from EL2 or below). elr_hyp
2894 * can be accessed also from Hyp mode, so forbid accesses from
2897 if (!arm_dc_feature(s
, ARM_FEATURE_EL2
) || s
->current_el
< 2 ||
2898 (s
->current_el
< 3 && *regno
!= 17)) {
2909 /* If we get here then some access check did not pass */
2910 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
2911 syn_uncategorized(), exc_target
);
2915 static void gen_msr_banked(DisasContext
*s
, int r
, int sysm
, int rn
)
2917 TCGv_i32 tcg_reg
, tcg_tgtmode
, tcg_regno
;
2918 int tgtmode
= 0, regno
= 0;
2920 if (!msr_banked_access_decode(s
, r
, sysm
, rn
, &tgtmode
, ®no
)) {
2924 /* Sync state because msr_banked() can raise exceptions */
2925 gen_set_condexec(s
);
2926 gen_set_pc_im(s
, s
->pc_curr
);
2927 tcg_reg
= load_reg(s
, rn
);
2928 tcg_tgtmode
= tcg_const_i32(tgtmode
);
2929 tcg_regno
= tcg_const_i32(regno
);
2930 gen_helper_msr_banked(cpu_env
, tcg_reg
, tcg_tgtmode
, tcg_regno
);
2931 tcg_temp_free_i32(tcg_tgtmode
);
2932 tcg_temp_free_i32(tcg_regno
);
2933 tcg_temp_free_i32(tcg_reg
);
2934 s
->base
.is_jmp
= DISAS_UPDATE
;
2937 static void gen_mrs_banked(DisasContext
*s
, int r
, int sysm
, int rn
)
2939 TCGv_i32 tcg_reg
, tcg_tgtmode
, tcg_regno
;
2940 int tgtmode
= 0, regno
= 0;
2942 if (!msr_banked_access_decode(s
, r
, sysm
, rn
, &tgtmode
, ®no
)) {
2946 /* Sync state because mrs_banked() can raise exceptions */
2947 gen_set_condexec(s
);
2948 gen_set_pc_im(s
, s
->pc_curr
);
2949 tcg_reg
= tcg_temp_new_i32();
2950 tcg_tgtmode
= tcg_const_i32(tgtmode
);
2951 tcg_regno
= tcg_const_i32(regno
);
2952 gen_helper_mrs_banked(tcg_reg
, cpu_env
, tcg_tgtmode
, tcg_regno
);
2953 tcg_temp_free_i32(tcg_tgtmode
);
2954 tcg_temp_free_i32(tcg_regno
);
2955 store_reg(s
, rn
, tcg_reg
);
2956 s
->base
.is_jmp
= DISAS_UPDATE
;
2959 /* Store value to PC as for an exception return (ie don't
2960 * mask bits). The subsequent call to gen_helper_cpsr_write_eret()
2961 * will do the masking based on the new value of the Thumb bit.
2963 static void store_pc_exc_ret(DisasContext
*s
, TCGv_i32 pc
)
2965 tcg_gen_mov_i32(cpu_R
[15], pc
);
2966 tcg_temp_free_i32(pc
);
2969 /* Generate a v6 exception return. Marks both values as dead. */
2970 static void gen_rfe(DisasContext
*s
, TCGv_i32 pc
, TCGv_i32 cpsr
)
2972 store_pc_exc_ret(s
, pc
);
2973 /* The cpsr_write_eret helper will mask the low bits of PC
2974 * appropriately depending on the new Thumb bit, so it must
2975 * be called after storing the new PC.
2977 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2980 gen_helper_cpsr_write_eret(cpu_env
, cpsr
);
2981 tcg_temp_free_i32(cpsr
);
2982 /* Must exit loop to check un-masked IRQs */
2983 s
->base
.is_jmp
= DISAS_EXIT
;
2986 /* Generate an old-style exception return. Marks pc as dead. */
2987 static void gen_exception_return(DisasContext
*s
, TCGv_i32 pc
)
2989 gen_rfe(s
, pc
, load_cpu_field(spsr
));
2992 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
2994 static inline void gen_neon_add(int size
, TCGv_i32 t0
, TCGv_i32 t1
)
2997 case 0: gen_helper_neon_add_u8(t0
, t0
, t1
); break;
2998 case 1: gen_helper_neon_add_u16(t0
, t0
, t1
); break;
2999 case 2: tcg_gen_add_i32(t0
, t0
, t1
); break;
3004 static inline void gen_neon_rsb(int size
, TCGv_i32 t0
, TCGv_i32 t1
)
3007 case 0: gen_helper_neon_sub_u8(t0
, t1
, t0
); break;
3008 case 1: gen_helper_neon_sub_u16(t0
, t1
, t0
); break;
3009 case 2: tcg_gen_sub_i32(t0
, t1
, t0
); break;
3014 static TCGv_i32
neon_load_scratch(int scratch
)
3016 TCGv_i32 tmp
= tcg_temp_new_i32();
3017 tcg_gen_ld_i32(tmp
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3021 static void neon_store_scratch(int scratch
, TCGv_i32 var
)
3023 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3024 tcg_temp_free_i32(var
);
3027 static inline TCGv_i32
neon_get_scalar(int size
, int reg
)
3031 tmp
= neon_load_reg(reg
& 7, reg
>> 4);
3033 gen_neon_dup_high16(tmp
);
3035 gen_neon_dup_low16(tmp
);
3038 tmp
= neon_load_reg(reg
& 15, reg
>> 4);
3043 static int gen_neon_unzip(int rd
, int rm
, int size
, int q
)
3047 if (!q
&& size
== 2) {
3050 pd
= vfp_reg_ptr(true, rd
);
3051 pm
= vfp_reg_ptr(true, rm
);
3055 gen_helper_neon_qunzip8(pd
, pm
);
3058 gen_helper_neon_qunzip16(pd
, pm
);
3061 gen_helper_neon_qunzip32(pd
, pm
);
3069 gen_helper_neon_unzip8(pd
, pm
);
3072 gen_helper_neon_unzip16(pd
, pm
);
3078 tcg_temp_free_ptr(pd
);
3079 tcg_temp_free_ptr(pm
);
3083 static int gen_neon_zip(int rd
, int rm
, int size
, int q
)
3087 if (!q
&& size
== 2) {
3090 pd
= vfp_reg_ptr(true, rd
);
3091 pm
= vfp_reg_ptr(true, rm
);
3095 gen_helper_neon_qzip8(pd
, pm
);
3098 gen_helper_neon_qzip16(pd
, pm
);
3101 gen_helper_neon_qzip32(pd
, pm
);
3109 gen_helper_neon_zip8(pd
, pm
);
3112 gen_helper_neon_zip16(pd
, pm
);
3118 tcg_temp_free_ptr(pd
);
3119 tcg_temp_free_ptr(pm
);
3123 static void gen_neon_trn_u8(TCGv_i32 t0
, TCGv_i32 t1
)
3127 rd
= tcg_temp_new_i32();
3128 tmp
= tcg_temp_new_i32();
3130 tcg_gen_shli_i32(rd
, t0
, 8);
3131 tcg_gen_andi_i32(rd
, rd
, 0xff00ff00);
3132 tcg_gen_andi_i32(tmp
, t1
, 0x00ff00ff);
3133 tcg_gen_or_i32(rd
, rd
, tmp
);
3135 tcg_gen_shri_i32(t1
, t1
, 8);
3136 tcg_gen_andi_i32(t1
, t1
, 0x00ff00ff);
3137 tcg_gen_andi_i32(tmp
, t0
, 0xff00ff00);
3138 tcg_gen_or_i32(t1
, t1
, tmp
);
3139 tcg_gen_mov_i32(t0
, rd
);
3141 tcg_temp_free_i32(tmp
);
3142 tcg_temp_free_i32(rd
);
3145 static void gen_neon_trn_u16(TCGv_i32 t0
, TCGv_i32 t1
)
3149 rd
= tcg_temp_new_i32();
3150 tmp
= tcg_temp_new_i32();
3152 tcg_gen_shli_i32(rd
, t0
, 16);
3153 tcg_gen_andi_i32(tmp
, t1
, 0xffff);
3154 tcg_gen_or_i32(rd
, rd
, tmp
);
3155 tcg_gen_shri_i32(t1
, t1
, 16);
3156 tcg_gen_andi_i32(tmp
, t0
, 0xffff0000);
3157 tcg_gen_or_i32(t1
, t1
, tmp
);
3158 tcg_gen_mov_i32(t0
, rd
);
3160 tcg_temp_free_i32(tmp
);
3161 tcg_temp_free_i32(rd
);
3164 static inline void gen_neon_narrow(int size
, TCGv_i32 dest
, TCGv_i64 src
)
3167 case 0: gen_helper_neon_narrow_u8(dest
, src
); break;
3168 case 1: gen_helper_neon_narrow_u16(dest
, src
); break;
3169 case 2: tcg_gen_extrl_i64_i32(dest
, src
); break;
3174 static inline void gen_neon_narrow_sats(int size
, TCGv_i32 dest
, TCGv_i64 src
)
3177 case 0: gen_helper_neon_narrow_sat_s8(dest
, cpu_env
, src
); break;
3178 case 1: gen_helper_neon_narrow_sat_s16(dest
, cpu_env
, src
); break;
3179 case 2: gen_helper_neon_narrow_sat_s32(dest
, cpu_env
, src
); break;
3184 static inline void gen_neon_narrow_satu(int size
, TCGv_i32 dest
, TCGv_i64 src
)
3187 case 0: gen_helper_neon_narrow_sat_u8(dest
, cpu_env
, src
); break;
3188 case 1: gen_helper_neon_narrow_sat_u16(dest
, cpu_env
, src
); break;
3189 case 2: gen_helper_neon_narrow_sat_u32(dest
, cpu_env
, src
); break;
3194 static inline void gen_neon_unarrow_sats(int size
, TCGv_i32 dest
, TCGv_i64 src
)
3197 case 0: gen_helper_neon_unarrow_sat8(dest
, cpu_env
, src
); break;
3198 case 1: gen_helper_neon_unarrow_sat16(dest
, cpu_env
, src
); break;
3199 case 2: gen_helper_neon_unarrow_sat32(dest
, cpu_env
, src
); break;
3204 static inline void gen_neon_widen(TCGv_i64 dest
, TCGv_i32 src
, int size
, int u
)
3208 case 0: gen_helper_neon_widen_u8(dest
, src
); break;
3209 case 1: gen_helper_neon_widen_u16(dest
, src
); break;
3210 case 2: tcg_gen_extu_i32_i64(dest
, src
); break;
3215 case 0: gen_helper_neon_widen_s8(dest
, src
); break;
3216 case 1: gen_helper_neon_widen_s16(dest
, src
); break;
3217 case 2: tcg_gen_ext_i32_i64(dest
, src
); break;
3221 tcg_temp_free_i32(src
);
3224 static inline void gen_neon_addl(int size
)
3227 case 0: gen_helper_neon_addl_u16(CPU_V001
); break;
3228 case 1: gen_helper_neon_addl_u32(CPU_V001
); break;
3229 case 2: tcg_gen_add_i64(CPU_V001
); break;
3234 static inline void gen_neon_negl(TCGv_i64 var
, int size
)
3237 case 0: gen_helper_neon_negl_u16(var
, var
); break;
3238 case 1: gen_helper_neon_negl_u32(var
, var
); break;
3240 tcg_gen_neg_i64(var
, var
);
3246 static inline void gen_neon_addl_saturate(TCGv_i64 op0
, TCGv_i64 op1
, int size
)
3249 case 1: gen_helper_neon_addl_saturate_s32(op0
, cpu_env
, op0
, op1
); break;
3250 case 2: gen_helper_neon_addl_saturate_s64(op0
, cpu_env
, op0
, op1
); break;
3255 static inline void gen_neon_mull(TCGv_i64 dest
, TCGv_i32 a
, TCGv_i32 b
,
3260 switch ((size
<< 1) | u
) {
3261 case 0: gen_helper_neon_mull_s8(dest
, a
, b
); break;
3262 case 1: gen_helper_neon_mull_u8(dest
, a
, b
); break;
3263 case 2: gen_helper_neon_mull_s16(dest
, a
, b
); break;
3264 case 3: gen_helper_neon_mull_u16(dest
, a
, b
); break;
3266 tmp
= gen_muls_i64_i32(a
, b
);
3267 tcg_gen_mov_i64(dest
, tmp
);
3268 tcg_temp_free_i64(tmp
);
3271 tmp
= gen_mulu_i64_i32(a
, b
);
3272 tcg_gen_mov_i64(dest
, tmp
);
3273 tcg_temp_free_i64(tmp
);
3278 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
3279 Don't forget to clean them now. */
3281 tcg_temp_free_i32(a
);
3282 tcg_temp_free_i32(b
);
3286 static void gen_neon_narrow_op(int op
, int u
, int size
,
3287 TCGv_i32 dest
, TCGv_i64 src
)
3291 gen_neon_unarrow_sats(size
, dest
, src
);
3293 gen_neon_narrow(size
, dest
, src
);
3297 gen_neon_narrow_satu(size
, dest
, src
);
3299 gen_neon_narrow_sats(size
, dest
, src
);
3304 /* Symbolic constants for op fields for Neon 2-register miscellaneous.
3305 * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
3308 #define NEON_2RM_VREV64 0
3309 #define NEON_2RM_VREV32 1
3310 #define NEON_2RM_VREV16 2
3311 #define NEON_2RM_VPADDL 4
3312 #define NEON_2RM_VPADDL_U 5
3313 #define NEON_2RM_AESE 6 /* Includes AESD */
3314 #define NEON_2RM_AESMC 7 /* Includes AESIMC */
3315 #define NEON_2RM_VCLS 8
3316 #define NEON_2RM_VCLZ 9
3317 #define NEON_2RM_VCNT 10
3318 #define NEON_2RM_VMVN 11
3319 #define NEON_2RM_VPADAL 12
3320 #define NEON_2RM_VPADAL_U 13
3321 #define NEON_2RM_VQABS 14
3322 #define NEON_2RM_VQNEG 15
3323 #define NEON_2RM_VCGT0 16
3324 #define NEON_2RM_VCGE0 17
3325 #define NEON_2RM_VCEQ0 18
3326 #define NEON_2RM_VCLE0 19
3327 #define NEON_2RM_VCLT0 20
3328 #define NEON_2RM_SHA1H 21
3329 #define NEON_2RM_VABS 22
3330 #define NEON_2RM_VNEG 23
3331 #define NEON_2RM_VCGT0_F 24
3332 #define NEON_2RM_VCGE0_F 25
3333 #define NEON_2RM_VCEQ0_F 26
3334 #define NEON_2RM_VCLE0_F 27
3335 #define NEON_2RM_VCLT0_F 28
3336 #define NEON_2RM_VABS_F 30
3337 #define NEON_2RM_VNEG_F 31
3338 #define NEON_2RM_VSWP 32
3339 #define NEON_2RM_VTRN 33
3340 #define NEON_2RM_VUZP 34
3341 #define NEON_2RM_VZIP 35
3342 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
3343 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
3344 #define NEON_2RM_VSHLL 38
3345 #define NEON_2RM_SHA1SU1 39 /* Includes SHA256SU0 */
3346 #define NEON_2RM_VRINTN 40
3347 #define NEON_2RM_VRINTX 41
3348 #define NEON_2RM_VRINTA 42
3349 #define NEON_2RM_VRINTZ 43
3350 #define NEON_2RM_VCVT_F16_F32 44
3351 #define NEON_2RM_VRINTM 45
3352 #define NEON_2RM_VCVT_F32_F16 46
3353 #define NEON_2RM_VRINTP 47
3354 #define NEON_2RM_VCVTAU 48
3355 #define NEON_2RM_VCVTAS 49
3356 #define NEON_2RM_VCVTNU 50
3357 #define NEON_2RM_VCVTNS 51
3358 #define NEON_2RM_VCVTPU 52
3359 #define NEON_2RM_VCVTPS 53
3360 #define NEON_2RM_VCVTMU 54
3361 #define NEON_2RM_VCVTMS 55
3362 #define NEON_2RM_VRECPE 56
3363 #define NEON_2RM_VRSQRTE 57
3364 #define NEON_2RM_VRECPE_F 58
3365 #define NEON_2RM_VRSQRTE_F 59
3366 #define NEON_2RM_VCVT_FS 60
3367 #define NEON_2RM_VCVT_FU 61
3368 #define NEON_2RM_VCVT_SF 62
3369 #define NEON_2RM_VCVT_UF 63
3371 static bool neon_2rm_is_v8_op(int op
)
3373 /* Return true if this neon 2reg-misc op is ARMv8 and up */
3375 case NEON_2RM_VRINTN
:
3376 case NEON_2RM_VRINTA
:
3377 case NEON_2RM_VRINTM
:
3378 case NEON_2RM_VRINTP
:
3379 case NEON_2RM_VRINTZ
:
3380 case NEON_2RM_VRINTX
:
3381 case NEON_2RM_VCVTAU
:
3382 case NEON_2RM_VCVTAS
:
3383 case NEON_2RM_VCVTNU
:
3384 case NEON_2RM_VCVTNS
:
3385 case NEON_2RM_VCVTPU
:
3386 case NEON_2RM_VCVTPS
:
3387 case NEON_2RM_VCVTMU
:
3388 case NEON_2RM_VCVTMS
:
3395 /* Each entry in this array has bit n set if the insn allows
3396 * size value n (otherwise it will UNDEF). Since unallocated
3397 * op values will have no bits set they always UNDEF.
3399 static const uint8_t neon_2rm_sizes
[] = {
3400 [NEON_2RM_VREV64
] = 0x7,
3401 [NEON_2RM_VREV32
] = 0x3,
3402 [NEON_2RM_VREV16
] = 0x1,
3403 [NEON_2RM_VPADDL
] = 0x7,
3404 [NEON_2RM_VPADDL_U
] = 0x7,
3405 [NEON_2RM_AESE
] = 0x1,
3406 [NEON_2RM_AESMC
] = 0x1,
3407 [NEON_2RM_VCLS
] = 0x7,
3408 [NEON_2RM_VCLZ
] = 0x7,
3409 [NEON_2RM_VCNT
] = 0x1,
3410 [NEON_2RM_VMVN
] = 0x1,
3411 [NEON_2RM_VPADAL
] = 0x7,
3412 [NEON_2RM_VPADAL_U
] = 0x7,
3413 [NEON_2RM_VQABS
] = 0x7,
3414 [NEON_2RM_VQNEG
] = 0x7,
3415 [NEON_2RM_VCGT0
] = 0x7,
3416 [NEON_2RM_VCGE0
] = 0x7,
3417 [NEON_2RM_VCEQ0
] = 0x7,
3418 [NEON_2RM_VCLE0
] = 0x7,
3419 [NEON_2RM_VCLT0
] = 0x7,
3420 [NEON_2RM_SHA1H
] = 0x4,
3421 [NEON_2RM_VABS
] = 0x7,
3422 [NEON_2RM_VNEG
] = 0x7,
3423 [NEON_2RM_VCGT0_F
] = 0x4,
3424 [NEON_2RM_VCGE0_F
] = 0x4,
3425 [NEON_2RM_VCEQ0_F
] = 0x4,
3426 [NEON_2RM_VCLE0_F
] = 0x4,
3427 [NEON_2RM_VCLT0_F
] = 0x4,
3428 [NEON_2RM_VABS_F
] = 0x4,
3429 [NEON_2RM_VNEG_F
] = 0x4,
3430 [NEON_2RM_VSWP
] = 0x1,
3431 [NEON_2RM_VTRN
] = 0x7,
3432 [NEON_2RM_VUZP
] = 0x7,
3433 [NEON_2RM_VZIP
] = 0x7,
3434 [NEON_2RM_VMOVN
] = 0x7,
3435 [NEON_2RM_VQMOVN
] = 0x7,
3436 [NEON_2RM_VSHLL
] = 0x7,
3437 [NEON_2RM_SHA1SU1
] = 0x4,
3438 [NEON_2RM_VRINTN
] = 0x4,
3439 [NEON_2RM_VRINTX
] = 0x4,
3440 [NEON_2RM_VRINTA
] = 0x4,
3441 [NEON_2RM_VRINTZ
] = 0x4,
3442 [NEON_2RM_VCVT_F16_F32
] = 0x2,
3443 [NEON_2RM_VRINTM
] = 0x4,
3444 [NEON_2RM_VCVT_F32_F16
] = 0x2,
3445 [NEON_2RM_VRINTP
] = 0x4,
3446 [NEON_2RM_VCVTAU
] = 0x4,
3447 [NEON_2RM_VCVTAS
] = 0x4,
3448 [NEON_2RM_VCVTNU
] = 0x4,
3449 [NEON_2RM_VCVTNS
] = 0x4,
3450 [NEON_2RM_VCVTPU
] = 0x4,
3451 [NEON_2RM_VCVTPS
] = 0x4,
3452 [NEON_2RM_VCVTMU
] = 0x4,
3453 [NEON_2RM_VCVTMS
] = 0x4,
3454 [NEON_2RM_VRECPE
] = 0x4,
3455 [NEON_2RM_VRSQRTE
] = 0x4,
3456 [NEON_2RM_VRECPE_F
] = 0x4,
3457 [NEON_2RM_VRSQRTE_F
] = 0x4,
3458 [NEON_2RM_VCVT_FS
] = 0x4,
3459 [NEON_2RM_VCVT_FU
] = 0x4,
3460 [NEON_2RM_VCVT_SF
] = 0x4,
3461 [NEON_2RM_VCVT_UF
] = 0x4,
3464 static void gen_gvec_fn3_qc(uint32_t rd_ofs
, uint32_t rn_ofs
, uint32_t rm_ofs
,
3465 uint32_t opr_sz
, uint32_t max_sz
,
3466 gen_helper_gvec_3_ptr
*fn
)
3468 TCGv_ptr qc_ptr
= tcg_temp_new_ptr();
3470 tcg_gen_addi_ptr(qc_ptr
, cpu_env
, offsetof(CPUARMState
, vfp
.qc
));
3471 tcg_gen_gvec_3_ptr(rd_ofs
, rn_ofs
, rm_ofs
, qc_ptr
,
3472 opr_sz
, max_sz
, 0, fn
);
3473 tcg_temp_free_ptr(qc_ptr
);
3476 void gen_gvec_sqrdmlah_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
3477 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
3479 static gen_helper_gvec_3_ptr
* const fns
[2] = {
3480 gen_helper_gvec_qrdmlah_s16
, gen_helper_gvec_qrdmlah_s32
3482 tcg_debug_assert(vece
>= 1 && vece
<= 2);
3483 gen_gvec_fn3_qc(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, fns
[vece
- 1]);
3486 void gen_gvec_sqrdmlsh_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
3487 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
3489 static gen_helper_gvec_3_ptr
* const fns
[2] = {
3490 gen_helper_gvec_qrdmlsh_s16
, gen_helper_gvec_qrdmlsh_s32
3492 tcg_debug_assert(vece
>= 1 && vece
<= 2);
3493 gen_gvec_fn3_qc(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, fns
[vece
- 1]);
3496 #define GEN_CMP0(NAME, COND) \
3497 static void gen_##NAME##0_i32(TCGv_i32 d, TCGv_i32 a) \
3499 tcg_gen_setcondi_i32(COND, d, a, 0); \
3500 tcg_gen_neg_i32(d, d); \
3502 static void gen_##NAME##0_i64(TCGv_i64 d, TCGv_i64 a) \
3504 tcg_gen_setcondi_i64(COND, d, a, 0); \
3505 tcg_gen_neg_i64(d, d); \
3507 static void gen_##NAME##0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) \
3509 TCGv_vec zero = tcg_const_zeros_vec_matching(d); \
3510 tcg_gen_cmp_vec(COND, vece, d, a, zero); \
3511 tcg_temp_free_vec(zero); \
3513 void gen_gvec_##NAME##0(unsigned vece, uint32_t d, uint32_t m, \
3514 uint32_t opr_sz, uint32_t max_sz) \
3516 const GVecGen2 op[4] = { \
3517 { .fno = gen_helper_gvec_##NAME##0_b, \
3518 .fniv = gen_##NAME##0_vec, \
3519 .opt_opc = vecop_list_cmp, \
3521 { .fno = gen_helper_gvec_##NAME##0_h, \
3522 .fniv = gen_##NAME##0_vec, \
3523 .opt_opc = vecop_list_cmp, \
3525 { .fni4 = gen_##NAME##0_i32, \
3526 .fniv = gen_##NAME##0_vec, \
3527 .opt_opc = vecop_list_cmp, \
3529 { .fni8 = gen_##NAME##0_i64, \
3530 .fniv = gen_##NAME##0_vec, \
3531 .opt_opc = vecop_list_cmp, \
3532 .prefer_i64 = TCG_TARGET_REG_BITS == 64, \
3535 tcg_gen_gvec_2(d, m, opr_sz, max_sz, &op[vece]); \
3538 static const TCGOpcode vecop_list_cmp
[] = {
3542 GEN_CMP0(ceq
, TCG_COND_EQ
)
3543 GEN_CMP0(cle
, TCG_COND_LE
)
3544 GEN_CMP0(cge
, TCG_COND_GE
)
3545 GEN_CMP0(clt
, TCG_COND_LT
)
3546 GEN_CMP0(cgt
, TCG_COND_GT
)
3550 static void gen_ssra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
3552 tcg_gen_vec_sar8i_i64(a
, a
, shift
);
3553 tcg_gen_vec_add8_i64(d
, d
, a
);
3556 static void gen_ssra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
3558 tcg_gen_vec_sar16i_i64(a
, a
, shift
);
3559 tcg_gen_vec_add16_i64(d
, d
, a
);
3562 static void gen_ssra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
3564 tcg_gen_sari_i32(a
, a
, shift
);
3565 tcg_gen_add_i32(d
, d
, a
);
3568 static void gen_ssra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
3570 tcg_gen_sari_i64(a
, a
, shift
);
3571 tcg_gen_add_i64(d
, d
, a
);
3574 static void gen_ssra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
3576 tcg_gen_sari_vec(vece
, a
, a
, sh
);
3577 tcg_gen_add_vec(vece
, d
, d
, a
);
3580 void gen_gvec_ssra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
3581 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
3583 static const TCGOpcode vecop_list
[] = {
3584 INDEX_op_sari_vec
, INDEX_op_add_vec
, 0
3586 static const GVecGen2i ops
[4] = {
3587 { .fni8
= gen_ssra8_i64
,
3588 .fniv
= gen_ssra_vec
,
3589 .fno
= gen_helper_gvec_ssra_b
,
3591 .opt_opc
= vecop_list
,
3593 { .fni8
= gen_ssra16_i64
,
3594 .fniv
= gen_ssra_vec
,
3595 .fno
= gen_helper_gvec_ssra_h
,
3597 .opt_opc
= vecop_list
,
3599 { .fni4
= gen_ssra32_i32
,
3600 .fniv
= gen_ssra_vec
,
3601 .fno
= gen_helper_gvec_ssra_s
,
3603 .opt_opc
= vecop_list
,
3605 { .fni8
= gen_ssra64_i64
,
3606 .fniv
= gen_ssra_vec
,
3607 .fno
= gen_helper_gvec_ssra_b
,
3608 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
3609 .opt_opc
= vecop_list
,
3614 /* tszimm encoding produces immediates in the range [1..esize]. */
3615 tcg_debug_assert(shift
> 0);
3616 tcg_debug_assert(shift
<= (8 << vece
));
3619 * Shifts larger than the element size are architecturally valid.
3620 * Signed results in all sign bits.
3622 shift
= MIN(shift
, (8 << vece
) - 1);
3623 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
3626 static void gen_usra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
3628 tcg_gen_vec_shr8i_i64(a
, a
, shift
);
3629 tcg_gen_vec_add8_i64(d
, d
, a
);
3632 static void gen_usra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
3634 tcg_gen_vec_shr16i_i64(a
, a
, shift
);
3635 tcg_gen_vec_add16_i64(d
, d
, a
);
3638 static void gen_usra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
3640 tcg_gen_shri_i32(a
, a
, shift
);
3641 tcg_gen_add_i32(d
, d
, a
);
3644 static void gen_usra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
3646 tcg_gen_shri_i64(a
, a
, shift
);
3647 tcg_gen_add_i64(d
, d
, a
);
3650 static void gen_usra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
3652 tcg_gen_shri_vec(vece
, a
, a
, sh
);
3653 tcg_gen_add_vec(vece
, d
, d
, a
);
3656 void gen_gvec_usra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
3657 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
3659 static const TCGOpcode vecop_list
[] = {
3660 INDEX_op_shri_vec
, INDEX_op_add_vec
, 0
3662 static const GVecGen2i ops
[4] = {
3663 { .fni8
= gen_usra8_i64
,
3664 .fniv
= gen_usra_vec
,
3665 .fno
= gen_helper_gvec_usra_b
,
3667 .opt_opc
= vecop_list
,
3669 { .fni8
= gen_usra16_i64
,
3670 .fniv
= gen_usra_vec
,
3671 .fno
= gen_helper_gvec_usra_h
,
3673 .opt_opc
= vecop_list
,
3675 { .fni4
= gen_usra32_i32
,
3676 .fniv
= gen_usra_vec
,
3677 .fno
= gen_helper_gvec_usra_s
,
3679 .opt_opc
= vecop_list
,
3681 { .fni8
= gen_usra64_i64
,
3682 .fniv
= gen_usra_vec
,
3683 .fno
= gen_helper_gvec_usra_d
,
3684 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
3686 .opt_opc
= vecop_list
,
3690 /* tszimm encoding produces immediates in the range [1..esize]. */
3691 tcg_debug_assert(shift
> 0);
3692 tcg_debug_assert(shift
<= (8 << vece
));
3695 * Shifts larger than the element size are architecturally valid.
3696 * Unsigned results in all zeros as input to accumulate: nop.
3698 if (shift
< (8 << vece
)) {
3699 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
3701 /* Nop, but we do need to clear the tail. */
3702 tcg_gen_gvec_mov(vece
, rd_ofs
, rd_ofs
, opr_sz
, max_sz
);
3707 * Shift one less than the requested amount, and the low bit is
3708 * the rounding bit. For the 8 and 16-bit operations, because we
3709 * mask the low bit, we can perform a normal integer shift instead
3710 * of a vector shift.
3712 static void gen_srshr8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
3714 TCGv_i64 t
= tcg_temp_new_i64();
3716 tcg_gen_shri_i64(t
, a
, sh
- 1);
3717 tcg_gen_andi_i64(t
, t
, dup_const(MO_8
, 1));
3718 tcg_gen_vec_sar8i_i64(d
, a
, sh
);
3719 tcg_gen_vec_add8_i64(d
, d
, t
);
3720 tcg_temp_free_i64(t
);
3723 static void gen_srshr16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
3725 TCGv_i64 t
= tcg_temp_new_i64();
3727 tcg_gen_shri_i64(t
, a
, sh
- 1);
3728 tcg_gen_andi_i64(t
, t
, dup_const(MO_16
, 1));
3729 tcg_gen_vec_sar16i_i64(d
, a
, sh
);
3730 tcg_gen_vec_add16_i64(d
, d
, t
);
3731 tcg_temp_free_i64(t
);
3734 static void gen_srshr32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t sh
)
3736 TCGv_i32 t
= tcg_temp_new_i32();
3738 tcg_gen_extract_i32(t
, a
, sh
- 1, 1);
3739 tcg_gen_sari_i32(d
, a
, sh
);
3740 tcg_gen_add_i32(d
, d
, t
);
3741 tcg_temp_free_i32(t
);
3744 static void gen_srshr64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
3746 TCGv_i64 t
= tcg_temp_new_i64();
3748 tcg_gen_extract_i64(t
, a
, sh
- 1, 1);
3749 tcg_gen_sari_i64(d
, a
, sh
);
3750 tcg_gen_add_i64(d
, d
, t
);
3751 tcg_temp_free_i64(t
);
3754 static void gen_srshr_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
3756 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
3757 TCGv_vec ones
= tcg_temp_new_vec_matching(d
);
3759 tcg_gen_shri_vec(vece
, t
, a
, sh
- 1);
3760 tcg_gen_dupi_vec(vece
, ones
, 1);
3761 tcg_gen_and_vec(vece
, t
, t
, ones
);
3762 tcg_gen_sari_vec(vece
, d
, a
, sh
);
3763 tcg_gen_add_vec(vece
, d
, d
, t
);
3765 tcg_temp_free_vec(t
);
3766 tcg_temp_free_vec(ones
);
3769 void gen_gvec_srshr(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
3770 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
3772 static const TCGOpcode vecop_list
[] = {
3773 INDEX_op_shri_vec
, INDEX_op_sari_vec
, INDEX_op_add_vec
, 0
3775 static const GVecGen2i ops
[4] = {
3776 { .fni8
= gen_srshr8_i64
,
3777 .fniv
= gen_srshr_vec
,
3778 .fno
= gen_helper_gvec_srshr_b
,
3779 .opt_opc
= vecop_list
,
3781 { .fni8
= gen_srshr16_i64
,
3782 .fniv
= gen_srshr_vec
,
3783 .fno
= gen_helper_gvec_srshr_h
,
3784 .opt_opc
= vecop_list
,
3786 { .fni4
= gen_srshr32_i32
,
3787 .fniv
= gen_srshr_vec
,
3788 .fno
= gen_helper_gvec_srshr_s
,
3789 .opt_opc
= vecop_list
,
3791 { .fni8
= gen_srshr64_i64
,
3792 .fniv
= gen_srshr_vec
,
3793 .fno
= gen_helper_gvec_srshr_d
,
3794 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
3795 .opt_opc
= vecop_list
,
3799 /* tszimm encoding produces immediates in the range [1..esize] */
3800 tcg_debug_assert(shift
> 0);
3801 tcg_debug_assert(shift
<= (8 << vece
));
3803 if (shift
== (8 << vece
)) {
3805 * Shifts larger than the element size are architecturally valid.
3806 * Signed results in all sign bits. With rounding, this produces
3807 * (-1 + 1) >> 1 == 0, or (0 + 1) >> 1 == 0.
3810 tcg_gen_gvec_dup_imm(vece
, rd_ofs
, opr_sz
, max_sz
, 0);
3812 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
3816 static void gen_srsra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
3818 TCGv_i64 t
= tcg_temp_new_i64();
3820 gen_srshr8_i64(t
, a
, sh
);
3821 tcg_gen_vec_add8_i64(d
, d
, t
);
3822 tcg_temp_free_i64(t
);
3825 static void gen_srsra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
3827 TCGv_i64 t
= tcg_temp_new_i64();
3829 gen_srshr16_i64(t
, a
, sh
);
3830 tcg_gen_vec_add16_i64(d
, d
, t
);
3831 tcg_temp_free_i64(t
);
3834 static void gen_srsra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t sh
)
3836 TCGv_i32 t
= tcg_temp_new_i32();
3838 gen_srshr32_i32(t
, a
, sh
);
3839 tcg_gen_add_i32(d
, d
, t
);
3840 tcg_temp_free_i32(t
);
3843 static void gen_srsra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
3845 TCGv_i64 t
= tcg_temp_new_i64();
3847 gen_srshr64_i64(t
, a
, sh
);
3848 tcg_gen_add_i64(d
, d
, t
);
3849 tcg_temp_free_i64(t
);
3852 static void gen_srsra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
3854 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
3856 gen_srshr_vec(vece
, t
, a
, sh
);
3857 tcg_gen_add_vec(vece
, d
, d
, t
);
3858 tcg_temp_free_vec(t
);
3861 void gen_gvec_srsra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
3862 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
3864 static const TCGOpcode vecop_list
[] = {
3865 INDEX_op_shri_vec
, INDEX_op_sari_vec
, INDEX_op_add_vec
, 0
3867 static const GVecGen2i ops
[4] = {
3868 { .fni8
= gen_srsra8_i64
,
3869 .fniv
= gen_srsra_vec
,
3870 .fno
= gen_helper_gvec_srsra_b
,
3871 .opt_opc
= vecop_list
,
3874 { .fni8
= gen_srsra16_i64
,
3875 .fniv
= gen_srsra_vec
,
3876 .fno
= gen_helper_gvec_srsra_h
,
3877 .opt_opc
= vecop_list
,
3880 { .fni4
= gen_srsra32_i32
,
3881 .fniv
= gen_srsra_vec
,
3882 .fno
= gen_helper_gvec_srsra_s
,
3883 .opt_opc
= vecop_list
,
3886 { .fni8
= gen_srsra64_i64
,
3887 .fniv
= gen_srsra_vec
,
3888 .fno
= gen_helper_gvec_srsra_d
,
3889 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
3890 .opt_opc
= vecop_list
,
3895 /* tszimm encoding produces immediates in the range [1..esize] */
3896 tcg_debug_assert(shift
> 0);
3897 tcg_debug_assert(shift
<= (8 << vece
));
3900 * Shifts larger than the element size are architecturally valid.
3901 * Signed results in all sign bits. With rounding, this produces
3902 * (-1 + 1) >> 1 == 0, or (0 + 1) >> 1 == 0.
3903 * I.e. always zero. With accumulation, this leaves D unchanged.
3905 if (shift
== (8 << vece
)) {
3906 /* Nop, but we do need to clear the tail. */
3907 tcg_gen_gvec_mov(vece
, rd_ofs
, rd_ofs
, opr_sz
, max_sz
);
3909 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
3913 static void gen_urshr8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
3915 TCGv_i64 t
= tcg_temp_new_i64();
3917 tcg_gen_shri_i64(t
, a
, sh
- 1);
3918 tcg_gen_andi_i64(t
, t
, dup_const(MO_8
, 1));
3919 tcg_gen_vec_shr8i_i64(d
, a
, sh
);
3920 tcg_gen_vec_add8_i64(d
, d
, t
);
3921 tcg_temp_free_i64(t
);
3924 static void gen_urshr16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
3926 TCGv_i64 t
= tcg_temp_new_i64();
3928 tcg_gen_shri_i64(t
, a
, sh
- 1);
3929 tcg_gen_andi_i64(t
, t
, dup_const(MO_16
, 1));
3930 tcg_gen_vec_shr16i_i64(d
, a
, sh
);
3931 tcg_gen_vec_add16_i64(d
, d
, t
);
3932 tcg_temp_free_i64(t
);
3935 static void gen_urshr32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t sh
)
3937 TCGv_i32 t
= tcg_temp_new_i32();
3939 tcg_gen_extract_i32(t
, a
, sh
- 1, 1);
3940 tcg_gen_shri_i32(d
, a
, sh
);
3941 tcg_gen_add_i32(d
, d
, t
);
3942 tcg_temp_free_i32(t
);
3945 static void gen_urshr64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
3947 TCGv_i64 t
= tcg_temp_new_i64();
3949 tcg_gen_extract_i64(t
, a
, sh
- 1, 1);
3950 tcg_gen_shri_i64(d
, a
, sh
);
3951 tcg_gen_add_i64(d
, d
, t
);
3952 tcg_temp_free_i64(t
);
3955 static void gen_urshr_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t shift
)
3957 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
3958 TCGv_vec ones
= tcg_temp_new_vec_matching(d
);
3960 tcg_gen_shri_vec(vece
, t
, a
, shift
- 1);
3961 tcg_gen_dupi_vec(vece
, ones
, 1);
3962 tcg_gen_and_vec(vece
, t
, t
, ones
);
3963 tcg_gen_shri_vec(vece
, d
, a
, shift
);
3964 tcg_gen_add_vec(vece
, d
, d
, t
);
3966 tcg_temp_free_vec(t
);
3967 tcg_temp_free_vec(ones
);
3970 void gen_gvec_urshr(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
3971 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
3973 static const TCGOpcode vecop_list
[] = {
3974 INDEX_op_shri_vec
, INDEX_op_add_vec
, 0
3976 static const GVecGen2i ops
[4] = {
3977 { .fni8
= gen_urshr8_i64
,
3978 .fniv
= gen_urshr_vec
,
3979 .fno
= gen_helper_gvec_urshr_b
,
3980 .opt_opc
= vecop_list
,
3982 { .fni8
= gen_urshr16_i64
,
3983 .fniv
= gen_urshr_vec
,
3984 .fno
= gen_helper_gvec_urshr_h
,
3985 .opt_opc
= vecop_list
,
3987 { .fni4
= gen_urshr32_i32
,
3988 .fniv
= gen_urshr_vec
,
3989 .fno
= gen_helper_gvec_urshr_s
,
3990 .opt_opc
= vecop_list
,
3992 { .fni8
= gen_urshr64_i64
,
3993 .fniv
= gen_urshr_vec
,
3994 .fno
= gen_helper_gvec_urshr_d
,
3995 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
3996 .opt_opc
= vecop_list
,
4000 /* tszimm encoding produces immediates in the range [1..esize] */
4001 tcg_debug_assert(shift
> 0);
4002 tcg_debug_assert(shift
<= (8 << vece
));
4004 if (shift
== (8 << vece
)) {
4006 * Shifts larger than the element size are architecturally valid.
4007 * Unsigned results in zero. With rounding, this produces a
4008 * copy of the most significant bit.
4010 tcg_gen_gvec_shri(vece
, rd_ofs
, rm_ofs
, shift
- 1, opr_sz
, max_sz
);
4012 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
4016 static void gen_ursra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4018 TCGv_i64 t
= tcg_temp_new_i64();
4021 tcg_gen_vec_shr8i_i64(t
, a
, 7);
4023 gen_urshr8_i64(t
, a
, sh
);
4025 tcg_gen_vec_add8_i64(d
, d
, t
);
4026 tcg_temp_free_i64(t
);
4029 static void gen_ursra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4031 TCGv_i64 t
= tcg_temp_new_i64();
4034 tcg_gen_vec_shr16i_i64(t
, a
, 15);
4036 gen_urshr16_i64(t
, a
, sh
);
4038 tcg_gen_vec_add16_i64(d
, d
, t
);
4039 tcg_temp_free_i64(t
);
4042 static void gen_ursra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t sh
)
4044 TCGv_i32 t
= tcg_temp_new_i32();
4047 tcg_gen_shri_i32(t
, a
, 31);
4049 gen_urshr32_i32(t
, a
, sh
);
4051 tcg_gen_add_i32(d
, d
, t
);
4052 tcg_temp_free_i32(t
);
4055 static void gen_ursra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4057 TCGv_i64 t
= tcg_temp_new_i64();
4060 tcg_gen_shri_i64(t
, a
, 63);
4062 gen_urshr64_i64(t
, a
, sh
);
4064 tcg_gen_add_i64(d
, d
, t
);
4065 tcg_temp_free_i64(t
);
4068 static void gen_ursra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
4070 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
4072 if (sh
== (8 << vece
)) {
4073 tcg_gen_shri_vec(vece
, t
, a
, sh
- 1);
4075 gen_urshr_vec(vece
, t
, a
, sh
);
4077 tcg_gen_add_vec(vece
, d
, d
, t
);
4078 tcg_temp_free_vec(t
);
4081 void gen_gvec_ursra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
4082 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
4084 static const TCGOpcode vecop_list
[] = {
4085 INDEX_op_shri_vec
, INDEX_op_add_vec
, 0
4087 static const GVecGen2i ops
[4] = {
4088 { .fni8
= gen_ursra8_i64
,
4089 .fniv
= gen_ursra_vec
,
4090 .fno
= gen_helper_gvec_ursra_b
,
4091 .opt_opc
= vecop_list
,
4094 { .fni8
= gen_ursra16_i64
,
4095 .fniv
= gen_ursra_vec
,
4096 .fno
= gen_helper_gvec_ursra_h
,
4097 .opt_opc
= vecop_list
,
4100 { .fni4
= gen_ursra32_i32
,
4101 .fniv
= gen_ursra_vec
,
4102 .fno
= gen_helper_gvec_ursra_s
,
4103 .opt_opc
= vecop_list
,
4106 { .fni8
= gen_ursra64_i64
,
4107 .fniv
= gen_ursra_vec
,
4108 .fno
= gen_helper_gvec_ursra_d
,
4109 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4110 .opt_opc
= vecop_list
,
4115 /* tszimm encoding produces immediates in the range [1..esize] */
4116 tcg_debug_assert(shift
> 0);
4117 tcg_debug_assert(shift
<= (8 << vece
));
4119 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
4122 static void gen_shr8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4124 uint64_t mask
= dup_const(MO_8
, 0xff >> shift
);
4125 TCGv_i64 t
= tcg_temp_new_i64();
4127 tcg_gen_shri_i64(t
, a
, shift
);
4128 tcg_gen_andi_i64(t
, t
, mask
);
4129 tcg_gen_andi_i64(d
, d
, ~mask
);
4130 tcg_gen_or_i64(d
, d
, t
);
4131 tcg_temp_free_i64(t
);
4134 static void gen_shr16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4136 uint64_t mask
= dup_const(MO_16
, 0xffff >> shift
);
4137 TCGv_i64 t
= tcg_temp_new_i64();
4139 tcg_gen_shri_i64(t
, a
, shift
);
4140 tcg_gen_andi_i64(t
, t
, mask
);
4141 tcg_gen_andi_i64(d
, d
, ~mask
);
4142 tcg_gen_or_i64(d
, d
, t
);
4143 tcg_temp_free_i64(t
);
4146 static void gen_shr32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
4148 tcg_gen_shri_i32(a
, a
, shift
);
4149 tcg_gen_deposit_i32(d
, d
, a
, 0, 32 - shift
);
4152 static void gen_shr64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4154 tcg_gen_shri_i64(a
, a
, shift
);
4155 tcg_gen_deposit_i64(d
, d
, a
, 0, 64 - shift
);
4158 static void gen_shr_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
4160 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
4161 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
4163 tcg_gen_dupi_vec(vece
, m
, MAKE_64BIT_MASK((8 << vece
) - sh
, sh
));
4164 tcg_gen_shri_vec(vece
, t
, a
, sh
);
4165 tcg_gen_and_vec(vece
, d
, d
, m
);
4166 tcg_gen_or_vec(vece
, d
, d
, t
);
4168 tcg_temp_free_vec(t
);
4169 tcg_temp_free_vec(m
);
4172 void gen_gvec_sri(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
4173 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
4175 static const TCGOpcode vecop_list
[] = { INDEX_op_shri_vec
, 0 };
4176 const GVecGen2i ops
[4] = {
4177 { .fni8
= gen_shr8_ins_i64
,
4178 .fniv
= gen_shr_ins_vec
,
4179 .fno
= gen_helper_gvec_sri_b
,
4181 .opt_opc
= vecop_list
,
4183 { .fni8
= gen_shr16_ins_i64
,
4184 .fniv
= gen_shr_ins_vec
,
4185 .fno
= gen_helper_gvec_sri_h
,
4187 .opt_opc
= vecop_list
,
4189 { .fni4
= gen_shr32_ins_i32
,
4190 .fniv
= gen_shr_ins_vec
,
4191 .fno
= gen_helper_gvec_sri_s
,
4193 .opt_opc
= vecop_list
,
4195 { .fni8
= gen_shr64_ins_i64
,
4196 .fniv
= gen_shr_ins_vec
,
4197 .fno
= gen_helper_gvec_sri_d
,
4198 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4200 .opt_opc
= vecop_list
,
4204 /* tszimm encoding produces immediates in the range [1..esize]. */
4205 tcg_debug_assert(shift
> 0);
4206 tcg_debug_assert(shift
<= (8 << vece
));
4208 /* Shift of esize leaves destination unchanged. */
4209 if (shift
< (8 << vece
)) {
4210 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
4212 /* Nop, but we do need to clear the tail. */
4213 tcg_gen_gvec_mov(vece
, rd_ofs
, rd_ofs
, opr_sz
, max_sz
);
4217 static void gen_shl8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4219 uint64_t mask
= dup_const(MO_8
, 0xff << shift
);
4220 TCGv_i64 t
= tcg_temp_new_i64();
4222 tcg_gen_shli_i64(t
, a
, shift
);
4223 tcg_gen_andi_i64(t
, t
, mask
);
4224 tcg_gen_andi_i64(d
, d
, ~mask
);
4225 tcg_gen_or_i64(d
, d
, t
);
4226 tcg_temp_free_i64(t
);
4229 static void gen_shl16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4231 uint64_t mask
= dup_const(MO_16
, 0xffff << shift
);
4232 TCGv_i64 t
= tcg_temp_new_i64();
4234 tcg_gen_shli_i64(t
, a
, shift
);
4235 tcg_gen_andi_i64(t
, t
, mask
);
4236 tcg_gen_andi_i64(d
, d
, ~mask
);
4237 tcg_gen_or_i64(d
, d
, t
);
4238 tcg_temp_free_i64(t
);
4241 static void gen_shl32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
4243 tcg_gen_deposit_i32(d
, d
, a
, shift
, 32 - shift
);
4246 static void gen_shl64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4248 tcg_gen_deposit_i64(d
, d
, a
, shift
, 64 - shift
);
4251 static void gen_shl_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
4253 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
4254 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
4256 tcg_gen_shli_vec(vece
, t
, a
, sh
);
4257 tcg_gen_dupi_vec(vece
, m
, MAKE_64BIT_MASK(0, sh
));
4258 tcg_gen_and_vec(vece
, d
, d
, m
);
4259 tcg_gen_or_vec(vece
, d
, d
, t
);
4261 tcg_temp_free_vec(t
);
4262 tcg_temp_free_vec(m
);
4265 void gen_gvec_sli(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
4266 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
4268 static const TCGOpcode vecop_list
[] = { INDEX_op_shli_vec
, 0 };
4269 const GVecGen2i ops
[4] = {
4270 { .fni8
= gen_shl8_ins_i64
,
4271 .fniv
= gen_shl_ins_vec
,
4272 .fno
= gen_helper_gvec_sli_b
,
4274 .opt_opc
= vecop_list
,
4276 { .fni8
= gen_shl16_ins_i64
,
4277 .fniv
= gen_shl_ins_vec
,
4278 .fno
= gen_helper_gvec_sli_h
,
4280 .opt_opc
= vecop_list
,
4282 { .fni4
= gen_shl32_ins_i32
,
4283 .fniv
= gen_shl_ins_vec
,
4284 .fno
= gen_helper_gvec_sli_s
,
4286 .opt_opc
= vecop_list
,
4288 { .fni8
= gen_shl64_ins_i64
,
4289 .fniv
= gen_shl_ins_vec
,
4290 .fno
= gen_helper_gvec_sli_d
,
4291 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4293 .opt_opc
= vecop_list
,
4297 /* tszimm encoding produces immediates in the range [0..esize-1]. */
4298 tcg_debug_assert(shift
>= 0);
4299 tcg_debug_assert(shift
< (8 << vece
));
4302 tcg_gen_gvec_mov(vece
, rd_ofs
, rm_ofs
, opr_sz
, max_sz
);
4304 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
4308 static void gen_mla8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4310 gen_helper_neon_mul_u8(a
, a
, b
);
4311 gen_helper_neon_add_u8(d
, d
, a
);
4314 static void gen_mls8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4316 gen_helper_neon_mul_u8(a
, a
, b
);
4317 gen_helper_neon_sub_u8(d
, d
, a
);
4320 static void gen_mla16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4322 gen_helper_neon_mul_u16(a
, a
, b
);
4323 gen_helper_neon_add_u16(d
, d
, a
);
4326 static void gen_mls16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4328 gen_helper_neon_mul_u16(a
, a
, b
);
4329 gen_helper_neon_sub_u16(d
, d
, a
);
4332 static void gen_mla32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4334 tcg_gen_mul_i32(a
, a
, b
);
4335 tcg_gen_add_i32(d
, d
, a
);
4338 static void gen_mls32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4340 tcg_gen_mul_i32(a
, a
, b
);
4341 tcg_gen_sub_i32(d
, d
, a
);
4344 static void gen_mla64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
4346 tcg_gen_mul_i64(a
, a
, b
);
4347 tcg_gen_add_i64(d
, d
, a
);
4350 static void gen_mls64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
4352 tcg_gen_mul_i64(a
, a
, b
);
4353 tcg_gen_sub_i64(d
, d
, a
);
4356 static void gen_mla_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
4358 tcg_gen_mul_vec(vece
, a
, a
, b
);
4359 tcg_gen_add_vec(vece
, d
, d
, a
);
4362 static void gen_mls_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
4364 tcg_gen_mul_vec(vece
, a
, a
, b
);
4365 tcg_gen_sub_vec(vece
, d
, d
, a
);
4368 /* Note that while NEON does not support VMLA and VMLS as 64-bit ops,
4369 * these tables are shared with AArch64 which does support them.
4371 void gen_gvec_mla(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
4372 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
4374 static const TCGOpcode vecop_list
[] = {
4375 INDEX_op_mul_vec
, INDEX_op_add_vec
, 0
4377 static const GVecGen3 ops
[4] = {
4378 { .fni4
= gen_mla8_i32
,
4379 .fniv
= gen_mla_vec
,
4381 .opt_opc
= vecop_list
,
4383 { .fni4
= gen_mla16_i32
,
4384 .fniv
= gen_mla_vec
,
4386 .opt_opc
= vecop_list
,
4388 { .fni4
= gen_mla32_i32
,
4389 .fniv
= gen_mla_vec
,
4391 .opt_opc
= vecop_list
,
4393 { .fni8
= gen_mla64_i64
,
4394 .fniv
= gen_mla_vec
,
4395 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4397 .opt_opc
= vecop_list
,
4400 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &ops
[vece
]);
4403 void gen_gvec_mls(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
4404 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
4406 static const TCGOpcode vecop_list
[] = {
4407 INDEX_op_mul_vec
, INDEX_op_sub_vec
, 0
4409 static const GVecGen3 ops
[4] = {
4410 { .fni4
= gen_mls8_i32
,
4411 .fniv
= gen_mls_vec
,
4413 .opt_opc
= vecop_list
,
4415 { .fni4
= gen_mls16_i32
,
4416 .fniv
= gen_mls_vec
,
4418 .opt_opc
= vecop_list
,
4420 { .fni4
= gen_mls32_i32
,
4421 .fniv
= gen_mls_vec
,
4423 .opt_opc
= vecop_list
,
4425 { .fni8
= gen_mls64_i64
,
4426 .fniv
= gen_mls_vec
,
4427 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4429 .opt_opc
= vecop_list
,
4432 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &ops
[vece
]);
4435 /* CMTST : test is "if (X & Y != 0)". */
4436 static void gen_cmtst_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4438 tcg_gen_and_i32(d
, a
, b
);
4439 tcg_gen_setcondi_i32(TCG_COND_NE
, d
, d
, 0);
4440 tcg_gen_neg_i32(d
, d
);
4443 void gen_cmtst_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
4445 tcg_gen_and_i64(d
, a
, b
);
4446 tcg_gen_setcondi_i64(TCG_COND_NE
, d
, d
, 0);
4447 tcg_gen_neg_i64(d
, d
);
4450 static void gen_cmtst_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
4452 tcg_gen_and_vec(vece
, d
, a
, b
);
4453 tcg_gen_dupi_vec(vece
, a
, 0);
4454 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, d
, d
, a
);
4457 void gen_gvec_cmtst(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
4458 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
4460 static const TCGOpcode vecop_list
[] = { INDEX_op_cmp_vec
, 0 };
4461 static const GVecGen3 ops
[4] = {
4462 { .fni4
= gen_helper_neon_tst_u8
,
4463 .fniv
= gen_cmtst_vec
,
4464 .opt_opc
= vecop_list
,
4466 { .fni4
= gen_helper_neon_tst_u16
,
4467 .fniv
= gen_cmtst_vec
,
4468 .opt_opc
= vecop_list
,
4470 { .fni4
= gen_cmtst_i32
,
4471 .fniv
= gen_cmtst_vec
,
4472 .opt_opc
= vecop_list
,
4474 { .fni8
= gen_cmtst_i64
,
4475 .fniv
= gen_cmtst_vec
,
4476 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4477 .opt_opc
= vecop_list
,
4480 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &ops
[vece
]);
4483 void gen_ushl_i32(TCGv_i32 dst
, TCGv_i32 src
, TCGv_i32 shift
)
4485 TCGv_i32 lval
= tcg_temp_new_i32();
4486 TCGv_i32 rval
= tcg_temp_new_i32();
4487 TCGv_i32 lsh
= tcg_temp_new_i32();
4488 TCGv_i32 rsh
= tcg_temp_new_i32();
4489 TCGv_i32 zero
= tcg_const_i32(0);
4490 TCGv_i32 max
= tcg_const_i32(32);
4493 * Rely on the TCG guarantee that out of range shifts produce
4494 * unspecified results, not undefined behaviour (i.e. no trap).
4495 * Discard out-of-range results after the fact.
4497 tcg_gen_ext8s_i32(lsh
, shift
);
4498 tcg_gen_neg_i32(rsh
, lsh
);
4499 tcg_gen_shl_i32(lval
, src
, lsh
);
4500 tcg_gen_shr_i32(rval
, src
, rsh
);
4501 tcg_gen_movcond_i32(TCG_COND_LTU
, dst
, lsh
, max
, lval
, zero
);
4502 tcg_gen_movcond_i32(TCG_COND_LTU
, dst
, rsh
, max
, rval
, dst
);
4504 tcg_temp_free_i32(lval
);
4505 tcg_temp_free_i32(rval
);
4506 tcg_temp_free_i32(lsh
);
4507 tcg_temp_free_i32(rsh
);
4508 tcg_temp_free_i32(zero
);
4509 tcg_temp_free_i32(max
);
4512 void gen_ushl_i64(TCGv_i64 dst
, TCGv_i64 src
, TCGv_i64 shift
)
4514 TCGv_i64 lval
= tcg_temp_new_i64();
4515 TCGv_i64 rval
= tcg_temp_new_i64();
4516 TCGv_i64 lsh
= tcg_temp_new_i64();
4517 TCGv_i64 rsh
= tcg_temp_new_i64();
4518 TCGv_i64 zero
= tcg_const_i64(0);
4519 TCGv_i64 max
= tcg_const_i64(64);
4522 * Rely on the TCG guarantee that out of range shifts produce
4523 * unspecified results, not undefined behaviour (i.e. no trap).
4524 * Discard out-of-range results after the fact.
4526 tcg_gen_ext8s_i64(lsh
, shift
);
4527 tcg_gen_neg_i64(rsh
, lsh
);
4528 tcg_gen_shl_i64(lval
, src
, lsh
);
4529 tcg_gen_shr_i64(rval
, src
, rsh
);
4530 tcg_gen_movcond_i64(TCG_COND_LTU
, dst
, lsh
, max
, lval
, zero
);
4531 tcg_gen_movcond_i64(TCG_COND_LTU
, dst
, rsh
, max
, rval
, dst
);
4533 tcg_temp_free_i64(lval
);
4534 tcg_temp_free_i64(rval
);
4535 tcg_temp_free_i64(lsh
);
4536 tcg_temp_free_i64(rsh
);
4537 tcg_temp_free_i64(zero
);
4538 tcg_temp_free_i64(max
);
4541 static void gen_ushl_vec(unsigned vece
, TCGv_vec dst
,
4542 TCGv_vec src
, TCGv_vec shift
)
4544 TCGv_vec lval
= tcg_temp_new_vec_matching(dst
);
4545 TCGv_vec rval
= tcg_temp_new_vec_matching(dst
);
4546 TCGv_vec lsh
= tcg_temp_new_vec_matching(dst
);
4547 TCGv_vec rsh
= tcg_temp_new_vec_matching(dst
);
4550 tcg_gen_neg_vec(vece
, rsh
, shift
);
4552 tcg_gen_mov_vec(lsh
, shift
);
4554 msk
= tcg_temp_new_vec_matching(dst
);
4555 tcg_gen_dupi_vec(vece
, msk
, 0xff);
4556 tcg_gen_and_vec(vece
, lsh
, shift
, msk
);
4557 tcg_gen_and_vec(vece
, rsh
, rsh
, msk
);
4558 tcg_temp_free_vec(msk
);
4562 * Rely on the TCG guarantee that out of range shifts produce
4563 * unspecified results, not undefined behaviour (i.e. no trap).
4564 * Discard out-of-range results after the fact.
4566 tcg_gen_shlv_vec(vece
, lval
, src
, lsh
);
4567 tcg_gen_shrv_vec(vece
, rval
, src
, rsh
);
4569 max
= tcg_temp_new_vec_matching(dst
);
4570 tcg_gen_dupi_vec(vece
, max
, 8 << vece
);
4573 * The choice of LT (signed) and GEU (unsigned) are biased toward
4574 * the instructions of the x86_64 host. For MO_8, the whole byte
4575 * is significant so we must use an unsigned compare; otherwise we
4576 * have already masked to a byte and so a signed compare works.
4577 * Other tcg hosts have a full set of comparisons and do not care.
4580 tcg_gen_cmp_vec(TCG_COND_GEU
, vece
, lsh
, lsh
, max
);
4581 tcg_gen_cmp_vec(TCG_COND_GEU
, vece
, rsh
, rsh
, max
);
4582 tcg_gen_andc_vec(vece
, lval
, lval
, lsh
);
4583 tcg_gen_andc_vec(vece
, rval
, rval
, rsh
);
4585 tcg_gen_cmp_vec(TCG_COND_LT
, vece
, lsh
, lsh
, max
);
4586 tcg_gen_cmp_vec(TCG_COND_LT
, vece
, rsh
, rsh
, max
);
4587 tcg_gen_and_vec(vece
, lval
, lval
, lsh
);
4588 tcg_gen_and_vec(vece
, rval
, rval
, rsh
);
4590 tcg_gen_or_vec(vece
, dst
, lval
, rval
);
4592 tcg_temp_free_vec(max
);
4593 tcg_temp_free_vec(lval
);
4594 tcg_temp_free_vec(rval
);
4595 tcg_temp_free_vec(lsh
);
4596 tcg_temp_free_vec(rsh
);
4599 void gen_gvec_ushl(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
4600 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
4602 static const TCGOpcode vecop_list
[] = {
4603 INDEX_op_neg_vec
, INDEX_op_shlv_vec
,
4604 INDEX_op_shrv_vec
, INDEX_op_cmp_vec
, 0
4606 static const GVecGen3 ops
[4] = {
4607 { .fniv
= gen_ushl_vec
,
4608 .fno
= gen_helper_gvec_ushl_b
,
4609 .opt_opc
= vecop_list
,
4611 { .fniv
= gen_ushl_vec
,
4612 .fno
= gen_helper_gvec_ushl_h
,
4613 .opt_opc
= vecop_list
,
4615 { .fni4
= gen_ushl_i32
,
4616 .fniv
= gen_ushl_vec
,
4617 .opt_opc
= vecop_list
,
4619 { .fni8
= gen_ushl_i64
,
4620 .fniv
= gen_ushl_vec
,
4621 .opt_opc
= vecop_list
,
4624 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &ops
[vece
]);
4627 void gen_sshl_i32(TCGv_i32 dst
, TCGv_i32 src
, TCGv_i32 shift
)
4629 TCGv_i32 lval
= tcg_temp_new_i32();
4630 TCGv_i32 rval
= tcg_temp_new_i32();
4631 TCGv_i32 lsh
= tcg_temp_new_i32();
4632 TCGv_i32 rsh
= tcg_temp_new_i32();
4633 TCGv_i32 zero
= tcg_const_i32(0);
4634 TCGv_i32 max
= tcg_const_i32(31);
4637 * Rely on the TCG guarantee that out of range shifts produce
4638 * unspecified results, not undefined behaviour (i.e. no trap).
4639 * Discard out-of-range results after the fact.
4641 tcg_gen_ext8s_i32(lsh
, shift
);
4642 tcg_gen_neg_i32(rsh
, lsh
);
4643 tcg_gen_shl_i32(lval
, src
, lsh
);
4644 tcg_gen_umin_i32(rsh
, rsh
, max
);
4645 tcg_gen_sar_i32(rval
, src
, rsh
);
4646 tcg_gen_movcond_i32(TCG_COND_LEU
, lval
, lsh
, max
, lval
, zero
);
4647 tcg_gen_movcond_i32(TCG_COND_LT
, dst
, lsh
, zero
, rval
, lval
);
4649 tcg_temp_free_i32(lval
);
4650 tcg_temp_free_i32(rval
);
4651 tcg_temp_free_i32(lsh
);
4652 tcg_temp_free_i32(rsh
);
4653 tcg_temp_free_i32(zero
);
4654 tcg_temp_free_i32(max
);
4657 void gen_sshl_i64(TCGv_i64 dst
, TCGv_i64 src
, TCGv_i64 shift
)
4659 TCGv_i64 lval
= tcg_temp_new_i64();
4660 TCGv_i64 rval
= tcg_temp_new_i64();
4661 TCGv_i64 lsh
= tcg_temp_new_i64();
4662 TCGv_i64 rsh
= tcg_temp_new_i64();
4663 TCGv_i64 zero
= tcg_const_i64(0);
4664 TCGv_i64 max
= tcg_const_i64(63);
4667 * Rely on the TCG guarantee that out of range shifts produce
4668 * unspecified results, not undefined behaviour (i.e. no trap).
4669 * Discard out-of-range results after the fact.
4671 tcg_gen_ext8s_i64(lsh
, shift
);
4672 tcg_gen_neg_i64(rsh
, lsh
);
4673 tcg_gen_shl_i64(lval
, src
, lsh
);
4674 tcg_gen_umin_i64(rsh
, rsh
, max
);
4675 tcg_gen_sar_i64(rval
, src
, rsh
);
4676 tcg_gen_movcond_i64(TCG_COND_LEU
, lval
, lsh
, max
, lval
, zero
);
4677 tcg_gen_movcond_i64(TCG_COND_LT
, dst
, lsh
, zero
, rval
, lval
);
4679 tcg_temp_free_i64(lval
);
4680 tcg_temp_free_i64(rval
);
4681 tcg_temp_free_i64(lsh
);
4682 tcg_temp_free_i64(rsh
);
4683 tcg_temp_free_i64(zero
);
4684 tcg_temp_free_i64(max
);
4687 static void gen_sshl_vec(unsigned vece
, TCGv_vec dst
,
4688 TCGv_vec src
, TCGv_vec shift
)
4690 TCGv_vec lval
= tcg_temp_new_vec_matching(dst
);
4691 TCGv_vec rval
= tcg_temp_new_vec_matching(dst
);
4692 TCGv_vec lsh
= tcg_temp_new_vec_matching(dst
);
4693 TCGv_vec rsh
= tcg_temp_new_vec_matching(dst
);
4694 TCGv_vec tmp
= tcg_temp_new_vec_matching(dst
);
4697 * Rely on the TCG guarantee that out of range shifts produce
4698 * unspecified results, not undefined behaviour (i.e. no trap).
4699 * Discard out-of-range results after the fact.
4701 tcg_gen_neg_vec(vece
, rsh
, shift
);
4703 tcg_gen_mov_vec(lsh
, shift
);
4705 tcg_gen_dupi_vec(vece
, tmp
, 0xff);
4706 tcg_gen_and_vec(vece
, lsh
, shift
, tmp
);
4707 tcg_gen_and_vec(vece
, rsh
, rsh
, tmp
);
4710 /* Bound rsh so out of bound right shift gets -1. */
4711 tcg_gen_dupi_vec(vece
, tmp
, (8 << vece
) - 1);
4712 tcg_gen_umin_vec(vece
, rsh
, rsh
, tmp
);
4713 tcg_gen_cmp_vec(TCG_COND_GT
, vece
, tmp
, lsh
, tmp
);
4715 tcg_gen_shlv_vec(vece
, lval
, src
, lsh
);
4716 tcg_gen_sarv_vec(vece
, rval
, src
, rsh
);
4718 /* Select in-bound left shift. */
4719 tcg_gen_andc_vec(vece
, lval
, lval
, tmp
);
4721 /* Select between left and right shift. */
4723 tcg_gen_dupi_vec(vece
, tmp
, 0);
4724 tcg_gen_cmpsel_vec(TCG_COND_LT
, vece
, dst
, lsh
, tmp
, rval
, lval
);
4726 tcg_gen_dupi_vec(vece
, tmp
, 0x80);
4727 tcg_gen_cmpsel_vec(TCG_COND_LT
, vece
, dst
, lsh
, tmp
, lval
, rval
);
4730 tcg_temp_free_vec(lval
);
4731 tcg_temp_free_vec(rval
);
4732 tcg_temp_free_vec(lsh
);
4733 tcg_temp_free_vec(rsh
);
4734 tcg_temp_free_vec(tmp
);
4737 void gen_gvec_sshl(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
4738 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
4740 static const TCGOpcode vecop_list
[] = {
4741 INDEX_op_neg_vec
, INDEX_op_umin_vec
, INDEX_op_shlv_vec
,
4742 INDEX_op_sarv_vec
, INDEX_op_cmp_vec
, INDEX_op_cmpsel_vec
, 0
4744 static const GVecGen3 ops
[4] = {
4745 { .fniv
= gen_sshl_vec
,
4746 .fno
= gen_helper_gvec_sshl_b
,
4747 .opt_opc
= vecop_list
,
4749 { .fniv
= gen_sshl_vec
,
4750 .fno
= gen_helper_gvec_sshl_h
,
4751 .opt_opc
= vecop_list
,
4753 { .fni4
= gen_sshl_i32
,
4754 .fniv
= gen_sshl_vec
,
4755 .opt_opc
= vecop_list
,
4757 { .fni8
= gen_sshl_i64
,
4758 .fniv
= gen_sshl_vec
,
4759 .opt_opc
= vecop_list
,
4762 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &ops
[vece
]);
4765 static void gen_uqadd_vec(unsigned vece
, TCGv_vec t
, TCGv_vec sat
,
4766 TCGv_vec a
, TCGv_vec b
)
4768 TCGv_vec x
= tcg_temp_new_vec_matching(t
);
4769 tcg_gen_add_vec(vece
, x
, a
, b
);
4770 tcg_gen_usadd_vec(vece
, t
, a
, b
);
4771 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, x
, x
, t
);
4772 tcg_gen_or_vec(vece
, sat
, sat
, x
);
4773 tcg_temp_free_vec(x
);
4776 void gen_gvec_uqadd_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
4777 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
4779 static const TCGOpcode vecop_list
[] = {
4780 INDEX_op_usadd_vec
, INDEX_op_cmp_vec
, INDEX_op_add_vec
, 0
4782 static const GVecGen4 ops
[4] = {
4783 { .fniv
= gen_uqadd_vec
,
4784 .fno
= gen_helper_gvec_uqadd_b
,
4786 .opt_opc
= vecop_list
,
4788 { .fniv
= gen_uqadd_vec
,
4789 .fno
= gen_helper_gvec_uqadd_h
,
4791 .opt_opc
= vecop_list
,
4793 { .fniv
= gen_uqadd_vec
,
4794 .fno
= gen_helper_gvec_uqadd_s
,
4796 .opt_opc
= vecop_list
,
4798 { .fniv
= gen_uqadd_vec
,
4799 .fno
= gen_helper_gvec_uqadd_d
,
4801 .opt_opc
= vecop_list
,
4804 tcg_gen_gvec_4(rd_ofs
, offsetof(CPUARMState
, vfp
.qc
),
4805 rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &ops
[vece
]);
4808 static void gen_sqadd_vec(unsigned vece
, TCGv_vec t
, TCGv_vec sat
,
4809 TCGv_vec a
, TCGv_vec b
)
4811 TCGv_vec x
= tcg_temp_new_vec_matching(t
);
4812 tcg_gen_add_vec(vece
, x
, a
, b
);
4813 tcg_gen_ssadd_vec(vece
, t
, a
, b
);
4814 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, x
, x
, t
);
4815 tcg_gen_or_vec(vece
, sat
, sat
, x
);
4816 tcg_temp_free_vec(x
);
4819 void gen_gvec_sqadd_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
4820 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
4822 static const TCGOpcode vecop_list
[] = {
4823 INDEX_op_ssadd_vec
, INDEX_op_cmp_vec
, INDEX_op_add_vec
, 0
4825 static const GVecGen4 ops
[4] = {
4826 { .fniv
= gen_sqadd_vec
,
4827 .fno
= gen_helper_gvec_sqadd_b
,
4828 .opt_opc
= vecop_list
,
4831 { .fniv
= gen_sqadd_vec
,
4832 .fno
= gen_helper_gvec_sqadd_h
,
4833 .opt_opc
= vecop_list
,
4836 { .fniv
= gen_sqadd_vec
,
4837 .fno
= gen_helper_gvec_sqadd_s
,
4838 .opt_opc
= vecop_list
,
4841 { .fniv
= gen_sqadd_vec
,
4842 .fno
= gen_helper_gvec_sqadd_d
,
4843 .opt_opc
= vecop_list
,
4847 tcg_gen_gvec_4(rd_ofs
, offsetof(CPUARMState
, vfp
.qc
),
4848 rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &ops
[vece
]);
4851 static void gen_uqsub_vec(unsigned vece
, TCGv_vec t
, TCGv_vec sat
,
4852 TCGv_vec a
, TCGv_vec b
)
4854 TCGv_vec x
= tcg_temp_new_vec_matching(t
);
4855 tcg_gen_sub_vec(vece
, x
, a
, b
);
4856 tcg_gen_ussub_vec(vece
, t
, a
, b
);
4857 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, x
, x
, t
);
4858 tcg_gen_or_vec(vece
, sat
, sat
, x
);
4859 tcg_temp_free_vec(x
);
4862 void gen_gvec_uqsub_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
4863 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
4865 static const TCGOpcode vecop_list
[] = {
4866 INDEX_op_ussub_vec
, INDEX_op_cmp_vec
, INDEX_op_sub_vec
, 0
4868 static const GVecGen4 ops
[4] = {
4869 { .fniv
= gen_uqsub_vec
,
4870 .fno
= gen_helper_gvec_uqsub_b
,
4871 .opt_opc
= vecop_list
,
4874 { .fniv
= gen_uqsub_vec
,
4875 .fno
= gen_helper_gvec_uqsub_h
,
4876 .opt_opc
= vecop_list
,
4879 { .fniv
= gen_uqsub_vec
,
4880 .fno
= gen_helper_gvec_uqsub_s
,
4881 .opt_opc
= vecop_list
,
4884 { .fniv
= gen_uqsub_vec
,
4885 .fno
= gen_helper_gvec_uqsub_d
,
4886 .opt_opc
= vecop_list
,
4890 tcg_gen_gvec_4(rd_ofs
, offsetof(CPUARMState
, vfp
.qc
),
4891 rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &ops
[vece
]);
4894 static void gen_sqsub_vec(unsigned vece
, TCGv_vec t
, TCGv_vec sat
,
4895 TCGv_vec a
, TCGv_vec b
)
4897 TCGv_vec x
= tcg_temp_new_vec_matching(t
);
4898 tcg_gen_sub_vec(vece
, x
, a
, b
);
4899 tcg_gen_sssub_vec(vece
, t
, a
, b
);
4900 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, x
, x
, t
);
4901 tcg_gen_or_vec(vece
, sat
, sat
, x
);
4902 tcg_temp_free_vec(x
);
4905 void gen_gvec_sqsub_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
4906 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
4908 static const TCGOpcode vecop_list
[] = {
4909 INDEX_op_sssub_vec
, INDEX_op_cmp_vec
, INDEX_op_sub_vec
, 0
4911 static const GVecGen4 ops
[4] = {
4912 { .fniv
= gen_sqsub_vec
,
4913 .fno
= gen_helper_gvec_sqsub_b
,
4914 .opt_opc
= vecop_list
,
4917 { .fniv
= gen_sqsub_vec
,
4918 .fno
= gen_helper_gvec_sqsub_h
,
4919 .opt_opc
= vecop_list
,
4922 { .fniv
= gen_sqsub_vec
,
4923 .fno
= gen_helper_gvec_sqsub_s
,
4924 .opt_opc
= vecop_list
,
4927 { .fniv
= gen_sqsub_vec
,
4928 .fno
= gen_helper_gvec_sqsub_d
,
4929 .opt_opc
= vecop_list
,
4933 tcg_gen_gvec_4(rd_ofs
, offsetof(CPUARMState
, vfp
.qc
),
4934 rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &ops
[vece
]);
4937 static void gen_sabd_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4939 TCGv_i32 t
= tcg_temp_new_i32();
4941 tcg_gen_sub_i32(t
, a
, b
);
4942 tcg_gen_sub_i32(d
, b
, a
);
4943 tcg_gen_movcond_i32(TCG_COND_LT
, d
, a
, b
, d
, t
);
4944 tcg_temp_free_i32(t
);
4947 static void gen_sabd_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
4949 TCGv_i64 t
= tcg_temp_new_i64();
4951 tcg_gen_sub_i64(t
, a
, b
);
4952 tcg_gen_sub_i64(d
, b
, a
);
4953 tcg_gen_movcond_i64(TCG_COND_LT
, d
, a
, b
, d
, t
);
4954 tcg_temp_free_i64(t
);
4957 static void gen_sabd_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
4959 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
4961 tcg_gen_smin_vec(vece
, t
, a
, b
);
4962 tcg_gen_smax_vec(vece
, d
, a
, b
);
4963 tcg_gen_sub_vec(vece
, d
, d
, t
);
4964 tcg_temp_free_vec(t
);
4967 void gen_gvec_sabd(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
4968 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
4970 static const TCGOpcode vecop_list
[] = {
4971 INDEX_op_sub_vec
, INDEX_op_smin_vec
, INDEX_op_smax_vec
, 0
4973 static const GVecGen3 ops
[4] = {
4974 { .fniv
= gen_sabd_vec
,
4975 .fno
= gen_helper_gvec_sabd_b
,
4976 .opt_opc
= vecop_list
,
4978 { .fniv
= gen_sabd_vec
,
4979 .fno
= gen_helper_gvec_sabd_h
,
4980 .opt_opc
= vecop_list
,
4982 { .fni4
= gen_sabd_i32
,
4983 .fniv
= gen_sabd_vec
,
4984 .fno
= gen_helper_gvec_sabd_s
,
4985 .opt_opc
= vecop_list
,
4987 { .fni8
= gen_sabd_i64
,
4988 .fniv
= gen_sabd_vec
,
4989 .fno
= gen_helper_gvec_sabd_d
,
4990 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4991 .opt_opc
= vecop_list
,
4994 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &ops
[vece
]);
4997 static void gen_uabd_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4999 TCGv_i32 t
= tcg_temp_new_i32();
5001 tcg_gen_sub_i32(t
, a
, b
);
5002 tcg_gen_sub_i32(d
, b
, a
);
5003 tcg_gen_movcond_i32(TCG_COND_LTU
, d
, a
, b
, d
, t
);
5004 tcg_temp_free_i32(t
);
5007 static void gen_uabd_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
5009 TCGv_i64 t
= tcg_temp_new_i64();
5011 tcg_gen_sub_i64(t
, a
, b
);
5012 tcg_gen_sub_i64(d
, b
, a
);
5013 tcg_gen_movcond_i64(TCG_COND_LTU
, d
, a
, b
, d
, t
);
5014 tcg_temp_free_i64(t
);
5017 static void gen_uabd_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
5019 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
5021 tcg_gen_umin_vec(vece
, t
, a
, b
);
5022 tcg_gen_umax_vec(vece
, d
, a
, b
);
5023 tcg_gen_sub_vec(vece
, d
, d
, t
);
5024 tcg_temp_free_vec(t
);
5027 void gen_gvec_uabd(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
5028 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
5030 static const TCGOpcode vecop_list
[] = {
5031 INDEX_op_sub_vec
, INDEX_op_umin_vec
, INDEX_op_umax_vec
, 0
5033 static const GVecGen3 ops
[4] = {
5034 { .fniv
= gen_uabd_vec
,
5035 .fno
= gen_helper_gvec_uabd_b
,
5036 .opt_opc
= vecop_list
,
5038 { .fniv
= gen_uabd_vec
,
5039 .fno
= gen_helper_gvec_uabd_h
,
5040 .opt_opc
= vecop_list
,
5042 { .fni4
= gen_uabd_i32
,
5043 .fniv
= gen_uabd_vec
,
5044 .fno
= gen_helper_gvec_uabd_s
,
5045 .opt_opc
= vecop_list
,
5047 { .fni8
= gen_uabd_i64
,
5048 .fniv
= gen_uabd_vec
,
5049 .fno
= gen_helper_gvec_uabd_d
,
5050 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
5051 .opt_opc
= vecop_list
,
5054 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &ops
[vece
]);
5057 static void gen_saba_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
5059 TCGv_i32 t
= tcg_temp_new_i32();
5060 gen_sabd_i32(t
, a
, b
);
5061 tcg_gen_add_i32(d
, d
, t
);
5062 tcg_temp_free_i32(t
);
5065 static void gen_saba_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
5067 TCGv_i64 t
= tcg_temp_new_i64();
5068 gen_sabd_i64(t
, a
, b
);
5069 tcg_gen_add_i64(d
, d
, t
);
5070 tcg_temp_free_i64(t
);
5073 static void gen_saba_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
5075 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
5076 gen_sabd_vec(vece
, t
, a
, b
);
5077 tcg_gen_add_vec(vece
, d
, d
, t
);
5078 tcg_temp_free_vec(t
);
5081 void gen_gvec_saba(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
5082 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
5084 static const TCGOpcode vecop_list
[] = {
5085 INDEX_op_sub_vec
, INDEX_op_add_vec
,
5086 INDEX_op_smin_vec
, INDEX_op_smax_vec
, 0
5088 static const GVecGen3 ops
[4] = {
5089 { .fniv
= gen_saba_vec
,
5090 .fno
= gen_helper_gvec_saba_b
,
5091 .opt_opc
= vecop_list
,
5094 { .fniv
= gen_saba_vec
,
5095 .fno
= gen_helper_gvec_saba_h
,
5096 .opt_opc
= vecop_list
,
5099 { .fni4
= gen_saba_i32
,
5100 .fniv
= gen_saba_vec
,
5101 .fno
= gen_helper_gvec_saba_s
,
5102 .opt_opc
= vecop_list
,
5105 { .fni8
= gen_saba_i64
,
5106 .fniv
= gen_saba_vec
,
5107 .fno
= gen_helper_gvec_saba_d
,
5108 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
5109 .opt_opc
= vecop_list
,
5113 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &ops
[vece
]);
5116 static void gen_uaba_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
5118 TCGv_i32 t
= tcg_temp_new_i32();
5119 gen_uabd_i32(t
, a
, b
);
5120 tcg_gen_add_i32(d
, d
, t
);
5121 tcg_temp_free_i32(t
);
5124 static void gen_uaba_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
5126 TCGv_i64 t
= tcg_temp_new_i64();
5127 gen_uabd_i64(t
, a
, b
);
5128 tcg_gen_add_i64(d
, d
, t
);
5129 tcg_temp_free_i64(t
);
5132 static void gen_uaba_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
5134 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
5135 gen_uabd_vec(vece
, t
, a
, b
);
5136 tcg_gen_add_vec(vece
, d
, d
, t
);
5137 tcg_temp_free_vec(t
);
5140 void gen_gvec_uaba(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
5141 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
5143 static const TCGOpcode vecop_list
[] = {
5144 INDEX_op_sub_vec
, INDEX_op_add_vec
,
5145 INDEX_op_umin_vec
, INDEX_op_umax_vec
, 0
5147 static const GVecGen3 ops
[4] = {
5148 { .fniv
= gen_uaba_vec
,
5149 .fno
= gen_helper_gvec_uaba_b
,
5150 .opt_opc
= vecop_list
,
5153 { .fniv
= gen_uaba_vec
,
5154 .fno
= gen_helper_gvec_uaba_h
,
5155 .opt_opc
= vecop_list
,
5158 { .fni4
= gen_uaba_i32
,
5159 .fniv
= gen_uaba_vec
,
5160 .fno
= gen_helper_gvec_uaba_s
,
5161 .opt_opc
= vecop_list
,
5164 { .fni8
= gen_uaba_i64
,
5165 .fniv
= gen_uaba_vec
,
5166 .fno
= gen_helper_gvec_uaba_d
,
5167 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
5168 .opt_opc
= vecop_list
,
5172 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &ops
[vece
]);
5175 /* Translate a NEON data processing instruction. Return nonzero if the
5176 instruction is invalid.
5177 We process data in a mixture of 32-bit and 64-bit chunks.
5178 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
5180 static int disas_neon_data_insn(DisasContext
*s
, uint32_t insn
)
5184 int rd
, rn
, rm
, rd_ofs
, rn_ofs
, rm_ofs
;
5190 TCGv_i32 tmp
, tmp2
, tmp3
, tmp4
, tmp5
;
5194 if (!arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
5198 /* FIXME: this access check should not take precedence over UNDEF
5199 * for invalid encodings; we will generate incorrect syndrome information
5200 * for attempts to execute invalid vfp/neon encodings with FP disabled.
5202 if (s
->fp_excp_el
) {
5203 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
5204 syn_simd_access_trap(1, 0xe, false), s
->fp_excp_el
);
5208 if (!s
->vfp_enabled
)
5210 q
= (insn
& (1 << 6)) != 0;
5211 u
= (insn
>> 24) & 1;
5212 VFP_DREG_D(rd
, insn
);
5213 VFP_DREG_N(rn
, insn
);
5214 VFP_DREG_M(rm
, insn
);
5215 size
= (insn
>> 20) & 3;
5216 vec_size
= q
? 16 : 8;
5217 rd_ofs
= neon_reg_offset(rd
, 0);
5218 rn_ofs
= neon_reg_offset(rn
, 0);
5219 rm_ofs
= neon_reg_offset(rm
, 0);
5221 if ((insn
& (1 << 23)) == 0) {
5222 /* Three register same length: handled by decodetree */
5224 } else if (insn
& (1 << 4)) {
5225 /* Two registers and shift or reg and imm: handled by decodetree */
5227 } else { /* (insn & 0x00800010 == 0x00800000) */
5229 op
= (insn
>> 8) & 0xf;
5230 if ((insn
& (1 << 6)) == 0) {
5231 /* Three registers of different lengths. */
5232 /* undefreq: bit 0 : UNDEF if size == 0
5233 * bit 1 : UNDEF if size == 1
5234 * bit 2 : UNDEF if size == 2
5235 * bit 3 : UNDEF if U == 1
5236 * Note that [2:0] set implies 'always UNDEF'
5239 /* prewiden, src1_wide, src2_wide, undefreq */
5240 static const int neon_3reg_wide
[16][4] = {
5241 {0, 0, 0, 7}, /* VADDL: handled by decodetree */
5242 {0, 0, 0, 7}, /* VADDW: handled by decodetree */
5243 {0, 0, 0, 7}, /* VSUBL: handled by decodetree */
5244 {0, 0, 0, 7}, /* VSUBW: handled by decodetree */
5245 {0, 0, 0, 7}, /* VADDHN: handled by decodetree */
5246 {0, 0, 0, 7}, /* VABAL */
5247 {0, 0, 0, 7}, /* VSUBHN: handled by decodetree */
5248 {0, 0, 0, 7}, /* VABDL */
5249 {0, 0, 0, 7}, /* VMLAL */
5250 {0, 0, 0, 7}, /* VQDMLAL */
5251 {0, 0, 0, 7}, /* VMLSL */
5252 {0, 0, 0, 7}, /* VQDMLSL */
5253 {0, 0, 0, 7}, /* Integer VMULL */
5254 {0, 0, 0, 7}, /* VQDMULL */
5255 {0, 0, 0, 0xa}, /* Polynomial VMULL */
5256 {0, 0, 0, 7}, /* Reserved: always UNDEF */
5259 undefreq
= neon_3reg_wide
[op
][3];
5261 if ((undefreq
& (1 << size
)) ||
5262 ((undefreq
& 8) && u
)) {
5269 /* Handle polynomial VMULL in a single pass. */
5273 tcg_gen_gvec_3_ool(rd_ofs
, rn_ofs
, rm_ofs
, 16, 16,
5274 0, gen_helper_neon_pmull_h
);
5277 if (!dc_isar_feature(aa32_pmull
, s
)) {
5280 tcg_gen_gvec_3_ool(rd_ofs
, rn_ofs
, rm_ofs
, 16, 16,
5281 0, gen_helper_gvec_pmull_q
);
5285 abort(); /* all others handled by decodetree */
5287 /* Two registers and a scalar. NB that for ops of this form
5288 * the ARM ARM labels bit 24 as Q, but it is in our variable
5295 case 1: /* Float VMLA scalar */
5296 case 5: /* Floating point VMLS scalar */
5297 case 9: /* Floating point VMUL scalar */
5302 case 0: /* Integer VMLA scalar */
5303 case 4: /* Integer VMLS scalar */
5304 case 8: /* Integer VMUL scalar */
5305 case 12: /* VQDMULH scalar */
5306 case 13: /* VQRDMULH scalar */
5307 if (u
&& ((rd
| rn
) & 1)) {
5310 tmp
= neon_get_scalar(size
, rm
);
5311 neon_store_scratch(0, tmp
);
5312 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
5313 tmp
= neon_load_scratch(0);
5314 tmp2
= neon_load_reg(rn
, pass
);
5317 gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5319 gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5321 } else if (op
== 13) {
5323 gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5325 gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5327 } else if (op
& 1) {
5328 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5329 gen_helper_vfp_muls(tmp
, tmp
, tmp2
, fpstatus
);
5330 tcg_temp_free_ptr(fpstatus
);
5333 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
5334 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
5335 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
5339 tcg_temp_free_i32(tmp2
);
5342 tmp2
= neon_load_reg(rd
, pass
);
5345 gen_neon_add(size
, tmp
, tmp2
);
5349 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5350 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
5351 tcg_temp_free_ptr(fpstatus
);
5355 gen_neon_rsb(size
, tmp
, tmp2
);
5359 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5360 gen_helper_vfp_subs(tmp
, tmp2
, tmp
, fpstatus
);
5361 tcg_temp_free_ptr(fpstatus
);
5367 tcg_temp_free_i32(tmp2
);
5369 neon_store_reg(rd
, pass
, tmp
);
5372 case 3: /* VQDMLAL scalar */
5373 case 7: /* VQDMLSL scalar */
5374 case 11: /* VQDMULL scalar */
5379 case 2: /* VMLAL sclar */
5380 case 6: /* VMLSL scalar */
5381 case 10: /* VMULL scalar */
5385 tmp2
= neon_get_scalar(size
, rm
);
5386 /* We need a copy of tmp2 because gen_neon_mull
5387 * deletes it during pass 0. */
5388 tmp4
= tcg_temp_new_i32();
5389 tcg_gen_mov_i32(tmp4
, tmp2
);
5390 tmp3
= neon_load_reg(rn
, 1);
5392 for (pass
= 0; pass
< 2; pass
++) {
5394 tmp
= neon_load_reg(rn
, 0);
5399 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
5401 neon_load_reg64(cpu_V1
, rd
+ pass
);
5405 gen_neon_negl(cpu_V0
, size
);
5408 gen_neon_addl(size
);
5411 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5413 gen_neon_negl(cpu_V0
, size
);
5415 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
5421 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5426 neon_store_reg64(cpu_V0
, rd
+ pass
);
5429 case 14: /* VQRDMLAH scalar */
5430 case 15: /* VQRDMLSH scalar */
5432 NeonGenThreeOpEnvFn
*fn
;
5434 if (!dc_isar_feature(aa32_rdm
, s
)) {
5437 if (u
&& ((rd
| rn
) & 1)) {
5442 fn
= gen_helper_neon_qrdmlah_s16
;
5444 fn
= gen_helper_neon_qrdmlah_s32
;
5448 fn
= gen_helper_neon_qrdmlsh_s16
;
5450 fn
= gen_helper_neon_qrdmlsh_s32
;
5454 tmp2
= neon_get_scalar(size
, rm
);
5455 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
5456 tmp
= neon_load_reg(rn
, pass
);
5457 tmp3
= neon_load_reg(rd
, pass
);
5458 fn(tmp
, cpu_env
, tmp
, tmp2
, tmp3
);
5459 tcg_temp_free_i32(tmp3
);
5460 neon_store_reg(rd
, pass
, tmp
);
5462 tcg_temp_free_i32(tmp2
);
5466 g_assert_not_reached();
5469 } else { /* size == 3 */
5472 imm
= (insn
>> 8) & 0xf;
5477 if (q
&& ((rd
| rn
| rm
) & 1)) {
5482 neon_load_reg64(cpu_V0
, rn
);
5484 neon_load_reg64(cpu_V1
, rn
+ 1);
5486 } else if (imm
== 8) {
5487 neon_load_reg64(cpu_V0
, rn
+ 1);
5489 neon_load_reg64(cpu_V1
, rm
);
5492 tmp64
= tcg_temp_new_i64();
5494 neon_load_reg64(cpu_V0
, rn
);
5495 neon_load_reg64(tmp64
, rn
+ 1);
5497 neon_load_reg64(cpu_V0
, rn
+ 1);
5498 neon_load_reg64(tmp64
, rm
);
5500 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, (imm
& 7) * 8);
5501 tcg_gen_shli_i64(cpu_V1
, tmp64
, 64 - ((imm
& 7) * 8));
5502 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5504 neon_load_reg64(cpu_V1
, rm
);
5506 neon_load_reg64(cpu_V1
, rm
+ 1);
5509 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
5510 tcg_gen_shri_i64(tmp64
, tmp64
, imm
* 8);
5511 tcg_gen_or_i64(cpu_V1
, cpu_V1
, tmp64
);
5512 tcg_temp_free_i64(tmp64
);
5515 neon_load_reg64(cpu_V0
, rn
);
5516 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, imm
* 8);
5517 neon_load_reg64(cpu_V1
, rm
);
5518 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
5519 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5521 neon_store_reg64(cpu_V0
, rd
);
5523 neon_store_reg64(cpu_V1
, rd
+ 1);
5525 } else if ((insn
& (1 << 11)) == 0) {
5526 /* Two register misc. */
5527 op
= ((insn
>> 12) & 0x30) | ((insn
>> 7) & 0xf);
5528 size
= (insn
>> 18) & 3;
5529 /* UNDEF for unknown op values and bad op-size combinations */
5530 if ((neon_2rm_sizes
[op
] & (1 << size
)) == 0) {
5533 if (neon_2rm_is_v8_op(op
) &&
5534 !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
5537 if ((op
!= NEON_2RM_VMOVN
&& op
!= NEON_2RM_VQMOVN
) &&
5538 q
&& ((rm
| rd
) & 1)) {
5542 case NEON_2RM_VREV64
:
5543 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
5544 tmp
= neon_load_reg(rm
, pass
* 2);
5545 tmp2
= neon_load_reg(rm
, pass
* 2 + 1);
5547 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
5548 case 1: gen_swap_half(tmp
); break;
5549 case 2: /* no-op */ break;
5552 neon_store_reg(rd
, pass
* 2 + 1, tmp
);
5554 neon_store_reg(rd
, pass
* 2, tmp2
);
5557 case 0: tcg_gen_bswap32_i32(tmp2
, tmp2
); break;
5558 case 1: gen_swap_half(tmp2
); break;
5561 neon_store_reg(rd
, pass
* 2, tmp2
);
5565 case NEON_2RM_VPADDL
: case NEON_2RM_VPADDL_U
:
5566 case NEON_2RM_VPADAL
: case NEON_2RM_VPADAL_U
:
5567 for (pass
= 0; pass
< q
+ 1; pass
++) {
5568 tmp
= neon_load_reg(rm
, pass
* 2);
5569 gen_neon_widen(cpu_V0
, tmp
, size
, op
& 1);
5570 tmp
= neon_load_reg(rm
, pass
* 2 + 1);
5571 gen_neon_widen(cpu_V1
, tmp
, size
, op
& 1);
5573 case 0: gen_helper_neon_paddl_u16(CPU_V001
); break;
5574 case 1: gen_helper_neon_paddl_u32(CPU_V001
); break;
5575 case 2: tcg_gen_add_i64(CPU_V001
); break;
5578 if (op
>= NEON_2RM_VPADAL
) {
5580 neon_load_reg64(cpu_V1
, rd
+ pass
);
5581 gen_neon_addl(size
);
5583 neon_store_reg64(cpu_V0
, rd
+ pass
);
5589 for (n
= 0; n
< (q
? 4 : 2); n
+= 2) {
5590 tmp
= neon_load_reg(rm
, n
);
5591 tmp2
= neon_load_reg(rd
, n
+ 1);
5592 neon_store_reg(rm
, n
, tmp2
);
5593 neon_store_reg(rd
, n
+ 1, tmp
);
5600 if (gen_neon_unzip(rd
, rm
, size
, q
)) {
5605 if (gen_neon_zip(rd
, rm
, size
, q
)) {
5609 case NEON_2RM_VMOVN
: case NEON_2RM_VQMOVN
:
5610 /* also VQMOVUN; op field and mnemonics don't line up */
5615 for (pass
= 0; pass
< 2; pass
++) {
5616 neon_load_reg64(cpu_V0
, rm
+ pass
);
5617 tmp
= tcg_temp_new_i32();
5618 gen_neon_narrow_op(op
== NEON_2RM_VMOVN
, q
, size
,
5623 neon_store_reg(rd
, 0, tmp2
);
5624 neon_store_reg(rd
, 1, tmp
);
5628 case NEON_2RM_VSHLL
:
5629 if (q
|| (rd
& 1)) {
5632 tmp
= neon_load_reg(rm
, 0);
5633 tmp2
= neon_load_reg(rm
, 1);
5634 for (pass
= 0; pass
< 2; pass
++) {
5637 gen_neon_widen(cpu_V0
, tmp
, size
, 1);
5638 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, 8 << size
);
5639 neon_store_reg64(cpu_V0
, rd
+ pass
);
5642 case NEON_2RM_VCVT_F16_F32
:
5647 if (!dc_isar_feature(aa32_fp16_spconv
, s
) ||
5651 fpst
= get_fpstatus_ptr(true);
5652 ahp
= get_ahp_flag();
5653 tmp
= neon_load_reg(rm
, 0);
5654 gen_helper_vfp_fcvt_f32_to_f16(tmp
, tmp
, fpst
, ahp
);
5655 tmp2
= neon_load_reg(rm
, 1);
5656 gen_helper_vfp_fcvt_f32_to_f16(tmp2
, tmp2
, fpst
, ahp
);
5657 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
5658 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
5659 tcg_temp_free_i32(tmp
);
5660 tmp
= neon_load_reg(rm
, 2);
5661 gen_helper_vfp_fcvt_f32_to_f16(tmp
, tmp
, fpst
, ahp
);
5662 tmp3
= neon_load_reg(rm
, 3);
5663 neon_store_reg(rd
, 0, tmp2
);
5664 gen_helper_vfp_fcvt_f32_to_f16(tmp3
, tmp3
, fpst
, ahp
);
5665 tcg_gen_shli_i32(tmp3
, tmp3
, 16);
5666 tcg_gen_or_i32(tmp3
, tmp3
, tmp
);
5667 neon_store_reg(rd
, 1, tmp3
);
5668 tcg_temp_free_i32(tmp
);
5669 tcg_temp_free_i32(ahp
);
5670 tcg_temp_free_ptr(fpst
);
5673 case NEON_2RM_VCVT_F32_F16
:
5677 if (!dc_isar_feature(aa32_fp16_spconv
, s
) ||
5681 fpst
= get_fpstatus_ptr(true);
5682 ahp
= get_ahp_flag();
5683 tmp3
= tcg_temp_new_i32();
5684 tmp
= neon_load_reg(rm
, 0);
5685 tmp2
= neon_load_reg(rm
, 1);
5686 tcg_gen_ext16u_i32(tmp3
, tmp
);
5687 gen_helper_vfp_fcvt_f16_to_f32(tmp3
, tmp3
, fpst
, ahp
);
5688 neon_store_reg(rd
, 0, tmp3
);
5689 tcg_gen_shri_i32(tmp
, tmp
, 16);
5690 gen_helper_vfp_fcvt_f16_to_f32(tmp
, tmp
, fpst
, ahp
);
5691 neon_store_reg(rd
, 1, tmp
);
5692 tmp3
= tcg_temp_new_i32();
5693 tcg_gen_ext16u_i32(tmp3
, tmp2
);
5694 gen_helper_vfp_fcvt_f16_to_f32(tmp3
, tmp3
, fpst
, ahp
);
5695 neon_store_reg(rd
, 2, tmp3
);
5696 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
5697 gen_helper_vfp_fcvt_f16_to_f32(tmp2
, tmp2
, fpst
, ahp
);
5698 neon_store_reg(rd
, 3, tmp2
);
5699 tcg_temp_free_i32(ahp
);
5700 tcg_temp_free_ptr(fpst
);
5703 case NEON_2RM_AESE
: case NEON_2RM_AESMC
:
5704 if (!dc_isar_feature(aa32_aes
, s
) || ((rm
| rd
) & 1)) {
5708 * Bit 6 is the lowest opcode bit; it distinguishes
5709 * between encryption (AESE/AESMC) and decryption
5712 if (op
== NEON_2RM_AESE
) {
5713 tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd
),
5714 vfp_reg_offset(true, rd
),
5715 vfp_reg_offset(true, rm
),
5716 16, 16, extract32(insn
, 6, 1),
5717 gen_helper_crypto_aese
);
5719 tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd
),
5720 vfp_reg_offset(true, rm
),
5721 16, 16, extract32(insn
, 6, 1),
5722 gen_helper_crypto_aesmc
);
5725 case NEON_2RM_SHA1H
:
5726 if (!dc_isar_feature(aa32_sha1
, s
) || ((rm
| rd
) & 1)) {
5729 tcg_gen_gvec_2_ool(rd_ofs
, rm_ofs
, 16, 16, 0,
5730 gen_helper_crypto_sha1h
);
5732 case NEON_2RM_SHA1SU1
:
5733 if ((rm
| rd
) & 1) {
5736 /* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */
5738 if (!dc_isar_feature(aa32_sha2
, s
)) {
5741 } else if (!dc_isar_feature(aa32_sha1
, s
)) {
5744 tcg_gen_gvec_2_ool(rd_ofs
, rm_ofs
, 16, 16, 0,
5745 q
? gen_helper_crypto_sha256su0
5746 : gen_helper_crypto_sha1su1
);
5749 tcg_gen_gvec_not(0, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
5752 tcg_gen_gvec_neg(size
, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
5755 tcg_gen_gvec_abs(size
, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
5758 case NEON_2RM_VCEQ0
:
5759 gen_gvec_ceq0(size
, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
5761 case NEON_2RM_VCGT0
:
5762 gen_gvec_cgt0(size
, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
5764 case NEON_2RM_VCLE0
:
5765 gen_gvec_cle0(size
, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
5767 case NEON_2RM_VCGE0
:
5768 gen_gvec_cge0(size
, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
5770 case NEON_2RM_VCLT0
:
5771 gen_gvec_clt0(size
, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
5776 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5777 tmp
= neon_load_reg(rm
, pass
);
5779 case NEON_2RM_VREV32
:
5781 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
5782 case 1: gen_swap_half(tmp
); break;
5786 case NEON_2RM_VREV16
:
5787 gen_rev16(tmp
, tmp
);
5791 case 0: gen_helper_neon_cls_s8(tmp
, tmp
); break;
5792 case 1: gen_helper_neon_cls_s16(tmp
, tmp
); break;
5793 case 2: gen_helper_neon_cls_s32(tmp
, tmp
); break;
5799 case 0: gen_helper_neon_clz_u8(tmp
, tmp
); break;
5800 case 1: gen_helper_neon_clz_u16(tmp
, tmp
); break;
5801 case 2: tcg_gen_clzi_i32(tmp
, tmp
, 32); break;
5806 gen_helper_neon_cnt_u8(tmp
, tmp
);
5808 case NEON_2RM_VQABS
:
5811 gen_helper_neon_qabs_s8(tmp
, cpu_env
, tmp
);
5814 gen_helper_neon_qabs_s16(tmp
, cpu_env
, tmp
);
5817 gen_helper_neon_qabs_s32(tmp
, cpu_env
, tmp
);
5822 case NEON_2RM_VQNEG
:
5825 gen_helper_neon_qneg_s8(tmp
, cpu_env
, tmp
);
5828 gen_helper_neon_qneg_s16(tmp
, cpu_env
, tmp
);
5831 gen_helper_neon_qneg_s32(tmp
, cpu_env
, tmp
);
5836 case NEON_2RM_VCGT0_F
:
5838 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5839 tmp2
= tcg_const_i32(0);
5840 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
5841 tcg_temp_free_i32(tmp2
);
5842 tcg_temp_free_ptr(fpstatus
);
5845 case NEON_2RM_VCGE0_F
:
5847 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5848 tmp2
= tcg_const_i32(0);
5849 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
, fpstatus
);
5850 tcg_temp_free_i32(tmp2
);
5851 tcg_temp_free_ptr(fpstatus
);
5854 case NEON_2RM_VCEQ0_F
:
5856 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5857 tmp2
= tcg_const_i32(0);
5858 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
, fpstatus
);
5859 tcg_temp_free_i32(tmp2
);
5860 tcg_temp_free_ptr(fpstatus
);
5863 case NEON_2RM_VCLE0_F
:
5865 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5866 tmp2
= tcg_const_i32(0);
5867 gen_helper_neon_cge_f32(tmp
, tmp2
, tmp
, fpstatus
);
5868 tcg_temp_free_i32(tmp2
);
5869 tcg_temp_free_ptr(fpstatus
);
5872 case NEON_2RM_VCLT0_F
:
5874 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5875 tmp2
= tcg_const_i32(0);
5876 gen_helper_neon_cgt_f32(tmp
, tmp2
, tmp
, fpstatus
);
5877 tcg_temp_free_i32(tmp2
);
5878 tcg_temp_free_ptr(fpstatus
);
5881 case NEON_2RM_VABS_F
:
5882 gen_helper_vfp_abss(tmp
, tmp
);
5884 case NEON_2RM_VNEG_F
:
5885 gen_helper_vfp_negs(tmp
, tmp
);
5888 tmp2
= neon_load_reg(rd
, pass
);
5889 neon_store_reg(rm
, pass
, tmp2
);
5892 tmp2
= neon_load_reg(rd
, pass
);
5894 case 0: gen_neon_trn_u8(tmp
, tmp2
); break;
5895 case 1: gen_neon_trn_u16(tmp
, tmp2
); break;
5898 neon_store_reg(rm
, pass
, tmp2
);
5900 case NEON_2RM_VRINTN
:
5901 case NEON_2RM_VRINTA
:
5902 case NEON_2RM_VRINTM
:
5903 case NEON_2RM_VRINTP
:
5904 case NEON_2RM_VRINTZ
:
5907 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5910 if (op
== NEON_2RM_VRINTZ
) {
5911 rmode
= FPROUNDING_ZERO
;
5913 rmode
= fp_decode_rm
[((op
& 0x6) >> 1) ^ 1];
5916 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5917 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
5919 gen_helper_rints(tmp
, tmp
, fpstatus
);
5920 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
5922 tcg_temp_free_ptr(fpstatus
);
5923 tcg_temp_free_i32(tcg_rmode
);
5926 case NEON_2RM_VRINTX
:
5928 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5929 gen_helper_rints_exact(tmp
, tmp
, fpstatus
);
5930 tcg_temp_free_ptr(fpstatus
);
5933 case NEON_2RM_VCVTAU
:
5934 case NEON_2RM_VCVTAS
:
5935 case NEON_2RM_VCVTNU
:
5936 case NEON_2RM_VCVTNS
:
5937 case NEON_2RM_VCVTPU
:
5938 case NEON_2RM_VCVTPS
:
5939 case NEON_2RM_VCVTMU
:
5940 case NEON_2RM_VCVTMS
:
5942 bool is_signed
= !extract32(insn
, 7, 1);
5943 TCGv_ptr fpst
= get_fpstatus_ptr(1);
5944 TCGv_i32 tcg_rmode
, tcg_shift
;
5945 int rmode
= fp_decode_rm
[extract32(insn
, 8, 2)];
5947 tcg_shift
= tcg_const_i32(0);
5948 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5949 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
5953 gen_helper_vfp_tosls(tmp
, tmp
,
5956 gen_helper_vfp_touls(tmp
, tmp
,
5960 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
5962 tcg_temp_free_i32(tcg_rmode
);
5963 tcg_temp_free_i32(tcg_shift
);
5964 tcg_temp_free_ptr(fpst
);
5967 case NEON_2RM_VRECPE
:
5968 gen_helper_recpe_u32(tmp
, tmp
);
5970 case NEON_2RM_VRSQRTE
:
5971 gen_helper_rsqrte_u32(tmp
, tmp
);
5973 case NEON_2RM_VRECPE_F
:
5975 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5976 gen_helper_recpe_f32(tmp
, tmp
, fpstatus
);
5977 tcg_temp_free_ptr(fpstatus
);
5980 case NEON_2RM_VRSQRTE_F
:
5982 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5983 gen_helper_rsqrte_f32(tmp
, tmp
, fpstatus
);
5984 tcg_temp_free_ptr(fpstatus
);
5987 case NEON_2RM_VCVT_FS
: /* VCVT.F32.S32 */
5989 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5990 gen_helper_vfp_sitos(tmp
, tmp
, fpstatus
);
5991 tcg_temp_free_ptr(fpstatus
);
5994 case NEON_2RM_VCVT_FU
: /* VCVT.F32.U32 */
5996 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5997 gen_helper_vfp_uitos(tmp
, tmp
, fpstatus
);
5998 tcg_temp_free_ptr(fpstatus
);
6001 case NEON_2RM_VCVT_SF
: /* VCVT.S32.F32 */
6003 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6004 gen_helper_vfp_tosizs(tmp
, tmp
, fpstatus
);
6005 tcg_temp_free_ptr(fpstatus
);
6008 case NEON_2RM_VCVT_UF
: /* VCVT.U32.F32 */
6010 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6011 gen_helper_vfp_touizs(tmp
, tmp
, fpstatus
);
6012 tcg_temp_free_ptr(fpstatus
);
6016 /* Reserved op values were caught by the
6017 * neon_2rm_sizes[] check earlier.
6021 neon_store_reg(rd
, pass
, tmp
);
6025 } else if ((insn
& (1 << 10)) == 0) {
6027 int n
= ((insn
>> 8) & 3) + 1;
6028 if ((rn
+ n
) > 32) {
6029 /* This is UNPREDICTABLE; we choose to UNDEF to avoid the
6030 * helper function running off the end of the register file.
6035 if (insn
& (1 << 6)) {
6036 tmp
= neon_load_reg(rd
, 0);
6038 tmp
= tcg_temp_new_i32();
6039 tcg_gen_movi_i32(tmp
, 0);
6041 tmp2
= neon_load_reg(rm
, 0);
6042 ptr1
= vfp_reg_ptr(true, rn
);
6043 tmp5
= tcg_const_i32(n
);
6044 gen_helper_neon_tbl(tmp2
, tmp2
, tmp
, ptr1
, tmp5
);
6045 tcg_temp_free_i32(tmp
);
6046 if (insn
& (1 << 6)) {
6047 tmp
= neon_load_reg(rd
, 1);
6049 tmp
= tcg_temp_new_i32();
6050 tcg_gen_movi_i32(tmp
, 0);
6052 tmp3
= neon_load_reg(rm
, 1);
6053 gen_helper_neon_tbl(tmp3
, tmp3
, tmp
, ptr1
, tmp5
);
6054 tcg_temp_free_i32(tmp5
);
6055 tcg_temp_free_ptr(ptr1
);
6056 neon_store_reg(rd
, 0, tmp2
);
6057 neon_store_reg(rd
, 1, tmp3
);
6058 tcg_temp_free_i32(tmp
);
6059 } else if ((insn
& 0x380) == 0) {
6064 if ((insn
& (7 << 16)) == 0 || (q
&& (rd
& 1))) {
6067 if (insn
& (1 << 16)) {
6069 element
= (insn
>> 17) & 7;
6070 } else if (insn
& (1 << 17)) {
6072 element
= (insn
>> 18) & 3;
6075 element
= (insn
>> 19) & 1;
6077 tcg_gen_gvec_dup_mem(size
, neon_reg_offset(rd
, 0),
6078 neon_element_offset(rm
, element
, size
),
6079 q
? 16 : 8, q
? 16 : 8);
6088 static int disas_coproc_insn(DisasContext
*s
, uint32_t insn
)
6090 int cpnum
, is64
, crn
, crm
, opc1
, opc2
, isread
, rt
, rt2
;
6091 const ARMCPRegInfo
*ri
;
6093 cpnum
= (insn
>> 8) & 0xf;
6095 /* First check for coprocessor space used for XScale/iwMMXt insns */
6096 if (arm_dc_feature(s
, ARM_FEATURE_XSCALE
) && (cpnum
< 2)) {
6097 if (extract32(s
->c15_cpar
, cpnum
, 1) == 0) {
6100 if (arm_dc_feature(s
, ARM_FEATURE_IWMMXT
)) {
6101 return disas_iwmmxt_insn(s
, insn
);
6102 } else if (arm_dc_feature(s
, ARM_FEATURE_XSCALE
)) {
6103 return disas_dsp_insn(s
, insn
);
6108 /* Otherwise treat as a generic register access */
6109 is64
= (insn
& (1 << 25)) == 0;
6110 if (!is64
&& ((insn
& (1 << 4)) == 0)) {
6118 opc1
= (insn
>> 4) & 0xf;
6120 rt2
= (insn
>> 16) & 0xf;
6122 crn
= (insn
>> 16) & 0xf;
6123 opc1
= (insn
>> 21) & 7;
6124 opc2
= (insn
>> 5) & 7;
6127 isread
= (insn
>> 20) & 1;
6128 rt
= (insn
>> 12) & 0xf;
6130 ri
= get_arm_cp_reginfo(s
->cp_regs
,
6131 ENCODE_CP_REG(cpnum
, is64
, s
->ns
, crn
, crm
, opc1
, opc2
));
6135 /* Check access permissions */
6136 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
6140 if (s
->hstr_active
|| ri
->accessfn
||
6141 (arm_dc_feature(s
, ARM_FEATURE_XSCALE
) && cpnum
< 14)) {
6142 /* Emit code to perform further access permissions checks at
6143 * runtime; this may result in an exception.
6144 * Note that on XScale all cp0..c13 registers do an access check
6145 * call in order to handle c15_cpar.
6148 TCGv_i32 tcg_syn
, tcg_isread
;
6151 /* Note that since we are an implementation which takes an
6152 * exception on a trapped conditional instruction only if the
6153 * instruction passes its condition code check, we can take
6154 * advantage of the clause in the ARM ARM that allows us to set
6155 * the COND field in the instruction to 0xE in all cases.
6156 * We could fish the actual condition out of the insn (ARM)
6157 * or the condexec bits (Thumb) but it isn't necessary.
6162 syndrome
= syn_cp14_rrt_trap(1, 0xe, opc1
, crm
, rt
, rt2
,
6165 syndrome
= syn_cp14_rt_trap(1, 0xe, opc1
, opc2
, crn
, crm
,
6171 syndrome
= syn_cp15_rrt_trap(1, 0xe, opc1
, crm
, rt
, rt2
,
6174 syndrome
= syn_cp15_rt_trap(1, 0xe, opc1
, opc2
, crn
, crm
,
6179 /* ARMv8 defines that only coprocessors 14 and 15 exist,
6180 * so this can only happen if this is an ARMv7 or earlier CPU,
6181 * in which case the syndrome information won't actually be
6184 assert(!arm_dc_feature(s
, ARM_FEATURE_V8
));
6185 syndrome
= syn_uncategorized();
6189 gen_set_condexec(s
);
6190 gen_set_pc_im(s
, s
->pc_curr
);
6191 tmpptr
= tcg_const_ptr(ri
);
6192 tcg_syn
= tcg_const_i32(syndrome
);
6193 tcg_isread
= tcg_const_i32(isread
);
6194 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
,
6196 tcg_temp_free_ptr(tmpptr
);
6197 tcg_temp_free_i32(tcg_syn
);
6198 tcg_temp_free_i32(tcg_isread
);
6199 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
6201 * The readfn or writefn might raise an exception;
6202 * synchronize the CPU state in case it does.
6204 gen_set_condexec(s
);
6205 gen_set_pc_im(s
, s
->pc_curr
);
6208 /* Handle special cases first */
6209 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
6216 gen_set_pc_im(s
, s
->base
.pc_next
);
6217 s
->base
.is_jmp
= DISAS_WFI
;
6223 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
6232 if (ri
->type
& ARM_CP_CONST
) {
6233 tmp64
= tcg_const_i64(ri
->resetvalue
);
6234 } else if (ri
->readfn
) {
6236 tmp64
= tcg_temp_new_i64();
6237 tmpptr
= tcg_const_ptr(ri
);
6238 gen_helper_get_cp_reg64(tmp64
, cpu_env
, tmpptr
);
6239 tcg_temp_free_ptr(tmpptr
);
6241 tmp64
= tcg_temp_new_i64();
6242 tcg_gen_ld_i64(tmp64
, cpu_env
, ri
->fieldoffset
);
6244 tmp
= tcg_temp_new_i32();
6245 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
6246 store_reg(s
, rt
, tmp
);
6247 tmp
= tcg_temp_new_i32();
6248 tcg_gen_extrh_i64_i32(tmp
, tmp64
);
6249 tcg_temp_free_i64(tmp64
);
6250 store_reg(s
, rt2
, tmp
);
6253 if (ri
->type
& ARM_CP_CONST
) {
6254 tmp
= tcg_const_i32(ri
->resetvalue
);
6255 } else if (ri
->readfn
) {
6257 tmp
= tcg_temp_new_i32();
6258 tmpptr
= tcg_const_ptr(ri
);
6259 gen_helper_get_cp_reg(tmp
, cpu_env
, tmpptr
);
6260 tcg_temp_free_ptr(tmpptr
);
6262 tmp
= load_cpu_offset(ri
->fieldoffset
);
6265 /* Destination register of r15 for 32 bit loads sets
6266 * the condition codes from the high 4 bits of the value
6269 tcg_temp_free_i32(tmp
);
6271 store_reg(s
, rt
, tmp
);
6276 if (ri
->type
& ARM_CP_CONST
) {
6277 /* If not forbidden by access permissions, treat as WI */
6282 TCGv_i32 tmplo
, tmphi
;
6283 TCGv_i64 tmp64
= tcg_temp_new_i64();
6284 tmplo
= load_reg(s
, rt
);
6285 tmphi
= load_reg(s
, rt2
);
6286 tcg_gen_concat_i32_i64(tmp64
, tmplo
, tmphi
);
6287 tcg_temp_free_i32(tmplo
);
6288 tcg_temp_free_i32(tmphi
);
6290 TCGv_ptr tmpptr
= tcg_const_ptr(ri
);
6291 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tmp64
);
6292 tcg_temp_free_ptr(tmpptr
);
6294 tcg_gen_st_i64(tmp64
, cpu_env
, ri
->fieldoffset
);
6296 tcg_temp_free_i64(tmp64
);
6301 tmp
= load_reg(s
, rt
);
6302 tmpptr
= tcg_const_ptr(ri
);
6303 gen_helper_set_cp_reg(cpu_env
, tmpptr
, tmp
);
6304 tcg_temp_free_ptr(tmpptr
);
6305 tcg_temp_free_i32(tmp
);
6307 TCGv_i32 tmp
= load_reg(s
, rt
);
6308 store_cpu_offset(tmp
, ri
->fieldoffset
);
6313 /* I/O operations must end the TB here (whether read or write) */
6314 need_exit_tb
= ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) &&
6315 (ri
->type
& ARM_CP_IO
));
6317 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
6319 * A write to any coprocessor register that ends a TB
6320 * must rebuild the hflags for the next TB.
6322 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
6323 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
6324 gen_helper_rebuild_hflags_m32(cpu_env
, tcg_el
);
6326 if (ri
->type
& ARM_CP_NEWEL
) {
6327 gen_helper_rebuild_hflags_a32_newel(cpu_env
);
6329 gen_helper_rebuild_hflags_a32(cpu_env
, tcg_el
);
6332 tcg_temp_free_i32(tcg_el
);
6334 * We default to ending the TB on a coprocessor register write,
6335 * but allow this to be suppressed by the register definition
6336 * (usually only necessary to work around guest bugs).
6338 need_exit_tb
= true;
6347 /* Unknown register; this might be a guest error or a QEMU
6348 * unimplemented feature.
6351 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch32 "
6352 "64 bit system register cp:%d opc1: %d crm:%d "
6354 isread
? "read" : "write", cpnum
, opc1
, crm
,
6355 s
->ns
? "non-secure" : "secure");
6357 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch32 "
6358 "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d "
6360 isread
? "read" : "write", cpnum
, opc1
, crn
, crm
, opc2
,
6361 s
->ns
? "non-secure" : "secure");
6368 /* Store a 64-bit value to a register pair. Clobbers val. */
6369 static void gen_storeq_reg(DisasContext
*s
, int rlow
, int rhigh
, TCGv_i64 val
)
6372 tmp
= tcg_temp_new_i32();
6373 tcg_gen_extrl_i64_i32(tmp
, val
);
6374 store_reg(s
, rlow
, tmp
);
6375 tmp
= tcg_temp_new_i32();
6376 tcg_gen_extrh_i64_i32(tmp
, val
);
6377 store_reg(s
, rhigh
, tmp
);
6380 /* load and add a 64-bit value from a register pair. */
6381 static void gen_addq(DisasContext
*s
, TCGv_i64 val
, int rlow
, int rhigh
)
6387 /* Load 64-bit value rd:rn. */
6388 tmpl
= load_reg(s
, rlow
);
6389 tmph
= load_reg(s
, rhigh
);
6390 tmp
= tcg_temp_new_i64();
6391 tcg_gen_concat_i32_i64(tmp
, tmpl
, tmph
);
6392 tcg_temp_free_i32(tmpl
);
6393 tcg_temp_free_i32(tmph
);
6394 tcg_gen_add_i64(val
, val
, tmp
);
6395 tcg_temp_free_i64(tmp
);
6398 /* Set N and Z flags from hi|lo. */
6399 static void gen_logicq_cc(TCGv_i32 lo
, TCGv_i32 hi
)
6401 tcg_gen_mov_i32(cpu_NF
, hi
);
6402 tcg_gen_or_i32(cpu_ZF
, lo
, hi
);
6405 /* Load/Store exclusive instructions are implemented by remembering
6406 the value/address loaded, and seeing if these are the same
6407 when the store is performed. This should be sufficient to implement
6408 the architecturally mandated semantics, and avoids having to monitor
6409 regular stores. The compare vs the remembered value is done during
6410 the cmpxchg operation, but we must compare the addresses manually. */
6411 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
6412 TCGv_i32 addr
, int size
)
6414 TCGv_i32 tmp
= tcg_temp_new_i32();
6415 MemOp opc
= size
| MO_ALIGN
| s
->be_data
;
6420 TCGv_i32 tmp2
= tcg_temp_new_i32();
6421 TCGv_i64 t64
= tcg_temp_new_i64();
6423 /* For AArch32, architecturally the 32-bit word at the lowest
6424 * address is always Rt and the one at addr+4 is Rt2, even if
6425 * the CPU is big-endian. That means we don't want to do a
6426 * gen_aa32_ld_i64(), which invokes gen_aa32_frob64() as if
6427 * for an architecturally 64-bit access, but instead do a
6428 * 64-bit access using MO_BE if appropriate and then split
6430 * This only makes a difference for BE32 user-mode, where
6431 * frob64() must not flip the two halves of the 64-bit data
6432 * but this code must treat BE32 user-mode like BE32 system.
6434 TCGv taddr
= gen_aa32_addr(s
, addr
, opc
);
6436 tcg_gen_qemu_ld_i64(t64
, taddr
, get_mem_index(s
), opc
);
6437 tcg_temp_free(taddr
);
6438 tcg_gen_mov_i64(cpu_exclusive_val
, t64
);
6439 if (s
->be_data
== MO_BE
) {
6440 tcg_gen_extr_i64_i32(tmp2
, tmp
, t64
);
6442 tcg_gen_extr_i64_i32(tmp
, tmp2
, t64
);
6444 tcg_temp_free_i64(t64
);
6446 store_reg(s
, rt2
, tmp2
);
6448 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
), opc
);
6449 tcg_gen_extu_i32_i64(cpu_exclusive_val
, tmp
);
6452 store_reg(s
, rt
, tmp
);
6453 tcg_gen_extu_i32_i64(cpu_exclusive_addr
, addr
);
6456 static void gen_clrex(DisasContext
*s
)
6458 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
6461 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
6462 TCGv_i32 addr
, int size
)
6464 TCGv_i32 t0
, t1
, t2
;
6467 TCGLabel
*done_label
;
6468 TCGLabel
*fail_label
;
6469 MemOp opc
= size
| MO_ALIGN
| s
->be_data
;
6471 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6477 fail_label
= gen_new_label();
6478 done_label
= gen_new_label();
6479 extaddr
= tcg_temp_new_i64();
6480 tcg_gen_extu_i32_i64(extaddr
, addr
);
6481 tcg_gen_brcond_i64(TCG_COND_NE
, extaddr
, cpu_exclusive_addr
, fail_label
);
6482 tcg_temp_free_i64(extaddr
);
6484 taddr
= gen_aa32_addr(s
, addr
, opc
);
6485 t0
= tcg_temp_new_i32();
6486 t1
= load_reg(s
, rt
);
6488 TCGv_i64 o64
= tcg_temp_new_i64();
6489 TCGv_i64 n64
= tcg_temp_new_i64();
6491 t2
= load_reg(s
, rt2
);
6492 /* For AArch32, architecturally the 32-bit word at the lowest
6493 * address is always Rt and the one at addr+4 is Rt2, even if
6494 * the CPU is big-endian. Since we're going to treat this as a
6495 * single 64-bit BE store, we need to put the two halves in the
6496 * opposite order for BE to LE, so that they end up in the right
6498 * We don't want gen_aa32_frob64() because that does the wrong
6499 * thing for BE32 usermode.
6501 if (s
->be_data
== MO_BE
) {
6502 tcg_gen_concat_i32_i64(n64
, t2
, t1
);
6504 tcg_gen_concat_i32_i64(n64
, t1
, t2
);
6506 tcg_temp_free_i32(t2
);
6508 tcg_gen_atomic_cmpxchg_i64(o64
, taddr
, cpu_exclusive_val
, n64
,
6509 get_mem_index(s
), opc
);
6510 tcg_temp_free_i64(n64
);
6512 tcg_gen_setcond_i64(TCG_COND_NE
, o64
, o64
, cpu_exclusive_val
);
6513 tcg_gen_extrl_i64_i32(t0
, o64
);
6515 tcg_temp_free_i64(o64
);
6517 t2
= tcg_temp_new_i32();
6518 tcg_gen_extrl_i64_i32(t2
, cpu_exclusive_val
);
6519 tcg_gen_atomic_cmpxchg_i32(t0
, taddr
, t2
, t1
, get_mem_index(s
), opc
);
6520 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t2
);
6521 tcg_temp_free_i32(t2
);
6523 tcg_temp_free_i32(t1
);
6524 tcg_temp_free(taddr
);
6525 tcg_gen_mov_i32(cpu_R
[rd
], t0
);
6526 tcg_temp_free_i32(t0
);
6527 tcg_gen_br(done_label
);
6529 gen_set_label(fail_label
);
6530 tcg_gen_movi_i32(cpu_R
[rd
], 1);
6531 gen_set_label(done_label
);
6532 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
6538 * @mode: mode field from insn (which stack to store to)
6539 * @amode: addressing mode (DA/IA/DB/IB), encoded as per P,U bits in ARM insn
6540 * @writeback: true if writeback bit set
6542 * Generate code for the SRS (Store Return State) insn.
6544 static void gen_srs(DisasContext
*s
,
6545 uint32_t mode
, uint32_t amode
, bool writeback
)
6552 * - trapped to EL3 if EL3 is AArch64 and we are at Secure EL1
6553 * and specified mode is monitor mode
6554 * - UNDEFINED in Hyp mode
6555 * - UNPREDICTABLE in User or System mode
6556 * - UNPREDICTABLE if the specified mode is:
6557 * -- not implemented
6558 * -- not a valid mode number
6559 * -- a mode that's at a higher exception level
6560 * -- Monitor, if we are Non-secure
6561 * For the UNPREDICTABLE cases we choose to UNDEF.
6563 if (s
->current_el
== 1 && !s
->ns
&& mode
== ARM_CPU_MODE_MON
) {
6564 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(), 3);
6568 if (s
->current_el
== 0 || s
->current_el
== 2) {
6573 case ARM_CPU_MODE_USR
:
6574 case ARM_CPU_MODE_FIQ
:
6575 case ARM_CPU_MODE_IRQ
:
6576 case ARM_CPU_MODE_SVC
:
6577 case ARM_CPU_MODE_ABT
:
6578 case ARM_CPU_MODE_UND
:
6579 case ARM_CPU_MODE_SYS
:
6581 case ARM_CPU_MODE_HYP
:
6582 if (s
->current_el
== 1 || !arm_dc_feature(s
, ARM_FEATURE_EL2
)) {
6586 case ARM_CPU_MODE_MON
:
6587 /* No need to check specifically for "are we non-secure" because
6588 * we've already made EL0 UNDEF and handled the trap for S-EL1;
6589 * so if this isn't EL3 then we must be non-secure.
6591 if (s
->current_el
!= 3) {
6600 unallocated_encoding(s
);
6604 addr
= tcg_temp_new_i32();
6605 tmp
= tcg_const_i32(mode
);
6606 /* get_r13_banked() will raise an exception if called from System mode */
6607 gen_set_condexec(s
);
6608 gen_set_pc_im(s
, s
->pc_curr
);
6609 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
6610 tcg_temp_free_i32(tmp
);
6627 tcg_gen_addi_i32(addr
, addr
, offset
);
6628 tmp
= load_reg(s
, 14);
6629 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
6630 tcg_temp_free_i32(tmp
);
6631 tmp
= load_cpu_field(spsr
);
6632 tcg_gen_addi_i32(addr
, addr
, 4);
6633 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
6634 tcg_temp_free_i32(tmp
);
6652 tcg_gen_addi_i32(addr
, addr
, offset
);
6653 tmp
= tcg_const_i32(mode
);
6654 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
6655 tcg_temp_free_i32(tmp
);
6657 tcg_temp_free_i32(addr
);
6658 s
->base
.is_jmp
= DISAS_UPDATE
;
6661 /* Generate a label used for skipping this instruction */
6662 static void arm_gen_condlabel(DisasContext
*s
)
6665 s
->condlabel
= gen_new_label();
6670 /* Skip this instruction if the ARM condition is false */
6671 static void arm_skip_unless(DisasContext
*s
, uint32_t cond
)
6673 arm_gen_condlabel(s
);
6674 arm_gen_test_cc(cond
^ 1, s
->condlabel
);
6679 * Constant expanders for the decoders.
6682 static int negate(DisasContext
*s
, int x
)
6687 static int plus_2(DisasContext
*s
, int x
)
6692 static int times_2(DisasContext
*s
, int x
)
6697 static int times_4(DisasContext
*s
, int x
)
6702 /* Return only the rotation part of T32ExpandImm. */
6703 static int t32_expandimm_rot(DisasContext
*s
, int x
)
6705 return x
& 0xc00 ? extract32(x
, 7, 5) : 0;
6708 /* Return the unrotated immediate from T32ExpandImm. */
6709 static int t32_expandimm_imm(DisasContext
*s
, int x
)
6711 int imm
= extract32(x
, 0, 8);
6713 switch (extract32(x
, 8, 4)) {
6715 /* Nothing to do. */
6717 case 1: /* 00XY00XY */
6720 case 2: /* XY00XY00 */
6723 case 3: /* XYXYXYXY */
6727 /* Rotated constant. */
6734 static int t32_branch24(DisasContext
*s
, int x
)
6736 /* Convert J1:J2 at x[22:21] to I2:I1, which involves I=J^~S. */
6737 x
^= !(x
< 0) * (3 << 21);
6738 /* Append the final zero. */
6742 static int t16_setflags(DisasContext
*s
)
6744 return s
->condexec_mask
== 0;
6747 static int t16_push_list(DisasContext
*s
, int x
)
6749 return (x
& 0xff) | (x
& 0x100) << (14 - 8);
6752 static int t16_pop_list(DisasContext
*s
, int x
)
6754 return (x
& 0xff) | (x
& 0x100) << (15 - 8);
6758 * Include the generated decoders.
6761 #include "decode-a32.inc.c"
6762 #include "decode-a32-uncond.inc.c"
6763 #include "decode-t32.inc.c"
6764 #include "decode-t16.inc.c"
6766 /* Helpers to swap operands for reverse-subtract. */
6767 static void gen_rsb(TCGv_i32 dst
, TCGv_i32 a
, TCGv_i32 b
)
6769 tcg_gen_sub_i32(dst
, b
, a
);
6772 static void gen_rsb_CC(TCGv_i32 dst
, TCGv_i32 a
, TCGv_i32 b
)
6774 gen_sub_CC(dst
, b
, a
);
6777 static void gen_rsc(TCGv_i32 dest
, TCGv_i32 a
, TCGv_i32 b
)
6779 gen_sub_carry(dest
, b
, a
);
6782 static void gen_rsc_CC(TCGv_i32 dest
, TCGv_i32 a
, TCGv_i32 b
)
6784 gen_sbc_CC(dest
, b
, a
);
6788 * Helpers for the data processing routines.
6790 * After the computation store the results back.
6791 * This may be suppressed altogether (STREG_NONE), require a runtime
6792 * check against the stack limits (STREG_SP_CHECK), or generate an
6793 * exception return. Oh, or store into a register.
6795 * Always return true, indicating success for a trans_* function.
6804 static bool store_reg_kind(DisasContext
*s
, int rd
,
6805 TCGv_i32 val
, StoreRegKind kind
)
6809 tcg_temp_free_i32(val
);
6812 /* See ALUWritePC: Interworking only from a32 mode. */
6814 store_reg(s
, rd
, val
);
6816 store_reg_bx(s
, rd
, val
);
6819 case STREG_SP_CHECK
:
6820 store_sp_checked(s
, val
);
6823 gen_exception_return(s
, val
);
6826 g_assert_not_reached();
6830 * Data Processing (register)
6832 * Operate, with set flags, one register source,
6833 * one immediate shifted register source, and a destination.
6835 static bool op_s_rrr_shi(DisasContext
*s
, arg_s_rrr_shi
*a
,
6836 void (*gen
)(TCGv_i32
, TCGv_i32
, TCGv_i32
),
6837 int logic_cc
, StoreRegKind kind
)
6839 TCGv_i32 tmp1
, tmp2
;
6841 tmp2
= load_reg(s
, a
->rm
);
6842 gen_arm_shift_im(tmp2
, a
->shty
, a
->shim
, logic_cc
);
6843 tmp1
= load_reg(s
, a
->rn
);
6845 gen(tmp1
, tmp1
, tmp2
);
6846 tcg_temp_free_i32(tmp2
);
6851 return store_reg_kind(s
, a
->rd
, tmp1
, kind
);
6854 static bool op_s_rxr_shi(DisasContext
*s
, arg_s_rrr_shi
*a
,
6855 void (*gen
)(TCGv_i32
, TCGv_i32
),
6856 int logic_cc
, StoreRegKind kind
)
6860 tmp
= load_reg(s
, a
->rm
);
6861 gen_arm_shift_im(tmp
, a
->shty
, a
->shim
, logic_cc
);
6867 return store_reg_kind(s
, a
->rd
, tmp
, kind
);
6871 * Data-processing (register-shifted register)
6873 * Operate, with set flags, one register source,
6874 * one register shifted register source, and a destination.
6876 static bool op_s_rrr_shr(DisasContext
*s
, arg_s_rrr_shr
*a
,
6877 void (*gen
)(TCGv_i32
, TCGv_i32
, TCGv_i32
),
6878 int logic_cc
, StoreRegKind kind
)
6880 TCGv_i32 tmp1
, tmp2
;
6882 tmp1
= load_reg(s
, a
->rs
);
6883 tmp2
= load_reg(s
, a
->rm
);
6884 gen_arm_shift_reg(tmp2
, a
->shty
, tmp1
, logic_cc
);
6885 tmp1
= load_reg(s
, a
->rn
);
6887 gen(tmp1
, tmp1
, tmp2
);
6888 tcg_temp_free_i32(tmp2
);
6893 return store_reg_kind(s
, a
->rd
, tmp1
, kind
);
6896 static bool op_s_rxr_shr(DisasContext
*s
, arg_s_rrr_shr
*a
,
6897 void (*gen
)(TCGv_i32
, TCGv_i32
),
6898 int logic_cc
, StoreRegKind kind
)
6900 TCGv_i32 tmp1
, tmp2
;
6902 tmp1
= load_reg(s
, a
->rs
);
6903 tmp2
= load_reg(s
, a
->rm
);
6904 gen_arm_shift_reg(tmp2
, a
->shty
, tmp1
, logic_cc
);
6910 return store_reg_kind(s
, a
->rd
, tmp2
, kind
);
6914 * Data-processing (immediate)
6916 * Operate, with set flags, one register source,
6917 * one rotated immediate, and a destination.
6919 * Note that logic_cc && a->rot setting CF based on the msb of the
6920 * immediate is the reason why we must pass in the unrotated form
6923 static bool op_s_rri_rot(DisasContext
*s
, arg_s_rri_rot
*a
,
6924 void (*gen
)(TCGv_i32
, TCGv_i32
, TCGv_i32
),
6925 int logic_cc
, StoreRegKind kind
)
6927 TCGv_i32 tmp1
, tmp2
;
6930 imm
= ror32(a
->imm
, a
->rot
);
6931 if (logic_cc
&& a
->rot
) {
6932 tcg_gen_movi_i32(cpu_CF
, imm
>> 31);
6934 tmp2
= tcg_const_i32(imm
);
6935 tmp1
= load_reg(s
, a
->rn
);
6937 gen(tmp1
, tmp1
, tmp2
);
6938 tcg_temp_free_i32(tmp2
);
6943 return store_reg_kind(s
, a
->rd
, tmp1
, kind
);
6946 static bool op_s_rxi_rot(DisasContext
*s
, arg_s_rri_rot
*a
,
6947 void (*gen
)(TCGv_i32
, TCGv_i32
),
6948 int logic_cc
, StoreRegKind kind
)
6953 imm
= ror32(a
->imm
, a
->rot
);
6954 if (logic_cc
&& a
->rot
) {
6955 tcg_gen_movi_i32(cpu_CF
, imm
>> 31);
6957 tmp
= tcg_const_i32(imm
);
6963 return store_reg_kind(s
, a
->rd
, tmp
, kind
);
6966 #define DO_ANY3(NAME, OP, L, K) \
6967 static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \
6968 { StoreRegKind k = (K); return op_s_rrr_shi(s, a, OP, L, k); } \
6969 static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \
6970 { StoreRegKind k = (K); return op_s_rrr_shr(s, a, OP, L, k); } \
6971 static bool trans_##NAME##_rri(DisasContext *s, arg_s_rri_rot *a) \
6972 { StoreRegKind k = (K); return op_s_rri_rot(s, a, OP, L, k); }
6974 #define DO_ANY2(NAME, OP, L, K) \
6975 static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \
6976 { StoreRegKind k = (K); return op_s_rxr_shi(s, a, OP, L, k); } \
6977 static bool trans_##NAME##_rxrr(DisasContext *s, arg_s_rrr_shr *a) \
6978 { StoreRegKind k = (K); return op_s_rxr_shr(s, a, OP, L, k); } \
6979 static bool trans_##NAME##_rxi(DisasContext *s, arg_s_rri_rot *a) \
6980 { StoreRegKind k = (K); return op_s_rxi_rot(s, a, OP, L, k); }
6982 #define DO_CMP2(NAME, OP, L) \
6983 static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \
6984 { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } \
6985 static bool trans_##NAME##_xrrr(DisasContext *s, arg_s_rrr_shr *a) \
6986 { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } \
6987 static bool trans_##NAME##_xri(DisasContext *s, arg_s_rri_rot *a) \
6988 { return op_s_rri_rot(s, a, OP, L, STREG_NONE); }
6990 DO_ANY3(AND
, tcg_gen_and_i32
, a
->s
, STREG_NORMAL
)
6991 DO_ANY3(EOR
, tcg_gen_xor_i32
, a
->s
, STREG_NORMAL
)
6992 DO_ANY3(ORR
, tcg_gen_or_i32
, a
->s
, STREG_NORMAL
)
6993 DO_ANY3(BIC
, tcg_gen_andc_i32
, a
->s
, STREG_NORMAL
)
6995 DO_ANY3(RSB
, a
->s
? gen_rsb_CC
: gen_rsb
, false, STREG_NORMAL
)
6996 DO_ANY3(ADC
, a
->s
? gen_adc_CC
: gen_add_carry
, false, STREG_NORMAL
)
6997 DO_ANY3(SBC
, a
->s
? gen_sbc_CC
: gen_sub_carry
, false, STREG_NORMAL
)
6998 DO_ANY3(RSC
, a
->s
? gen_rsc_CC
: gen_rsc
, false, STREG_NORMAL
)
7000 DO_CMP2(TST
, tcg_gen_and_i32
, true)
7001 DO_CMP2(TEQ
, tcg_gen_xor_i32
, true)
7002 DO_CMP2(CMN
, gen_add_CC
, false)
7003 DO_CMP2(CMP
, gen_sub_CC
, false)
7005 DO_ANY3(ADD
, a
->s
? gen_add_CC
: tcg_gen_add_i32
, false,
7006 a
->rd
== 13 && a
->rn
== 13 ? STREG_SP_CHECK
: STREG_NORMAL
)
7009 * Note for the computation of StoreRegKind we return out of the
7010 * middle of the functions that are expanded by DO_ANY3, and that
7011 * we modify a->s via that parameter before it is used by OP.
7013 DO_ANY3(SUB
, a
->s
? gen_sub_CC
: tcg_gen_sub_i32
, false,
7015 StoreRegKind ret
= STREG_NORMAL
;
7016 if (a
->rd
== 15 && a
->s
) {
7018 * See ALUExceptionReturn:
7019 * In User mode, UNPREDICTABLE; we choose UNDEF.
7020 * In Hyp mode, UNDEFINED.
7022 if (IS_USER(s
) || s
->current_el
== 2) {
7023 unallocated_encoding(s
);
7026 /* There is no writeback of nzcv to PSTATE. */
7028 ret
= STREG_EXC_RET
;
7029 } else if (a
->rd
== 13 && a
->rn
== 13) {
7030 ret
= STREG_SP_CHECK
;
7035 DO_ANY2(MOV
, tcg_gen_mov_i32
, a
->s
,
7037 StoreRegKind ret
= STREG_NORMAL
;
7038 if (a
->rd
== 15 && a
->s
) {
7040 * See ALUExceptionReturn:
7041 * In User mode, UNPREDICTABLE; we choose UNDEF.
7042 * In Hyp mode, UNDEFINED.
7044 if (IS_USER(s
) || s
->current_el
== 2) {
7045 unallocated_encoding(s
);
7048 /* There is no writeback of nzcv to PSTATE. */
7050 ret
= STREG_EXC_RET
;
7051 } else if (a
->rd
== 13) {
7052 ret
= STREG_SP_CHECK
;
7057 DO_ANY2(MVN
, tcg_gen_not_i32
, a
->s
, STREG_NORMAL
)
7060 * ORN is only available with T32, so there is no register-shifted-register
7061 * form of the insn. Using the DO_ANY3 macro would create an unused function.
7063 static bool trans_ORN_rrri(DisasContext
*s
, arg_s_rrr_shi
*a
)
7065 return op_s_rrr_shi(s
, a
, tcg_gen_orc_i32
, a
->s
, STREG_NORMAL
);
7068 static bool trans_ORN_rri(DisasContext
*s
, arg_s_rri_rot
*a
)
7070 return op_s_rri_rot(s
, a
, tcg_gen_orc_i32
, a
->s
, STREG_NORMAL
);
7077 static bool trans_ADR(DisasContext
*s
, arg_ri
*a
)
7079 store_reg_bx(s
, a
->rd
, add_reg_for_lit(s
, 15, a
->imm
));
7083 static bool trans_MOVW(DisasContext
*s
, arg_MOVW
*a
)
7087 if (!ENABLE_ARCH_6T2
) {
7091 tmp
= tcg_const_i32(a
->imm
);
7092 store_reg(s
, a
->rd
, tmp
);
7096 static bool trans_MOVT(DisasContext
*s
, arg_MOVW
*a
)
7100 if (!ENABLE_ARCH_6T2
) {
7104 tmp
= load_reg(s
, a
->rd
);
7105 tcg_gen_ext16u_i32(tmp
, tmp
);
7106 tcg_gen_ori_i32(tmp
, tmp
, a
->imm
<< 16);
7107 store_reg(s
, a
->rd
, tmp
);
7112 * Multiply and multiply accumulate
7115 static bool op_mla(DisasContext
*s
, arg_s_rrrr
*a
, bool add
)
7119 t1
= load_reg(s
, a
->rn
);
7120 t2
= load_reg(s
, a
->rm
);
7121 tcg_gen_mul_i32(t1
, t1
, t2
);
7122 tcg_temp_free_i32(t2
);
7124 t2
= load_reg(s
, a
->ra
);
7125 tcg_gen_add_i32(t1
, t1
, t2
);
7126 tcg_temp_free_i32(t2
);
7131 store_reg(s
, a
->rd
, t1
);
7135 static bool trans_MUL(DisasContext
*s
, arg_MUL
*a
)
7137 return op_mla(s
, a
, false);
7140 static bool trans_MLA(DisasContext
*s
, arg_MLA
*a
)
7142 return op_mla(s
, a
, true);
7145 static bool trans_MLS(DisasContext
*s
, arg_MLS
*a
)
7149 if (!ENABLE_ARCH_6T2
) {
7152 t1
= load_reg(s
, a
->rn
);
7153 t2
= load_reg(s
, a
->rm
);
7154 tcg_gen_mul_i32(t1
, t1
, t2
);
7155 tcg_temp_free_i32(t2
);
7156 t2
= load_reg(s
, a
->ra
);
7157 tcg_gen_sub_i32(t1
, t2
, t1
);
7158 tcg_temp_free_i32(t2
);
7159 store_reg(s
, a
->rd
, t1
);
7163 static bool op_mlal(DisasContext
*s
, arg_s_rrrr
*a
, bool uns
, bool add
)
7165 TCGv_i32 t0
, t1
, t2
, t3
;
7167 t0
= load_reg(s
, a
->rm
);
7168 t1
= load_reg(s
, a
->rn
);
7170 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
7172 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
7175 t2
= load_reg(s
, a
->ra
);
7176 t3
= load_reg(s
, a
->rd
);
7177 tcg_gen_add2_i32(t0
, t1
, t0
, t1
, t2
, t3
);
7178 tcg_temp_free_i32(t2
);
7179 tcg_temp_free_i32(t3
);
7182 gen_logicq_cc(t0
, t1
);
7184 store_reg(s
, a
->ra
, t0
);
7185 store_reg(s
, a
->rd
, t1
);
7189 static bool trans_UMULL(DisasContext
*s
, arg_UMULL
*a
)
7191 return op_mlal(s
, a
, true, false);
7194 static bool trans_SMULL(DisasContext
*s
, arg_SMULL
*a
)
7196 return op_mlal(s
, a
, false, false);
7199 static bool trans_UMLAL(DisasContext
*s
, arg_UMLAL
*a
)
7201 return op_mlal(s
, a
, true, true);
7204 static bool trans_SMLAL(DisasContext
*s
, arg_SMLAL
*a
)
7206 return op_mlal(s
, a
, false, true);
7209 static bool trans_UMAAL(DisasContext
*s
, arg_UMAAL
*a
)
7211 TCGv_i32 t0
, t1
, t2
, zero
;
7214 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
7219 t0
= load_reg(s
, a
->rm
);
7220 t1
= load_reg(s
, a
->rn
);
7221 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
7222 zero
= tcg_const_i32(0);
7223 t2
= load_reg(s
, a
->ra
);
7224 tcg_gen_add2_i32(t0
, t1
, t0
, t1
, t2
, zero
);
7225 tcg_temp_free_i32(t2
);
7226 t2
= load_reg(s
, a
->rd
);
7227 tcg_gen_add2_i32(t0
, t1
, t0
, t1
, t2
, zero
);
7228 tcg_temp_free_i32(t2
);
7229 tcg_temp_free_i32(zero
);
7230 store_reg(s
, a
->ra
, t0
);
7231 store_reg(s
, a
->rd
, t1
);
7236 * Saturating addition and subtraction
7239 static bool op_qaddsub(DisasContext
*s
, arg_rrr
*a
, bool add
, bool doub
)
7244 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
7245 : !ENABLE_ARCH_5TE
) {
7249 t0
= load_reg(s
, a
->rm
);
7250 t1
= load_reg(s
, a
->rn
);
7252 gen_helper_add_saturate(t1
, cpu_env
, t1
, t1
);
7255 gen_helper_add_saturate(t0
, cpu_env
, t0
, t1
);
7257 gen_helper_sub_saturate(t0
, cpu_env
, t0
, t1
);
7259 tcg_temp_free_i32(t1
);
7260 store_reg(s
, a
->rd
, t0
);
7264 #define DO_QADDSUB(NAME, ADD, DOUB) \
7265 static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
7267 return op_qaddsub(s, a, ADD, DOUB); \
7270 DO_QADDSUB(QADD
, true, false)
7271 DO_QADDSUB(QSUB
, false, false)
7272 DO_QADDSUB(QDADD
, true, true)
7273 DO_QADDSUB(QDSUB
, false, true)
7278 * Halfword multiply and multiply accumulate
7281 static bool op_smlaxxx(DisasContext
*s
, arg_rrrr
*a
,
7282 int add_long
, bool nt
, bool mt
)
7284 TCGv_i32 t0
, t1
, tl
, th
;
7287 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
7288 : !ENABLE_ARCH_5TE
) {
7292 t0
= load_reg(s
, a
->rn
);
7293 t1
= load_reg(s
, a
->rm
);
7294 gen_mulxy(t0
, t1
, nt
, mt
);
7295 tcg_temp_free_i32(t1
);
7299 store_reg(s
, a
->rd
, t0
);
7302 t1
= load_reg(s
, a
->ra
);
7303 gen_helper_add_setq(t0
, cpu_env
, t0
, t1
);
7304 tcg_temp_free_i32(t1
);
7305 store_reg(s
, a
->rd
, t0
);
7308 tl
= load_reg(s
, a
->ra
);
7309 th
= load_reg(s
, a
->rd
);
7310 /* Sign-extend the 32-bit product to 64 bits. */
7311 t1
= tcg_temp_new_i32();
7312 tcg_gen_sari_i32(t1
, t0
, 31);
7313 tcg_gen_add2_i32(tl
, th
, tl
, th
, t0
, t1
);
7314 tcg_temp_free_i32(t0
);
7315 tcg_temp_free_i32(t1
);
7316 store_reg(s
, a
->ra
, tl
);
7317 store_reg(s
, a
->rd
, th
);
7320 g_assert_not_reached();
7325 #define DO_SMLAX(NAME, add, nt, mt) \
7326 static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \
7328 return op_smlaxxx(s, a, add, nt, mt); \
7331 DO_SMLAX(SMULBB
, 0, 0, 0)
7332 DO_SMLAX(SMULBT
, 0, 0, 1)
7333 DO_SMLAX(SMULTB
, 0, 1, 0)
7334 DO_SMLAX(SMULTT
, 0, 1, 1)
7336 DO_SMLAX(SMLABB
, 1, 0, 0)
7337 DO_SMLAX(SMLABT
, 1, 0, 1)
7338 DO_SMLAX(SMLATB
, 1, 1, 0)
7339 DO_SMLAX(SMLATT
, 1, 1, 1)
7341 DO_SMLAX(SMLALBB
, 2, 0, 0)
7342 DO_SMLAX(SMLALBT
, 2, 0, 1)
7343 DO_SMLAX(SMLALTB
, 2, 1, 0)
7344 DO_SMLAX(SMLALTT
, 2, 1, 1)
7348 static bool op_smlawx(DisasContext
*s
, arg_rrrr
*a
, bool add
, bool mt
)
7352 if (!ENABLE_ARCH_5TE
) {
7356 t0
= load_reg(s
, a
->rn
);
7357 t1
= load_reg(s
, a
->rm
);
7359 * Since the nominal result is product<47:16>, shift the 16-bit
7360 * input up by 16 bits, so that the result is at product<63:32>.
7363 tcg_gen_andi_i32(t1
, t1
, 0xffff0000);
7365 tcg_gen_shli_i32(t1
, t1
, 16);
7367 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
7368 tcg_temp_free_i32(t0
);
7370 t0
= load_reg(s
, a
->ra
);
7371 gen_helper_add_setq(t1
, cpu_env
, t1
, t0
);
7372 tcg_temp_free_i32(t0
);
7374 store_reg(s
, a
->rd
, t1
);
7378 #define DO_SMLAWX(NAME, add, mt) \
7379 static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \
7381 return op_smlawx(s, a, add, mt); \
7384 DO_SMLAWX(SMULWB
, 0, 0)
7385 DO_SMLAWX(SMULWT
, 0, 1)
7386 DO_SMLAWX(SMLAWB
, 1, 0)
7387 DO_SMLAWX(SMLAWT
, 1, 1)
7392 * MSR (immediate) and hints
7395 static bool trans_YIELD(DisasContext
*s
, arg_YIELD
*a
)
7398 * When running single-threaded TCG code, use the helper to ensure that
7399 * the next round-robin scheduled vCPU gets a crack. When running in
7400 * MTTCG we don't generate jumps to the helper as it won't affect the
7401 * scheduling of other vCPUs.
7403 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
7404 gen_set_pc_im(s
, s
->base
.pc_next
);
7405 s
->base
.is_jmp
= DISAS_YIELD
;
7410 static bool trans_WFE(DisasContext
*s
, arg_WFE
*a
)
7413 * When running single-threaded TCG code, use the helper to ensure that
7414 * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we
7415 * just skip this instruction. Currently the SEV/SEVL instructions,
7416 * which are *one* of many ways to wake the CPU from WFE, are not
7417 * implemented so we can't sleep like WFI does.
7419 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
7420 gen_set_pc_im(s
, s
->base
.pc_next
);
7421 s
->base
.is_jmp
= DISAS_WFE
;
7426 static bool trans_WFI(DisasContext
*s
, arg_WFI
*a
)
7428 /* For WFI, halt the vCPU until an IRQ. */
7429 gen_set_pc_im(s
, s
->base
.pc_next
);
7430 s
->base
.is_jmp
= DISAS_WFI
;
7434 static bool trans_NOP(DisasContext
*s
, arg_NOP
*a
)
7439 static bool trans_MSR_imm(DisasContext
*s
, arg_MSR_imm
*a
)
7441 uint32_t val
= ror32(a
->imm
, a
->rot
* 2);
7442 uint32_t mask
= msr_mask(s
, a
->mask
, a
->r
);
7444 if (gen_set_psr_im(s
, mask
, a
->r
, val
)) {
7445 unallocated_encoding(s
);
7451 * Cyclic Redundancy Check
7454 static bool op_crc32(DisasContext
*s
, arg_rrr
*a
, bool c
, MemOp sz
)
7456 TCGv_i32 t1
, t2
, t3
;
7458 if (!dc_isar_feature(aa32_crc32
, s
)) {
7462 t1
= load_reg(s
, a
->rn
);
7463 t2
= load_reg(s
, a
->rm
);
7474 g_assert_not_reached();
7476 t3
= tcg_const_i32(1 << sz
);
7478 gen_helper_crc32c(t1
, t1
, t2
, t3
);
7480 gen_helper_crc32(t1
, t1
, t2
, t3
);
7482 tcg_temp_free_i32(t2
);
7483 tcg_temp_free_i32(t3
);
7484 store_reg(s
, a
->rd
, t1
);
7488 #define DO_CRC32(NAME, c, sz) \
7489 static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
7490 { return op_crc32(s, a, c, sz); }
7492 DO_CRC32(CRC32B
, false, MO_8
)
7493 DO_CRC32(CRC32H
, false, MO_16
)
7494 DO_CRC32(CRC32W
, false, MO_32
)
7495 DO_CRC32(CRC32CB
, true, MO_8
)
7496 DO_CRC32(CRC32CH
, true, MO_16
)
7497 DO_CRC32(CRC32CW
, true, MO_32
)
7502 * Miscellaneous instructions
7505 static bool trans_MRS_bank(DisasContext
*s
, arg_MRS_bank
*a
)
7507 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
7510 gen_mrs_banked(s
, a
->r
, a
->sysm
, a
->rd
);
7514 static bool trans_MSR_bank(DisasContext
*s
, arg_MSR_bank
*a
)
7516 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
7519 gen_msr_banked(s
, a
->r
, a
->sysm
, a
->rn
);
7523 static bool trans_MRS_reg(DisasContext
*s
, arg_MRS_reg
*a
)
7527 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
7532 unallocated_encoding(s
);
7535 tmp
= load_cpu_field(spsr
);
7537 tmp
= tcg_temp_new_i32();
7538 gen_helper_cpsr_read(tmp
, cpu_env
);
7540 store_reg(s
, a
->rd
, tmp
);
7544 static bool trans_MSR_reg(DisasContext
*s
, arg_MSR_reg
*a
)
7547 uint32_t mask
= msr_mask(s
, a
->mask
, a
->r
);
7549 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
7552 tmp
= load_reg(s
, a
->rn
);
7553 if (gen_set_psr(s
, mask
, a
->r
, tmp
)) {
7554 unallocated_encoding(s
);
7559 static bool trans_MRS_v7m(DisasContext
*s
, arg_MRS_v7m
*a
)
7563 if (!arm_dc_feature(s
, ARM_FEATURE_M
)) {
7566 tmp
= tcg_const_i32(a
->sysm
);
7567 gen_helper_v7m_mrs(tmp
, cpu_env
, tmp
);
7568 store_reg(s
, a
->rd
, tmp
);
7572 static bool trans_MSR_v7m(DisasContext
*s
, arg_MSR_v7m
*a
)
7576 if (!arm_dc_feature(s
, ARM_FEATURE_M
)) {
7579 addr
= tcg_const_i32((a
->mask
<< 10) | a
->sysm
);
7580 reg
= load_reg(s
, a
->rn
);
7581 gen_helper_v7m_msr(cpu_env
, addr
, reg
);
7582 tcg_temp_free_i32(addr
);
7583 tcg_temp_free_i32(reg
);
7584 /* If we wrote to CONTROL, the EL might have changed */
7585 gen_helper_rebuild_hflags_m32_newel(cpu_env
);
7590 static bool trans_BX(DisasContext
*s
, arg_BX
*a
)
7592 if (!ENABLE_ARCH_4T
) {
7595 gen_bx_excret(s
, load_reg(s
, a
->rm
));
7599 static bool trans_BXJ(DisasContext
*s
, arg_BXJ
*a
)
7601 if (!ENABLE_ARCH_5J
|| arm_dc_feature(s
, ARM_FEATURE_M
)) {
7604 /* Trivial implementation equivalent to bx. */
7605 gen_bx(s
, load_reg(s
, a
->rm
));
7609 static bool trans_BLX_r(DisasContext
*s
, arg_BLX_r
*a
)
7613 if (!ENABLE_ARCH_5
) {
7616 tmp
= load_reg(s
, a
->rm
);
7617 tcg_gen_movi_i32(cpu_R
[14], s
->base
.pc_next
| s
->thumb
);
7623 * BXNS/BLXNS: only exist for v8M with the security extensions,
7624 * and always UNDEF if NonSecure. We don't implement these in
7625 * the user-only mode either (in theory you can use them from
7626 * Secure User mode but they are too tied in to system emulation).
7628 static bool trans_BXNS(DisasContext
*s
, arg_BXNS
*a
)
7630 if (!s
->v8m_secure
|| IS_USER_ONLY
) {
7631 unallocated_encoding(s
);
7638 static bool trans_BLXNS(DisasContext
*s
, arg_BLXNS
*a
)
7640 if (!s
->v8m_secure
|| IS_USER_ONLY
) {
7641 unallocated_encoding(s
);
7643 gen_blxns(s
, a
->rm
);
7648 static bool trans_CLZ(DisasContext
*s
, arg_CLZ
*a
)
7652 if (!ENABLE_ARCH_5
) {
7655 tmp
= load_reg(s
, a
->rm
);
7656 tcg_gen_clzi_i32(tmp
, tmp
, 32);
7657 store_reg(s
, a
->rd
, tmp
);
7661 static bool trans_ERET(DisasContext
*s
, arg_ERET
*a
)
7665 if (!arm_dc_feature(s
, ARM_FEATURE_V7VE
)) {
7669 unallocated_encoding(s
);
7672 if (s
->current_el
== 2) {
7673 /* ERET from Hyp uses ELR_Hyp, not LR */
7674 tmp
= load_cpu_field(elr_el
[2]);
7676 tmp
= load_reg(s
, 14);
7678 gen_exception_return(s
, tmp
);
7682 static bool trans_HLT(DisasContext
*s
, arg_HLT
*a
)
7688 static bool trans_BKPT(DisasContext
*s
, arg_BKPT
*a
)
7690 if (!ENABLE_ARCH_5
) {
7693 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
7694 semihosting_enabled() &&
7695 #ifndef CONFIG_USER_ONLY
7699 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
7701 gen_exception_bkpt_insn(s
, syn_aa32_bkpt(a
->imm
, false));
7706 static bool trans_HVC(DisasContext
*s
, arg_HVC
*a
)
7708 if (!ENABLE_ARCH_7
|| arm_dc_feature(s
, ARM_FEATURE_M
)) {
7712 unallocated_encoding(s
);
7719 static bool trans_SMC(DisasContext
*s
, arg_SMC
*a
)
7721 if (!ENABLE_ARCH_6K
|| arm_dc_feature(s
, ARM_FEATURE_M
)) {
7725 unallocated_encoding(s
);
7732 static bool trans_SG(DisasContext
*s
, arg_SG
*a
)
7734 if (!arm_dc_feature(s
, ARM_FEATURE_M
) ||
7735 !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
7740 * The bulk of the behaviour for this instruction is implemented
7741 * in v7m_handle_execute_nsc(), which deals with the insn when
7742 * it is executed by a CPU in non-secure state from memory
7743 * which is Secure & NonSecure-Callable.
7744 * Here we only need to handle the remaining cases:
7745 * * in NS memory (including the "security extension not
7746 * implemented" case) : NOP
7747 * * in S memory but CPU already secure (clear IT bits)
7748 * We know that the attribute for the memory this insn is
7749 * in must match the current CPU state, because otherwise
7750 * get_phys_addr_pmsav8 would have generated an exception.
7752 if (s
->v8m_secure
) {
7753 /* Like the IT insn, we don't need to generate any code */
7754 s
->condexec_cond
= 0;
7755 s
->condexec_mask
= 0;
7760 static bool trans_TT(DisasContext
*s
, arg_TT
*a
)
7764 if (!arm_dc_feature(s
, ARM_FEATURE_M
) ||
7765 !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
7768 if (a
->rd
== 13 || a
->rd
== 15 || a
->rn
== 15) {
7769 /* We UNDEF for these UNPREDICTABLE cases */
7770 unallocated_encoding(s
);
7773 if (a
->A
&& !s
->v8m_secure
) {
7774 /* This case is UNDEFINED. */
7775 unallocated_encoding(s
);
7779 addr
= load_reg(s
, a
->rn
);
7780 tmp
= tcg_const_i32((a
->A
<< 1) | a
->T
);
7781 gen_helper_v7m_tt(tmp
, cpu_env
, addr
, tmp
);
7782 tcg_temp_free_i32(addr
);
7783 store_reg(s
, a
->rd
, tmp
);
7788 * Load/store register index
7791 static ISSInfo
make_issinfo(DisasContext
*s
, int rd
, bool p
, bool w
)
7795 /* ISS not valid if writeback */
7798 if (s
->base
.pc_next
- s
->pc_curr
== 2) {
7807 static TCGv_i32
op_addr_rr_pre(DisasContext
*s
, arg_ldst_rr
*a
)
7809 TCGv_i32 addr
= load_reg(s
, a
->rn
);
7811 if (s
->v8m_stackcheck
&& a
->rn
== 13 && a
->w
) {
7812 gen_helper_v8m_stackcheck(cpu_env
, addr
);
7816 TCGv_i32 ofs
= load_reg(s
, a
->rm
);
7817 gen_arm_shift_im(ofs
, a
->shtype
, a
->shimm
, 0);
7819 tcg_gen_add_i32(addr
, addr
, ofs
);
7821 tcg_gen_sub_i32(addr
, addr
, ofs
);
7823 tcg_temp_free_i32(ofs
);
7828 static void op_addr_rr_post(DisasContext
*s
, arg_ldst_rr
*a
,
7829 TCGv_i32 addr
, int address_offset
)
7832 TCGv_i32 ofs
= load_reg(s
, a
->rm
);
7833 gen_arm_shift_im(ofs
, a
->shtype
, a
->shimm
, 0);
7835 tcg_gen_add_i32(addr
, addr
, ofs
);
7837 tcg_gen_sub_i32(addr
, addr
, ofs
);
7839 tcg_temp_free_i32(ofs
);
7841 tcg_temp_free_i32(addr
);
7844 tcg_gen_addi_i32(addr
, addr
, address_offset
);
7845 store_reg(s
, a
->rn
, addr
);
7848 static bool op_load_rr(DisasContext
*s
, arg_ldst_rr
*a
,
7849 MemOp mop
, int mem_idx
)
7851 ISSInfo issinfo
= make_issinfo(s
, a
->rt
, a
->p
, a
->w
);
7854 addr
= op_addr_rr_pre(s
, a
);
7856 tmp
= tcg_temp_new_i32();
7857 gen_aa32_ld_i32(s
, tmp
, addr
, mem_idx
, mop
| s
->be_data
);
7858 disas_set_da_iss(s
, mop
, issinfo
);
7861 * Perform base writeback before the loaded value to
7862 * ensure correct behavior with overlapping index registers.
7864 op_addr_rr_post(s
, a
, addr
, 0);
7865 store_reg_from_load(s
, a
->rt
, tmp
);
7869 static bool op_store_rr(DisasContext
*s
, arg_ldst_rr
*a
,
7870 MemOp mop
, int mem_idx
)
7872 ISSInfo issinfo
= make_issinfo(s
, a
->rt
, a
->p
, a
->w
) | ISSIsWrite
;
7875 addr
= op_addr_rr_pre(s
, a
);
7877 tmp
= load_reg(s
, a
->rt
);
7878 gen_aa32_st_i32(s
, tmp
, addr
, mem_idx
, mop
| s
->be_data
);
7879 disas_set_da_iss(s
, mop
, issinfo
);
7880 tcg_temp_free_i32(tmp
);
7882 op_addr_rr_post(s
, a
, addr
, 0);
7886 static bool trans_LDRD_rr(DisasContext
*s
, arg_ldst_rr
*a
)
7888 int mem_idx
= get_mem_index(s
);
7891 if (!ENABLE_ARCH_5TE
) {
7895 unallocated_encoding(s
);
7898 addr
= op_addr_rr_pre(s
, a
);
7900 tmp
= tcg_temp_new_i32();
7901 gen_aa32_ld_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
7902 store_reg(s
, a
->rt
, tmp
);
7904 tcg_gen_addi_i32(addr
, addr
, 4);
7906 tmp
= tcg_temp_new_i32();
7907 gen_aa32_ld_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
7908 store_reg(s
, a
->rt
+ 1, tmp
);
7910 /* LDRD w/ base writeback is undefined if the registers overlap. */
7911 op_addr_rr_post(s
, a
, addr
, -4);
7915 static bool trans_STRD_rr(DisasContext
*s
, arg_ldst_rr
*a
)
7917 int mem_idx
= get_mem_index(s
);
7920 if (!ENABLE_ARCH_5TE
) {
7924 unallocated_encoding(s
);
7927 addr
= op_addr_rr_pre(s
, a
);
7929 tmp
= load_reg(s
, a
->rt
);
7930 gen_aa32_st_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
7931 tcg_temp_free_i32(tmp
);
7933 tcg_gen_addi_i32(addr
, addr
, 4);
7935 tmp
= load_reg(s
, a
->rt
+ 1);
7936 gen_aa32_st_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
7937 tcg_temp_free_i32(tmp
);
7939 op_addr_rr_post(s
, a
, addr
, -4);
7944 * Load/store immediate index
7947 static TCGv_i32
op_addr_ri_pre(DisasContext
*s
, arg_ldst_ri
*a
)
7955 if (s
->v8m_stackcheck
&& a
->rn
== 13 && a
->w
) {
7957 * Stackcheck. Here we know 'addr' is the current SP;
7958 * U is set if we're moving SP up, else down. It is
7959 * UNKNOWN whether the limit check triggers when SP starts
7960 * below the limit and ends up above it; we chose to do so.
7963 TCGv_i32 newsp
= tcg_temp_new_i32();
7964 tcg_gen_addi_i32(newsp
, cpu_R
[13], ofs
);
7965 gen_helper_v8m_stackcheck(cpu_env
, newsp
);
7966 tcg_temp_free_i32(newsp
);
7968 gen_helper_v8m_stackcheck(cpu_env
, cpu_R
[13]);
7972 return add_reg_for_lit(s
, a
->rn
, a
->p
? ofs
: 0);
7975 static void op_addr_ri_post(DisasContext
*s
, arg_ldst_ri
*a
,
7976 TCGv_i32 addr
, int address_offset
)
7980 address_offset
+= a
->imm
;
7982 address_offset
-= a
->imm
;
7985 tcg_temp_free_i32(addr
);
7988 tcg_gen_addi_i32(addr
, addr
, address_offset
);
7989 store_reg(s
, a
->rn
, addr
);
7992 static bool op_load_ri(DisasContext
*s
, arg_ldst_ri
*a
,
7993 MemOp mop
, int mem_idx
)
7995 ISSInfo issinfo
= make_issinfo(s
, a
->rt
, a
->p
, a
->w
);
7998 addr
= op_addr_ri_pre(s
, a
);
8000 tmp
= tcg_temp_new_i32();
8001 gen_aa32_ld_i32(s
, tmp
, addr
, mem_idx
, mop
| s
->be_data
);
8002 disas_set_da_iss(s
, mop
, issinfo
);
8005 * Perform base writeback before the loaded value to
8006 * ensure correct behavior with overlapping index registers.
8008 op_addr_ri_post(s
, a
, addr
, 0);
8009 store_reg_from_load(s
, a
->rt
, tmp
);
8013 static bool op_store_ri(DisasContext
*s
, arg_ldst_ri
*a
,
8014 MemOp mop
, int mem_idx
)
8016 ISSInfo issinfo
= make_issinfo(s
, a
->rt
, a
->p
, a
->w
) | ISSIsWrite
;
8019 addr
= op_addr_ri_pre(s
, a
);
8021 tmp
= load_reg(s
, a
->rt
);
8022 gen_aa32_st_i32(s
, tmp
, addr
, mem_idx
, mop
| s
->be_data
);
8023 disas_set_da_iss(s
, mop
, issinfo
);
8024 tcg_temp_free_i32(tmp
);
8026 op_addr_ri_post(s
, a
, addr
, 0);
8030 static bool op_ldrd_ri(DisasContext
*s
, arg_ldst_ri
*a
, int rt2
)
8032 int mem_idx
= get_mem_index(s
);
8035 addr
= op_addr_ri_pre(s
, a
);
8037 tmp
= tcg_temp_new_i32();
8038 gen_aa32_ld_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
8039 store_reg(s
, a
->rt
, tmp
);
8041 tcg_gen_addi_i32(addr
, addr
, 4);
8043 tmp
= tcg_temp_new_i32();
8044 gen_aa32_ld_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
8045 store_reg(s
, rt2
, tmp
);
8047 /* LDRD w/ base writeback is undefined if the registers overlap. */
8048 op_addr_ri_post(s
, a
, addr
, -4);
8052 static bool trans_LDRD_ri_a32(DisasContext
*s
, arg_ldst_ri
*a
)
8054 if (!ENABLE_ARCH_5TE
|| (a
->rt
& 1)) {
8057 return op_ldrd_ri(s
, a
, a
->rt
+ 1);
8060 static bool trans_LDRD_ri_t32(DisasContext
*s
, arg_ldst_ri2
*a
)
8063 .u
= a
->u
, .w
= a
->w
, .p
= a
->p
,
8064 .rn
= a
->rn
, .rt
= a
->rt
, .imm
= a
->imm
8066 return op_ldrd_ri(s
, &b
, a
->rt2
);
8069 static bool op_strd_ri(DisasContext
*s
, arg_ldst_ri
*a
, int rt2
)
8071 int mem_idx
= get_mem_index(s
);
8074 addr
= op_addr_ri_pre(s
, a
);
8076 tmp
= load_reg(s
, a
->rt
);
8077 gen_aa32_st_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
8078 tcg_temp_free_i32(tmp
);
8080 tcg_gen_addi_i32(addr
, addr
, 4);
8082 tmp
= load_reg(s
, rt2
);
8083 gen_aa32_st_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
8084 tcg_temp_free_i32(tmp
);
8086 op_addr_ri_post(s
, a
, addr
, -4);
8090 static bool trans_STRD_ri_a32(DisasContext
*s
, arg_ldst_ri
*a
)
8092 if (!ENABLE_ARCH_5TE
|| (a
->rt
& 1)) {
8095 return op_strd_ri(s
, a
, a
->rt
+ 1);
8098 static bool trans_STRD_ri_t32(DisasContext
*s
, arg_ldst_ri2
*a
)
8101 .u
= a
->u
, .w
= a
->w
, .p
= a
->p
,
8102 .rn
= a
->rn
, .rt
= a
->rt
, .imm
= a
->imm
8104 return op_strd_ri(s
, &b
, a
->rt2
);
8107 #define DO_LDST(NAME, WHICH, MEMOP) \
8108 static bool trans_##NAME##_ri(DisasContext *s, arg_ldst_ri *a) \
8110 return op_##WHICH##_ri(s, a, MEMOP, get_mem_index(s)); \
8112 static bool trans_##NAME##T_ri(DisasContext *s, arg_ldst_ri *a) \
8114 return op_##WHICH##_ri(s, a, MEMOP, get_a32_user_mem_index(s)); \
8116 static bool trans_##NAME##_rr(DisasContext *s, arg_ldst_rr *a) \
8118 return op_##WHICH##_rr(s, a, MEMOP, get_mem_index(s)); \
8120 static bool trans_##NAME##T_rr(DisasContext *s, arg_ldst_rr *a) \
8122 return op_##WHICH##_rr(s, a, MEMOP, get_a32_user_mem_index(s)); \
8125 DO_LDST(LDR
, load
, MO_UL
)
8126 DO_LDST(LDRB
, load
, MO_UB
)
8127 DO_LDST(LDRH
, load
, MO_UW
)
8128 DO_LDST(LDRSB
, load
, MO_SB
)
8129 DO_LDST(LDRSH
, load
, MO_SW
)
8131 DO_LDST(STR
, store
, MO_UL
)
8132 DO_LDST(STRB
, store
, MO_UB
)
8133 DO_LDST(STRH
, store
, MO_UW
)
8138 * Synchronization primitives
8141 static bool op_swp(DisasContext
*s
, arg_SWP
*a
, MemOp opc
)
8147 addr
= load_reg(s
, a
->rn
);
8148 taddr
= gen_aa32_addr(s
, addr
, opc
);
8149 tcg_temp_free_i32(addr
);
8151 tmp
= load_reg(s
, a
->rt2
);
8152 tcg_gen_atomic_xchg_i32(tmp
, taddr
, tmp
, get_mem_index(s
), opc
);
8153 tcg_temp_free(taddr
);
8155 store_reg(s
, a
->rt
, tmp
);
8159 static bool trans_SWP(DisasContext
*s
, arg_SWP
*a
)
8161 return op_swp(s
, a
, MO_UL
| MO_ALIGN
);
8164 static bool trans_SWPB(DisasContext
*s
, arg_SWP
*a
)
8166 return op_swp(s
, a
, MO_UB
);
8170 * Load/Store Exclusive and Load-Acquire/Store-Release
8173 static bool op_strex(DisasContext
*s
, arg_STREX
*a
, MemOp mop
, bool rel
)
8176 /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
8177 bool v8a
= ENABLE_ARCH_8
&& !arm_dc_feature(s
, ARM_FEATURE_M
);
8179 /* We UNDEF for these UNPREDICTABLE cases. */
8180 if (a
->rd
== 15 || a
->rn
== 15 || a
->rt
== 15
8181 || a
->rd
== a
->rn
|| a
->rd
== a
->rt
8182 || (!v8a
&& s
->thumb
&& (a
->rd
== 13 || a
->rt
== 13))
8186 || (!v8a
&& s
->thumb
&& a
->rt2
== 13)))) {
8187 unallocated_encoding(s
);
8192 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
8195 addr
= tcg_temp_local_new_i32();
8196 load_reg_var(s
, addr
, a
->rn
);
8197 tcg_gen_addi_i32(addr
, addr
, a
->imm
);
8199 gen_store_exclusive(s
, a
->rd
, a
->rt
, a
->rt2
, addr
, mop
);
8200 tcg_temp_free_i32(addr
);
8204 static bool trans_STREX(DisasContext
*s
, arg_STREX
*a
)
8206 if (!ENABLE_ARCH_6
) {
8209 return op_strex(s
, a
, MO_32
, false);
8212 static bool trans_STREXD_a32(DisasContext
*s
, arg_STREX
*a
)
8214 if (!ENABLE_ARCH_6K
) {
8217 /* We UNDEF for these UNPREDICTABLE cases. */
8219 unallocated_encoding(s
);
8223 return op_strex(s
, a
, MO_64
, false);
8226 static bool trans_STREXD_t32(DisasContext
*s
, arg_STREX
*a
)
8228 return op_strex(s
, a
, MO_64
, false);
8231 static bool trans_STREXB(DisasContext
*s
, arg_STREX
*a
)
8233 if (s
->thumb
? !ENABLE_ARCH_7
: !ENABLE_ARCH_6K
) {
8236 return op_strex(s
, a
, MO_8
, false);
8239 static bool trans_STREXH(DisasContext
*s
, arg_STREX
*a
)
8241 if (s
->thumb
? !ENABLE_ARCH_7
: !ENABLE_ARCH_6K
) {
8244 return op_strex(s
, a
, MO_16
, false);
8247 static bool trans_STLEX(DisasContext
*s
, arg_STREX
*a
)
8249 if (!ENABLE_ARCH_8
) {
8252 return op_strex(s
, a
, MO_32
, true);
8255 static bool trans_STLEXD_a32(DisasContext
*s
, arg_STREX
*a
)
8257 if (!ENABLE_ARCH_8
) {
8260 /* We UNDEF for these UNPREDICTABLE cases. */
8262 unallocated_encoding(s
);
8266 return op_strex(s
, a
, MO_64
, true);
8269 static bool trans_STLEXD_t32(DisasContext
*s
, arg_STREX
*a
)
8271 if (!ENABLE_ARCH_8
) {
8274 return op_strex(s
, a
, MO_64
, true);
8277 static bool trans_STLEXB(DisasContext
*s
, arg_STREX
*a
)
8279 if (!ENABLE_ARCH_8
) {
8282 return op_strex(s
, a
, MO_8
, true);
8285 static bool trans_STLEXH(DisasContext
*s
, arg_STREX
*a
)
8287 if (!ENABLE_ARCH_8
) {
8290 return op_strex(s
, a
, MO_16
, true);
8293 static bool op_stl(DisasContext
*s
, arg_STL
*a
, MemOp mop
)
8297 if (!ENABLE_ARCH_8
) {
8300 /* We UNDEF for these UNPREDICTABLE cases. */
8301 if (a
->rn
== 15 || a
->rt
== 15) {
8302 unallocated_encoding(s
);
8306 addr
= load_reg(s
, a
->rn
);
8307 tmp
= load_reg(s
, a
->rt
);
8308 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
8309 gen_aa32_st_i32(s
, tmp
, addr
, get_mem_index(s
), mop
| s
->be_data
);
8310 disas_set_da_iss(s
, mop
, a
->rt
| ISSIsAcqRel
| ISSIsWrite
);
8312 tcg_temp_free_i32(tmp
);
8313 tcg_temp_free_i32(addr
);
8317 static bool trans_STL(DisasContext
*s
, arg_STL
*a
)
8319 return op_stl(s
, a
, MO_UL
);
8322 static bool trans_STLB(DisasContext
*s
, arg_STL
*a
)
8324 return op_stl(s
, a
, MO_UB
);
8327 static bool trans_STLH(DisasContext
*s
, arg_STL
*a
)
8329 return op_stl(s
, a
, MO_UW
);
8332 static bool op_ldrex(DisasContext
*s
, arg_LDREX
*a
, MemOp mop
, bool acq
)
8335 /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
8336 bool v8a
= ENABLE_ARCH_8
&& !arm_dc_feature(s
, ARM_FEATURE_M
);
8338 /* We UNDEF for these UNPREDICTABLE cases. */
8339 if (a
->rn
== 15 || a
->rt
== 15
8340 || (!v8a
&& s
->thumb
&& a
->rt
== 13)
8342 && (a
->rt2
== 15 || a
->rt
== a
->rt2
8343 || (!v8a
&& s
->thumb
&& a
->rt2
== 13)))) {
8344 unallocated_encoding(s
);
8348 addr
= tcg_temp_local_new_i32();
8349 load_reg_var(s
, addr
, a
->rn
);
8350 tcg_gen_addi_i32(addr
, addr
, a
->imm
);
8352 gen_load_exclusive(s
, a
->rt
, a
->rt2
, addr
, mop
);
8353 tcg_temp_free_i32(addr
);
8356 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
8361 static bool trans_LDREX(DisasContext
*s
, arg_LDREX
*a
)
8363 if (!ENABLE_ARCH_6
) {
8366 return op_ldrex(s
, a
, MO_32
, false);
8369 static bool trans_LDREXD_a32(DisasContext
*s
, arg_LDREX
*a
)
8371 if (!ENABLE_ARCH_6K
) {
8374 /* We UNDEF for these UNPREDICTABLE cases. */
8376 unallocated_encoding(s
);
8380 return op_ldrex(s
, a
, MO_64
, false);
8383 static bool trans_LDREXD_t32(DisasContext
*s
, arg_LDREX
*a
)
8385 return op_ldrex(s
, a
, MO_64
, false);
8388 static bool trans_LDREXB(DisasContext
*s
, arg_LDREX
*a
)
8390 if (s
->thumb
? !ENABLE_ARCH_7
: !ENABLE_ARCH_6K
) {
8393 return op_ldrex(s
, a
, MO_8
, false);
8396 static bool trans_LDREXH(DisasContext
*s
, arg_LDREX
*a
)
8398 if (s
->thumb
? !ENABLE_ARCH_7
: !ENABLE_ARCH_6K
) {
8401 return op_ldrex(s
, a
, MO_16
, false);
8404 static bool trans_LDAEX(DisasContext
*s
, arg_LDREX
*a
)
8406 if (!ENABLE_ARCH_8
) {
8409 return op_ldrex(s
, a
, MO_32
, true);
8412 static bool trans_LDAEXD_a32(DisasContext
*s
, arg_LDREX
*a
)
8414 if (!ENABLE_ARCH_8
) {
8417 /* We UNDEF for these UNPREDICTABLE cases. */
8419 unallocated_encoding(s
);
8423 return op_ldrex(s
, a
, MO_64
, true);
8426 static bool trans_LDAEXD_t32(DisasContext
*s
, arg_LDREX
*a
)
8428 if (!ENABLE_ARCH_8
) {
8431 return op_ldrex(s
, a
, MO_64
, true);
8434 static bool trans_LDAEXB(DisasContext
*s
, arg_LDREX
*a
)
8436 if (!ENABLE_ARCH_8
) {
8439 return op_ldrex(s
, a
, MO_8
, true);
8442 static bool trans_LDAEXH(DisasContext
*s
, arg_LDREX
*a
)
8444 if (!ENABLE_ARCH_8
) {
8447 return op_ldrex(s
, a
, MO_16
, true);
8450 static bool op_lda(DisasContext
*s
, arg_LDA
*a
, MemOp mop
)
8454 if (!ENABLE_ARCH_8
) {
8457 /* We UNDEF for these UNPREDICTABLE cases. */
8458 if (a
->rn
== 15 || a
->rt
== 15) {
8459 unallocated_encoding(s
);
8463 addr
= load_reg(s
, a
->rn
);
8464 tmp
= tcg_temp_new_i32();
8465 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
), mop
| s
->be_data
);
8466 disas_set_da_iss(s
, mop
, a
->rt
| ISSIsAcqRel
);
8467 tcg_temp_free_i32(addr
);
8469 store_reg(s
, a
->rt
, tmp
);
8470 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
8474 static bool trans_LDA(DisasContext
*s
, arg_LDA
*a
)
8476 return op_lda(s
, a
, MO_UL
);
8479 static bool trans_LDAB(DisasContext
*s
, arg_LDA
*a
)
8481 return op_lda(s
, a
, MO_UB
);
8484 static bool trans_LDAH(DisasContext
*s
, arg_LDA
*a
)
8486 return op_lda(s
, a
, MO_UW
);
8490 * Media instructions
8493 static bool trans_USADA8(DisasContext
*s
, arg_USADA8
*a
)
8497 if (!ENABLE_ARCH_6
) {
8501 t1
= load_reg(s
, a
->rn
);
8502 t2
= load_reg(s
, a
->rm
);
8503 gen_helper_usad8(t1
, t1
, t2
);
8504 tcg_temp_free_i32(t2
);
8506 t2
= load_reg(s
, a
->ra
);
8507 tcg_gen_add_i32(t1
, t1
, t2
);
8508 tcg_temp_free_i32(t2
);
8510 store_reg(s
, a
->rd
, t1
);
8514 static bool op_bfx(DisasContext
*s
, arg_UBFX
*a
, bool u
)
8517 int width
= a
->widthm1
+ 1;
8520 if (!ENABLE_ARCH_6T2
) {
8523 if (shift
+ width
> 32) {
8524 /* UNPREDICTABLE; we choose to UNDEF */
8525 unallocated_encoding(s
);
8529 tmp
= load_reg(s
, a
->rn
);
8531 tcg_gen_extract_i32(tmp
, tmp
, shift
, width
);
8533 tcg_gen_sextract_i32(tmp
, tmp
, shift
, width
);
8535 store_reg(s
, a
->rd
, tmp
);
8539 static bool trans_SBFX(DisasContext
*s
, arg_SBFX
*a
)
8541 return op_bfx(s
, a
, false);
8544 static bool trans_UBFX(DisasContext
*s
, arg_UBFX
*a
)
8546 return op_bfx(s
, a
, true);
8549 static bool trans_BFCI(DisasContext
*s
, arg_BFCI
*a
)
8552 int msb
= a
->msb
, lsb
= a
->lsb
;
8555 if (!ENABLE_ARCH_6T2
) {
8559 /* UNPREDICTABLE; we choose to UNDEF */
8560 unallocated_encoding(s
);
8564 width
= msb
+ 1 - lsb
;
8567 tmp
= tcg_const_i32(0);
8570 tmp
= load_reg(s
, a
->rn
);
8573 TCGv_i32 tmp2
= load_reg(s
, a
->rd
);
8574 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, lsb
, width
);
8575 tcg_temp_free_i32(tmp2
);
8577 store_reg(s
, a
->rd
, tmp
);
8581 static bool trans_UDF(DisasContext
*s
, arg_UDF
*a
)
8583 unallocated_encoding(s
);
8588 * Parallel addition and subtraction
8591 static bool op_par_addsub(DisasContext
*s
, arg_rrr
*a
,
8592 void (*gen
)(TCGv_i32
, TCGv_i32
, TCGv_i32
))
8597 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
8602 t0
= load_reg(s
, a
->rn
);
8603 t1
= load_reg(s
, a
->rm
);
8607 tcg_temp_free_i32(t1
);
8608 store_reg(s
, a
->rd
, t0
);
8612 static bool op_par_addsub_ge(DisasContext
*s
, arg_rrr
*a
,
8613 void (*gen
)(TCGv_i32
, TCGv_i32
,
8614 TCGv_i32
, TCGv_ptr
))
8620 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
8625 t0
= load_reg(s
, a
->rn
);
8626 t1
= load_reg(s
, a
->rm
);
8628 ge
= tcg_temp_new_ptr();
8629 tcg_gen_addi_ptr(ge
, cpu_env
, offsetof(CPUARMState
, GE
));
8630 gen(t0
, t0
, t1
, ge
);
8632 tcg_temp_free_ptr(ge
);
8633 tcg_temp_free_i32(t1
);
8634 store_reg(s
, a
->rd
, t0
);
8638 #define DO_PAR_ADDSUB(NAME, helper) \
8639 static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
8641 return op_par_addsub(s, a, helper); \
8644 #define DO_PAR_ADDSUB_GE(NAME, helper) \
8645 static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
8647 return op_par_addsub_ge(s, a, helper); \
8650 DO_PAR_ADDSUB_GE(SADD16
, gen_helper_sadd16
)
8651 DO_PAR_ADDSUB_GE(SASX
, gen_helper_saddsubx
)
8652 DO_PAR_ADDSUB_GE(SSAX
, gen_helper_ssubaddx
)
8653 DO_PAR_ADDSUB_GE(SSUB16
, gen_helper_ssub16
)
8654 DO_PAR_ADDSUB_GE(SADD8
, gen_helper_sadd8
)
8655 DO_PAR_ADDSUB_GE(SSUB8
, gen_helper_ssub8
)
8657 DO_PAR_ADDSUB_GE(UADD16
, gen_helper_uadd16
)
8658 DO_PAR_ADDSUB_GE(UASX
, gen_helper_uaddsubx
)
8659 DO_PAR_ADDSUB_GE(USAX
, gen_helper_usubaddx
)
8660 DO_PAR_ADDSUB_GE(USUB16
, gen_helper_usub16
)
8661 DO_PAR_ADDSUB_GE(UADD8
, gen_helper_uadd8
)
8662 DO_PAR_ADDSUB_GE(USUB8
, gen_helper_usub8
)
8664 DO_PAR_ADDSUB(QADD16
, gen_helper_qadd16
)
8665 DO_PAR_ADDSUB(QASX
, gen_helper_qaddsubx
)
8666 DO_PAR_ADDSUB(QSAX
, gen_helper_qsubaddx
)
8667 DO_PAR_ADDSUB(QSUB16
, gen_helper_qsub16
)
8668 DO_PAR_ADDSUB(QADD8
, gen_helper_qadd8
)
8669 DO_PAR_ADDSUB(QSUB8
, gen_helper_qsub8
)
8671 DO_PAR_ADDSUB(UQADD16
, gen_helper_uqadd16
)
8672 DO_PAR_ADDSUB(UQASX
, gen_helper_uqaddsubx
)
8673 DO_PAR_ADDSUB(UQSAX
, gen_helper_uqsubaddx
)
8674 DO_PAR_ADDSUB(UQSUB16
, gen_helper_uqsub16
)
8675 DO_PAR_ADDSUB(UQADD8
, gen_helper_uqadd8
)
8676 DO_PAR_ADDSUB(UQSUB8
, gen_helper_uqsub8
)
8678 DO_PAR_ADDSUB(SHADD16
, gen_helper_shadd16
)
8679 DO_PAR_ADDSUB(SHASX
, gen_helper_shaddsubx
)
8680 DO_PAR_ADDSUB(SHSAX
, gen_helper_shsubaddx
)
8681 DO_PAR_ADDSUB(SHSUB16
, gen_helper_shsub16
)
8682 DO_PAR_ADDSUB(SHADD8
, gen_helper_shadd8
)
8683 DO_PAR_ADDSUB(SHSUB8
, gen_helper_shsub8
)
8685 DO_PAR_ADDSUB(UHADD16
, gen_helper_uhadd16
)
8686 DO_PAR_ADDSUB(UHASX
, gen_helper_uhaddsubx
)
8687 DO_PAR_ADDSUB(UHSAX
, gen_helper_uhsubaddx
)
8688 DO_PAR_ADDSUB(UHSUB16
, gen_helper_uhsub16
)
8689 DO_PAR_ADDSUB(UHADD8
, gen_helper_uhadd8
)
8690 DO_PAR_ADDSUB(UHSUB8
, gen_helper_uhsub8
)
8692 #undef DO_PAR_ADDSUB
8693 #undef DO_PAR_ADDSUB_GE
8696 * Packing, unpacking, saturation, and reversal
8699 static bool trans_PKH(DisasContext
*s
, arg_PKH
*a
)
8705 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
8710 tn
= load_reg(s
, a
->rn
);
8711 tm
= load_reg(s
, a
->rm
);
8717 tcg_gen_sari_i32(tm
, tm
, shift
);
8718 tcg_gen_deposit_i32(tn
, tn
, tm
, 0, 16);
8721 tcg_gen_shli_i32(tm
, tm
, shift
);
8722 tcg_gen_deposit_i32(tn
, tm
, tn
, 0, 16);
8724 tcg_temp_free_i32(tm
);
8725 store_reg(s
, a
->rd
, tn
);
8729 static bool op_sat(DisasContext
*s
, arg_sat
*a
,
8730 void (*gen
)(TCGv_i32
, TCGv_env
, TCGv_i32
, TCGv_i32
))
8732 TCGv_i32 tmp
, satimm
;
8735 if (!ENABLE_ARCH_6
) {
8739 tmp
= load_reg(s
, a
->rn
);
8741 tcg_gen_sari_i32(tmp
, tmp
, shift
? shift
: 31);
8743 tcg_gen_shli_i32(tmp
, tmp
, shift
);
8746 satimm
= tcg_const_i32(a
->satimm
);
8747 gen(tmp
, cpu_env
, tmp
, satimm
);
8748 tcg_temp_free_i32(satimm
);
8750 store_reg(s
, a
->rd
, tmp
);
8754 static bool trans_SSAT(DisasContext
*s
, arg_sat
*a
)
8756 return op_sat(s
, a
, gen_helper_ssat
);
8759 static bool trans_USAT(DisasContext
*s
, arg_sat
*a
)
8761 return op_sat(s
, a
, gen_helper_usat
);
8764 static bool trans_SSAT16(DisasContext
*s
, arg_sat
*a
)
8766 if (s
->thumb
&& !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
8769 return op_sat(s
, a
, gen_helper_ssat16
);
8772 static bool trans_USAT16(DisasContext
*s
, arg_sat
*a
)
8774 if (s
->thumb
&& !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
8777 return op_sat(s
, a
, gen_helper_usat16
);
8780 static bool op_xta(DisasContext
*s
, arg_rrr_rot
*a
,
8781 void (*gen_extract
)(TCGv_i32
, TCGv_i32
),
8782 void (*gen_add
)(TCGv_i32
, TCGv_i32
, TCGv_i32
))
8786 if (!ENABLE_ARCH_6
) {
8790 tmp
= load_reg(s
, a
->rm
);
8792 * TODO: In many cases we could do a shift instead of a rotate.
8793 * Combined with a simple extend, that becomes an extract.
8795 tcg_gen_rotri_i32(tmp
, tmp
, a
->rot
* 8);
8796 gen_extract(tmp
, tmp
);
8799 TCGv_i32 tmp2
= load_reg(s
, a
->rn
);
8800 gen_add(tmp
, tmp
, tmp2
);
8801 tcg_temp_free_i32(tmp2
);
8803 store_reg(s
, a
->rd
, tmp
);
8807 static bool trans_SXTAB(DisasContext
*s
, arg_rrr_rot
*a
)
8809 return op_xta(s
, a
, tcg_gen_ext8s_i32
, tcg_gen_add_i32
);
8812 static bool trans_SXTAH(DisasContext
*s
, arg_rrr_rot
*a
)
8814 return op_xta(s
, a
, tcg_gen_ext16s_i32
, tcg_gen_add_i32
);
8817 static bool trans_SXTAB16(DisasContext
*s
, arg_rrr_rot
*a
)
8819 if (s
->thumb
&& !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
8822 return op_xta(s
, a
, gen_helper_sxtb16
, gen_add16
);
8825 static bool trans_UXTAB(DisasContext
*s
, arg_rrr_rot
*a
)
8827 return op_xta(s
, a
, tcg_gen_ext8u_i32
, tcg_gen_add_i32
);
8830 static bool trans_UXTAH(DisasContext
*s
, arg_rrr_rot
*a
)
8832 return op_xta(s
, a
, tcg_gen_ext16u_i32
, tcg_gen_add_i32
);
8835 static bool trans_UXTAB16(DisasContext
*s
, arg_rrr_rot
*a
)
8837 if (s
->thumb
&& !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
8840 return op_xta(s
, a
, gen_helper_uxtb16
, gen_add16
);
8843 static bool trans_SEL(DisasContext
*s
, arg_rrr
*a
)
8845 TCGv_i32 t1
, t2
, t3
;
8848 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
8853 t1
= load_reg(s
, a
->rn
);
8854 t2
= load_reg(s
, a
->rm
);
8855 t3
= tcg_temp_new_i32();
8856 tcg_gen_ld_i32(t3
, cpu_env
, offsetof(CPUARMState
, GE
));
8857 gen_helper_sel_flags(t1
, t3
, t1
, t2
);
8858 tcg_temp_free_i32(t3
);
8859 tcg_temp_free_i32(t2
);
8860 store_reg(s
, a
->rd
, t1
);
8864 static bool op_rr(DisasContext
*s
, arg_rr
*a
,
8865 void (*gen
)(TCGv_i32
, TCGv_i32
))
8869 tmp
= load_reg(s
, a
->rm
);
8871 store_reg(s
, a
->rd
, tmp
);
8875 static bool trans_REV(DisasContext
*s
, arg_rr
*a
)
8877 if (!ENABLE_ARCH_6
) {
8880 return op_rr(s
, a
, tcg_gen_bswap32_i32
);
8883 static bool trans_REV16(DisasContext
*s
, arg_rr
*a
)
8885 if (!ENABLE_ARCH_6
) {
8888 return op_rr(s
, a
, gen_rev16
);
8891 static bool trans_REVSH(DisasContext
*s
, arg_rr
*a
)
8893 if (!ENABLE_ARCH_6
) {
8896 return op_rr(s
, a
, gen_revsh
);
8899 static bool trans_RBIT(DisasContext
*s
, arg_rr
*a
)
8901 if (!ENABLE_ARCH_6T2
) {
8904 return op_rr(s
, a
, gen_helper_rbit
);
8908 * Signed multiply, signed and unsigned divide
8911 static bool op_smlad(DisasContext
*s
, arg_rrrr
*a
, bool m_swap
, bool sub
)
8915 if (!ENABLE_ARCH_6
) {
8919 t1
= load_reg(s
, a
->rn
);
8920 t2
= load_reg(s
, a
->rm
);
8924 gen_smul_dual(t1
, t2
);
8927 /* This subtraction cannot overflow. */
8928 tcg_gen_sub_i32(t1
, t1
, t2
);
8931 * This addition cannot overflow 32 bits; however it may
8932 * overflow considered as a signed operation, in which case
8933 * we must set the Q flag.
8935 gen_helper_add_setq(t1
, cpu_env
, t1
, t2
);
8937 tcg_temp_free_i32(t2
);
8940 t2
= load_reg(s
, a
->ra
);
8941 gen_helper_add_setq(t1
, cpu_env
, t1
, t2
);
8942 tcg_temp_free_i32(t2
);
8944 store_reg(s
, a
->rd
, t1
);
8948 static bool trans_SMLAD(DisasContext
*s
, arg_rrrr
*a
)
8950 return op_smlad(s
, a
, false, false);
8953 static bool trans_SMLADX(DisasContext
*s
, arg_rrrr
*a
)
8955 return op_smlad(s
, a
, true, false);
8958 static bool trans_SMLSD(DisasContext
*s
, arg_rrrr
*a
)
8960 return op_smlad(s
, a
, false, true);
8963 static bool trans_SMLSDX(DisasContext
*s
, arg_rrrr
*a
)
8965 return op_smlad(s
, a
, true, true);
8968 static bool op_smlald(DisasContext
*s
, arg_rrrr
*a
, bool m_swap
, bool sub
)
8973 if (!ENABLE_ARCH_6
) {
8977 t1
= load_reg(s
, a
->rn
);
8978 t2
= load_reg(s
, a
->rm
);
8982 gen_smul_dual(t1
, t2
);
8984 l1
= tcg_temp_new_i64();
8985 l2
= tcg_temp_new_i64();
8986 tcg_gen_ext_i32_i64(l1
, t1
);
8987 tcg_gen_ext_i32_i64(l2
, t2
);
8988 tcg_temp_free_i32(t1
);
8989 tcg_temp_free_i32(t2
);
8992 tcg_gen_sub_i64(l1
, l1
, l2
);
8994 tcg_gen_add_i64(l1
, l1
, l2
);
8996 tcg_temp_free_i64(l2
);
8998 gen_addq(s
, l1
, a
->ra
, a
->rd
);
8999 gen_storeq_reg(s
, a
->ra
, a
->rd
, l1
);
9000 tcg_temp_free_i64(l1
);
9004 static bool trans_SMLALD(DisasContext
*s
, arg_rrrr
*a
)
9006 return op_smlald(s
, a
, false, false);
9009 static bool trans_SMLALDX(DisasContext
*s
, arg_rrrr
*a
)
9011 return op_smlald(s
, a
, true, false);
9014 static bool trans_SMLSLD(DisasContext
*s
, arg_rrrr
*a
)
9016 return op_smlald(s
, a
, false, true);
9019 static bool trans_SMLSLDX(DisasContext
*s
, arg_rrrr
*a
)
9021 return op_smlald(s
, a
, true, true);
9024 static bool op_smmla(DisasContext
*s
, arg_rrrr
*a
, bool round
, bool sub
)
9029 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
9034 t1
= load_reg(s
, a
->rn
);
9035 t2
= load_reg(s
, a
->rm
);
9036 tcg_gen_muls2_i32(t2
, t1
, t1
, t2
);
9039 TCGv_i32 t3
= load_reg(s
, a
->ra
);
9042 * For SMMLS, we need a 64-bit subtract. Borrow caused by
9043 * a non-zero multiplicand lowpart, and the correct result
9044 * lowpart for rounding.
9046 TCGv_i32 zero
= tcg_const_i32(0);
9047 tcg_gen_sub2_i32(t2
, t1
, zero
, t3
, t2
, t1
);
9048 tcg_temp_free_i32(zero
);
9050 tcg_gen_add_i32(t1
, t1
, t3
);
9052 tcg_temp_free_i32(t3
);
9056 * Adding 0x80000000 to the 64-bit quantity means that we have
9057 * carry in to the high word when the low word has the msb set.
9059 tcg_gen_shri_i32(t2
, t2
, 31);
9060 tcg_gen_add_i32(t1
, t1
, t2
);
9062 tcg_temp_free_i32(t2
);
9063 store_reg(s
, a
->rd
, t1
);
9067 static bool trans_SMMLA(DisasContext
*s
, arg_rrrr
*a
)
9069 return op_smmla(s
, a
, false, false);
9072 static bool trans_SMMLAR(DisasContext
*s
, arg_rrrr
*a
)
9074 return op_smmla(s
, a
, true, false);
9077 static bool trans_SMMLS(DisasContext
*s
, arg_rrrr
*a
)
9079 return op_smmla(s
, a
, false, true);
9082 static bool trans_SMMLSR(DisasContext
*s
, arg_rrrr
*a
)
9084 return op_smmla(s
, a
, true, true);
9087 static bool op_div(DisasContext
*s
, arg_rrr
*a
, bool u
)
9092 ? !dc_isar_feature(aa32_thumb_div
, s
)
9093 : !dc_isar_feature(aa32_arm_div
, s
)) {
9097 t1
= load_reg(s
, a
->rn
);
9098 t2
= load_reg(s
, a
->rm
);
9100 gen_helper_udiv(t1
, t1
, t2
);
9102 gen_helper_sdiv(t1
, t1
, t2
);
9104 tcg_temp_free_i32(t2
);
9105 store_reg(s
, a
->rd
, t1
);
9109 static bool trans_SDIV(DisasContext
*s
, arg_rrr
*a
)
9111 return op_div(s
, a
, false);
9114 static bool trans_UDIV(DisasContext
*s
, arg_rrr
*a
)
9116 return op_div(s
, a
, true);
9120 * Block data transfer
9123 static TCGv_i32
op_addr_block_pre(DisasContext
*s
, arg_ldst_block
*a
, int n
)
9125 TCGv_i32 addr
= load_reg(s
, a
->rn
);
9130 tcg_gen_addi_i32(addr
, addr
, 4);
9133 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
9135 } else if (!a
->i
&& n
!= 1) {
9136 /* post decrement */
9137 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
9140 if (s
->v8m_stackcheck
&& a
->rn
== 13 && a
->w
) {
9142 * If the writeback is incrementing SP rather than
9143 * decrementing it, and the initial SP is below the
9144 * stack limit but the final written-back SP would
9145 * be above, then then we must not perform any memory
9146 * accesses, but it is IMPDEF whether we generate
9147 * an exception. We choose to do so in this case.
9148 * At this point 'addr' is the lowest address, so
9149 * either the original SP (if incrementing) or our
9150 * final SP (if decrementing), so that's what we check.
9152 gen_helper_v8m_stackcheck(cpu_env
, addr
);
9158 static void op_addr_block_post(DisasContext
*s
, arg_ldst_block
*a
,
9159 TCGv_i32 addr
, int n
)
9165 /* post increment */
9166 tcg_gen_addi_i32(addr
, addr
, 4);
9168 /* post decrement */
9169 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
9171 } else if (!a
->i
&& n
!= 1) {
9173 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
9175 store_reg(s
, a
->rn
, addr
);
9177 tcg_temp_free_i32(addr
);
9181 static bool op_stm(DisasContext
*s
, arg_ldst_block
*a
, int min_n
)
9183 int i
, j
, n
, list
, mem_idx
;
9185 TCGv_i32 addr
, tmp
, tmp2
;
9190 /* Only usable in supervisor mode. */
9191 unallocated_encoding(s
);
9198 if (n
< min_n
|| a
->rn
== 15) {
9199 unallocated_encoding(s
);
9203 addr
= op_addr_block_pre(s
, a
, n
);
9204 mem_idx
= get_mem_index(s
);
9206 for (i
= j
= 0; i
< 16; i
++) {
9207 if (!(list
& (1 << i
))) {
9211 if (user
&& i
!= 15) {
9212 tmp
= tcg_temp_new_i32();
9213 tmp2
= tcg_const_i32(i
);
9214 gen_helper_get_user_reg(tmp
, cpu_env
, tmp2
);
9215 tcg_temp_free_i32(tmp2
);
9217 tmp
= load_reg(s
, i
);
9219 gen_aa32_st32(s
, tmp
, addr
, mem_idx
);
9220 tcg_temp_free_i32(tmp
);
9222 /* No need to add after the last transfer. */
9224 tcg_gen_addi_i32(addr
, addr
, 4);
9228 op_addr_block_post(s
, a
, addr
, n
);
9232 static bool trans_STM(DisasContext
*s
, arg_ldst_block
*a
)
9234 /* BitCount(list) < 1 is UNPREDICTABLE */
9235 return op_stm(s
, a
, 1);
9238 static bool trans_STM_t32(DisasContext
*s
, arg_ldst_block
*a
)
9240 /* Writeback register in register list is UNPREDICTABLE for T32. */
9241 if (a
->w
&& (a
->list
& (1 << a
->rn
))) {
9242 unallocated_encoding(s
);
9245 /* BitCount(list) < 2 is UNPREDICTABLE */
9246 return op_stm(s
, a
, 2);
9249 static bool do_ldm(DisasContext
*s
, arg_ldst_block
*a
, int min_n
)
9251 int i
, j
, n
, list
, mem_idx
;
9254 bool exc_return
= false;
9255 TCGv_i32 addr
, tmp
, tmp2
, loaded_var
;
9258 /* LDM (user), LDM (exception return) */
9260 /* Only usable in supervisor mode. */
9261 unallocated_encoding(s
);
9264 if (extract32(a
->list
, 15, 1)) {
9268 /* LDM (user) does not allow writeback. */
9270 unallocated_encoding(s
);
9278 if (n
< min_n
|| a
->rn
== 15) {
9279 unallocated_encoding(s
);
9283 addr
= op_addr_block_pre(s
, a
, n
);
9284 mem_idx
= get_mem_index(s
);
9285 loaded_base
= false;
9288 for (i
= j
= 0; i
< 16; i
++) {
9289 if (!(list
& (1 << i
))) {
9293 tmp
= tcg_temp_new_i32();
9294 gen_aa32_ld32u(s
, tmp
, addr
, mem_idx
);
9296 tmp2
= tcg_const_i32(i
);
9297 gen_helper_set_user_reg(cpu_env
, tmp2
, tmp
);
9298 tcg_temp_free_i32(tmp2
);
9299 tcg_temp_free_i32(tmp
);
9300 } else if (i
== a
->rn
) {
9303 } else if (i
== 15 && exc_return
) {
9304 store_pc_exc_ret(s
, tmp
);
9306 store_reg_from_load(s
, i
, tmp
);
9309 /* No need to add after the last transfer. */
9311 tcg_gen_addi_i32(addr
, addr
, 4);
9315 op_addr_block_post(s
, a
, addr
, n
);
9318 /* Note that we reject base == pc above. */
9319 store_reg(s
, a
->rn
, loaded_var
);
9323 /* Restore CPSR from SPSR. */
9324 tmp
= load_cpu_field(spsr
);
9325 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
9328 gen_helper_cpsr_write_eret(cpu_env
, tmp
);
9329 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
9332 tcg_temp_free_i32(tmp
);
9333 /* Must exit loop to check un-masked IRQs */
9334 s
->base
.is_jmp
= DISAS_EXIT
;
9339 static bool trans_LDM_a32(DisasContext
*s
, arg_ldst_block
*a
)
9342 * Writeback register in register list is UNPREDICTABLE
9343 * for ArchVersion() >= 7. Prior to v7, A32 would write
9344 * an UNKNOWN value to the base register.
9346 if (ENABLE_ARCH_7
&& a
->w
&& (a
->list
& (1 << a
->rn
))) {
9347 unallocated_encoding(s
);
9350 /* BitCount(list) < 1 is UNPREDICTABLE */
9351 return do_ldm(s
, a
, 1);
9354 static bool trans_LDM_t32(DisasContext
*s
, arg_ldst_block
*a
)
9356 /* Writeback register in register list is UNPREDICTABLE for T32. */
9357 if (a
->w
&& (a
->list
& (1 << a
->rn
))) {
9358 unallocated_encoding(s
);
9361 /* BitCount(list) < 2 is UNPREDICTABLE */
9362 return do_ldm(s
, a
, 2);
9365 static bool trans_LDM_t16(DisasContext
*s
, arg_ldst_block
*a
)
9367 /* Writeback is conditional on the base register not being loaded. */
9368 a
->w
= !(a
->list
& (1 << a
->rn
));
9369 /* BitCount(list) < 1 is UNPREDICTABLE */
9370 return do_ldm(s
, a
, 1);
9374 * Branch, branch with link
9377 static bool trans_B(DisasContext
*s
, arg_i
*a
)
9379 gen_jmp(s
, read_pc(s
) + a
->imm
);
9383 static bool trans_B_cond_thumb(DisasContext
*s
, arg_ci
*a
)
9385 /* This has cond from encoding, required to be outside IT block. */
9386 if (a
->cond
>= 0xe) {
9389 if (s
->condexec_mask
) {
9390 unallocated_encoding(s
);
9393 arm_skip_unless(s
, a
->cond
);
9394 gen_jmp(s
, read_pc(s
) + a
->imm
);
9398 static bool trans_BL(DisasContext
*s
, arg_i
*a
)
9400 tcg_gen_movi_i32(cpu_R
[14], s
->base
.pc_next
| s
->thumb
);
9401 gen_jmp(s
, read_pc(s
) + a
->imm
);
9405 static bool trans_BLX_i(DisasContext
*s
, arg_BLX_i
*a
)
9409 /* For A32, ARCH(5) is checked near the start of the uncond block. */
9410 if (s
->thumb
&& (a
->imm
& 2)) {
9413 tcg_gen_movi_i32(cpu_R
[14], s
->base
.pc_next
| s
->thumb
);
9414 tmp
= tcg_const_i32(!s
->thumb
);
9415 store_cpu_field(tmp
, thumb
);
9416 gen_jmp(s
, (read_pc(s
) & ~3) + a
->imm
);
9420 static bool trans_BL_BLX_prefix(DisasContext
*s
, arg_BL_BLX_prefix
*a
)
9422 assert(!arm_dc_feature(s
, ARM_FEATURE_THUMB2
));
9423 tcg_gen_movi_i32(cpu_R
[14], read_pc(s
) + (a
->imm
<< 12));
9427 static bool trans_BL_suffix(DisasContext
*s
, arg_BL_suffix
*a
)
9429 TCGv_i32 tmp
= tcg_temp_new_i32();
9431 assert(!arm_dc_feature(s
, ARM_FEATURE_THUMB2
));
9432 tcg_gen_addi_i32(tmp
, cpu_R
[14], (a
->imm
<< 1) | 1);
9433 tcg_gen_movi_i32(cpu_R
[14], s
->base
.pc_next
| 1);
9438 static bool trans_BLX_suffix(DisasContext
*s
, arg_BLX_suffix
*a
)
9442 assert(!arm_dc_feature(s
, ARM_FEATURE_THUMB2
));
9443 if (!ENABLE_ARCH_5
) {
9446 tmp
= tcg_temp_new_i32();
9447 tcg_gen_addi_i32(tmp
, cpu_R
[14], a
->imm
<< 1);
9448 tcg_gen_andi_i32(tmp
, tmp
, 0xfffffffc);
9449 tcg_gen_movi_i32(cpu_R
[14], s
->base
.pc_next
| 1);
9454 static bool op_tbranch(DisasContext
*s
, arg_tbranch
*a
, bool half
)
9458 tmp
= load_reg(s
, a
->rm
);
9460 tcg_gen_add_i32(tmp
, tmp
, tmp
);
9462 addr
= load_reg(s
, a
->rn
);
9463 tcg_gen_add_i32(addr
, addr
, tmp
);
9465 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
),
9466 half
? MO_UW
| s
->be_data
: MO_UB
);
9467 tcg_temp_free_i32(addr
);
9469 tcg_gen_add_i32(tmp
, tmp
, tmp
);
9470 tcg_gen_addi_i32(tmp
, tmp
, read_pc(s
));
9471 store_reg(s
, 15, tmp
);
9475 static bool trans_TBB(DisasContext
*s
, arg_tbranch
*a
)
9477 return op_tbranch(s
, a
, false);
9480 static bool trans_TBH(DisasContext
*s
, arg_tbranch
*a
)
9482 return op_tbranch(s
, a
, true);
9485 static bool trans_CBZ(DisasContext
*s
, arg_CBZ
*a
)
9487 TCGv_i32 tmp
= load_reg(s
, a
->rn
);
9489 arm_gen_condlabel(s
);
9490 tcg_gen_brcondi_i32(a
->nz
? TCG_COND_EQ
: TCG_COND_NE
,
9491 tmp
, 0, s
->condlabel
);
9492 tcg_temp_free_i32(tmp
);
9493 gen_jmp(s
, read_pc(s
) + a
->imm
);
9498 * Supervisor call - both T32 & A32 come here so we need to check
9499 * which mode we are in when checking for semihosting.
9502 static bool trans_SVC(DisasContext
*s
, arg_SVC
*a
)
9504 const uint32_t semihost_imm
= s
->thumb
? 0xab : 0x123456;
9506 if (!arm_dc_feature(s
, ARM_FEATURE_M
) && semihosting_enabled() &&
9507 #ifndef CONFIG_USER_ONLY
9510 (a
->imm
== semihost_imm
)) {
9511 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
9513 gen_set_pc_im(s
, s
->base
.pc_next
);
9514 s
->svc_imm
= a
->imm
;
9515 s
->base
.is_jmp
= DISAS_SWI
;
9521 * Unconditional system instructions
9524 static bool trans_RFE(DisasContext
*s
, arg_RFE
*a
)
9526 static const int8_t pre_offset
[4] = {
9527 /* DA */ -4, /* IA */ 0, /* DB */ -8, /* IB */ 4
9529 static const int8_t post_offset
[4] = {
9530 /* DA */ -8, /* IA */ 4, /* DB */ -4, /* IB */ 0
9532 TCGv_i32 addr
, t1
, t2
;
9534 if (!ENABLE_ARCH_6
|| arm_dc_feature(s
, ARM_FEATURE_M
)) {
9538 unallocated_encoding(s
);
9542 addr
= load_reg(s
, a
->rn
);
9543 tcg_gen_addi_i32(addr
, addr
, pre_offset
[a
->pu
]);
9545 /* Load PC into tmp and CPSR into tmp2. */
9546 t1
= tcg_temp_new_i32();
9547 gen_aa32_ld32u(s
, t1
, addr
, get_mem_index(s
));
9548 tcg_gen_addi_i32(addr
, addr
, 4);
9549 t2
= tcg_temp_new_i32();
9550 gen_aa32_ld32u(s
, t2
, addr
, get_mem_index(s
));
9553 /* Base writeback. */
9554 tcg_gen_addi_i32(addr
, addr
, post_offset
[a
->pu
]);
9555 store_reg(s
, a
->rn
, addr
);
9557 tcg_temp_free_i32(addr
);
9563 static bool trans_SRS(DisasContext
*s
, arg_SRS
*a
)
9565 if (!ENABLE_ARCH_6
|| arm_dc_feature(s
, ARM_FEATURE_M
)) {
9568 gen_srs(s
, a
->mode
, a
->pu
, a
->w
);
9572 static bool trans_CPS(DisasContext
*s
, arg_CPS
*a
)
9576 if (!ENABLE_ARCH_6
|| arm_dc_feature(s
, ARM_FEATURE_M
)) {
9580 /* Implemented as NOP in user mode. */
9583 /* TODO: There are quite a lot of UNPREDICTABLE argument combinations. */
9605 gen_set_psr_im(s
, mask
, 0, val
);
9610 static bool trans_CPS_v7m(DisasContext
*s
, arg_CPS_v7m
*a
)
9612 TCGv_i32 tmp
, addr
, el
;
9614 if (!arm_dc_feature(s
, ARM_FEATURE_M
)) {
9618 /* Implemented as NOP in user mode. */
9622 tmp
= tcg_const_i32(a
->im
);
9625 addr
= tcg_const_i32(19);
9626 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
9627 tcg_temp_free_i32(addr
);
9631 addr
= tcg_const_i32(16);
9632 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
9633 tcg_temp_free_i32(addr
);
9635 el
= tcg_const_i32(s
->current_el
);
9636 gen_helper_rebuild_hflags_m32(cpu_env
, el
);
9637 tcg_temp_free_i32(el
);
9638 tcg_temp_free_i32(tmp
);
9644 * Clear-Exclusive, Barriers
9647 static bool trans_CLREX(DisasContext
*s
, arg_CLREX
*a
)
9650 ? !ENABLE_ARCH_7
&& !arm_dc_feature(s
, ARM_FEATURE_M
)
9651 : !ENABLE_ARCH_6K
) {
9658 static bool trans_DSB(DisasContext
*s
, arg_DSB
*a
)
9660 if (!ENABLE_ARCH_7
&& !arm_dc_feature(s
, ARM_FEATURE_M
)) {
9663 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
9667 static bool trans_DMB(DisasContext
*s
, arg_DMB
*a
)
9669 return trans_DSB(s
, NULL
);
9672 static bool trans_ISB(DisasContext
*s
, arg_ISB
*a
)
9674 if (!ENABLE_ARCH_7
&& !arm_dc_feature(s
, ARM_FEATURE_M
)) {
9678 * We need to break the TB after this insn to execute
9679 * self-modifying code correctly and also to take
9680 * any pending interrupts immediately.
9682 gen_goto_tb(s
, 0, s
->base
.pc_next
);
9686 static bool trans_SB(DisasContext
*s
, arg_SB
*a
)
9688 if (!dc_isar_feature(aa32_sb
, s
)) {
9692 * TODO: There is no speculation barrier opcode
9693 * for TCG; MB and end the TB instead.
9695 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
9696 gen_goto_tb(s
, 0, s
->base
.pc_next
);
9700 static bool trans_SETEND(DisasContext
*s
, arg_SETEND
*a
)
9702 if (!ENABLE_ARCH_6
) {
9705 if (a
->E
!= (s
->be_data
== MO_BE
)) {
9706 gen_helper_setend(cpu_env
);
9707 s
->base
.is_jmp
= DISAS_UPDATE
;
9713 * Preload instructions
9714 * All are nops, contingent on the appropriate arch level.
9717 static bool trans_PLD(DisasContext
*s
, arg_PLD
*a
)
9719 return ENABLE_ARCH_5TE
;
9722 static bool trans_PLDW(DisasContext
*s
, arg_PLD
*a
)
9724 return arm_dc_feature(s
, ARM_FEATURE_V7MP
);
9727 static bool trans_PLI(DisasContext
*s
, arg_PLD
*a
)
9729 return ENABLE_ARCH_7
;
9736 static bool trans_IT(DisasContext
*s
, arg_IT
*a
)
9738 int cond_mask
= a
->cond_mask
;
9741 * No actual code generated for this insn, just setup state.
9743 * Combinations of firstcond and mask which set up an 0b1111
9744 * condition are UNPREDICTABLE; we take the CONSTRAINED
9745 * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110,
9746 * i.e. both meaning "execute always".
9748 s
->condexec_cond
= (cond_mask
>> 4) & 0xe;
9749 s
->condexec_mask
= cond_mask
& 0x1f;
9757 static void disas_arm_insn(DisasContext
*s
, unsigned int insn
)
9759 unsigned int cond
= insn
>> 28;
9761 /* M variants do not implement ARM mode; this must raise the INVSTATE
9762 * UsageFault exception.
9764 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
9765 gen_exception_insn(s
, s
->pc_curr
, EXCP_INVSTATE
, syn_uncategorized(),
9766 default_exception_el(s
));
9771 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
9772 * choose to UNDEF. In ARMv5 and above the space is used
9773 * for miscellaneous unconditional instructions.
9777 /* Unconditional instructions. */
9778 /* TODO: Perhaps merge these into one decodetree output file. */
9779 if (disas_a32_uncond(s
, insn
) ||
9780 disas_vfp_uncond(s
, insn
) ||
9781 disas_neon_dp(s
, insn
) ||
9782 disas_neon_ls(s
, insn
) ||
9783 disas_neon_shared(s
, insn
)) {
9786 /* fall back to legacy decoder */
9788 if (((insn
>> 25) & 7) == 1) {
9789 /* NEON Data processing. */
9790 if (disas_neon_data_insn(s
, insn
)) {
9795 if ((insn
& 0x0e000f00) == 0x0c000100) {
9796 if (arm_dc_feature(s
, ARM_FEATURE_IWMMXT
)) {
9797 /* iWMMXt register transfer. */
9798 if (extract32(s
->c15_cpar
, 1, 1)) {
9799 if (!disas_iwmmxt_insn(s
, insn
)) {
9808 /* if not always execute, we generate a conditional jump to
9810 arm_skip_unless(s
, cond
);
9813 /* TODO: Perhaps merge these into one decodetree output file. */
9814 if (disas_a32(s
, insn
) ||
9815 disas_vfp(s
, insn
)) {
9818 /* fall back to legacy decoder */
9820 switch ((insn
>> 24) & 0xf) {
9824 if (((insn
>> 8) & 0xe) == 10) {
9825 /* VFP, but failed disas_vfp. */
9828 if (disas_coproc_insn(s
, insn
)) {
9835 unallocated_encoding(s
);
9840 static bool thumb_insn_is_16bit(DisasContext
*s
, uint32_t pc
, uint32_t insn
)
9843 * Return true if this is a 16 bit instruction. We must be precise
9844 * about this (matching the decode).
9846 if ((insn
>> 11) < 0x1d) {
9847 /* Definitely a 16-bit instruction */
9851 /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
9852 * first half of a 32-bit Thumb insn. Thumb-1 cores might
9853 * end up actually treating this as two 16-bit insns, though,
9854 * if it's half of a bl/blx pair that might span a page boundary.
9856 if (arm_dc_feature(s
, ARM_FEATURE_THUMB2
) ||
9857 arm_dc_feature(s
, ARM_FEATURE_M
)) {
9858 /* Thumb2 cores (including all M profile ones) always treat
9859 * 32-bit insns as 32-bit.
9864 if ((insn
>> 11) == 0x1e && pc
- s
->page_start
< TARGET_PAGE_SIZE
- 3) {
9865 /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
9866 * is not on the next page; we merge this into a 32-bit
9871 /* 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF);
9872 * 0b1111_1xxx_xxxx_xxxx : BL suffix;
9873 * 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix on the end of a page
9874 * -- handle as single 16 bit insn
9879 /* Translate a 32-bit thumb instruction. */
9880 static void disas_thumb2_insn(DisasContext
*s
, uint32_t insn
)
9883 * ARMv6-M supports a limited subset of Thumb2 instructions.
9884 * Other Thumb1 architectures allow only 32-bit
9885 * combined BL/BLX prefix and suffix.
9887 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
9888 !arm_dc_feature(s
, ARM_FEATURE_V7
)) {
9891 static const uint32_t armv6m_insn
[] = {0xf3808000 /* msr */,
9892 0xf3b08040 /* dsb */,
9893 0xf3b08050 /* dmb */,
9894 0xf3b08060 /* isb */,
9895 0xf3e08000 /* mrs */,
9896 0xf000d000 /* bl */};
9897 static const uint32_t armv6m_mask
[] = {0xffe0d000,
9904 for (i
= 0; i
< ARRAY_SIZE(armv6m_insn
); i
++) {
9905 if ((insn
& armv6m_mask
[i
]) == armv6m_insn
[i
]) {
9913 } else if ((insn
& 0xf800e800) != 0xf000e800) {
9917 if ((insn
& 0xef000000) == 0xef000000) {
9919 * T32 encodings 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
9921 * A32 encodings 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
9923 uint32_t a32_insn
= (insn
& 0xe2ffffff) |
9924 ((insn
& (1 << 28)) >> 4) | (1 << 28);
9926 if (disas_neon_dp(s
, a32_insn
)) {
9931 if ((insn
& 0xff100000) == 0xf9000000) {
9933 * T32 encodings 0b1111_1001_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
9935 * A32 encodings 0b1111_0100_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
9937 uint32_t a32_insn
= (insn
& 0x00ffffff) | 0xf4000000;
9939 if (disas_neon_ls(s
, a32_insn
)) {
9945 * TODO: Perhaps merge these into one decodetree output file.
9946 * Note disas_vfp is written for a32 with cond field in the
9947 * top nibble. The t32 encoding requires 0xe in the top nibble.
9949 if (disas_t32(s
, insn
) ||
9950 disas_vfp_uncond(s
, insn
) ||
9951 disas_neon_shared(s
, insn
) ||
9952 ((insn
>> 28) == 0xe && disas_vfp(s
, insn
))) {
9955 /* fall back to legacy decoder */
9957 switch ((insn
>> 25) & 0xf) {
9958 case 0: case 1: case 2: case 3:
9959 /* 16-bit instructions. Should never happen. */
9961 case 6: case 7: case 14: case 15:
9963 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
9964 /* 0b111x_11xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx */
9965 if (extract32(insn
, 24, 2) == 3) {
9966 goto illegal_op
; /* op0 = 0b11 : unallocated */
9969 if (((insn
>> 8) & 0xe) == 10 &&
9970 dc_isar_feature(aa32_fpsp_v2
, s
)) {
9971 /* FP, and the CPU supports it */
9974 /* All other insns: NOCP */
9975 gen_exception_insn(s
, s
->pc_curr
, EXCP_NOCP
,
9976 syn_uncategorized(),
9977 default_exception_el(s
));
9981 if (((insn
>> 24) & 3) == 3) {
9982 /* Translate into the equivalent ARM encoding. */
9983 insn
= (insn
& 0xe2ffffff) | ((insn
& (1 << 28)) >> 4) | (1 << 28);
9984 if (disas_neon_data_insn(s
, insn
)) {
9987 } else if (((insn
>> 8) & 0xe) == 10) {
9988 /* VFP, but failed disas_vfp. */
9991 if (insn
& (1 << 28))
9993 if (disas_coproc_insn(s
, insn
)) {
10002 unallocated_encoding(s
);
10006 static void disas_thumb_insn(DisasContext
*s
, uint32_t insn
)
10008 if (!disas_t16(s
, insn
)) {
10009 unallocated_encoding(s
);
10013 static bool insn_crosses_page(CPUARMState
*env
, DisasContext
*s
)
10015 /* Return true if the insn at dc->base.pc_next might cross a page boundary.
10016 * (False positives are OK, false negatives are not.)
10017 * We know this is a Thumb insn, and our caller ensures we are
10018 * only called if dc->base.pc_next is less than 4 bytes from the page
10019 * boundary, so we cross the page if the first 16 bits indicate
10020 * that this is a 32 bit insn.
10022 uint16_t insn
= arm_lduw_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
10024 return !thumb_insn_is_16bit(s
, s
->base
.pc_next
, insn
);
10027 static void arm_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
10029 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
10030 CPUARMState
*env
= cs
->env_ptr
;
10031 ARMCPU
*cpu
= env_archcpu(env
);
10032 uint32_t tb_flags
= dc
->base
.tb
->flags
;
10033 uint32_t condexec
, core_mmu_idx
;
10035 dc
->isar
= &cpu
->isar
;
10039 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
10040 * there is no secure EL1, so we route exceptions to EL3.
10042 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
10043 !arm_el_is_aa64(env
, 3);
10044 dc
->thumb
= FIELD_EX32(tb_flags
, TBFLAG_AM32
, THUMB
);
10045 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
10046 condexec
= FIELD_EX32(tb_flags
, TBFLAG_AM32
, CONDEXEC
);
10047 dc
->condexec_mask
= (condexec
& 0xf) << 1;
10048 dc
->condexec_cond
= condexec
>> 4;
10050 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
10051 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, core_mmu_idx
);
10052 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
10053 #if !defined(CONFIG_USER_ONLY)
10054 dc
->user
= (dc
->current_el
== 0);
10056 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
10058 if (arm_feature(env
, ARM_FEATURE_M
)) {
10059 dc
->vfp_enabled
= 1;
10060 dc
->be_data
= MO_TE
;
10061 dc
->v7m_handler_mode
= FIELD_EX32(tb_flags
, TBFLAG_M32
, HANDLER
);
10062 dc
->v8m_secure
= arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
10063 regime_is_secure(env
, dc
->mmu_idx
);
10064 dc
->v8m_stackcheck
= FIELD_EX32(tb_flags
, TBFLAG_M32
, STACKCHECK
);
10065 dc
->v8m_fpccr_s_wrong
=
10066 FIELD_EX32(tb_flags
, TBFLAG_M32
, FPCCR_S_WRONG
);
10067 dc
->v7m_new_fp_ctxt_needed
=
10068 FIELD_EX32(tb_flags
, TBFLAG_M32
, NEW_FP_CTXT_NEEDED
);
10069 dc
->v7m_lspact
= FIELD_EX32(tb_flags
, TBFLAG_M32
, LSPACT
);
10072 FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
10073 dc
->debug_target_el
=
10074 FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
10075 dc
->sctlr_b
= FIELD_EX32(tb_flags
, TBFLAG_A32
, SCTLR_B
);
10076 dc
->hstr_active
= FIELD_EX32(tb_flags
, TBFLAG_A32
, HSTR_ACTIVE
);
10077 dc
->ns
= FIELD_EX32(tb_flags
, TBFLAG_A32
, NS
);
10078 dc
->vfp_enabled
= FIELD_EX32(tb_flags
, TBFLAG_A32
, VFPEN
);
10079 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
10080 dc
->c15_cpar
= FIELD_EX32(tb_flags
, TBFLAG_A32
, XSCALE_CPAR
);
10082 dc
->vec_len
= FIELD_EX32(tb_flags
, TBFLAG_A32
, VECLEN
);
10083 dc
->vec_stride
= FIELD_EX32(tb_flags
, TBFLAG_A32
, VECSTRIDE
);
10086 dc
->cp_regs
= cpu
->cp_regs
;
10087 dc
->features
= env
->features
;
10089 /* Single step state. The code-generation logic here is:
10091 * generate code with no special handling for single-stepping (except
10092 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
10093 * this happens anyway because those changes are all system register or
10095 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
10096 * emit code for one insn
10097 * emit code to clear PSTATE.SS
10098 * emit code to generate software step exception for completed step
10099 * end TB (as usual for having generated an exception)
10100 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
10101 * emit code to generate a software step exception
10104 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
10105 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
10106 dc
->is_ldex
= false;
10108 dc
->page_start
= dc
->base
.pc_first
& TARGET_PAGE_MASK
;
10110 /* If architectural single step active, limit to 1. */
10111 if (is_singlestepping(dc
)) {
10112 dc
->base
.max_insns
= 1;
10115 /* ARM is a fixed-length ISA. Bound the number of insns to execute
10116 to those left on the page. */
10118 int bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
10119 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
10122 cpu_V0
= tcg_temp_new_i64();
10123 cpu_V1
= tcg_temp_new_i64();
10124 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
10125 cpu_M0
= tcg_temp_new_i64();
10128 static void arm_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
10130 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
10132 /* A note on handling of the condexec (IT) bits:
10134 * We want to avoid the overhead of having to write the updated condexec
10135 * bits back to the CPUARMState for every instruction in an IT block. So:
10136 * (1) if the condexec bits are not already zero then we write
10137 * zero back into the CPUARMState now. This avoids complications trying
10138 * to do it at the end of the block. (For example if we don't do this
10139 * it's hard to identify whether we can safely skip writing condexec
10140 * at the end of the TB, which we definitely want to do for the case
10141 * where a TB doesn't do anything with the IT state at all.)
10142 * (2) if we are going to leave the TB then we call gen_set_condexec()
10143 * which will write the correct value into CPUARMState if zero is wrong.
10144 * This is done both for leaving the TB at the end, and for leaving
10145 * it because of an exception we know will happen, which is done in
10146 * gen_exception_insn(). The latter is necessary because we need to
10147 * leave the TB with the PC/IT state just prior to execution of the
10148 * instruction which caused the exception.
10149 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
10150 * then the CPUARMState will be wrong and we need to reset it.
10151 * This is handled in the same way as restoration of the
10152 * PC in these situations; we save the value of the condexec bits
10153 * for each PC via tcg_gen_insn_start(), and restore_state_to_opc()
10154 * then uses this to restore them after an exception.
10156 * Note that there are no instructions which can read the condexec
10157 * bits, and none which can write non-static values to them, so
10158 * we don't need to care about whether CPUARMState is correct in the
10162 /* Reset the conditional execution bits immediately. This avoids
10163 complications trying to do it at the end of the block. */
10164 if (dc
->condexec_mask
|| dc
->condexec_cond
) {
10165 TCGv_i32 tmp
= tcg_temp_new_i32();
10166 tcg_gen_movi_i32(tmp
, 0);
10167 store_cpu_field(tmp
, condexec_bits
);
10171 static void arm_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
10173 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
10175 tcg_gen_insn_start(dc
->base
.pc_next
,
10176 (dc
->condexec_cond
<< 4) | (dc
->condexec_mask
>> 1),
10178 dc
->insn_start
= tcg_last_op();
10181 static bool arm_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
10182 const CPUBreakpoint
*bp
)
10184 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
10186 if (bp
->flags
& BP_CPU
) {
10187 gen_set_condexec(dc
);
10188 gen_set_pc_im(dc
, dc
->base
.pc_next
);
10189 gen_helper_check_breakpoints(cpu_env
);
10190 /* End the TB early; it's likely not going to be executed */
10191 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
10193 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
10194 /* The address covered by the breakpoint must be
10195 included in [tb->pc, tb->pc + tb->size) in order
10196 to for it to be properly cleared -- thus we
10197 increment the PC here so that the logic setting
10198 tb->size below does the right thing. */
10199 /* TODO: Advance PC by correct instruction length to
10200 * avoid disassembler error messages */
10201 dc
->base
.pc_next
+= 2;
10202 dc
->base
.is_jmp
= DISAS_NORETURN
;
10208 static bool arm_pre_translate_insn(DisasContext
*dc
)
10210 #ifdef CONFIG_USER_ONLY
10211 /* Intercept jump to the magic kernel page. */
10212 if (dc
->base
.pc_next
>= 0xffff0000) {
10213 /* We always get here via a jump, so know we are not in a
10214 conditional execution block. */
10215 gen_exception_internal(EXCP_KERNEL_TRAP
);
10216 dc
->base
.is_jmp
= DISAS_NORETURN
;
10221 if (dc
->ss_active
&& !dc
->pstate_ss
) {
10222 /* Singlestep state is Active-pending.
10223 * If we're in this state at the start of a TB then either
10224 * a) we just took an exception to an EL which is being debugged
10225 * and this is the first insn in the exception handler
10226 * b) debug exceptions were masked and we just unmasked them
10227 * without changing EL (eg by clearing PSTATE.D)
10228 * In either case we're going to take a swstep exception in the
10229 * "did not step an insn" case, and so the syndrome ISV and EX
10230 * bits should be zero.
10232 assert(dc
->base
.num_insns
== 1);
10233 gen_swstep_exception(dc
, 0, 0);
10234 dc
->base
.is_jmp
= DISAS_NORETURN
;
10241 static void arm_post_translate_insn(DisasContext
*dc
)
10243 if (dc
->condjmp
&& !dc
->base
.is_jmp
) {
10244 gen_set_label(dc
->condlabel
);
10247 translator_loop_temp_check(&dc
->base
);
10250 static void arm_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
10252 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
10253 CPUARMState
*env
= cpu
->env_ptr
;
10256 if (arm_pre_translate_insn(dc
)) {
10260 dc
->pc_curr
= dc
->base
.pc_next
;
10261 insn
= arm_ldl_code(env
, dc
->base
.pc_next
, dc
->sctlr_b
);
10263 dc
->base
.pc_next
+= 4;
10264 disas_arm_insn(dc
, insn
);
10266 arm_post_translate_insn(dc
);
10268 /* ARM is a fixed-length ISA. We performed the cross-page check
10269 in init_disas_context by adjusting max_insns. */
10272 static bool thumb_insn_is_unconditional(DisasContext
*s
, uint32_t insn
)
10274 /* Return true if this Thumb insn is always unconditional,
10275 * even inside an IT block. This is true of only a very few
10276 * instructions: BKPT, HLT, and SG.
10278 * A larger class of instructions are UNPREDICTABLE if used
10279 * inside an IT block; we do not need to detect those here, because
10280 * what we do by default (perform the cc check and update the IT
10281 * bits state machine) is a permitted CONSTRAINED UNPREDICTABLE
10282 * choice for those situations.
10284 * insn is either a 16-bit or a 32-bit instruction; the two are
10285 * distinguishable because for the 16-bit case the top 16 bits
10286 * are zeroes, and that isn't a valid 32-bit encoding.
10288 if ((insn
& 0xffffff00) == 0xbe00) {
10293 if ((insn
& 0xffffffc0) == 0xba80 && arm_dc_feature(s
, ARM_FEATURE_V8
) &&
10294 !arm_dc_feature(s
, ARM_FEATURE_M
)) {
10295 /* HLT: v8A only. This is unconditional even when it is going to
10296 * UNDEF; see the v8A ARM ARM DDI0487B.a H3.3.
10297 * For v7 cores this was a plain old undefined encoding and so
10298 * honours its cc check. (We might be using the encoding as
10299 * a semihosting trap, but we don't change the cc check behaviour
10300 * on that account, because a debugger connected to a real v7A
10301 * core and emulating semihosting traps by catching the UNDEF
10302 * exception would also only see cases where the cc check passed.
10303 * No guest code should be trying to do a HLT semihosting trap
10304 * in an IT block anyway.
10309 if (insn
== 0xe97fe97f && arm_dc_feature(s
, ARM_FEATURE_V8
) &&
10310 arm_dc_feature(s
, ARM_FEATURE_M
)) {
10318 static void thumb_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
10320 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
10321 CPUARMState
*env
= cpu
->env_ptr
;
10325 if (arm_pre_translate_insn(dc
)) {
10329 dc
->pc_curr
= dc
->base
.pc_next
;
10330 insn
= arm_lduw_code(env
, dc
->base
.pc_next
, dc
->sctlr_b
);
10331 is_16bit
= thumb_insn_is_16bit(dc
, dc
->base
.pc_next
, insn
);
10332 dc
->base
.pc_next
+= 2;
10334 uint32_t insn2
= arm_lduw_code(env
, dc
->base
.pc_next
, dc
->sctlr_b
);
10336 insn
= insn
<< 16 | insn2
;
10337 dc
->base
.pc_next
+= 2;
10341 if (dc
->condexec_mask
&& !thumb_insn_is_unconditional(dc
, insn
)) {
10342 uint32_t cond
= dc
->condexec_cond
;
10345 * Conditionally skip the insn. Note that both 0xe and 0xf mean
10346 * "always"; 0xf is not "never".
10349 arm_skip_unless(dc
, cond
);
10354 disas_thumb_insn(dc
, insn
);
10356 disas_thumb2_insn(dc
, insn
);
10359 /* Advance the Thumb condexec condition. */
10360 if (dc
->condexec_mask
) {
10361 dc
->condexec_cond
= ((dc
->condexec_cond
& 0xe) |
10362 ((dc
->condexec_mask
>> 4) & 1));
10363 dc
->condexec_mask
= (dc
->condexec_mask
<< 1) & 0x1f;
10364 if (dc
->condexec_mask
== 0) {
10365 dc
->condexec_cond
= 0;
10369 arm_post_translate_insn(dc
);
10371 /* Thumb is a variable-length ISA. Stop translation when the next insn
10372 * will touch a new page. This ensures that prefetch aborts occur at
10375 * We want to stop the TB if the next insn starts in a new page,
10376 * or if it spans between this page and the next. This means that
10377 * if we're looking at the last halfword in the page we need to
10378 * see if it's a 16-bit Thumb insn (which will fit in this TB)
10379 * or a 32-bit Thumb insn (which won't).
10380 * This is to avoid generating a silly TB with a single 16-bit insn
10381 * in it at the end of this page (which would execute correctly
10382 * but isn't very efficient).
10384 if (dc
->base
.is_jmp
== DISAS_NEXT
10385 && (dc
->base
.pc_next
- dc
->page_start
>= TARGET_PAGE_SIZE
10386 || (dc
->base
.pc_next
- dc
->page_start
>= TARGET_PAGE_SIZE
- 3
10387 && insn_crosses_page(env
, dc
)))) {
10388 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
10392 static void arm_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
10394 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
10396 if (tb_cflags(dc
->base
.tb
) & CF_LAST_IO
&& dc
->condjmp
) {
10397 /* FIXME: This can theoretically happen with self-modifying code. */
10398 cpu_abort(cpu
, "IO on conditional branch instruction");
10401 /* At this stage dc->condjmp will only be set when the skipped
10402 instruction was a conditional branch or trap, and the PC has
10403 already been written. */
10404 gen_set_condexec(dc
);
10405 if (dc
->base
.is_jmp
== DISAS_BX_EXCRET
) {
10406 /* Exception return branches need some special case code at the
10407 * end of the TB, which is complex enough that it has to
10408 * handle the single-step vs not and the condition-failed
10409 * insn codepath itself.
10411 gen_bx_excret_final_code(dc
);
10412 } else if (unlikely(is_singlestepping(dc
))) {
10413 /* Unconditional and "condition passed" instruction codepath. */
10414 switch (dc
->base
.is_jmp
) {
10416 gen_ss_advance(dc
);
10417 gen_exception(EXCP_SWI
, syn_aa32_svc(dc
->svc_imm
, dc
->thumb
),
10418 default_exception_el(dc
));
10421 gen_ss_advance(dc
);
10422 gen_exception(EXCP_HVC
, syn_aa32_hvc(dc
->svc_imm
), 2);
10425 gen_ss_advance(dc
);
10426 gen_exception(EXCP_SMC
, syn_aa32_smc(), 3);
10429 case DISAS_TOO_MANY
:
10431 gen_set_pc_im(dc
, dc
->base
.pc_next
);
10434 /* FIXME: Single stepping a WFI insn will not halt the CPU. */
10435 gen_singlestep_exception(dc
);
10437 case DISAS_NORETURN
:
10441 /* While branches must always occur at the end of an IT block,
10442 there are a few other things that can cause us to terminate
10443 the TB in the middle of an IT block:
10444 - Exception generating instructions (bkpt, swi, undefined).
10446 - Hardware watchpoints.
10447 Hardware breakpoints have already been handled and skip this code.
10449 switch(dc
->base
.is_jmp
) {
10451 case DISAS_TOO_MANY
:
10452 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
10458 gen_set_pc_im(dc
, dc
->base
.pc_next
);
10461 /* indicate that the hash table must be used to find the next TB */
10462 tcg_gen_exit_tb(NULL
, 0);
10464 case DISAS_NORETURN
:
10465 /* nothing more to generate */
10469 TCGv_i32 tmp
= tcg_const_i32((dc
->thumb
&&
10470 !(dc
->insn
& (1U << 31))) ? 2 : 4);
10472 gen_helper_wfi(cpu_env
, tmp
);
10473 tcg_temp_free_i32(tmp
);
10474 /* The helper doesn't necessarily throw an exception, but we
10475 * must go back to the main loop to check for interrupts anyway.
10477 tcg_gen_exit_tb(NULL
, 0);
10481 gen_helper_wfe(cpu_env
);
10484 gen_helper_yield(cpu_env
);
10487 gen_exception(EXCP_SWI
, syn_aa32_svc(dc
->svc_imm
, dc
->thumb
),
10488 default_exception_el(dc
));
10491 gen_exception(EXCP_HVC
, syn_aa32_hvc(dc
->svc_imm
), 2);
10494 gen_exception(EXCP_SMC
, syn_aa32_smc(), 3);
10500 /* "Condition failed" instruction codepath for the branch/trap insn */
10501 gen_set_label(dc
->condlabel
);
10502 gen_set_condexec(dc
);
10503 if (unlikely(is_singlestepping(dc
))) {
10504 gen_set_pc_im(dc
, dc
->base
.pc_next
);
10505 gen_singlestep_exception(dc
);
10507 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
10512 static void arm_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cpu
)
10514 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
10516 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
10517 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
10520 static const TranslatorOps arm_translator_ops
= {
10521 .init_disas_context
= arm_tr_init_disas_context
,
10522 .tb_start
= arm_tr_tb_start
,
10523 .insn_start
= arm_tr_insn_start
,
10524 .breakpoint_check
= arm_tr_breakpoint_check
,
10525 .translate_insn
= arm_tr_translate_insn
,
10526 .tb_stop
= arm_tr_tb_stop
,
10527 .disas_log
= arm_tr_disas_log
,
10530 static const TranslatorOps thumb_translator_ops
= {
10531 .init_disas_context
= arm_tr_init_disas_context
,
10532 .tb_start
= arm_tr_tb_start
,
10533 .insn_start
= arm_tr_insn_start
,
10534 .breakpoint_check
= arm_tr_breakpoint_check
,
10535 .translate_insn
= thumb_tr_translate_insn
,
10536 .tb_stop
= arm_tr_tb_stop
,
10537 .disas_log
= arm_tr_disas_log
,
10540 /* generate intermediate code for basic block 'tb'. */
10541 void gen_intermediate_code(CPUState
*cpu
, TranslationBlock
*tb
, int max_insns
)
10543 DisasContext dc
= { };
10544 const TranslatorOps
*ops
= &arm_translator_ops
;
10546 if (FIELD_EX32(tb
->flags
, TBFLAG_AM32
, THUMB
)) {
10547 ops
= &thumb_translator_ops
;
10549 #ifdef TARGET_AARCH64
10550 if (FIELD_EX32(tb
->flags
, TBFLAG_ANY
, AARCH64_STATE
)) {
10551 ops
= &aarch64_translator_ops
;
10555 translator_loop(ops
, &dc
.base
, cpu
, tb
, max_insns
);
10558 void restore_state_to_opc(CPUARMState
*env
, TranslationBlock
*tb
,
10559 target_ulong
*data
)
10563 env
->condexec_bits
= 0;
10564 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
10566 env
->regs
[15] = data
[0];
10567 env
->condexec_bits
= data
[1];
10568 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;