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cirrus: fix patterncopy checks
[qemu/ar7.git] / hw / display / cirrus_vga.c
blob1bcf9a481fcae242af8cd27cfdce5ad400f76221
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "trace.h"
32 #include "hw/hw.h"
33 #include "hw/pci/pci.h"
34 #include "ui/console.h"
35 #include "ui/pixel_ops.h"
36 #include "vga_int.h"
37 #include "hw/loader.h"
38
39 /*
40 * TODO:
41 * - destination write mask support not complete (bits 5..7)
42 * - optimize linear mappings
43 * - optimize bitblt functions
44 */
45
46 //#define DEBUG_CIRRUS
47 //#define DEBUG_BITBLT
48
49 /***************************************
50 *
51 * definitions
52 *
53 ***************************************/
54
55 // ID
56 #define CIRRUS_ID_CLGD5422 (0x23<<2)
57 #define CIRRUS_ID_CLGD5426 (0x24<<2)
58 #define CIRRUS_ID_CLGD5424 (0x25<<2)
59 #define CIRRUS_ID_CLGD5428 (0x26<<2)
60 #define CIRRUS_ID_CLGD5430 (0x28<<2)
61 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
62 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
63 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
64
65 // sequencer 0x07
66 #define CIRRUS_SR7_BPP_VGA 0x00
67 #define CIRRUS_SR7_BPP_SVGA 0x01
68 #define CIRRUS_SR7_BPP_MASK 0x0e
69 #define CIRRUS_SR7_BPP_8 0x00
70 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
71 #define CIRRUS_SR7_BPP_24 0x04
72 #define CIRRUS_SR7_BPP_16 0x06
73 #define CIRRUS_SR7_BPP_32 0x08
74 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
75
76 // sequencer 0x0f
77 #define CIRRUS_MEMSIZE_512k 0x08
78 #define CIRRUS_MEMSIZE_1M 0x10
79 #define CIRRUS_MEMSIZE_2M 0x18
80 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
81
82 // sequencer 0x12
83 #define CIRRUS_CURSOR_SHOW 0x01
84 #define CIRRUS_CURSOR_HIDDENPEL 0x02
85 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
86
87 // sequencer 0x17
88 #define CIRRUS_BUSTYPE_VLBFAST 0x10
89 #define CIRRUS_BUSTYPE_PCI 0x20
90 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
91 #define CIRRUS_BUSTYPE_ISA 0x38
92 #define CIRRUS_MMIO_ENABLE 0x04
93 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
94 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
95
96 // control 0x0b
97 #define CIRRUS_BANKING_DUAL 0x01
98 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
99
100 // control 0x30
101 #define CIRRUS_BLTMODE_BACKWARDS 0x01
102 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
103 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
104 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
105 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
106 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
107 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
108 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
109 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
110 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
111 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
112
113 // control 0x31
114 #define CIRRUS_BLT_BUSY 0x01
115 #define CIRRUS_BLT_START 0x02
116 #define CIRRUS_BLT_RESET 0x04
117 #define CIRRUS_BLT_FIFOUSED 0x10
118 #define CIRRUS_BLT_AUTOSTART 0x80
119
120 // control 0x32
121 #define CIRRUS_ROP_0 0x00
122 #define CIRRUS_ROP_SRC_AND_DST 0x05
123 #define CIRRUS_ROP_NOP 0x06
124 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
125 #define CIRRUS_ROP_NOTDST 0x0b
126 #define CIRRUS_ROP_SRC 0x0d
127 #define CIRRUS_ROP_1 0x0e
128 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
129 #define CIRRUS_ROP_SRC_XOR_DST 0x59
130 #define CIRRUS_ROP_SRC_OR_DST 0x6d
131 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
132 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
133 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
134 #define CIRRUS_ROP_NOTSRC 0xd0
135 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
136 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
137
138 #define CIRRUS_ROP_NOP_INDEX 2
139 #define CIRRUS_ROP_SRC_INDEX 5
140
141 // control 0x33
142 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
143 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
144 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
145
146 // memory-mapped IO
147 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
148 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
149 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
150 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
151 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
152 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
153 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
154 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
155 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
156 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
157 #define CIRRUS_MMIO_BLTROP 0x1a // byte
158 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
161 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
162 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
164 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
169 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
170 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
171 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
172 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
173 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
174 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
175 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
176
177 #define CIRRUS_PNPMMIO_SIZE 0x1000
178
179 struct CirrusVGAState;
180 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
181 uint8_t * dst, const uint8_t * src,
182 int dstpitch, int srcpitch,
183 int bltwidth, int bltheight);
184 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
185 uint8_t *dst, int dst_pitch, int width, int height);
186
187 typedef struct CirrusVGAState {
188 VGACommonState vga;
189
190 MemoryRegion cirrus_vga_io;
191 MemoryRegion cirrus_linear_io;
192 MemoryRegion cirrus_linear_bitblt_io;
193 MemoryRegion cirrus_mmio_io;
194 MemoryRegion pci_bar;
195 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
196 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
197 MemoryRegion low_mem; /* always mapped, overridden by: */
198 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
199 uint32_t cirrus_addr_mask;
200 uint32_t linear_mmio_mask;
201 uint8_t cirrus_shadow_gr0;
202 uint8_t cirrus_shadow_gr1;
203 uint8_t cirrus_hidden_dac_lockindex;
204 uint8_t cirrus_hidden_dac_data;
205 uint32_t cirrus_bank_base[2];
206 uint32_t cirrus_bank_limit[2];
207 uint8_t cirrus_hidden_palette[48];
208 int cirrus_blt_pixelwidth;
209 int cirrus_blt_width;
210 int cirrus_blt_height;
211 int cirrus_blt_dstpitch;
212 int cirrus_blt_srcpitch;
213 uint32_t cirrus_blt_fgcol;
214 uint32_t cirrus_blt_bgcol;
215 uint32_t cirrus_blt_dstaddr;
216 uint32_t cirrus_blt_srcaddr;
217 uint8_t cirrus_blt_mode;
218 uint8_t cirrus_blt_modeext;
219 cirrus_bitblt_rop_t cirrus_rop;
220 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
221 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
222 uint8_t *cirrus_srcptr;
223 uint8_t *cirrus_srcptr_end;
224 uint32_t cirrus_srccounter;
225 /* hwcursor display state */
226 int last_hw_cursor_size;
227 int last_hw_cursor_x;
228 int last_hw_cursor_y;
229 int last_hw_cursor_y_start;
230 int last_hw_cursor_y_end;
231 int real_vram_size; /* XXX: suppress that */
232 int device_id;
233 int bustype;
234 } CirrusVGAState;
235
236 typedef struct PCICirrusVGAState {
237 PCIDevice dev;
238 CirrusVGAState cirrus_vga;
239 } PCICirrusVGAState;
240
241 #define TYPE_PCI_CIRRUS_VGA "cirrus-vga"
242 #define PCI_CIRRUS_VGA(obj) \
243 OBJECT_CHECK(PCICirrusVGAState, (obj), TYPE_PCI_CIRRUS_VGA)
244
245 #define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga"
246 #define ISA_CIRRUS_VGA(obj) \
247 OBJECT_CHECK(ISACirrusVGAState, (obj), TYPE_ISA_CIRRUS_VGA)
248
249 typedef struct ISACirrusVGAState {
250 ISADevice parent_obj;
251
252 CirrusVGAState cirrus_vga;
253 } ISACirrusVGAState;
254
255 static uint8_t rop_to_index[256];
256
257 /***************************************
258 *
259 * prototypes.
260 *
261 ***************************************/
262
263
264 static void cirrus_bitblt_reset(CirrusVGAState *s);
265 static void cirrus_update_memory_access(CirrusVGAState *s);
266
267 /***************************************
268 *
269 * raster operations
270 *
271 ***************************************/
272
273 static bool blit_region_is_unsafe(struct CirrusVGAState *s,
274 int32_t pitch, int32_t addr)
275 {
276 if (pitch < 0) {
277 int64_t min = addr
278 + ((int64_t)s->cirrus_blt_height - 1) * pitch
279 - s->cirrus_blt_width;
280 if (min < -1 || addr >= s->vga.vram_size) {
281 return true;
282 }
283 } else {
284 int64_t max = addr
285 + ((int64_t)s->cirrus_blt_height-1) * pitch
286 + s->cirrus_blt_width;
287 if (max > s->vga.vram_size) {
288 return true;
289 }
290 }
291 return false;
292 }
293
294 static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only,
295 bool zero_src_pitch_ok)
296 {
297 int32_t check_pitch;
298
299 /* should be the case, see cirrus_bitblt_start */
300 assert(s->cirrus_blt_width > 0);
301 assert(s->cirrus_blt_height > 0);
302
303 if (s->cirrus_blt_width > CIRRUS_BLTBUFSIZE) {
304 return true;
305 }
306
307 if (!s->cirrus_blt_dstpitch) {
308 return true;
309 }
310
311 if (blit_region_is_unsafe(s, s->cirrus_blt_dstpitch,
312 s->cirrus_blt_dstaddr)) {
313 return true;
314 }
315 if (dst_only) {
316 return false;
317 }
318
319 check_pitch = s->cirrus_blt_srcpitch;
320 if (!zero_src_pitch_ok && !check_pitch) {
321 check_pitch = s->cirrus_blt_width;
322 }
323
324 if (blit_region_is_unsafe(s, check_pitch,
325 s->cirrus_blt_srcaddr)) {
326 return true;
327 }
328
329 return false;
330 }
331
332 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
333 uint8_t *dst,const uint8_t *src,
334 int dstpitch,int srcpitch,
335 int bltwidth,int bltheight)
336 {
337 }
338
339 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
340 uint8_t *dst,
341 int dstpitch, int bltwidth,int bltheight)
342 {
343 }
344
345 #define ROP_NAME 0
346 #define ROP_FN(d, s) 0
347 #include "cirrus_vga_rop.h"
348
349 #define ROP_NAME src_and_dst
350 #define ROP_FN(d, s) (s) & (d)
351 #include "cirrus_vga_rop.h"
352
353 #define ROP_NAME src_and_notdst
354 #define ROP_FN(d, s) (s) & (~(d))
355 #include "cirrus_vga_rop.h"
356
357 #define ROP_NAME notdst
358 #define ROP_FN(d, s) ~(d)
359 #include "cirrus_vga_rop.h"
360
361 #define ROP_NAME src
362 #define ROP_FN(d, s) s
363 #include "cirrus_vga_rop.h"
364
365 #define ROP_NAME 1
366 #define ROP_FN(d, s) ~0
367 #include "cirrus_vga_rop.h"
368
369 #define ROP_NAME notsrc_and_dst
370 #define ROP_FN(d, s) (~(s)) & (d)
371 #include "cirrus_vga_rop.h"
372
373 #define ROP_NAME src_xor_dst
374 #define ROP_FN(d, s) (s) ^ (d)
375 #include "cirrus_vga_rop.h"
376
377 #define ROP_NAME src_or_dst
378 #define ROP_FN(d, s) (s) | (d)
379 #include "cirrus_vga_rop.h"
380
381 #define ROP_NAME notsrc_or_notdst
382 #define ROP_FN(d, s) (~(s)) | (~(d))
383 #include "cirrus_vga_rop.h"
384
385 #define ROP_NAME src_notxor_dst
386 #define ROP_FN(d, s) ~((s) ^ (d))
387 #include "cirrus_vga_rop.h"
388
389 #define ROP_NAME src_or_notdst
390 #define ROP_FN(d, s) (s) | (~(d))
391 #include "cirrus_vga_rop.h"
392
393 #define ROP_NAME notsrc
394 #define ROP_FN(d, s) (~(s))
395 #include "cirrus_vga_rop.h"
396
397 #define ROP_NAME notsrc_or_dst
398 #define ROP_FN(d, s) (~(s)) | (d)
399 #include "cirrus_vga_rop.h"
400
401 #define ROP_NAME notsrc_and_notdst
402 #define ROP_FN(d, s) (~(s)) & (~(d))
403 #include "cirrus_vga_rop.h"
404
405 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
406 cirrus_bitblt_rop_fwd_0,
407 cirrus_bitblt_rop_fwd_src_and_dst,
408 cirrus_bitblt_rop_nop,
409 cirrus_bitblt_rop_fwd_src_and_notdst,
410 cirrus_bitblt_rop_fwd_notdst,
411 cirrus_bitblt_rop_fwd_src,
412 cirrus_bitblt_rop_fwd_1,
413 cirrus_bitblt_rop_fwd_notsrc_and_dst,
414 cirrus_bitblt_rop_fwd_src_xor_dst,
415 cirrus_bitblt_rop_fwd_src_or_dst,
416 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
417 cirrus_bitblt_rop_fwd_src_notxor_dst,
418 cirrus_bitblt_rop_fwd_src_or_notdst,
419 cirrus_bitblt_rop_fwd_notsrc,
420 cirrus_bitblt_rop_fwd_notsrc_or_dst,
421 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
422 };
423
424 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
425 cirrus_bitblt_rop_bkwd_0,
426 cirrus_bitblt_rop_bkwd_src_and_dst,
427 cirrus_bitblt_rop_nop,
428 cirrus_bitblt_rop_bkwd_src_and_notdst,
429 cirrus_bitblt_rop_bkwd_notdst,
430 cirrus_bitblt_rop_bkwd_src,
431 cirrus_bitblt_rop_bkwd_1,
432 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
433 cirrus_bitblt_rop_bkwd_src_xor_dst,
434 cirrus_bitblt_rop_bkwd_src_or_dst,
435 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
436 cirrus_bitblt_rop_bkwd_src_notxor_dst,
437 cirrus_bitblt_rop_bkwd_src_or_notdst,
438 cirrus_bitblt_rop_bkwd_notsrc,
439 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
440 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
441 };
442
443 #define TRANSP_ROP(name) {\
444 name ## _8,\
445 name ## _16,\
446 }
447 #define TRANSP_NOP(func) {\
448 func,\
449 func,\
450 }
451
452 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
454 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
455 TRANSP_NOP(cirrus_bitblt_rop_nop),
456 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
457 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
458 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
459 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
460 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
461 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
462 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
463 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
464 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
465 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
466 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
467 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
468 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
469 };
470
471 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
473 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
474 TRANSP_NOP(cirrus_bitblt_rop_nop),
475 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
476 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
477 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
478 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
479 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
480 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
481 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
482 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
483 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
484 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
485 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
486 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
487 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
488 };
489
490 #define ROP2(name) {\
491 name ## _8,\
492 name ## _16,\
493 name ## _24,\
494 name ## _32,\
495 }
496
497 #define ROP_NOP2(func) {\
498 func,\
499 func,\
500 func,\
501 func,\
502 }
503
504 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
505 ROP2(cirrus_patternfill_0),
506 ROP2(cirrus_patternfill_src_and_dst),
507 ROP_NOP2(cirrus_bitblt_rop_nop),
508 ROP2(cirrus_patternfill_src_and_notdst),
509 ROP2(cirrus_patternfill_notdst),
510 ROP2(cirrus_patternfill_src),
511 ROP2(cirrus_patternfill_1),
512 ROP2(cirrus_patternfill_notsrc_and_dst),
513 ROP2(cirrus_patternfill_src_xor_dst),
514 ROP2(cirrus_patternfill_src_or_dst),
515 ROP2(cirrus_patternfill_notsrc_or_notdst),
516 ROP2(cirrus_patternfill_src_notxor_dst),
517 ROP2(cirrus_patternfill_src_or_notdst),
518 ROP2(cirrus_patternfill_notsrc),
519 ROP2(cirrus_patternfill_notsrc_or_dst),
520 ROP2(cirrus_patternfill_notsrc_and_notdst),
521 };
522
523 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
524 ROP2(cirrus_colorexpand_transp_0),
525 ROP2(cirrus_colorexpand_transp_src_and_dst),
526 ROP_NOP2(cirrus_bitblt_rop_nop),
527 ROP2(cirrus_colorexpand_transp_src_and_notdst),
528 ROP2(cirrus_colorexpand_transp_notdst),
529 ROP2(cirrus_colorexpand_transp_src),
530 ROP2(cirrus_colorexpand_transp_1),
531 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
532 ROP2(cirrus_colorexpand_transp_src_xor_dst),
533 ROP2(cirrus_colorexpand_transp_src_or_dst),
534 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
535 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
536 ROP2(cirrus_colorexpand_transp_src_or_notdst),
537 ROP2(cirrus_colorexpand_transp_notsrc),
538 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
539 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
540 };
541
542 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
543 ROP2(cirrus_colorexpand_0),
544 ROP2(cirrus_colorexpand_src_and_dst),
545 ROP_NOP2(cirrus_bitblt_rop_nop),
546 ROP2(cirrus_colorexpand_src_and_notdst),
547 ROP2(cirrus_colorexpand_notdst),
548 ROP2(cirrus_colorexpand_src),
549 ROP2(cirrus_colorexpand_1),
550 ROP2(cirrus_colorexpand_notsrc_and_dst),
551 ROP2(cirrus_colorexpand_src_xor_dst),
552 ROP2(cirrus_colorexpand_src_or_dst),
553 ROP2(cirrus_colorexpand_notsrc_or_notdst),
554 ROP2(cirrus_colorexpand_src_notxor_dst),
555 ROP2(cirrus_colorexpand_src_or_notdst),
556 ROP2(cirrus_colorexpand_notsrc),
557 ROP2(cirrus_colorexpand_notsrc_or_dst),
558 ROP2(cirrus_colorexpand_notsrc_and_notdst),
559 };
560
561 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
562 ROP2(cirrus_colorexpand_pattern_transp_0),
563 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
564 ROP_NOP2(cirrus_bitblt_rop_nop),
565 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
566 ROP2(cirrus_colorexpand_pattern_transp_notdst),
567 ROP2(cirrus_colorexpand_pattern_transp_src),
568 ROP2(cirrus_colorexpand_pattern_transp_1),
569 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
570 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
571 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
572 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
573 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
574 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
575 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
576 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
577 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
578 };
579
580 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
581 ROP2(cirrus_colorexpand_pattern_0),
582 ROP2(cirrus_colorexpand_pattern_src_and_dst),
583 ROP_NOP2(cirrus_bitblt_rop_nop),
584 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
585 ROP2(cirrus_colorexpand_pattern_notdst),
586 ROP2(cirrus_colorexpand_pattern_src),
587 ROP2(cirrus_colorexpand_pattern_1),
588 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
589 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
590 ROP2(cirrus_colorexpand_pattern_src_or_dst),
591 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
592 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
593 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
594 ROP2(cirrus_colorexpand_pattern_notsrc),
595 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
596 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
597 };
598
599 static const cirrus_fill_t cirrus_fill[16][4] = {
600 ROP2(cirrus_fill_0),
601 ROP2(cirrus_fill_src_and_dst),
602 ROP_NOP2(cirrus_bitblt_fill_nop),
603 ROP2(cirrus_fill_src_and_notdst),
604 ROP2(cirrus_fill_notdst),
605 ROP2(cirrus_fill_src),
606 ROP2(cirrus_fill_1),
607 ROP2(cirrus_fill_notsrc_and_dst),
608 ROP2(cirrus_fill_src_xor_dst),
609 ROP2(cirrus_fill_src_or_dst),
610 ROP2(cirrus_fill_notsrc_or_notdst),
611 ROP2(cirrus_fill_src_notxor_dst),
612 ROP2(cirrus_fill_src_or_notdst),
613 ROP2(cirrus_fill_notsrc),
614 ROP2(cirrus_fill_notsrc_or_dst),
615 ROP2(cirrus_fill_notsrc_and_notdst),
616 };
617
618 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
619 {
620 unsigned int color;
621 switch (s->cirrus_blt_pixelwidth) {
622 case 1:
623 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
624 break;
625 case 2:
626 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
627 s->cirrus_blt_fgcol = le16_to_cpu(color);
628 break;
629 case 3:
630 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
631 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
632 break;
633 default:
634 case 4:
635 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
636 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
637 s->cirrus_blt_fgcol = le32_to_cpu(color);
638 break;
639 }
640 }
641
642 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
643 {
644 unsigned int color;
645 switch (s->cirrus_blt_pixelwidth) {
646 case 1:
647 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
648 break;
649 case 2:
650 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
651 s->cirrus_blt_bgcol = le16_to_cpu(color);
652 break;
653 case 3:
654 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
655 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
656 break;
657 default:
658 case 4:
659 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
660 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
661 s->cirrus_blt_bgcol = le32_to_cpu(color);
662 break;
663 }
664 }
665
666 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
667 int off_pitch, int bytesperline,
668 int lines)
669 {
670 int y;
671 int off_cur;
672 int off_cur_end;
673
674 if (off_pitch < 0) {
675 off_begin -= bytesperline - 1;
676 }
677
678 for (y = 0; y < lines; y++) {
679 off_cur = off_begin;
680 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
681 assert(off_cur_end >= off_cur);
682 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
683 off_begin += off_pitch;
684 }
685 }
686
687 static int cirrus_bitblt_common_patterncopy(CirrusVGAState *s, bool videosrc)
688 {
689 uint32_t patternsize;
690 uint8_t *dst;
691 uint8_t *src;
692
693 dst = s->vga.vram_ptr + s->cirrus_blt_dstaddr;
694
695 if (videosrc) {
696 switch (s->vga.get_bpp(&s->vga)) {
697 case 8:
698 patternsize = 64;
699 break;
700 case 15:
701 case 16:
702 patternsize = 128;
703 break;
704 case 24:
705 case 32:
706 default:
707 patternsize = 256;
708 break;
709 }
710 s->cirrus_blt_srcaddr &= ~(patternsize - 1);
711 if (s->cirrus_blt_srcaddr + patternsize > s->vga.vram_size) {
712 return 0;
713 }
714 src = s->vga.vram_ptr + s->cirrus_blt_srcaddr;
715 } else {
716 src = s->cirrus_bltbuf;
717 }
718
719 if (blit_is_unsafe(s, true, true)) {
720 return 0;
721 }
722
723 (*s->cirrus_rop) (s, dst, src,
724 s->cirrus_blt_dstpitch, 0,
725 s->cirrus_blt_width, s->cirrus_blt_height);
726 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
727 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
728 s->cirrus_blt_height);
729 return 1;
730 }
731
732 /* fill */
733
734 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
735 {
736 cirrus_fill_t rop_func;
737
738 if (blit_is_unsafe(s, true, true)) {
739 return 0;
740 }
741 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
742 rop_func(s, s->vga.vram_ptr + s->cirrus_blt_dstaddr,
743 s->cirrus_blt_dstpitch,
744 s->cirrus_blt_width, s->cirrus_blt_height);
745 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
746 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
747 s->cirrus_blt_height);
748 cirrus_bitblt_reset(s);
749 return 1;
750 }
751
752 /***************************************
753 *
754 * bitblt (video-to-video)
755 *
756 ***************************************/
757
758 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
759 {
760 return cirrus_bitblt_common_patterncopy(s, true);
761 }
762
763 static int cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
764 {
765 int sx = 0, sy = 0;
766 int dx = 0, dy = 0;
767 int depth = 0;
768 int notify = 0;
769
770 /* make sure to only copy if it's a plain copy ROP */
771 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
772 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
773
774 int width, height;
775
776 depth = s->vga.get_bpp(&s->vga) / 8;
777 if (!depth) {
778 return 0;
779 }
780 s->vga.get_resolution(&s->vga, &width, &height);
781
782 /* extra x, y */
783 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
784 sy = (src / ABS(s->cirrus_blt_srcpitch));
785 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
786 dy = (dst / ABS(s->cirrus_blt_dstpitch));
787
788 /* normalize width */
789 w /= depth;
790
791 /* if we're doing a backward copy, we have to adjust
792 our x/y to be the upper left corner (instead of the lower
793 right corner) */
794 if (s->cirrus_blt_dstpitch < 0) {
795 sx -= (s->cirrus_blt_width / depth) - 1;
796 dx -= (s->cirrus_blt_width / depth) - 1;
797 sy -= s->cirrus_blt_height - 1;
798 dy -= s->cirrus_blt_height - 1;
799 }
800
801 /* are we in the visible portion of memory? */
802 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
803 (sx + w) <= width && (sy + h) <= height &&
804 (dx + w) <= width && (dy + h) <= height) {
805 notify = 1;
806 }
807 }
808
809 /* we have to flush all pending changes so that the copy
810 is generated at the appropriate moment in time */
811 if (notify)
812 graphic_hw_update(s->vga.con);
813
814 (*s->cirrus_rop) (s, s->vga.vram_ptr + s->cirrus_blt_dstaddr,
815 s->vga.vram_ptr + s->cirrus_blt_srcaddr,
816 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
817 s->cirrus_blt_width, s->cirrus_blt_height);
818
819 if (notify) {
820 qemu_console_copy(s->vga.con,
821 sx, sy, dx, dy,
822 s->cirrus_blt_width / depth,
823 s->cirrus_blt_height);
824 }
825
826 /* we don't have to notify the display that this portion has
827 changed since qemu_console_copy implies this */
828
829 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
830 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
831 s->cirrus_blt_height);
832
833 return 1;
834 }
835
836 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
837 {
838 if (blit_is_unsafe(s, false, false))
839 return 0;
840
841 return cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
842 s->cirrus_blt_srcaddr - s->vga.start_addr,
843 s->cirrus_blt_width, s->cirrus_blt_height);
844 }
845
846 /***************************************
847 *
848 * bitblt (cpu-to-video)
849 *
850 ***************************************/
851
852 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
853 {
854 int copy_count;
855 uint8_t *end_ptr;
856
857 if (s->cirrus_srccounter > 0) {
858 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
859 cirrus_bitblt_common_patterncopy(s, false);
860 the_end:
861 s->cirrus_srccounter = 0;
862 cirrus_bitblt_reset(s);
863 } else {
864 /* at least one scan line */
865 do {
866 (*s->cirrus_rop)(s, s->vga.vram_ptr + s->cirrus_blt_dstaddr,
867 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
868 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
869 s->cirrus_blt_width, 1);
870 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
871 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
872 if (s->cirrus_srccounter <= 0)
873 goto the_end;
874 /* more bytes than needed can be transferred because of
875 word alignment, so we keep them for the next line */
876 /* XXX: keep alignment to speed up transfer */
877 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
878 copy_count = s->cirrus_srcptr_end - end_ptr;
879 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
880 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
881 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
882 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
883 }
884 }
885 }
886
887 /***************************************
888 *
889 * bitblt wrapper
890 *
891 ***************************************/
892
893 static void cirrus_bitblt_reset(CirrusVGAState * s)
894 {
895 int need_update;
896
897 s->vga.gr[0x31] &=
898 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
899 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
900 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
901 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
902 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
903 s->cirrus_srccounter = 0;
904 if (!need_update)
905 return;
906 cirrus_update_memory_access(s);
907 }
908
909 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
910 {
911 int w;
912
913 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
914 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
915 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
916
917 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
918 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
919 s->cirrus_blt_srcpitch = 8;
920 } else {
921 /* XXX: check for 24 bpp */
922 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
923 }
924 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
925 } else {
926 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
927 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
928 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
929 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
930 else
931 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
932 } else {
933 /* always align input size to 32 bits */
934 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
935 }
936 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
937 }
938 s->cirrus_srcptr = s->cirrus_bltbuf;
939 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
940 cirrus_update_memory_access(s);
941 return 1;
942 }
943
944 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
945 {
946 /* XXX */
947 #ifdef DEBUG_BITBLT
948 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
949 #endif
950 return 0;
951 }
952
953 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
954 {
955 int ret;
956
957 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
958 ret = cirrus_bitblt_videotovideo_patterncopy(s);
959 } else {
960 ret = cirrus_bitblt_videotovideo_copy(s);
961 }
962 if (ret)
963 cirrus_bitblt_reset(s);
964 return ret;
965 }
966
967 static void cirrus_bitblt_start(CirrusVGAState * s)
968 {
969 uint8_t blt_rop;
970
971 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
972
973 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
974 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
975 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
976 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
977 s->cirrus_blt_dstaddr =
978 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
979 s->cirrus_blt_srcaddr =
980 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
981 s->cirrus_blt_mode = s->vga.gr[0x30];
982 s->cirrus_blt_modeext = s->vga.gr[0x33];
983 blt_rop = s->vga.gr[0x32];
984
985 s->cirrus_blt_dstaddr &= s->cirrus_addr_mask;
986 s->cirrus_blt_srcaddr &= s->cirrus_addr_mask;
987
988 #ifdef DEBUG_BITBLT
989 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
990 blt_rop,
991 s->cirrus_blt_mode,
992 s->cirrus_blt_modeext,
993 s->cirrus_blt_width,
994 s->cirrus_blt_height,
995 s->cirrus_blt_dstpitch,
996 s->cirrus_blt_srcpitch,
997 s->cirrus_blt_dstaddr,
998 s->cirrus_blt_srcaddr,
999 s->vga.gr[0x2f]);
1000 #endif
1001
1002 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
1003 case CIRRUS_BLTMODE_PIXELWIDTH8:
1004 s->cirrus_blt_pixelwidth = 1;
1005 break;
1006 case CIRRUS_BLTMODE_PIXELWIDTH16:
1007 s->cirrus_blt_pixelwidth = 2;
1008 break;
1009 case CIRRUS_BLTMODE_PIXELWIDTH24:
1010 s->cirrus_blt_pixelwidth = 3;
1011 break;
1012 case CIRRUS_BLTMODE_PIXELWIDTH32:
1013 s->cirrus_blt_pixelwidth = 4;
1014 break;
1015 default:
1016 #ifdef DEBUG_BITBLT
1017 printf("cirrus: bitblt - pixel width is unknown\n");
1018 #endif
1019 goto bitblt_ignore;
1020 }
1021 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
1022
1023 if ((s->
1024 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
1025 CIRRUS_BLTMODE_MEMSYSDEST))
1026 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
1027 #ifdef DEBUG_BITBLT
1028 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
1029 #endif
1030 goto bitblt_ignore;
1031 }
1032
1033 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
1034 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
1035 CIRRUS_BLTMODE_TRANSPARENTCOMP |
1036 CIRRUS_BLTMODE_PATTERNCOPY |
1037 CIRRUS_BLTMODE_COLOREXPAND)) ==
1038 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
1039 cirrus_bitblt_fgcol(s);
1040 cirrus_bitblt_solidfill(s, blt_rop);
1041 } else {
1042 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1043 CIRRUS_BLTMODE_PATTERNCOPY)) ==
1044 CIRRUS_BLTMODE_COLOREXPAND) {
1045
1046 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1047 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1048 cirrus_bitblt_bgcol(s);
1049 else
1050 cirrus_bitblt_fgcol(s);
1051 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1052 } else {
1053 cirrus_bitblt_fgcol(s);
1054 cirrus_bitblt_bgcol(s);
1055 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1056 }
1057 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1058 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1059 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1060 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1061 cirrus_bitblt_bgcol(s);
1062 else
1063 cirrus_bitblt_fgcol(s);
1064 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1065 } else {
1066 cirrus_bitblt_fgcol(s);
1067 cirrus_bitblt_bgcol(s);
1068 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1069 }
1070 } else {
1071 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1072 }
1073 } else {
1074 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1075 if (s->cirrus_blt_pixelwidth > 2) {
1076 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1077 goto bitblt_ignore;
1078 }
1079 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1080 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1081 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1082 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1083 } else {
1084 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1085 }
1086 } else {
1087 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1088 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1089 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1090 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1091 } else {
1092 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1093 }
1094 }
1095 }
1096 // setup bitblt engine.
1097 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1098 if (!cirrus_bitblt_cputovideo(s))
1099 goto bitblt_ignore;
1100 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1101 if (!cirrus_bitblt_videotocpu(s))
1102 goto bitblt_ignore;
1103 } else {
1104 if (!cirrus_bitblt_videotovideo(s))
1105 goto bitblt_ignore;
1106 }
1107 }
1108 return;
1109 bitblt_ignore:;
1110 cirrus_bitblt_reset(s);
1111 }
1112
1113 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1114 {
1115 unsigned old_value;
1116
1117 old_value = s->vga.gr[0x31];
1118 s->vga.gr[0x31] = reg_value;
1119
1120 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1121 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1122 cirrus_bitblt_reset(s);
1123 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1124 ((reg_value & CIRRUS_BLT_START) != 0)) {
1125 cirrus_bitblt_start(s);
1126 }
1127 }
1128
1129
1130 /***************************************
1131 *
1132 * basic parameters
1133 *
1134 ***************************************/
1135
1136 static void cirrus_get_offsets(VGACommonState *s1,
1137 uint32_t *pline_offset,
1138 uint32_t *pstart_addr,
1139 uint32_t *pline_compare)
1140 {
1141 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1142 uint32_t start_addr, line_offset, line_compare;
1143
1144 line_offset = s->vga.cr[0x13]
1145 | ((s->vga.cr[0x1b] & 0x10) << 4);
1146 line_offset <<= 3;
1147 *pline_offset = line_offset;
1148
1149 start_addr = (s->vga.cr[0x0c] << 8)
1150 | s->vga.cr[0x0d]
1151 | ((s->vga.cr[0x1b] & 0x01) << 16)
1152 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1153 | ((s->vga.cr[0x1d] & 0x80) << 12);
1154 *pstart_addr = start_addr;
1155
1156 line_compare = s->vga.cr[0x18] |
1157 ((s->vga.cr[0x07] & 0x10) << 4) |
1158 ((s->vga.cr[0x09] & 0x40) << 3);
1159 *pline_compare = line_compare;
1160 }
1161
1162 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1163 {
1164 uint32_t ret = 16;
1165
1166 switch (s->cirrus_hidden_dac_data & 0xf) {
1167 case 0:
1168 ret = 15;
1169 break; /* Sierra HiColor */
1170 case 1:
1171 ret = 16;
1172 break; /* XGA HiColor */
1173 default:
1174 #ifdef DEBUG_CIRRUS
1175 printf("cirrus: invalid DAC value %x in 16bpp\n",
1176 (s->cirrus_hidden_dac_data & 0xf));
1177 #endif
1178 ret = 15; /* XXX */
1179 break;
1180 }
1181 return ret;
1182 }
1183
1184 static int cirrus_get_bpp(VGACommonState *s1)
1185 {
1186 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1187 uint32_t ret = 8;
1188
1189 if ((s->vga.sr[0x07] & 0x01) != 0) {
1190 /* Cirrus SVGA */
1191 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1192 case CIRRUS_SR7_BPP_8:
1193 ret = 8;
1194 break;
1195 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1196 ret = cirrus_get_bpp16_depth(s);
1197 break;
1198 case CIRRUS_SR7_BPP_24:
1199 ret = 24;
1200 break;
1201 case CIRRUS_SR7_BPP_16:
1202 ret = cirrus_get_bpp16_depth(s);
1203 break;
1204 case CIRRUS_SR7_BPP_32:
1205 ret = 32;
1206 break;
1207 default:
1208 #ifdef DEBUG_CIRRUS
1209 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1210 #endif
1211 ret = 8;
1212 break;
1213 }
1214 } else {
1215 /* VGA */
1216 ret = 0;
1217 }
1218
1219 return ret;
1220 }
1221
1222 static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1223 {
1224 int width, height;
1225
1226 width = (s->cr[0x01] + 1) * 8;
1227 height = s->cr[0x12] |
1228 ((s->cr[0x07] & 0x02) << 7) |
1229 ((s->cr[0x07] & 0x40) << 3);
1230 height = (height + 1);
1231 /* interlace support */
1232 if (s->cr[0x1a] & 0x01)
1233 height = height * 2;
1234 *pwidth = width;
1235 *pheight = height;
1236 }
1237
1238 /***************************************
1239 *
1240 * bank memory
1241 *
1242 ***************************************/
1243
1244 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1245 {
1246 unsigned offset;
1247 unsigned limit;
1248
1249 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1250 offset = s->vga.gr[0x09 + bank_index];
1251 else /* single bank */
1252 offset = s->vga.gr[0x09];
1253
1254 if ((s->vga.gr[0x0b] & 0x20) != 0)
1255 offset <<= 14;
1256 else
1257 offset <<= 12;
1258
1259 if (s->real_vram_size <= offset)
1260 limit = 0;
1261 else
1262 limit = s->real_vram_size - offset;
1263
1264 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1265 if (limit > 0x8000) {
1266 offset += 0x8000;
1267 limit -= 0x8000;
1268 } else {
1269 limit = 0;
1270 }
1271 }
1272
1273 if (limit > 0) {
1274 s->cirrus_bank_base[bank_index] = offset;
1275 s->cirrus_bank_limit[bank_index] = limit;
1276 } else {
1277 s->cirrus_bank_base[bank_index] = 0;
1278 s->cirrus_bank_limit[bank_index] = 0;
1279 }
1280 }
1281
1282 /***************************************
1283 *
1284 * I/O access between 0x3c4-0x3c5
1285 *
1286 ***************************************/
1287
1288 static int cirrus_vga_read_sr(CirrusVGAState * s)
1289 {
1290 switch (s->vga.sr_index) {
1291 case 0x00: // Standard VGA
1292 case 0x01: // Standard VGA
1293 case 0x02: // Standard VGA
1294 case 0x03: // Standard VGA
1295 case 0x04: // Standard VGA
1296 return s->vga.sr[s->vga.sr_index];
1297 case 0x06: // Unlock Cirrus extensions
1298 return s->vga.sr[s->vga.sr_index];
1299 case 0x10:
1300 case 0x30:
1301 case 0x50:
1302 case 0x70: // Graphics Cursor X
1303 case 0x90:
1304 case 0xb0:
1305 case 0xd0:
1306 case 0xf0: // Graphics Cursor X
1307 return s->vga.sr[0x10];
1308 case 0x11:
1309 case 0x31:
1310 case 0x51:
1311 case 0x71: // Graphics Cursor Y
1312 case 0x91:
1313 case 0xb1:
1314 case 0xd1:
1315 case 0xf1: // Graphics Cursor Y
1316 return s->vga.sr[0x11];
1317 case 0x05: // ???
1318 case 0x07: // Extended Sequencer Mode
1319 case 0x08: // EEPROM Control
1320 case 0x09: // Scratch Register 0
1321 case 0x0a: // Scratch Register 1
1322 case 0x0b: // VCLK 0
1323 case 0x0c: // VCLK 1
1324 case 0x0d: // VCLK 2
1325 case 0x0e: // VCLK 3
1326 case 0x0f: // DRAM Control
1327 case 0x12: // Graphics Cursor Attribute
1328 case 0x13: // Graphics Cursor Pattern Address
1329 case 0x14: // Scratch Register 2
1330 case 0x15: // Scratch Register 3
1331 case 0x16: // Performance Tuning Register
1332 case 0x17: // Configuration Readback and Extended Control
1333 case 0x18: // Signature Generator Control
1334 case 0x19: // Signal Generator Result
1335 case 0x1a: // Signal Generator Result
1336 case 0x1b: // VCLK 0 Denominator & Post
1337 case 0x1c: // VCLK 1 Denominator & Post
1338 case 0x1d: // VCLK 2 Denominator & Post
1339 case 0x1e: // VCLK 3 Denominator & Post
1340 case 0x1f: // BIOS Write Enable and MCLK select
1341 #ifdef DEBUG_CIRRUS
1342 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
1343 #endif
1344 return s->vga.sr[s->vga.sr_index];
1345 default:
1346 #ifdef DEBUG_CIRRUS
1347 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
1348 #endif
1349 return 0xff;
1350 break;
1351 }
1352 }
1353
1354 static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
1355 {
1356 switch (s->vga.sr_index) {
1357 case 0x00: // Standard VGA
1358 case 0x01: // Standard VGA
1359 case 0x02: // Standard VGA
1360 case 0x03: // Standard VGA
1361 case 0x04: // Standard VGA
1362 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1363 if (s->vga.sr_index == 1)
1364 s->vga.update_retrace_info(&s->vga);
1365 break;
1366 case 0x06: // Unlock Cirrus extensions
1367 val &= 0x17;
1368 if (val == 0x12) {
1369 s->vga.sr[s->vga.sr_index] = 0x12;
1370 } else {
1371 s->vga.sr[s->vga.sr_index] = 0x0f;
1372 }
1373 break;
1374 case 0x10:
1375 case 0x30:
1376 case 0x50:
1377 case 0x70: // Graphics Cursor X
1378 case 0x90:
1379 case 0xb0:
1380 case 0xd0:
1381 case 0xf0: // Graphics Cursor X
1382 s->vga.sr[0x10] = val;
1383 s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
1384 break;
1385 case 0x11:
1386 case 0x31:
1387 case 0x51:
1388 case 0x71: // Graphics Cursor Y
1389 case 0x91:
1390 case 0xb1:
1391 case 0xd1:
1392 case 0xf1: // Graphics Cursor Y
1393 s->vga.sr[0x11] = val;
1394 s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
1395 break;
1396 case 0x07: // Extended Sequencer Mode
1397 cirrus_update_memory_access(s);
1398 case 0x08: // EEPROM Control
1399 case 0x09: // Scratch Register 0
1400 case 0x0a: // Scratch Register 1
1401 case 0x0b: // VCLK 0
1402 case 0x0c: // VCLK 1
1403 case 0x0d: // VCLK 2
1404 case 0x0e: // VCLK 3
1405 case 0x0f: // DRAM Control
1406 case 0x13: // Graphics Cursor Pattern Address
1407 case 0x14: // Scratch Register 2
1408 case 0x15: // Scratch Register 3
1409 case 0x16: // Performance Tuning Register
1410 case 0x18: // Signature Generator Control
1411 case 0x19: // Signature Generator Result
1412 case 0x1a: // Signature Generator Result
1413 case 0x1b: // VCLK 0 Denominator & Post
1414 case 0x1c: // VCLK 1 Denominator & Post
1415 case 0x1d: // VCLK 2 Denominator & Post
1416 case 0x1e: // VCLK 3 Denominator & Post
1417 case 0x1f: // BIOS Write Enable and MCLK select
1418 s->vga.sr[s->vga.sr_index] = val;
1419 #ifdef DEBUG_CIRRUS
1420 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1421 s->vga.sr_index, val);
1422 #endif
1423 break;
1424 case 0x12: // Graphics Cursor Attribute
1425 s->vga.sr[0x12] = val;
1426 s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW);
1427 #ifdef DEBUG_CIRRUS
1428 printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n",
1429 val, s->vga.force_shadow);
1430 #endif
1431 break;
1432 case 0x17: // Configuration Readback and Extended Control
1433 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1434 | (val & 0xc7);
1435 cirrus_update_memory_access(s);
1436 break;
1437 default:
1438 #ifdef DEBUG_CIRRUS
1439 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1440 s->vga.sr_index, val);
1441 #endif
1442 break;
1443 }
1444 }
1445
1446 /***************************************
1447 *
1448 * I/O access at 0x3c6
1449 *
1450 ***************************************/
1451
1452 static int cirrus_read_hidden_dac(CirrusVGAState * s)
1453 {
1454 if (++s->cirrus_hidden_dac_lockindex == 5) {
1455 s->cirrus_hidden_dac_lockindex = 0;
1456 return s->cirrus_hidden_dac_data;
1457 }
1458 return 0xff;
1459 }
1460
1461 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1462 {
1463 if (s->cirrus_hidden_dac_lockindex == 4) {
1464 s->cirrus_hidden_dac_data = reg_value;
1465 #if defined(DEBUG_CIRRUS)
1466 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1467 #endif
1468 }
1469 s->cirrus_hidden_dac_lockindex = 0;
1470 }
1471
1472 /***************************************
1473 *
1474 * I/O access at 0x3c9
1475 *
1476 ***************************************/
1477
1478 static int cirrus_vga_read_palette(CirrusVGAState * s)
1479 {
1480 int val;
1481
1482 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1483 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1484 s->vga.dac_sub_index];
1485 } else {
1486 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1487 }
1488 if (++s->vga.dac_sub_index == 3) {
1489 s->vga.dac_sub_index = 0;
1490 s->vga.dac_read_index++;
1491 }
1492 return val;
1493 }
1494
1495 static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
1496 {
1497 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1498 if (++s->vga.dac_sub_index == 3) {
1499 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1500 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1501 s->vga.dac_cache, 3);
1502 } else {
1503 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1504 }
1505 /* XXX update cursor */
1506 s->vga.dac_sub_index = 0;
1507 s->vga.dac_write_index++;
1508 }
1509 }
1510
1511 /***************************************
1512 *
1513 * I/O access between 0x3ce-0x3cf
1514 *
1515 ***************************************/
1516
1517 static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
1518 {
1519 switch (reg_index) {
1520 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1521 return s->cirrus_shadow_gr0;
1522 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1523 return s->cirrus_shadow_gr1;
1524 case 0x02: // Standard VGA
1525 case 0x03: // Standard VGA
1526 case 0x04: // Standard VGA
1527 case 0x06: // Standard VGA
1528 case 0x07: // Standard VGA
1529 case 0x08: // Standard VGA
1530 return s->vga.gr[s->vga.gr_index];
1531 case 0x05: // Standard VGA, Cirrus extended mode
1532 default:
1533 break;
1534 }
1535
1536 if (reg_index < 0x3a) {
1537 return s->vga.gr[reg_index];
1538 } else {
1539 #ifdef DEBUG_CIRRUS
1540 printf("cirrus: inport gr_index %02x\n", reg_index);
1541 #endif
1542 return 0xff;
1543 }
1544 }
1545
1546 static void
1547 cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1548 {
1549 #if defined(DEBUG_BITBLT) && 0
1550 printf("gr%02x: %02x\n", reg_index, reg_value);
1551 #endif
1552 switch (reg_index) {
1553 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1554 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1555 s->cirrus_shadow_gr0 = reg_value;
1556 break;
1557 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1558 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1559 s->cirrus_shadow_gr1 = reg_value;
1560 break;
1561 case 0x02: // Standard VGA
1562 case 0x03: // Standard VGA
1563 case 0x04: // Standard VGA
1564 case 0x06: // Standard VGA
1565 case 0x07: // Standard VGA
1566 case 0x08: // Standard VGA
1567 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1568 break;
1569 case 0x05: // Standard VGA, Cirrus extended mode
1570 s->vga.gr[reg_index] = reg_value & 0x7f;
1571 cirrus_update_memory_access(s);
1572 break;
1573 case 0x09: // bank offset #0
1574 case 0x0A: // bank offset #1
1575 s->vga.gr[reg_index] = reg_value;
1576 cirrus_update_bank_ptr(s, 0);
1577 cirrus_update_bank_ptr(s, 1);
1578 cirrus_update_memory_access(s);
1579 break;
1580 case 0x0B:
1581 s->vga.gr[reg_index] = reg_value;
1582 cirrus_update_bank_ptr(s, 0);
1583 cirrus_update_bank_ptr(s, 1);
1584 cirrus_update_memory_access(s);
1585 break;
1586 case 0x10: // BGCOLOR 0x0000ff00
1587 case 0x11: // FGCOLOR 0x0000ff00
1588 case 0x12: // BGCOLOR 0x00ff0000
1589 case 0x13: // FGCOLOR 0x00ff0000
1590 case 0x14: // BGCOLOR 0xff000000
1591 case 0x15: // FGCOLOR 0xff000000
1592 case 0x20: // BLT WIDTH 0x0000ff
1593 case 0x22: // BLT HEIGHT 0x0000ff
1594 case 0x24: // BLT DEST PITCH 0x0000ff
1595 case 0x26: // BLT SRC PITCH 0x0000ff
1596 case 0x28: // BLT DEST ADDR 0x0000ff
1597 case 0x29: // BLT DEST ADDR 0x00ff00
1598 case 0x2c: // BLT SRC ADDR 0x0000ff
1599 case 0x2d: // BLT SRC ADDR 0x00ff00
1600 case 0x2f: // BLT WRITEMASK
1601 case 0x30: // BLT MODE
1602 case 0x32: // RASTER OP
1603 case 0x33: // BLT MODEEXT
1604 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1605 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1606 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1607 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1608 s->vga.gr[reg_index] = reg_value;
1609 break;
1610 case 0x21: // BLT WIDTH 0x001f00
1611 case 0x23: // BLT HEIGHT 0x001f00
1612 case 0x25: // BLT DEST PITCH 0x001f00
1613 case 0x27: // BLT SRC PITCH 0x001f00
1614 s->vga.gr[reg_index] = reg_value & 0x1f;
1615 break;
1616 case 0x2a: // BLT DEST ADDR 0x3f0000
1617 s->vga.gr[reg_index] = reg_value & 0x3f;
1618 /* if auto start mode, starts bit blt now */
1619 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1620 cirrus_bitblt_start(s);
1621 }
1622 break;
1623 case 0x2e: // BLT SRC ADDR 0x3f0000
1624 s->vga.gr[reg_index] = reg_value & 0x3f;
1625 break;
1626 case 0x31: // BLT STATUS/START
1627 cirrus_write_bitblt(s, reg_value);
1628 break;
1629 default:
1630 #ifdef DEBUG_CIRRUS
1631 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1632 reg_value);
1633 #endif
1634 break;
1635 }
1636 }
1637
1638 /***************************************
1639 *
1640 * I/O access between 0x3d4-0x3d5
1641 *
1642 ***************************************/
1643
1644 static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
1645 {
1646 switch (reg_index) {
1647 case 0x00: // Standard VGA
1648 case 0x01: // Standard VGA
1649 case 0x02: // Standard VGA
1650 case 0x03: // Standard VGA
1651 case 0x04: // Standard VGA
1652 case 0x05: // Standard VGA
1653 case 0x06: // Standard VGA
1654 case 0x07: // Standard VGA
1655 case 0x08: // Standard VGA
1656 case 0x09: // Standard VGA
1657 case 0x0a: // Standard VGA
1658 case 0x0b: // Standard VGA
1659 case 0x0c: // Standard VGA
1660 case 0x0d: // Standard VGA
1661 case 0x0e: // Standard VGA
1662 case 0x0f: // Standard VGA
1663 case 0x10: // Standard VGA
1664 case 0x11: // Standard VGA
1665 case 0x12: // Standard VGA
1666 case 0x13: // Standard VGA
1667 case 0x14: // Standard VGA
1668 case 0x15: // Standard VGA
1669 case 0x16: // Standard VGA
1670 case 0x17: // Standard VGA
1671 case 0x18: // Standard VGA
1672 return s->vga.cr[s->vga.cr_index];
1673 case 0x24: // Attribute Controller Toggle Readback (R)
1674 return (s->vga.ar_flip_flop << 7);
1675 case 0x19: // Interlace End
1676 case 0x1a: // Miscellaneous Control
1677 case 0x1b: // Extended Display Control
1678 case 0x1c: // Sync Adjust and Genlock
1679 case 0x1d: // Overlay Extended Control
1680 case 0x22: // Graphics Data Latches Readback (R)
1681 case 0x25: // Part Status
1682 case 0x27: // Part ID (R)
1683 return s->vga.cr[s->vga.cr_index];
1684 case 0x26: // Attribute Controller Index Readback (R)
1685 return s->vga.ar_index & 0x3f;
1686 break;
1687 default:
1688 #ifdef DEBUG_CIRRUS
1689 printf("cirrus: inport cr_index %02x\n", reg_index);
1690 #endif
1691 return 0xff;
1692 }
1693 }
1694
1695 static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
1696 {
1697 switch (s->vga.cr_index) {
1698 case 0x00: // Standard VGA
1699 case 0x01: // Standard VGA
1700 case 0x02: // Standard VGA
1701 case 0x03: // Standard VGA
1702 case 0x04: // Standard VGA
1703 case 0x05: // Standard VGA
1704 case 0x06: // Standard VGA
1705 case 0x07: // Standard VGA
1706 case 0x08: // Standard VGA
1707 case 0x09: // Standard VGA
1708 case 0x0a: // Standard VGA
1709 case 0x0b: // Standard VGA
1710 case 0x0c: // Standard VGA
1711 case 0x0d: // Standard VGA
1712 case 0x0e: // Standard VGA
1713 case 0x0f: // Standard VGA
1714 case 0x10: // Standard VGA
1715 case 0x11: // Standard VGA
1716 case 0x12: // Standard VGA
1717 case 0x13: // Standard VGA
1718 case 0x14: // Standard VGA
1719 case 0x15: // Standard VGA
1720 case 0x16: // Standard VGA
1721 case 0x17: // Standard VGA
1722 case 0x18: // Standard VGA
1723 /* handle CR0-7 protection */
1724 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1725 /* can always write bit 4 of CR7 */
1726 if (s->vga.cr_index == 7)
1727 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1728 return;
1729 }
1730 s->vga.cr[s->vga.cr_index] = reg_value;
1731 switch(s->vga.cr_index) {
1732 case 0x00:
1733 case 0x04:
1734 case 0x05:
1735 case 0x06:
1736 case 0x07:
1737 case 0x11:
1738 case 0x17:
1739 s->vga.update_retrace_info(&s->vga);
1740 break;
1741 }
1742 break;
1743 case 0x19: // Interlace End
1744 case 0x1a: // Miscellaneous Control
1745 case 0x1b: // Extended Display Control
1746 case 0x1c: // Sync Adjust and Genlock
1747 case 0x1d: // Overlay Extended Control
1748 s->vga.cr[s->vga.cr_index] = reg_value;
1749 #ifdef DEBUG_CIRRUS
1750 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1751 s->vga.cr_index, reg_value);
1752 #endif
1753 break;
1754 case 0x22: // Graphics Data Latches Readback (R)
1755 case 0x24: // Attribute Controller Toggle Readback (R)
1756 case 0x26: // Attribute Controller Index Readback (R)
1757 case 0x27: // Part ID (R)
1758 break;
1759 case 0x25: // Part Status
1760 default:
1761 #ifdef DEBUG_CIRRUS
1762 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1763 s->vga.cr_index, reg_value);
1764 #endif
1765 break;
1766 }
1767 }
1768
1769 /***************************************
1770 *
1771 * memory-mapped I/O (bitblt)
1772 *
1773 ***************************************/
1774
1775 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1776 {
1777 int value = 0xff;
1778
1779 switch (address) {
1780 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1781 value = cirrus_vga_read_gr(s, 0x00);
1782 break;
1783 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1784 value = cirrus_vga_read_gr(s, 0x10);
1785 break;
1786 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1787 value = cirrus_vga_read_gr(s, 0x12);
1788 break;
1789 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1790 value = cirrus_vga_read_gr(s, 0x14);
1791 break;
1792 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1793 value = cirrus_vga_read_gr(s, 0x01);
1794 break;
1795 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1796 value = cirrus_vga_read_gr(s, 0x11);
1797 break;
1798 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1799 value = cirrus_vga_read_gr(s, 0x13);
1800 break;
1801 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1802 value = cirrus_vga_read_gr(s, 0x15);
1803 break;
1804 case (CIRRUS_MMIO_BLTWIDTH + 0):
1805 value = cirrus_vga_read_gr(s, 0x20);
1806 break;
1807 case (CIRRUS_MMIO_BLTWIDTH + 1):
1808 value = cirrus_vga_read_gr(s, 0x21);
1809 break;
1810 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1811 value = cirrus_vga_read_gr(s, 0x22);
1812 break;
1813 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1814 value = cirrus_vga_read_gr(s, 0x23);
1815 break;
1816 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1817 value = cirrus_vga_read_gr(s, 0x24);
1818 break;
1819 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1820 value = cirrus_vga_read_gr(s, 0x25);
1821 break;
1822 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1823 value = cirrus_vga_read_gr(s, 0x26);
1824 break;
1825 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1826 value = cirrus_vga_read_gr(s, 0x27);
1827 break;
1828 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1829 value = cirrus_vga_read_gr(s, 0x28);
1830 break;
1831 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1832 value = cirrus_vga_read_gr(s, 0x29);
1833 break;
1834 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1835 value = cirrus_vga_read_gr(s, 0x2a);
1836 break;
1837 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1838 value = cirrus_vga_read_gr(s, 0x2c);
1839 break;
1840 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1841 value = cirrus_vga_read_gr(s, 0x2d);
1842 break;
1843 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1844 value = cirrus_vga_read_gr(s, 0x2e);
1845 break;
1846 case CIRRUS_MMIO_BLTWRITEMASK:
1847 value = cirrus_vga_read_gr(s, 0x2f);
1848 break;
1849 case CIRRUS_MMIO_BLTMODE:
1850 value = cirrus_vga_read_gr(s, 0x30);
1851 break;
1852 case CIRRUS_MMIO_BLTROP:
1853 value = cirrus_vga_read_gr(s, 0x32);
1854 break;
1855 case CIRRUS_MMIO_BLTMODEEXT:
1856 value = cirrus_vga_read_gr(s, 0x33);
1857 break;
1858 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1859 value = cirrus_vga_read_gr(s, 0x34);
1860 break;
1861 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1862 value = cirrus_vga_read_gr(s, 0x35);
1863 break;
1864 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1865 value = cirrus_vga_read_gr(s, 0x38);
1866 break;
1867 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1868 value = cirrus_vga_read_gr(s, 0x39);
1869 break;
1870 case CIRRUS_MMIO_BLTSTATUS:
1871 value = cirrus_vga_read_gr(s, 0x31);
1872 break;
1873 default:
1874 #ifdef DEBUG_CIRRUS
1875 printf("cirrus: mmio read - address 0x%04x\n", address);
1876 #endif
1877 break;
1878 }
1879
1880 trace_vga_cirrus_write_blt(address, value);
1881 return (uint8_t) value;
1882 }
1883
1884 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1885 uint8_t value)
1886 {
1887 trace_vga_cirrus_write_blt(address, value);
1888 switch (address) {
1889 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1890 cirrus_vga_write_gr(s, 0x00, value);
1891 break;
1892 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1893 cirrus_vga_write_gr(s, 0x10, value);
1894 break;
1895 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1896 cirrus_vga_write_gr(s, 0x12, value);
1897 break;
1898 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1899 cirrus_vga_write_gr(s, 0x14, value);
1900 break;
1901 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1902 cirrus_vga_write_gr(s, 0x01, value);
1903 break;
1904 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1905 cirrus_vga_write_gr(s, 0x11, value);
1906 break;
1907 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1908 cirrus_vga_write_gr(s, 0x13, value);
1909 break;
1910 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1911 cirrus_vga_write_gr(s, 0x15, value);
1912 break;
1913 case (CIRRUS_MMIO_BLTWIDTH + 0):
1914 cirrus_vga_write_gr(s, 0x20, value);
1915 break;
1916 case (CIRRUS_MMIO_BLTWIDTH + 1):
1917 cirrus_vga_write_gr(s, 0x21, value);
1918 break;
1919 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1920 cirrus_vga_write_gr(s, 0x22, value);
1921 break;
1922 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1923 cirrus_vga_write_gr(s, 0x23, value);
1924 break;
1925 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1926 cirrus_vga_write_gr(s, 0x24, value);
1927 break;
1928 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1929 cirrus_vga_write_gr(s, 0x25, value);
1930 break;
1931 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1932 cirrus_vga_write_gr(s, 0x26, value);
1933 break;
1934 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1935 cirrus_vga_write_gr(s, 0x27, value);
1936 break;
1937 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1938 cirrus_vga_write_gr(s, 0x28, value);
1939 break;
1940 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1941 cirrus_vga_write_gr(s, 0x29, value);
1942 break;
1943 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1944 cirrus_vga_write_gr(s, 0x2a, value);
1945 break;
1946 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1947 /* ignored */
1948 break;
1949 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1950 cirrus_vga_write_gr(s, 0x2c, value);
1951 break;
1952 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1953 cirrus_vga_write_gr(s, 0x2d, value);
1954 break;
1955 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1956 cirrus_vga_write_gr(s, 0x2e, value);
1957 break;
1958 case CIRRUS_MMIO_BLTWRITEMASK:
1959 cirrus_vga_write_gr(s, 0x2f, value);
1960 break;
1961 case CIRRUS_MMIO_BLTMODE:
1962 cirrus_vga_write_gr(s, 0x30, value);
1963 break;
1964 case CIRRUS_MMIO_BLTROP:
1965 cirrus_vga_write_gr(s, 0x32, value);
1966 break;
1967 case CIRRUS_MMIO_BLTMODEEXT:
1968 cirrus_vga_write_gr(s, 0x33, value);
1969 break;
1970 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1971 cirrus_vga_write_gr(s, 0x34, value);
1972 break;
1973 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1974 cirrus_vga_write_gr(s, 0x35, value);
1975 break;
1976 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1977 cirrus_vga_write_gr(s, 0x38, value);
1978 break;
1979 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1980 cirrus_vga_write_gr(s, 0x39, value);
1981 break;
1982 case CIRRUS_MMIO_BLTSTATUS:
1983 cirrus_vga_write_gr(s, 0x31, value);
1984 break;
1985 default:
1986 #ifdef DEBUG_CIRRUS
1987 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1988 address, value);
1989 #endif
1990 break;
1991 }
1992 }
1993
1994 /***************************************
1995 *
1996 * write mode 4/5
1997 *
1998 ***************************************/
1999
2000 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
2001 unsigned mode,
2002 unsigned offset,
2003 uint32_t mem_value)
2004 {
2005 int x;
2006 unsigned val = mem_value;
2007 uint8_t *dst;
2008
2009 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
2010 for (x = 0; x < 8; x++) {
2011 if (val & 0x80) {
2012 *dst = s->cirrus_shadow_gr1;
2013 } else if (mode == 5) {
2014 *dst = s->cirrus_shadow_gr0;
2015 }
2016 val <<= 1;
2017 dst++;
2018 }
2019 memory_region_set_dirty(&s->vga.vram, offset, 8);
2020 }
2021
2022 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
2023 unsigned mode,
2024 unsigned offset,
2025 uint32_t mem_value)
2026 {
2027 int x;
2028 unsigned val = mem_value;
2029 uint8_t *dst;
2030
2031 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
2032 for (x = 0; x < 8; x++) {
2033 if (val & 0x80) {
2034 *dst = s->cirrus_shadow_gr1;
2035 *(dst + 1) = s->vga.gr[0x11];
2036 } else if (mode == 5) {
2037 *dst = s->cirrus_shadow_gr0;
2038 *(dst + 1) = s->vga.gr[0x10];
2039 }
2040 val <<= 1;
2041 dst += 2;
2042 }
2043 memory_region_set_dirty(&s->vga.vram, offset, 16);
2044 }
2045
2046 /***************************************
2047 *
2048 * memory access between 0xa0000-0xbffff
2049 *
2050 ***************************************/
2051
2052 static uint64_t cirrus_vga_mem_read(void *opaque,
2053 hwaddr addr,
2054 uint32_t size)
2055 {
2056 CirrusVGAState *s = opaque;
2057 unsigned bank_index;
2058 unsigned bank_offset;
2059 uint32_t val;
2060
2061 if ((s->vga.sr[0x07] & 0x01) == 0) {
2062 return vga_mem_readb(&s->vga, addr);
2063 }
2064
2065 if (addr < 0x10000) {
2066 /* XXX handle bitblt */
2067 /* video memory */
2068 bank_index = addr >> 15;
2069 bank_offset = addr & 0x7fff;
2070 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2071 bank_offset += s->cirrus_bank_base[bank_index];
2072 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2073 bank_offset <<= 4;
2074 } else if (s->vga.gr[0x0B] & 0x02) {
2075 bank_offset <<= 3;
2076 }
2077 bank_offset &= s->cirrus_addr_mask;
2078 val = *(s->vga.vram_ptr + bank_offset);
2079 } else
2080 val = 0xff;
2081 } else if (addr >= 0x18000 && addr < 0x18100) {
2082 /* memory-mapped I/O */
2083 val = 0xff;
2084 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2085 val = cirrus_mmio_blt_read(s, addr & 0xff);
2086 }
2087 } else {
2088 val = 0xff;
2089 #ifdef DEBUG_CIRRUS
2090 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
2091 #endif
2092 }
2093 return val;
2094 }
2095
2096 static void cirrus_vga_mem_write(void *opaque,
2097 hwaddr addr,
2098 uint64_t mem_value,
2099 uint32_t size)
2100 {
2101 CirrusVGAState *s = opaque;
2102 unsigned bank_index;
2103 unsigned bank_offset;
2104 unsigned mode;
2105
2106 if ((s->vga.sr[0x07] & 0x01) == 0) {
2107 vga_mem_writeb(&s->vga, addr, mem_value);
2108 return;
2109 }
2110
2111 if (addr < 0x10000) {
2112 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2113 /* bitblt */
2114 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2115 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2116 cirrus_bitblt_cputovideo_next(s);
2117 }
2118 } else {
2119 /* video memory */
2120 bank_index = addr >> 15;
2121 bank_offset = addr & 0x7fff;
2122 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2123 bank_offset += s->cirrus_bank_base[bank_index];
2124 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2125 bank_offset <<= 4;
2126 } else if (s->vga.gr[0x0B] & 0x02) {
2127 bank_offset <<= 3;
2128 }
2129 bank_offset &= s->cirrus_addr_mask;
2130 mode = s->vga.gr[0x05] & 0x7;
2131 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2132 *(s->vga.vram_ptr + bank_offset) = mem_value;
2133 memory_region_set_dirty(&s->vga.vram, bank_offset,
2134 sizeof(mem_value));
2135 } else {
2136 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2137 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2138 bank_offset,
2139 mem_value);
2140 } else {
2141 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2142 bank_offset,
2143 mem_value);
2144 }
2145 }
2146 }
2147 }
2148 } else if (addr >= 0x18000 && addr < 0x18100) {
2149 /* memory-mapped I/O */
2150 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2151 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2152 }
2153 } else {
2154 #ifdef DEBUG_CIRRUS
2155 printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr,
2156 mem_value);
2157 #endif
2158 }
2159 }
2160
2161 static const MemoryRegionOps cirrus_vga_mem_ops = {
2162 .read = cirrus_vga_mem_read,
2163 .write = cirrus_vga_mem_write,
2164 .endianness = DEVICE_LITTLE_ENDIAN,
2165 .impl = {
2166 .min_access_size = 1,
2167 .max_access_size = 1,
2168 },
2169 };
2170
2171 /***************************************
2172 *
2173 * hardware cursor
2174 *
2175 ***************************************/
2176
2177 static inline void invalidate_cursor1(CirrusVGAState *s)
2178 {
2179 if (s->last_hw_cursor_size) {
2180 vga_invalidate_scanlines(&s->vga,
2181 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2182 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2183 }
2184 }
2185
2186 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2187 {
2188 const uint8_t *src;
2189 uint32_t content;
2190 int y, y_min, y_max;
2191
2192 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2193 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2194 src += (s->vga.sr[0x13] & 0x3c) * 256;
2195 y_min = 64;
2196 y_max = -1;
2197 for(y = 0; y < 64; y++) {
2198 content = ((uint32_t *)src)[0] |
2199 ((uint32_t *)src)[1] |
2200 ((uint32_t *)src)[2] |
2201 ((uint32_t *)src)[3];
2202 if (content) {
2203 if (y < y_min)
2204 y_min = y;
2205 if (y > y_max)
2206 y_max = y;
2207 }
2208 src += 16;
2209 }
2210 } else {
2211 src += (s->vga.sr[0x13] & 0x3f) * 256;
2212 y_min = 32;
2213 y_max = -1;
2214 for(y = 0; y < 32; y++) {
2215 content = ((uint32_t *)src)[0] |
2216 ((uint32_t *)(src + 128))[0];
2217 if (content) {
2218 if (y < y_min)
2219 y_min = y;
2220 if (y > y_max)
2221 y_max = y;
2222 }
2223 src += 4;
2224 }
2225 }
2226 if (y_min > y_max) {
2227 s->last_hw_cursor_y_start = 0;
2228 s->last_hw_cursor_y_end = 0;
2229 } else {
2230 s->last_hw_cursor_y_start = y_min;
2231 s->last_hw_cursor_y_end = y_max + 1;
2232 }
2233 }
2234
2235 /* NOTE: we do not currently handle the cursor bitmap change, so we
2236 update the cursor only if it moves. */
2237 static void cirrus_cursor_invalidate(VGACommonState *s1)
2238 {
2239 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2240 int size;
2241
2242 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2243 size = 0;
2244 } else {
2245 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2246 size = 64;
2247 else
2248 size = 32;
2249 }
2250 /* invalidate last cursor and new cursor if any change */
2251 if (s->last_hw_cursor_size != size ||
2252 s->last_hw_cursor_x != s->vga.hw_cursor_x ||
2253 s->last_hw_cursor_y != s->vga.hw_cursor_y) {
2254
2255 invalidate_cursor1(s);
2256
2257 s->last_hw_cursor_size = size;
2258 s->last_hw_cursor_x = s->vga.hw_cursor_x;
2259 s->last_hw_cursor_y = s->vga.hw_cursor_y;
2260 /* compute the real cursor min and max y */
2261 cirrus_cursor_compute_yrange(s);
2262 invalidate_cursor1(s);
2263 }
2264 }
2265
2266 static void vga_draw_cursor_line(uint8_t *d1,
2267 const uint8_t *src1,
2268 int poffset, int w,
2269 unsigned int color0,
2270 unsigned int color1,
2271 unsigned int color_xor)
2272 {
2273 const uint8_t *plane0, *plane1;
2274 int x, b0, b1;
2275 uint8_t *d;
2276
2277 d = d1;
2278 plane0 = src1;
2279 plane1 = src1 + poffset;
2280 for (x = 0; x < w; x++) {
2281 b0 = (plane0[x >> 3] >> (7 - (x & 7))) & 1;
2282 b1 = (plane1[x >> 3] >> (7 - (x & 7))) & 1;
2283 switch (b0 | (b1 << 1)) {
2284 case 0:
2285 break;
2286 case 1:
2287 ((uint32_t *)d)[0] ^= color_xor;
2288 break;
2289 case 2:
2290 ((uint32_t *)d)[0] = color0;
2291 break;
2292 case 3:
2293 ((uint32_t *)d)[0] = color1;
2294 break;
2295 }
2296 d += 4;
2297 }
2298 }
2299
2300 static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
2301 {
2302 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2303 int w, h, x1, x2, poffset;
2304 unsigned int color0, color1;
2305 const uint8_t *palette, *src;
2306 uint32_t content;
2307
2308 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2309 return;
2310 /* fast test to see if the cursor intersects with the scan line */
2311 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2312 h = 64;
2313 } else {
2314 h = 32;
2315 }
2316 if (scr_y < s->vga.hw_cursor_y ||
2317 scr_y >= (s->vga.hw_cursor_y + h)) {
2318 return;
2319 }
2320
2321 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2322 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2323 src += (s->vga.sr[0x13] & 0x3c) * 256;
2324 src += (scr_y - s->vga.hw_cursor_y) * 16;
2325 poffset = 8;
2326 content = ((uint32_t *)src)[0] |
2327 ((uint32_t *)src)[1] |
2328 ((uint32_t *)src)[2] |
2329 ((uint32_t *)src)[3];
2330 } else {
2331 src += (s->vga.sr[0x13] & 0x3f) * 256;
2332 src += (scr_y - s->vga.hw_cursor_y) * 4;
2333
2334
2335 poffset = 128;
2336 content = ((uint32_t *)src)[0] |
2337 ((uint32_t *)(src + 128))[0];
2338 }
2339 /* if nothing to draw, no need to continue */
2340 if (!content)
2341 return;
2342 w = h;
2343
2344 x1 = s->vga.hw_cursor_x;
2345 if (x1 >= s->vga.last_scr_width)
2346 return;
2347 x2 = s->vga.hw_cursor_x + w;
2348 if (x2 > s->vga.last_scr_width)
2349 x2 = s->vga.last_scr_width;
2350 w = x2 - x1;
2351 palette = s->cirrus_hidden_palette;
2352 color0 = rgb_to_pixel32(c6_to_8(palette[0x0 * 3]),
2353 c6_to_8(palette[0x0 * 3 + 1]),
2354 c6_to_8(palette[0x0 * 3 + 2]));
2355 color1 = rgb_to_pixel32(c6_to_8(palette[0xf * 3]),
2356 c6_to_8(palette[0xf * 3 + 1]),
2357 c6_to_8(palette[0xf * 3 + 2]));
2358 d1 += x1 * 4;
2359 vga_draw_cursor_line(d1, src, poffset, w, color0, color1, 0xffffff);
2360 }
2361
2362 /***************************************
2363 *
2364 * LFB memory access
2365 *
2366 ***************************************/
2367
2368 static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
2369 unsigned size)
2370 {
2371 CirrusVGAState *s = opaque;
2372 uint32_t ret;
2373
2374 addr &= s->cirrus_addr_mask;
2375
2376 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2377 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2378 /* memory-mapped I/O */
2379 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2380 } else if (0) {
2381 /* XXX handle bitblt */
2382 ret = 0xff;
2383 } else {
2384 /* video memory */
2385 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2386 addr <<= 4;
2387 } else if (s->vga.gr[0x0B] & 0x02) {
2388 addr <<= 3;
2389 }
2390 addr &= s->cirrus_addr_mask;
2391 ret = *(s->vga.vram_ptr + addr);
2392 }
2393
2394 return ret;
2395 }
2396
2397 static void cirrus_linear_write(void *opaque, hwaddr addr,
2398 uint64_t val, unsigned size)
2399 {
2400 CirrusVGAState *s = opaque;
2401 unsigned mode;
2402
2403 addr &= s->cirrus_addr_mask;
2404
2405 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2406 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2407 /* memory-mapped I/O */
2408 cirrus_mmio_blt_write(s, addr & 0xff, val);
2409 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2410 /* bitblt */
2411 *s->cirrus_srcptr++ = (uint8_t) val;
2412 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2413 cirrus_bitblt_cputovideo_next(s);
2414 }
2415 } else {
2416 /* video memory */
2417 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2418 addr <<= 4;
2419 } else if (s->vga.gr[0x0B] & 0x02) {
2420 addr <<= 3;
2421 }
2422 addr &= s->cirrus_addr_mask;
2423
2424 mode = s->vga.gr[0x05] & 0x7;
2425 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2426 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2427 memory_region_set_dirty(&s->vga.vram, addr, 1);
2428 } else {
2429 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2430 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2431 } else {
2432 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2433 }
2434 }
2435 }
2436 }
2437
2438 /***************************************
2439 *
2440 * system to screen memory access
2441 *
2442 ***************************************/
2443
2444
2445 static uint64_t cirrus_linear_bitblt_read(void *opaque,
2446 hwaddr addr,
2447 unsigned size)
2448 {
2449 CirrusVGAState *s = opaque;
2450 uint32_t ret;
2451
2452 /* XXX handle bitblt */
2453 (void)s;
2454 ret = 0xff;
2455 return ret;
2456 }
2457
2458 static void cirrus_linear_bitblt_write(void *opaque,
2459 hwaddr addr,
2460 uint64_t val,
2461 unsigned size)
2462 {
2463 CirrusVGAState *s = opaque;
2464
2465 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2466 /* bitblt */
2467 *s->cirrus_srcptr++ = (uint8_t) val;
2468 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2469 cirrus_bitblt_cputovideo_next(s);
2470 }
2471 }
2472 }
2473
2474 static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2475 .read = cirrus_linear_bitblt_read,
2476 .write = cirrus_linear_bitblt_write,
2477 .endianness = DEVICE_LITTLE_ENDIAN,
2478 .impl = {
2479 .min_access_size = 1,
2480 .max_access_size = 1,
2481 },
2482 };
2483
2484 static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2485 {
2486 MemoryRegion *mr = &s->cirrus_bank[bank];
2487 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2488 && !((s->vga.sr[0x07] & 0x01) == 0)
2489 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2490 && !(s->vga.gr[0x0B] & 0x02);
2491
2492 memory_region_set_enabled(mr, enabled);
2493 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
2494 }
2495
2496 static void map_linear_vram(CirrusVGAState *s)
2497 {
2498 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
2499 s->linear_vram = true;
2500 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2501 }
2502 map_linear_vram_bank(s, 0);
2503 map_linear_vram_bank(s, 1);
2504 }
2505
2506 static void unmap_linear_vram(CirrusVGAState *s)
2507 {
2508 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
2509 s->linear_vram = false;
2510 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
2511 }
2512 memory_region_set_enabled(&s->cirrus_bank[0], false);
2513 memory_region_set_enabled(&s->cirrus_bank[1], false);
2514 }
2515
2516 /* Compute the memory access functions */
2517 static void cirrus_update_memory_access(CirrusVGAState *s)
2518 {
2519 unsigned mode;
2520
2521 memory_region_transaction_begin();
2522 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2523 goto generic_io;
2524 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2525 goto generic_io;
2526 } else {
2527 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2528 goto generic_io;
2529 } else if (s->vga.gr[0x0B] & 0x02) {
2530 goto generic_io;
2531 }
2532
2533 mode = s->vga.gr[0x05] & 0x7;
2534 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2535 map_linear_vram(s);
2536 } else {
2537 generic_io:
2538 unmap_linear_vram(s);
2539 }
2540 }
2541 memory_region_transaction_commit();
2542 }
2543
2544
2545 /* I/O ports */
2546
2547 static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
2548 unsigned size)
2549 {
2550 CirrusVGAState *c = opaque;
2551 VGACommonState *s = &c->vga;
2552 int val, index;
2553
2554 addr += 0x3b0;
2555
2556 if (vga_ioport_invalid(s, addr)) {
2557 val = 0xff;
2558 } else {
2559 switch (addr) {
2560 case 0x3c0:
2561 if (s->ar_flip_flop == 0) {
2562 val = s->ar_index;
2563 } else {
2564 val = 0;
2565 }
2566 break;
2567 case 0x3c1:
2568 index = s->ar_index & 0x1f;
2569 if (index < 21)
2570 val = s->ar[index];
2571 else
2572 val = 0;
2573 break;
2574 case 0x3c2:
2575 val = s->st00;
2576 break;
2577 case 0x3c4:
2578 val = s->sr_index;
2579 break;
2580 case 0x3c5:
2581 val = cirrus_vga_read_sr(c);
2582 break;
2583 #ifdef DEBUG_VGA_REG
2584 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2585 #endif
2586 break;
2587 case 0x3c6:
2588 val = cirrus_read_hidden_dac(c);
2589 break;
2590 case 0x3c7:
2591 val = s->dac_state;
2592 break;
2593 case 0x3c8:
2594 val = s->dac_write_index;
2595 c->cirrus_hidden_dac_lockindex = 0;
2596 break;
2597 case 0x3c9:
2598 val = cirrus_vga_read_palette(c);
2599 break;
2600 case 0x3ca:
2601 val = s->fcr;
2602 break;
2603 case 0x3cc:
2604 val = s->msr;
2605 break;
2606 case 0x3ce:
2607 val = s->gr_index;
2608 break;
2609 case 0x3cf:
2610 val = cirrus_vga_read_gr(c, s->gr_index);
2611 #ifdef DEBUG_VGA_REG
2612 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2613 #endif
2614 break;
2615 case 0x3b4:
2616 case 0x3d4:
2617 val = s->cr_index;
2618 break;
2619 case 0x3b5:
2620 case 0x3d5:
2621 val = cirrus_vga_read_cr(c, s->cr_index);
2622 #ifdef DEBUG_VGA_REG
2623 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2624 #endif
2625 break;
2626 case 0x3ba:
2627 case 0x3da:
2628 /* just toggle to fool polling */
2629 val = s->st01 = s->retrace(s);
2630 s->ar_flip_flop = 0;
2631 break;
2632 default:
2633 val = 0x00;
2634 break;
2635 }
2636 }
2637 trace_vga_cirrus_read_io(addr, val);
2638 return val;
2639 }
2640
2641 static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
2642 unsigned size)
2643 {
2644 CirrusVGAState *c = opaque;
2645 VGACommonState *s = &c->vga;
2646 int index;
2647
2648 addr += 0x3b0;
2649
2650 /* check port range access depending on color/monochrome mode */
2651 if (vga_ioport_invalid(s, addr)) {
2652 return;
2653 }
2654 trace_vga_cirrus_write_io(addr, val);
2655
2656 switch (addr) {
2657 case 0x3c0:
2658 if (s->ar_flip_flop == 0) {
2659 val &= 0x3f;
2660 s->ar_index = val;
2661 } else {
2662 index = s->ar_index & 0x1f;
2663 switch (index) {
2664 case 0x00 ... 0x0f:
2665 s->ar[index] = val & 0x3f;
2666 break;
2667 case 0x10:
2668 s->ar[index] = val & ~0x10;
2669 break;
2670 case 0x11:
2671 s->ar[index] = val;
2672 break;
2673 case 0x12:
2674 s->ar[index] = val & ~0xc0;
2675 break;
2676 case 0x13:
2677 s->ar[index] = val & ~0xf0;
2678 break;
2679 case 0x14:
2680 s->ar[index] = val & ~0xf0;
2681 break;
2682 default:
2683 break;
2684 }
2685 }
2686 s->ar_flip_flop ^= 1;
2687 break;
2688 case 0x3c2:
2689 s->msr = val & ~0x10;
2690 s->update_retrace_info(s);
2691 break;
2692 case 0x3c4:
2693 s->sr_index = val;
2694 break;
2695 case 0x3c5:
2696 #ifdef DEBUG_VGA_REG
2697 printf("vga: write SR%x = 0x%02" PRIu64 "\n", s->sr_index, val);
2698 #endif
2699 cirrus_vga_write_sr(c, val);
2700 break;
2701 case 0x3c6:
2702 cirrus_write_hidden_dac(c, val);
2703 break;
2704 case 0x3c7:
2705 s->dac_read_index = val;
2706 s->dac_sub_index = 0;
2707 s->dac_state = 3;
2708 break;
2709 case 0x3c8:
2710 s->dac_write_index = val;
2711 s->dac_sub_index = 0;
2712 s->dac_state = 0;
2713 break;
2714 case 0x3c9:
2715 cirrus_vga_write_palette(c, val);
2716 break;
2717 case 0x3ce:
2718 s->gr_index = val;
2719 break;
2720 case 0x3cf:
2721 #ifdef DEBUG_VGA_REG
2722 printf("vga: write GR%x = 0x%02" PRIu64 "\n", s->gr_index, val);
2723 #endif
2724 cirrus_vga_write_gr(c, s->gr_index, val);
2725 break;
2726 case 0x3b4:
2727 case 0x3d4:
2728 s->cr_index = val;
2729 break;
2730 case 0x3b5:
2731 case 0x3d5:
2732 #ifdef DEBUG_VGA_REG
2733 printf("vga: write CR%x = 0x%02"PRIu64"\n", s->cr_index, val);
2734 #endif
2735 cirrus_vga_write_cr(c, val);
2736 break;
2737 case 0x3ba:
2738 case 0x3da:
2739 s->fcr = val & 0x10;
2740 break;
2741 }
2742 }
2743
2744 /***************************************
2745 *
2746 * memory-mapped I/O access
2747 *
2748 ***************************************/
2749
2750 static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
2751 unsigned size)
2752 {
2753 CirrusVGAState *s = opaque;
2754
2755 if (addr >= 0x100) {
2756 return cirrus_mmio_blt_read(s, addr - 0x100);
2757 } else {
2758 return cirrus_vga_ioport_read(s, addr + 0x10, size);
2759 }
2760 }
2761
2762 static void cirrus_mmio_write(void *opaque, hwaddr addr,
2763 uint64_t val, unsigned size)
2764 {
2765 CirrusVGAState *s = opaque;
2766
2767 if (addr >= 0x100) {
2768 cirrus_mmio_blt_write(s, addr - 0x100, val);
2769 } else {
2770 cirrus_vga_ioport_write(s, addr + 0x10, val, size);
2771 }
2772 }
2773
2774 static const MemoryRegionOps cirrus_mmio_io_ops = {
2775 .read = cirrus_mmio_read,
2776 .write = cirrus_mmio_write,
2777 .endianness = DEVICE_LITTLE_ENDIAN,
2778 .impl = {
2779 .min_access_size = 1,
2780 .max_access_size = 1,
2781 },
2782 };
2783
2784 /* load/save state */
2785
2786 static int cirrus_post_load(void *opaque, int version_id)
2787 {
2788 CirrusVGAState *s = opaque;
2789
2790 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2791 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2792
2793 cirrus_update_memory_access(s);
2794 /* force refresh */
2795 s->vga.graphic_mode = -1;
2796 cirrus_update_bank_ptr(s, 0);
2797 cirrus_update_bank_ptr(s, 1);
2798 return 0;
2799 }
2800
2801 static const VMStateDescription vmstate_cirrus_vga = {
2802 .name = "cirrus_vga",
2803 .version_id = 2,
2804 .minimum_version_id = 1,
2805 .post_load = cirrus_post_load,
2806 .fields = (VMStateField[]) {
2807 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2808 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2809 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2810 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2811 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2812 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2813 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2814 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2815 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2816 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2817 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2818 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2819 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2820 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2821 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2822 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2823 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2824 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2825 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2826 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2827 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2828 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2829 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2830 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2831 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2832 VMSTATE_UINT32(vga.hw_cursor_x, CirrusVGAState),
2833 VMSTATE_UINT32(vga.hw_cursor_y, CirrusVGAState),
2834 /* XXX: we do not save the bitblt state - we assume we do not save
2835 the state when the blitter is active */
2836 VMSTATE_END_OF_LIST()
2837 }
2838 };
2839
2840 static const VMStateDescription vmstate_pci_cirrus_vga = {
2841 .name = "cirrus_vga",
2842 .version_id = 2,
2843 .minimum_version_id = 2,
2844 .fields = (VMStateField[]) {
2845 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2846 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2847 vmstate_cirrus_vga, CirrusVGAState),
2848 VMSTATE_END_OF_LIST()
2849 }
2850 };
2851
2852 /***************************************
2853 *
2854 * initialize
2855 *
2856 ***************************************/
2857
2858 static void cirrus_reset(void *opaque)
2859 {
2860 CirrusVGAState *s = opaque;
2861
2862 vga_common_reset(&s->vga);
2863 unmap_linear_vram(s);
2864 s->vga.sr[0x06] = 0x0f;
2865 if (s->device_id == CIRRUS_ID_CLGD5446) {
2866 /* 4MB 64 bit memory config, always PCI */
2867 s->vga.sr[0x1F] = 0x2d; // MemClock
2868 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2869 s->vga.sr[0x0f] = 0x98;
2870 s->vga.sr[0x17] = 0x20;
2871 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2872 } else {
2873 s->vga.sr[0x1F] = 0x22; // MemClock
2874 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2875 s->vga.sr[0x17] = s->bustype;
2876 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2877 }
2878 s->vga.cr[0x27] = s->device_id;
2879
2880 s->cirrus_hidden_dac_lockindex = 5;
2881 s->cirrus_hidden_dac_data = 0;
2882 }
2883
2884 static const MemoryRegionOps cirrus_linear_io_ops = {
2885 .read = cirrus_linear_read,
2886 .write = cirrus_linear_write,
2887 .endianness = DEVICE_LITTLE_ENDIAN,
2888 .impl = {
2889 .min_access_size = 1,
2890 .max_access_size = 1,
2891 },
2892 };
2893
2894 static const MemoryRegionOps cirrus_vga_io_ops = {
2895 .read = cirrus_vga_ioport_read,
2896 .write = cirrus_vga_ioport_write,
2897 .endianness = DEVICE_LITTLE_ENDIAN,
2898 .impl = {
2899 .min_access_size = 1,
2900 .max_access_size = 1,
2901 },
2902 };
2903
2904 static void cirrus_init_common(CirrusVGAState *s, Object *owner,
2905 int device_id, int is_pci,
2906 MemoryRegion *system_memory,
2907 MemoryRegion *system_io)
2908 {
2909 int i;
2910 static int inited;
2911
2912 if (!inited) {
2913 inited = 1;
2914 for(i = 0;i < 256; i++)
2915 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2916 rop_to_index[CIRRUS_ROP_0] = 0;
2917 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2918 rop_to_index[CIRRUS_ROP_NOP] = 2;
2919 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2920 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2921 rop_to_index[CIRRUS_ROP_SRC] = 5;
2922 rop_to_index[CIRRUS_ROP_1] = 6;
2923 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2924 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2925 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2926 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2927 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2928 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2929 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2930 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2931 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2932 s->device_id = device_id;
2933 if (is_pci)
2934 s->bustype = CIRRUS_BUSTYPE_PCI;
2935 else
2936 s->bustype = CIRRUS_BUSTYPE_ISA;
2937 }
2938
2939 /* Register ioport 0x3b0 - 0x3df */
2940 memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s,
2941 "cirrus-io", 0x30);
2942 memory_region_set_flush_coalesced(&s->cirrus_vga_io);
2943 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
2944
2945 memory_region_init(&s->low_mem_container, owner,
2946 "cirrus-lowmem-container",
2947 0x20000);
2948
2949 memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s,
2950 "cirrus-low-memory", 0x20000);
2951 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
2952 for (i = 0; i < 2; ++i) {
2953 static const char *names[] = { "vga.bank0", "vga.bank1" };
2954 MemoryRegion *bank = &s->cirrus_bank[i];
2955 memory_region_init_alias(bank, owner, names[i], &s->vga.vram,
2956 0, 0x8000);
2957 memory_region_set_enabled(bank, false);
2958 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2959 bank, 1);
2960 }
2961 memory_region_add_subregion_overlap(system_memory,
2962 0x000a0000,
2963 &s->low_mem_container,
2964 1);
2965 memory_region_set_coalescing(&s->low_mem);
2966
2967 /* I/O handler for LFB */
2968 memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s,
2969 "cirrus-linear-io", s->vga.vram_size_mb
2970 * 1024 * 1024);
2971 memory_region_set_flush_coalesced(&s->cirrus_linear_io);
2972
2973 /* I/O handler for LFB */
2974 memory_region_init_io(&s->cirrus_linear_bitblt_io, owner,
2975 &cirrus_linear_bitblt_io_ops,
2976 s,
2977 "cirrus-bitblt-mmio",
2978 0x400000);
2979 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
2980
2981 /* I/O handler for memory-mapped I/O */
2982 memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s,
2983 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
2984 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
2985
2986 s->real_vram_size =
2987 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2988
2989 /* XXX: s->vga.vram_size must be a power of two */
2990 s->cirrus_addr_mask = s->real_vram_size - 1;
2991 s->linear_mmio_mask = s->real_vram_size - 256;
2992
2993 s->vga.get_bpp = cirrus_get_bpp;
2994 s->vga.get_offsets = cirrus_get_offsets;
2995 s->vga.get_resolution = cirrus_get_resolution;
2996 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2997 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
2998
2999 qemu_register_reset(cirrus_reset, s);
3000 }
3001
3002 /***************************************
3003 *
3004 * ISA bus support
3005 *
3006 ***************************************/
3007
3008 static void isa_cirrus_vga_realizefn(DeviceState *dev, Error **errp)
3009 {
3010 ISADevice *isadev = ISA_DEVICE(dev);
3011 ISACirrusVGAState *d = ISA_CIRRUS_VGA(dev);
3012 VGACommonState *s = &d->cirrus_vga.vga;
3013
3014 /* follow real hardware, cirrus card emulated has 4 MB video memory.
3015 Also accept 8 MB/16 MB for backward compatibility. */
3016 if (s->vram_size_mb != 4 && s->vram_size_mb != 8 &&
3017 s->vram_size_mb != 16) {
3018 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
3019 s->vram_size_mb);
3020 return;
3021 }
3022 vga_common_init(s, OBJECT(dev), true);
3023 cirrus_init_common(&d->cirrus_vga, OBJECT(dev), CIRRUS_ID_CLGD5430, 0,
3024 isa_address_space(isadev),
3025 isa_address_space_io(isadev));
3026 s->con = graphic_console_init(dev, 0, s->hw_ops, s);
3027 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
3028 /* XXX ISA-LFB support */
3029 /* FIXME not qdev yet */
3030 }
3031
3032 static Property isa_cirrus_vga_properties[] = {
3033 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState,
3034 cirrus_vga.vga.vram_size_mb, 8),
3035 DEFINE_PROP_END_OF_LIST(),
3036 };
3037
3038 static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data)
3039 {
3040 DeviceClass *dc = DEVICE_CLASS(klass);
3041
3042 dc->vmsd = &vmstate_cirrus_vga;
3043 dc->realize = isa_cirrus_vga_realizefn;
3044 dc->props = isa_cirrus_vga_properties;
3045 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
3046 }
3047
3048 static const TypeInfo isa_cirrus_vga_info = {
3049 .name = TYPE_ISA_CIRRUS_VGA,
3050 .parent = TYPE_ISA_DEVICE,
3051 .instance_size = sizeof(ISACirrusVGAState),
3052 .class_init = isa_cirrus_vga_class_init,
3053 };
3054
3055 /***************************************
3056 *
3057 * PCI bus support
3058 *
3059 ***************************************/
3060
3061 static void pci_cirrus_vga_realize(PCIDevice *dev, Error **errp)
3062 {
3063 PCICirrusVGAState *d = PCI_CIRRUS_VGA(dev);
3064 CirrusVGAState *s = &d->cirrus_vga;
3065 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
3066 int16_t device_id = pc->device_id;
3067
3068 /* follow real hardware, cirrus card emulated has 4 MB video memory.
3069 Also accept 8 MB/16 MB for backward compatibility. */
3070 if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 &&
3071 s->vga.vram_size_mb != 16) {
3072 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
3073 s->vga.vram_size_mb);
3074 return;
3075 }
3076 /* setup VGA */
3077 vga_common_init(&s->vga, OBJECT(dev), true);
3078 cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
3079 pci_address_space_io(dev));
3080 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga);
3081
3082 /* setup PCI */
3083
3084 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000);
3085
3086 /* XXX: add byte swapping apertures */
3087 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
3088 memory_region_add_subregion(&s->pci_bar, 0x1000000,
3089 &s->cirrus_linear_bitblt_io);
3090
3091 /* setup memory space */
3092 /* memory #0 LFB */
3093 /* memory #1 memory-mapped I/O */
3094 /* XXX: s->vga.vram_size must be a power of two */
3095 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
3096 if (device_id == CIRRUS_ID_CLGD5446) {
3097 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
3098 }
3099 }
3100
3101 static Property pci_vga_cirrus_properties[] = {
3102 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
3103 cirrus_vga.vga.vram_size_mb, 8),
3104 DEFINE_PROP_END_OF_LIST(),
3105 };
3106
3107 static void cirrus_vga_class_init(ObjectClass *klass, void *data)
3108 {
3109 DeviceClass *dc = DEVICE_CLASS(klass);
3110 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3111
3112 k->realize = pci_cirrus_vga_realize;
3113 k->romfile = VGABIOS_CIRRUS_FILENAME;
3114 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
3115 k->device_id = CIRRUS_ID_CLGD5446;
3116 k->class_id = PCI_CLASS_DISPLAY_VGA;
3117 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
3118 dc->desc = "Cirrus CLGD 54xx VGA";
3119 dc->vmsd = &vmstate_pci_cirrus_vga;
3120 dc->props = pci_vga_cirrus_properties;
3121 dc->hotpluggable = false;
3122 }
3123
3124 static const TypeInfo cirrus_vga_info = {
3125 .name = TYPE_PCI_CIRRUS_VGA,
3126 .parent = TYPE_PCI_DEVICE,
3127 .instance_size = sizeof(PCICirrusVGAState),
3128 .class_init = cirrus_vga_class_init,
3129 };
3130
3131 static void cirrus_vga_register_types(void)
3132 {
3133 type_register_static(&isa_cirrus_vga_info);
3134 type_register_static(&cirrus_vga_info);
3135 }
3136
3137 type_init(cirrus_vga_register_types)
AR7 emulation for QEMU