2 * ColdFire UART emulation.
4 * Copyright (c) 2007 CodeSourcery.
6 * This code is licensed under the GPL
8 #include "qemu/osdep.h"
10 #include "hw/sysbus.h"
11 #include "hw/m68k/mcf.h"
12 #include "chardev/char-fe.h"
13 #include "exec/address-spaces.h"
16 SysBusDevice parent_obj
;
35 #define TYPE_MCF_UART "mcf-uart"
36 #define MCF_UART(obj) OBJECT_CHECK(mcf_uart_state, (obj), TYPE_MCF_UART)
38 /* UART Status Register bits. */
39 #define MCF_UART_RxRDY 0x01
40 #define MCF_UART_FFULL 0x02
41 #define MCF_UART_TxRDY 0x04
42 #define MCF_UART_TxEMP 0x08
43 #define MCF_UART_OE 0x10
44 #define MCF_UART_PE 0x20
45 #define MCF_UART_FE 0x40
46 #define MCF_UART_RB 0x80
48 /* Interrupt flags. */
49 #define MCF_UART_TxINT 0x01
50 #define MCF_UART_RxINT 0x02
51 #define MCF_UART_DBINT 0x04
52 #define MCF_UART_COSINT 0x80
55 #define MCF_UART_BC0 0x01
56 #define MCF_UART_BC1 0x02
57 #define MCF_UART_PT 0x04
58 #define MCF_UART_PM0 0x08
59 #define MCF_UART_PM1 0x10
60 #define MCF_UART_ERR 0x20
61 #define MCF_UART_RxIRQ 0x40
62 #define MCF_UART_RxRTS 0x80
64 static void mcf_uart_update(mcf_uart_state
*s
)
66 s
->isr
&= ~(MCF_UART_TxINT
| MCF_UART_RxINT
);
67 if (s
->sr
& MCF_UART_TxRDY
)
68 s
->isr
|= MCF_UART_TxINT
;
69 if ((s
->sr
& ((s
->mr
[0] & MCF_UART_RxIRQ
)
70 ? MCF_UART_FFULL
: MCF_UART_RxRDY
)) != 0)
71 s
->isr
|= MCF_UART_RxINT
;
73 qemu_set_irq(s
->irq
, (s
->isr
& s
->imr
) != 0);
76 uint64_t mcf_uart_read(void *opaque
, hwaddr addr
,
79 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
80 switch (addr
& 0x3f) {
82 return s
->mr
[s
->current_mr
];
95 for (i
= 0; i
< s
->fifo_len
; i
++)
96 s
->fifo
[i
] = s
->fifo
[i
+ 1];
97 s
->sr
&= ~MCF_UART_FFULL
;
99 s
->sr
&= ~MCF_UART_RxRDY
;
101 qemu_chr_fe_accept_input(&s
->chr
);
105 /* TODO: Implement IPCR. */
118 /* Update TxRDY flag and set data if present and enabled. */
119 static void mcf_uart_do_tx(mcf_uart_state
*s
)
121 if (s
->tx_enabled
&& (s
->sr
& MCF_UART_TxEMP
) == 0) {
122 /* XXX this blocks entire thread. Rewrite to use
123 * qemu_chr_fe_write and background I/O callbacks */
124 qemu_chr_fe_write_all(&s
->chr
, (unsigned char *)&s
->tb
, 1);
125 s
->sr
|= MCF_UART_TxEMP
;
128 s
->sr
|= MCF_UART_TxRDY
;
130 s
->sr
&= ~MCF_UART_TxRDY
;
134 static void mcf_do_command(mcf_uart_state
*s
, uint8_t cmd
)
137 switch ((cmd
>> 4) & 7) {
140 case 1: /* Reset mode register pointer. */
143 case 2: /* Reset receiver. */
146 s
->sr
&= ~(MCF_UART_RxRDY
| MCF_UART_FFULL
);
148 case 3: /* Reset transmitter. */
150 s
->sr
|= MCF_UART_TxEMP
;
151 s
->sr
&= ~MCF_UART_TxRDY
;
153 case 4: /* Reset error status. */
155 case 5: /* Reset break-change interrupt. */
156 s
->isr
&= ~MCF_UART_DBINT
;
158 case 6: /* Start break. */
159 case 7: /* Stop break. */
163 /* Transmitter command. */
164 switch ((cmd
>> 2) & 3) {
167 case 1: /* Enable. */
171 case 2: /* Disable. */
175 case 3: /* Reserved. */
176 fprintf(stderr
, "mcf_uart: Bad TX command\n");
180 /* Receiver command. */
184 case 1: /* Enable. */
190 case 3: /* Reserved. */
191 fprintf(stderr
, "mcf_uart: Bad RX command\n");
196 void mcf_uart_write(void *opaque
, hwaddr addr
,
197 uint64_t val
, unsigned size
)
199 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
200 switch (addr
& 0x3f) {
202 s
->mr
[s
->current_mr
] = val
;
206 /* CSR is ignored. */
208 case 0x08: /* Command Register. */
209 mcf_do_command(s
, val
);
211 case 0x0c: /* Transmit Buffer. */
212 s
->sr
&= ~MCF_UART_TxEMP
;
217 /* ACR is ignored. */
228 static void mcf_uart_reset(DeviceState
*dev
)
230 mcf_uart_state
*s
= MCF_UART(dev
);
235 s
->sr
= MCF_UART_TxEMP
;
242 static void mcf_uart_push_byte(mcf_uart_state
*s
, uint8_t data
)
244 /* Break events overwrite the last byte if the fifo is full. */
245 if (s
->fifo_len
== 4)
248 s
->fifo
[s
->fifo_len
] = data
;
250 s
->sr
|= MCF_UART_RxRDY
;
251 if (s
->fifo_len
== 4)
252 s
->sr
|= MCF_UART_FFULL
;
257 static void mcf_uart_event(void *opaque
, int event
)
259 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
262 case CHR_EVENT_BREAK
:
263 s
->isr
|= MCF_UART_DBINT
;
264 mcf_uart_push_byte(s
, 0);
271 static int mcf_uart_can_receive(void *opaque
)
273 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
275 return s
->rx_enabled
&& (s
->sr
& MCF_UART_FFULL
) == 0;
278 static void mcf_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
280 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
282 mcf_uart_push_byte(s
, buf
[0]);
285 static const MemoryRegionOps mcf_uart_ops
= {
286 .read
= mcf_uart_read
,
287 .write
= mcf_uart_write
,
288 .endianness
= DEVICE_NATIVE_ENDIAN
,
291 static void mcf_uart_instance_init(Object
*obj
)
293 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
294 mcf_uart_state
*s
= MCF_UART(dev
);
296 memory_region_init_io(&s
->iomem
, obj
, &mcf_uart_ops
, s
, "uart", 0x40);
297 sysbus_init_mmio(dev
, &s
->iomem
);
299 sysbus_init_irq(dev
, &s
->irq
);
302 static void mcf_uart_realize(DeviceState
*dev
, Error
**errp
)
304 mcf_uart_state
*s
= MCF_UART(dev
);
306 qemu_chr_fe_set_handlers(&s
->chr
, mcf_uart_can_receive
, mcf_uart_receive
,
307 mcf_uart_event
, NULL
, s
, NULL
, true);
310 static Property mcf_uart_properties
[] = {
311 DEFINE_PROP_CHR("chardev", mcf_uart_state
, chr
),
312 DEFINE_PROP_END_OF_LIST(),
315 static void mcf_uart_class_init(ObjectClass
*oc
, void *data
)
317 DeviceClass
*dc
= DEVICE_CLASS(oc
);
319 dc
->realize
= mcf_uart_realize
;
320 dc
->reset
= mcf_uart_reset
;
321 dc
->props
= mcf_uart_properties
;
322 set_bit(DEVICE_CATEGORY_INPUT
, dc
->categories
);
325 static const TypeInfo mcf_uart_info
= {
326 .name
= TYPE_MCF_UART
,
327 .parent
= TYPE_SYS_BUS_DEVICE
,
328 .instance_size
= sizeof(mcf_uart_state
),
329 .instance_init
= mcf_uart_instance_init
,
330 .class_init
= mcf_uart_class_init
,
333 static void mcf_uart_register(void)
335 type_register_static(&mcf_uart_info
);
338 type_init(mcf_uart_register
)
340 void *mcf_uart_init(qemu_irq irq
, Chardev
*chrdrv
)
344 dev
= qdev_create(NULL
, TYPE_MCF_UART
);
346 qdev_prop_set_chr(dev
, "chardev", chrdrv
);
348 qdev_init_nofail(dev
);
350 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, irq
);
355 void mcf_uart_mm_init(hwaddr base
, qemu_irq irq
, Chardev
*chrdrv
)
359 dev
= mcf_uart_init(irq
, chrdrv
);
360 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);