4 * Copyright (c) 2005 Samuel Tardieu
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
25 #include "qemu-common.h"
26 #include "migration/vmstate.h"
27 #include "exec/exec-all.h"
28 #include "fpu/softfloat.h"
31 static void superh_cpu_set_pc(CPUState
*cs
, vaddr value
)
33 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
38 static void superh_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
40 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
43 cpu
->env
.flags
= tb
->flags
& TB_FLAG_ENVFLAGS_MASK
;
46 static bool superh_cpu_has_work(CPUState
*cs
)
48 return cs
->interrupt_request
& CPU_INTERRUPT_HARD
;
51 /* CPUClass::reset() */
52 static void superh_cpu_reset(CPUState
*s
)
54 SuperHCPU
*cpu
= SUPERH_CPU(s
);
55 SuperHCPUClass
*scc
= SUPERH_CPU_GET_CLASS(cpu
);
56 CPUSH4State
*env
= &cpu
->env
;
60 memset(env
, 0, offsetof(CPUSH4State
, end_reset_fields
));
63 #if defined(CONFIG_USER_ONLY)
64 env
->fpscr
= FPSCR_PR
; /* value for userspace according to the kernel */
65 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
); /* ?! */
67 env
->sr
= (1u << SR_MD
) | (1u << SR_RB
) | (1u << SR_BL
) |
68 (1u << SR_I3
) | (1u << SR_I2
) | (1u << SR_I1
) | (1u << SR_I0
);
69 env
->fpscr
= FPSCR_DN
| FPSCR_RM_ZERO
; /* CPU reset value according to SH4 manual */
70 set_float_rounding_mode(float_round_to_zero
, &env
->fp_status
);
71 set_flush_to_zero(1, &env
->fp_status
);
73 set_default_nan_mode(1, &env
->fp_status
);
74 set_snan_bit_is_one(1, &env
->fp_status
);
77 static void superh_cpu_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
79 info
->mach
= bfd_mach_sh4
;
80 info
->print_insn
= print_insn_sh
;
83 typedef struct SuperHCPUListState
{
84 fprintf_function cpu_fprintf
;
88 static void superh_cpu_list_entry(gpointer data
, gpointer user_data
)
90 SuperHCPUListState
*s
= user_data
;
91 const char *typename
= object_class_get_name(OBJECT_CLASS(data
));
92 int len
= strlen(typename
) - strlen(SUPERH_CPU_TYPE_SUFFIX
);
94 (*s
->cpu_fprintf
)(s
->file
, "%.*s\n", len
, typename
);
97 void sh4_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
99 SuperHCPUListState s
= {
100 .cpu_fprintf
= cpu_fprintf
,
105 list
= object_class_get_list_sorted(TYPE_SUPERH_CPU
, false);
106 g_slist_foreach(list
, superh_cpu_list_entry
, &s
);
110 static ObjectClass
*superh_cpu_class_by_name(const char *cpu_model
)
113 char *s
, *typename
= NULL
;
115 s
= g_ascii_strdown(cpu_model
, -1);
116 if (strcmp(s
, "any") == 0) {
117 oc
= object_class_by_name(TYPE_SH7750R_CPU
);
121 typename
= g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s
);
122 oc
= object_class_by_name(typename
);
123 if (oc
!= NULL
&& object_class_is_abstract(oc
)) {
133 static void sh7750r_cpu_initfn(Object
*obj
)
135 SuperHCPU
*cpu
= SUPERH_CPU(obj
);
136 CPUSH4State
*env
= &cpu
->env
;
138 env
->id
= SH_CPU_SH7750R
;
139 env
->features
= SH_FEATURE_BCR3_AND_BCR4
;
142 static void sh7750r_class_init(ObjectClass
*oc
, void *data
)
144 SuperHCPUClass
*scc
= SUPERH_CPU_CLASS(oc
);
146 scc
->pvr
= 0x00050000;
147 scc
->prr
= 0x00000100;
148 scc
->cvr
= 0x00110000;
151 static void sh7751r_cpu_initfn(Object
*obj
)
153 SuperHCPU
*cpu
= SUPERH_CPU(obj
);
154 CPUSH4State
*env
= &cpu
->env
;
156 env
->id
= SH_CPU_SH7751R
;
157 env
->features
= SH_FEATURE_BCR3_AND_BCR4
;
160 static void sh7751r_class_init(ObjectClass
*oc
, void *data
)
162 SuperHCPUClass
*scc
= SUPERH_CPU_CLASS(oc
);
164 scc
->pvr
= 0x04050005;
165 scc
->prr
= 0x00000113;
166 scc
->cvr
= 0x00110000; /* Neutered caches, should be 0x20480000 */
169 static void sh7785_cpu_initfn(Object
*obj
)
171 SuperHCPU
*cpu
= SUPERH_CPU(obj
);
172 CPUSH4State
*env
= &cpu
->env
;
174 env
->id
= SH_CPU_SH7785
;
175 env
->features
= SH_FEATURE_SH4A
;
178 static void sh7785_class_init(ObjectClass
*oc
, void *data
)
180 SuperHCPUClass
*scc
= SUPERH_CPU_CLASS(oc
);
182 scc
->pvr
= 0x10300700;
183 scc
->prr
= 0x00000200;
184 scc
->cvr
= 0x71440211;
187 static void superh_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
189 CPUState
*cs
= CPU(dev
);
190 SuperHCPUClass
*scc
= SUPERH_CPU_GET_CLASS(dev
);
191 Error
*local_err
= NULL
;
193 cpu_exec_realizefn(cs
, &local_err
);
194 if (local_err
!= NULL
) {
195 error_propagate(errp
, local_err
);
202 scc
->parent_realize(dev
, errp
);
205 static void superh_cpu_initfn(Object
*obj
)
207 CPUState
*cs
= CPU(obj
);
208 SuperHCPU
*cpu
= SUPERH_CPU(obj
);
209 CPUSH4State
*env
= &cpu
->env
;
213 env
->movcal_backup_tail
= &(env
->movcal_backup
);
216 static const VMStateDescription vmstate_sh_cpu
= {
221 static void superh_cpu_class_init(ObjectClass
*oc
, void *data
)
223 DeviceClass
*dc
= DEVICE_CLASS(oc
);
224 CPUClass
*cc
= CPU_CLASS(oc
);
225 SuperHCPUClass
*scc
= SUPERH_CPU_CLASS(oc
);
227 device_class_set_parent_realize(dc
, superh_cpu_realizefn
,
228 &scc
->parent_realize
);
230 scc
->parent_reset
= cc
->reset
;
231 cc
->reset
= superh_cpu_reset
;
233 cc
->class_by_name
= superh_cpu_class_by_name
;
234 cc
->has_work
= superh_cpu_has_work
;
235 cc
->do_interrupt
= superh_cpu_do_interrupt
;
236 cc
->cpu_exec_interrupt
= superh_cpu_exec_interrupt
;
237 cc
->dump_state
= superh_cpu_dump_state
;
238 cc
->set_pc
= superh_cpu_set_pc
;
239 cc
->synchronize_from_tb
= superh_cpu_synchronize_from_tb
;
240 cc
->gdb_read_register
= superh_cpu_gdb_read_register
;
241 cc
->gdb_write_register
= superh_cpu_gdb_write_register
;
242 #ifdef CONFIG_USER_ONLY
243 cc
->handle_mmu_fault
= superh_cpu_handle_mmu_fault
;
245 cc
->do_unaligned_access
= superh_cpu_do_unaligned_access
;
246 cc
->get_phys_page_debug
= superh_cpu_get_phys_page_debug
;
248 cc
->disas_set_info
= superh_cpu_disas_set_info
;
249 cc
->tcg_initialize
= sh4_translate_init
;
251 cc
->gdb_num_core_regs
= 59;
253 dc
->vmsd
= &vmstate_sh_cpu
;
256 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
259 .parent = TYPE_SUPERH_CPU, \
260 .class_init = cinit, \
261 .instance_init = initfn, \
263 static const TypeInfo superh_cpu_type_infos
[] = {
265 .name
= TYPE_SUPERH_CPU
,
267 .instance_size
= sizeof(SuperHCPU
),
268 .instance_init
= superh_cpu_initfn
,
270 .class_size
= sizeof(SuperHCPUClass
),
271 .class_init
= superh_cpu_class_init
,
273 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU
, sh7750r_class_init
,
275 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU
, sh7751r_class_init
,
277 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU
, sh7785_class_init
,
282 DEFINE_TYPES(superh_cpu_type_infos
)