hw/dma/sun4m_iommu.c

   1 /*
   2  * QEMU Sun4m iommu emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sparc/sun4m.h"
  27 #include "hw/sysbus.h"
  28 #include "exec/address-spaces.h"
  29 #include "trace.h"
  30
  31 /*
  32  * I/O MMU used by Sun4m systems
  33  *
  34  * Chipset docs:
  35  * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
  36  * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
  37  */
  38
  39 #define IOMMU_CTRL          (0x0000 >> 2)
  40 #define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
  41 #define IOMMU_CTRL_VERS     0x0f000000 /* Version */
  42 #define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
  43 #define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
  44 #define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
  45 #define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
  46 #define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
  47 #define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
  48 #define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
  49 #define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
  50 #define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
  51 #define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
  52 #define IOMMU_CTRL_MASK     0x0000001d
  53
  54 #define IOMMU_BASE          (0x0004 >> 2)
  55 #define IOMMU_BASE_MASK     0x07fffc00
  56
  57 #define IOMMU_TLBFLUSH      (0x0014 >> 2)
  58 #define IOMMU_TLBFLUSH_MASK 0xffffffff
  59
  60 #define IOMMU_PGFLUSH       (0x0018 >> 2)
  61 #define IOMMU_PGFLUSH_MASK  0xffffffff
  62
  63 #define IOMMU_AFSR          (0x1000 >> 2)
  64 #define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
  65 #define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after
  66                                           transaction */
  67 #define IOMMU_AFSR_TO       0x20000000 /* Write access took more than
  68                                           12.8 us. */
  69 #define IOMMU_AFSR_BE       0x10000000 /* Write access received error
  70                                           acknowledge */
  71 #define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
  72 #define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
  73 #define IOMMU_AFSR_RESV     0x00800000 /* Reserved, forced to 0x8 by
  74                                           hardware */
  75 #define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
  76 #define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
  77 #define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
  78 #define IOMMU_AFSR_MASK     0xff0fffff
  79
  80 #define IOMMU_AFAR          (0x1004 >> 2)
  81
  82 #define IOMMU_AER           (0x1008 >> 2) /* Arbiter Enable Register */
  83 #define IOMMU_AER_EN_P0_ARB 0x00000001    /* MBus master 0x8 (Always 1) */
  84 #define IOMMU_AER_EN_P1_ARB 0x00000002    /* MBus master 0x9 */
  85 #define IOMMU_AER_EN_P2_ARB 0x00000004    /* MBus master 0xa */
  86 #define IOMMU_AER_EN_P3_ARB 0x00000008    /* MBus master 0xb */
  87 #define IOMMU_AER_EN_0      0x00010000    /* SBus slot 0 */
  88 #define IOMMU_AER_EN_1      0x00020000    /* SBus slot 1 */
  89 #define IOMMU_AER_EN_2      0x00040000    /* SBus slot 2 */
  90 #define IOMMU_AER_EN_3      0x00080000    /* SBus slot 3 */
  91 #define IOMMU_AER_EN_F      0x00100000    /* SBus on-board */
  92 #define IOMMU_AER_SBW       0x80000000    /* S-to-M asynchronous writes */
  93 #define IOMMU_AER_MASK      0x801f000f
  94
  95 #define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
  96 #define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
  97 #define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
  98 #define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
  99 #define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when
 100                                           bypass enabled */
 101 #define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
 102 #define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
 103 #define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
 104                                           produced by this device as pure
 105                                           physical. */
 106 #define IOMMU_SBCFG_MASK    0x00010003
 107
 108 #define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
 109 #define IOMMU_ARBEN_MASK    0x001f0000
 110 #define IOMMU_MID           0x00000008
 111
 112 #define IOMMU_MASK_ID       (0x3018 >> 2) /* Mask ID */
 113 #define IOMMU_MASK_ID_MASK  0x00ffffff
 114
 115 #define IOMMU_MSII_MASK     0x26000000 /* microSPARC II mask number */
 116 #define IOMMU_TS_MASK       0x23000000 /* turboSPARC mask number */
 117
 118 /* The format of an iopte in the page tables */
 119 #define IOPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12]) */
 120 #define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or
 121                                           Viking/MXCC) */
 122 #define IOPTE_WRITE         0x00000004 /* Writable */
 123 #define IOPTE_VALID         0x00000002 /* IOPTE is valid */
 124 #define IOPTE_WAZ           0x00000001 /* Write as zeros */
 125
 126 #define IOMMU_PAGE_SHIFT    12
 127 #define IOMMU_PAGE_SIZE     (1 << IOMMU_PAGE_SHIFT)
 128 #define IOMMU_PAGE_MASK     ~(IOMMU_PAGE_SIZE - 1)
 129
 130 static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
 131                                unsigned size)
 132 {
 133     IOMMUState *s = opaque;
 134     hwaddr saddr;
 135     uint32_t ret;
 136
 137     saddr = addr >> 2;
 138     switch (saddr) {
 139     default:
 140         ret = s->regs[saddr];
 141         break;
 142     case IOMMU_AFAR:
 143     case IOMMU_AFSR:
 144         ret = s->regs[saddr];
 145         qemu_irq_lower(s->irq);
 146         break;
 147     }
 148     trace_sun4m_iommu_mem_readl(saddr, ret);
 149     return ret;
 150 }
 151
 152 static void iommu_mem_write(void *opaque, hwaddr addr,
 153                             uint64_t val, unsigned size)
 154 {
 155     IOMMUState *s = opaque;
 156     hwaddr saddr;
 157
 158     saddr = addr >> 2;
 159     trace_sun4m_iommu_mem_writel(saddr, val);
 160     switch (saddr) {
 161     case IOMMU_CTRL:
 162         switch (val & IOMMU_CTRL_RNGE) {
 163         case IOMMU_RNGE_16MB:
 164             s->iostart = 0xffffffffff000000ULL;
 165             break;
 166         case IOMMU_RNGE_32MB:
 167             s->iostart = 0xfffffffffe000000ULL;
 168             break;
 169         case IOMMU_RNGE_64MB:
 170             s->iostart = 0xfffffffffc000000ULL;
 171             break;
 172         case IOMMU_RNGE_128MB:
 173             s->iostart = 0xfffffffff8000000ULL;
 174             break;
 175         case IOMMU_RNGE_256MB:
 176             s->iostart = 0xfffffffff0000000ULL;
 177             break;
 178         case IOMMU_RNGE_512MB:
 179             s->iostart = 0xffffffffe0000000ULL;
 180             break;
 181         case IOMMU_RNGE_1GB:
 182             s->iostart = 0xffffffffc0000000ULL;
 183             break;
 184         default:
 185         case IOMMU_RNGE_2GB:
 186             s->iostart = 0xffffffff80000000ULL;
 187             break;
 188         }
 189         trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
 190         s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
 191         break;
 192     case IOMMU_BASE:
 193         s->regs[saddr] = val & IOMMU_BASE_MASK;
 194         break;
 195     case IOMMU_TLBFLUSH:
 196         trace_sun4m_iommu_mem_writel_tlbflush(val);
 197         s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
 198         break;
 199     case IOMMU_PGFLUSH:
 200         trace_sun4m_iommu_mem_writel_pgflush(val);
 201         s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
 202         break;
 203     case IOMMU_AFAR:
 204         s->regs[saddr] = val;
 205         qemu_irq_lower(s->irq);
 206         break;
 207     case IOMMU_AER:
 208         s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
 209         break;
 210     case IOMMU_AFSR:
 211         s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
 212         qemu_irq_lower(s->irq);
 213         break;
 214     case IOMMU_SBCFG0:
 215     case IOMMU_SBCFG1:
 216     case IOMMU_SBCFG2:
 217     case IOMMU_SBCFG3:
 218         s->regs[saddr] = val & IOMMU_SBCFG_MASK;
 219         break;
 220     case IOMMU_ARBEN:
 221         // XXX implement SBus probing: fault when reading unmapped
 222         // addresses, fault cause and address stored to MMU/IOMMU
 223         s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
 224         break;
 225     case IOMMU_MASK_ID:
 226         s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
 227         break;
 228     default:
 229         s->regs[saddr] = val;
 230         break;
 231     }
 232 }
 233
 234 static const MemoryRegionOps iommu_mem_ops = {
 235     .read = iommu_mem_read,
 236     .write = iommu_mem_write,
 237     .endianness = DEVICE_NATIVE_ENDIAN,
 238     .valid = {
 239         .min_access_size = 4,
 240         .max_access_size = 4,
 241     },
 242 };
 243
 244 static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
 245 {
 246     uint32_t ret;
 247     hwaddr iopte;
 248     hwaddr pa = addr;
 249
 250     iopte = s->regs[IOMMU_BASE] << 4;
 251     addr &= ~s->iostart;
 252     iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
 253     ret = address_space_ldl_be(&address_space_memory, iopte,
 254                                MEMTXATTRS_UNSPECIFIED, NULL);
 255     trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
 256     return ret;
 257 }
 258
 259 static hwaddr iommu_translate_pa(hwaddr addr,
 260                                              uint32_t pte)
 261 {
 262     hwaddr pa;
 263
 264     pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
 265     trace_sun4m_iommu_translate_pa(addr, pa, pte);
 266     return pa;
 267 }
 268
 269 static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
 270                            int is_write)
 271 {
 272     trace_sun4m_iommu_bad_addr(addr);
 273     s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
 274         IOMMU_AFSR_FAV;
 275     if (!is_write)
 276         s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
 277     s->regs[IOMMU_AFAR] = addr;
 278     qemu_irq_raise(s->irq);
 279 }
 280
 281 /* Called from RCU critical section */
 282 static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu,
 283                                            hwaddr addr,
 284                                            IOMMUAccessFlags flags)
 285 {
 286     IOMMUState *is = container_of(iommu, IOMMUState, iommu);
 287     hwaddr page, pa;
 288     int is_write = (flags & IOMMU_WO) ? 1 : 0;
 289     uint32_t pte;
 290     IOMMUTLBEntry ret = {
 291         .target_as = &address_space_memory,
 292         .iova = 0,
 293         .translated_addr = 0,
 294         .addr_mask = ~(hwaddr)0,
 295         .perm = IOMMU_NONE,
 296     };
 297
 298     page = addr & IOMMU_PAGE_MASK;
 299     pte = iommu_page_get_flags(is, page);
 300     if (!(pte & IOPTE_VALID)) {
 301         iommu_bad_addr(is, page, is_write);
 302         return ret;
 303     }
 304
 305     pa = iommu_translate_pa(addr, pte);
 306     if (is_write && !(pte & IOPTE_WRITE)) {
 307         iommu_bad_addr(is, page, is_write);
 308         return ret;
 309     }
 310
 311     if (pte & IOPTE_WRITE) {
 312         ret.perm = IOMMU_RW;
 313     } else {
 314         ret.perm = IOMMU_RO;
 315     }
 316
 317     ret.iova = page;
 318     ret.translated_addr = pa;
 319     ret.addr_mask = ~IOMMU_PAGE_MASK;
 320
 321     return ret;
 322 }
 323
 324 static const VMStateDescription vmstate_iommu = {
 325     .name ="iommu",
 326     .version_id = 2,
 327     .minimum_version_id = 2,
 328     .fields = (VMStateField[]) {
 329         VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
 330         VMSTATE_UINT64(iostart, IOMMUState),
 331         VMSTATE_END_OF_LIST()
 332     }
 333 };
 334
 335 static void iommu_reset(DeviceState *d)
 336 {
 337     IOMMUState *s = SUN4M_IOMMU(d);
 338
 339     memset(s->regs, 0, IOMMU_NREGS * 4);
 340     s->iostart = 0;
 341     s->regs[IOMMU_CTRL] = s->version;
 342     s->regs[IOMMU_ARBEN] = IOMMU_MID;
 343     s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
 344     s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
 345     s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
 346 }
 347
 348 static void iommu_init(Object *obj)
 349 {
 350     IOMMUState *s = SUN4M_IOMMU(obj);
 351     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 352
 353     memory_region_init_iommu(&s->iommu, sizeof(s->iommu),
 354                              TYPE_SUN4M_IOMMU_MEMORY_REGION, OBJECT(dev),
 355                              "iommu-sun4m", UINT64_MAX);
 356     address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as");
 357
 358     sysbus_init_irq(dev, &s->irq);
 359
 360     memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu",
 361                           IOMMU_NREGS * sizeof(uint32_t));
 362     sysbus_init_mmio(dev, &s->iomem);
 363 }
 364
 365 static Property iommu_properties[] = {
 366     DEFINE_PROP_UINT32("version", IOMMUState, version, 0),
 367     DEFINE_PROP_END_OF_LIST(),
 368 };
 369
 370 static void iommu_class_init(ObjectClass *klass, void *data)
 371 {
 372     DeviceClass *dc = DEVICE_CLASS(klass);
 373
 374     dc->reset = iommu_reset;
 375     dc->vmsd = &vmstate_iommu;
 376     dc->props = iommu_properties;
 377 }
 378
 379 static const TypeInfo iommu_info = {
 380     .name          = TYPE_SUN4M_IOMMU,
 381     .parent        = TYPE_SYS_BUS_DEVICE,
 382     .instance_size = sizeof(IOMMUState),
 383     .instance_init = iommu_init,
 384     .class_init    = iommu_class_init,
 385 };
 386
 387 static void sun4m_iommu_memory_region_class_init(ObjectClass *klass, void *data)
 388 {
 389     IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
 390
 391     imrc->translate = sun4m_translate_iommu;
 392 }
 393
 394 static const TypeInfo sun4m_iommu_memory_region_info = {
 395     .parent = TYPE_IOMMU_MEMORY_REGION,
 396     .name = TYPE_SUN4M_IOMMU_MEMORY_REGION,
 397     .class_init = sun4m_iommu_memory_region_class_init,
 398 };
 399
 400 static void iommu_register_types(void)
 401 {
 402     type_register_static(&iommu_info);
 403     type_register_static(&sun4m_iommu_memory_region_info);
 404 }
 405
 406 type_init(iommu_register_types)