hw/isa/vt82c686.c

   1 /*
   2  * VT82C686B south bridge support
   3  *
   4  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
   5  * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
   6  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
   7  * This code is licensed under the GNU GPL v2.
   8  *
   9  * Contributions after 2012-01-13 are licensed under the terms of the
  10  * GNU GPL, version 2 or (at your option) any later version.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "hw/isa/vt82c686.h"
  15 #include "hw/pci/pci.h"
  16 #include "hw/qdev-properties.h"
  17 #include "hw/isa/isa.h"
  18 #include "hw/isa/superio.h"
  19 #include "migration/vmstate.h"
  20 #include "hw/isa/apm.h"
  21 #include "hw/acpi/acpi.h"
  22 #include "hw/i2c/pm_smbus.h"
  23 #include "qapi/error.h"
  24 #include "qemu/module.h"
  25 #include "qemu/timer.h"
  26 #include "exec/address-spaces.h"
  27 #include "trace.h"
  28
  29 OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM)
  30
  31 struct VT686PMState {
  32     PCIDevice dev;
  33     MemoryRegion io;
  34     ACPIREGS ar;
  35     APMState apm;
  36     PMSMBus smb;
  37     uint32_t smb_io_base;
  38 };
  39
  40 static void pm_io_space_update(VT686PMState *s)
  41 {
  42     uint32_t pm_io_base;
  43
  44     pm_io_base = pci_get_long(s->dev.config + 0x40);
  45     pm_io_base &= 0xffc0;
  46
  47     memory_region_transaction_begin();
  48     memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
  49     memory_region_set_address(&s->io, pm_io_base);
  50     memory_region_transaction_commit();
  51 }
  52
  53 static int vmstate_acpi_post_load(void *opaque, int version_id)
  54 {
  55     VT686PMState *s = opaque;
  56
  57     pm_io_space_update(s);
  58     return 0;
  59 }
  60
  61 static const VMStateDescription vmstate_acpi = {
  62     .name = "vt82c686b_pm",
  63     .version_id = 1,
  64     .minimum_version_id = 1,
  65     .post_load = vmstate_acpi_post_load,
  66     .fields = (VMStateField[]) {
  67         VMSTATE_PCI_DEVICE(dev, VT686PMState),
  68         VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
  69         VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
  70         VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
  71         VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
  72         VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState),
  73         VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
  74         VMSTATE_END_OF_LIST()
  75     }
  76 };
  77
  78 static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len)
  79 {
  80     trace_via_pm_write(addr, val, len);
  81     pci_default_write_config(d, addr, val, len);
  82 }
  83
  84 static void pm_update_sci(VT686PMState *s)
  85 {
  86     int sci_level, pmsts;
  87
  88     pmsts = acpi_pm1_evt_get_sts(&s->ar);
  89     sci_level = (((pmsts & s->ar.pm1.evt.en) &
  90                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  91                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  92                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  93                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
  94     pci_set_irq(&s->dev, sci_level);
  95     /* schedule a timer interruption if needed */
  96     acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
  97                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
  98 }
  99
 100 static void pm_tmr_timer(ACPIREGS *ar)
 101 {
 102     VT686PMState *s = container_of(ar, VT686PMState, ar);
 103     pm_update_sci(s);
 104 }
 105
 106 static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp)
 107 {
 108     VT686PMState *s = VT82C686B_PM(dev);
 109     uint8_t *pci_conf;
 110
 111     pci_conf = s->dev.config;
 112     pci_set_word(pci_conf + PCI_COMMAND, 0);
 113     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
 114                  PCI_STATUS_DEVSEL_MEDIUM);
 115
 116     /* 0x48-0x4B is Power Management I/O Base */
 117     pci_set_long(pci_conf + 0x48, 0x00000001);
 118
 119     /* SMB ports:0xeee0~0xeeef */
 120     s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0);
 121     pci_conf[0x90] = s->smb_io_base | 1;
 122     pci_conf[0x91] = s->smb_io_base >> 8;
 123     pci_conf[0xd2] = 0x90;
 124     pm_smbus_init(DEVICE(s), &s->smb, false);
 125     memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
 126
 127     apm_init(dev, &s->apm, NULL, s);
 128
 129     memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64);
 130     memory_region_set_enabled(&s->io, false);
 131     memory_region_add_subregion(get_system_io(), 0, &s->io);
 132
 133     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 134     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 135     acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2);
 136 }
 137
 138 static Property via_pm_properties[] = {
 139     DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
 140     DEFINE_PROP_END_OF_LIST(),
 141 };
 142
 143 static void via_pm_class_init(ObjectClass *klass, void *data)
 144 {
 145     DeviceClass *dc = DEVICE_CLASS(klass);
 146     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 147
 148     k->realize = vt82c686b_pm_realize;
 149     k->config_write = pm_write_config;
 150     k->vendor_id = PCI_VENDOR_ID_VIA;
 151     k->device_id = PCI_DEVICE_ID_VIA_ACPI;
 152     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 153     k->revision = 0x40;
 154     dc->desc = "PM";
 155     dc->vmsd = &vmstate_acpi;
 156     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 157     device_class_set_props(dc, via_pm_properties);
 158 }
 159
 160 static const TypeInfo via_pm_info = {
 161     .name          = TYPE_VT82C686B_PM,
 162     .parent        = TYPE_PCI_DEVICE,
 163     .instance_size = sizeof(VT686PMState),
 164     .class_init    = via_pm_class_init,
 165     .interfaces = (InterfaceInfo[]) {
 166         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 167         { },
 168     },
 169 };
 170
 171
 172 typedef struct SuperIOConfig {
 173     uint8_t regs[0x100];
 174     uint8_t index;
 175     MemoryRegion io;
 176 } SuperIOConfig;
 177
 178 static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
 179                               unsigned size)
 180 {
 181     SuperIOConfig *sc = opaque;
 182
 183     if (addr == 0x3f0) { /* config index register */
 184         sc->index = data & 0xff;
 185     } else {
 186         bool can_write = true;
 187         /* 0x3f1, config data register */
 188         trace_via_superio_write(sc->index, data & 0xff);
 189         switch (sc->index) {
 190         case 0x00 ... 0xdf:
 191         case 0xe4:
 192         case 0xe5:
 193         case 0xe9 ... 0xed:
 194         case 0xf3:
 195         case 0xf5:
 196         case 0xf7:
 197         case 0xf9 ... 0xfb:
 198         case 0xfd ... 0xff:
 199             can_write = false;
 200             break;
 201         /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
 202         default:
 203             break;
 204
 205         }
 206         if (can_write) {
 207             sc->regs[sc->index] = data & 0xff;
 208         }
 209     }
 210 }
 211
 212 static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
 213 {
 214     SuperIOConfig *sc = opaque;
 215     uint8_t val = sc->regs[sc->index];
 216
 217     trace_via_superio_read(sc->index, val);
 218     return val;
 219 }
 220
 221 static const MemoryRegionOps superio_cfg_ops = {
 222     .read = superio_cfg_read,
 223     .write = superio_cfg_write,
 224     .endianness = DEVICE_NATIVE_ENDIAN,
 225     .impl = {
 226         .min_access_size = 1,
 227         .max_access_size = 1,
 228     },
 229 };
 230
 231
 232 OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
 233
 234 struct VT82C686BISAState {
 235     PCIDevice dev;
 236     SuperIOConfig superio_cfg;
 237 };
 238
 239 static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
 240                                    uint32_t val, int len)
 241 {
 242     VT82C686BISAState *s = VT82C686B_ISA(d);
 243
 244     trace_via_isa_write(addr, val, len);
 245     pci_default_write_config(d, addr, val, len);
 246     if (addr == 0x85) {
 247         /* BIT(1): enable or disable superio config io ports */
 248         memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1));
 249     }
 250 }
 251
 252 static const VMStateDescription vmstate_via = {
 253     .name = "vt82c686b",
 254     .version_id = 1,
 255     .minimum_version_id = 1,
 256     .fields = (VMStateField[]) {
 257         VMSTATE_PCI_DEVICE(dev, VT82C686BISAState),
 258         VMSTATE_END_OF_LIST()
 259     }
 260 };
 261
 262 static void vt82c686b_isa_reset(DeviceState *dev)
 263 {
 264     VT82C686BISAState *s = VT82C686B_ISA(dev);
 265     uint8_t *pci_conf = s->dev.config;
 266
 267     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 268     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 269                  PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
 270     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 271
 272     pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
 273     pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
 274     pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
 275     pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
 276     pci_conf[0x59] = 0x04;
 277     pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
 278     pci_conf[0x5f] = 0x04;
 279     pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
 280
 281     s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */
 282     s->superio_cfg.regs[0xe2] = 0x03; /* Function select */
 283     s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */
 284     s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */
 285     s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */
 286     s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */
 287 }
 288
 289 static void vt82c686b_realize(PCIDevice *d, Error **errp)
 290 {
 291     VT82C686BISAState *s = VT82C686B_ISA(d);
 292     uint8_t *pci_conf;
 293     ISABus *isa_bus;
 294     uint8_t *wmask;
 295     int i;
 296
 297     isa_bus = isa_bus_new(DEVICE(d), get_system_memory(),
 298                           pci_address_space_io(d), errp);
 299     if (!isa_bus) {
 300         return;
 301     }
 302
 303     pci_conf = d->config;
 304     pci_config_set_prog_interface(pci_conf, 0x0);
 305
 306     wmask = d->wmask;
 307     for (i = 0x00; i < 0xff; i++) {
 308         if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) {
 309             wmask[i] = 0x00;
 310         }
 311     }
 312
 313     memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops,
 314                           &s->superio_cfg, "superio_cfg", 2);
 315     memory_region_set_enabled(&s->superio_cfg.io, false);
 316     /*
 317      * The floppy also uses 0x3f0 and 0x3f1.
 318      * But we do not emulate a floppy, so just set it here.
 319      */
 320     memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
 321                                 &s->superio_cfg.io);
 322 }
 323
 324 static void via_class_init(ObjectClass *klass, void *data)
 325 {
 326     DeviceClass *dc = DEVICE_CLASS(klass);
 327     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 328
 329     k->realize = vt82c686b_realize;
 330     k->config_write = vt82c686b_write_config;
 331     k->vendor_id = PCI_VENDOR_ID_VIA;
 332     k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
 333     k->class_id = PCI_CLASS_BRIDGE_ISA;
 334     k->revision = 0x40;
 335     dc->reset = vt82c686b_isa_reset;
 336     dc->desc = "ISA bridge";
 337     dc->vmsd = &vmstate_via;
 338     /*
 339      * Reason: part of VIA VT82C686 southbridge, needs to be wired up,
 340      * e.g. by mips_fuloong2e_init()
 341      */
 342     dc->user_creatable = false;
 343 }
 344
 345 static const TypeInfo via_info = {
 346     .name          = TYPE_VT82C686B_ISA,
 347     .parent        = TYPE_PCI_DEVICE,
 348     .instance_size = sizeof(VT82C686BISAState),
 349     .class_init    = via_class_init,
 350     .interfaces = (InterfaceInfo[]) {
 351         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 352         { },
 353     },
 354 };
 355
 356
 357 static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
 358 {
 359     ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
 360
 361     sc->serial.count = 2;
 362     sc->parallel.count = 1;
 363     sc->ide.count = 0;
 364     sc->floppy.count = 1;
 365 }
 366
 367 static const TypeInfo via_superio_info = {
 368     .name          = TYPE_VT82C686B_SUPERIO,
 369     .parent        = TYPE_ISA_SUPERIO,
 370     .instance_size = sizeof(ISASuperIODevice),
 371     .class_size    = sizeof(ISASuperIOClass),
 372     .class_init    = vt82c686b_superio_class_init,
 373 };
 374
 375
 376 static void vt82c686b_register_types(void)
 377 {
 378     type_register_static(&via_pm_info);
 379     type_register_static(&via_info);
 380     type_register_static(&via_superio_info);
 381 }
 382
 383 type_init(vt82c686b_register_types)