2 * QEMU GRLIB IRQMP Emulator
4 * (Multiprocessor and extended interrupt not supported)
6 * Copyright (c) 2010-2019 AdaCore
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
29 #include "hw/sysbus.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/sparc/grlib.h"
36 #include "qapi/error.h"
37 #include "qemu/module.h"
38 #include "qom/object.h"
40 #define IRQMP_MAX_CPU 16
41 #define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */
43 /* Memory mapped register offsets */
44 #define LEVEL_OFFSET 0x00
45 #define PENDING_OFFSET 0x04
46 #define FORCE0_OFFSET 0x08
47 #define CLEAR_OFFSET 0x0C
48 #define MP_STATUS_OFFSET 0x10
49 #define BROADCAST_OFFSET 0x14
50 #define MASK_OFFSET 0x40
51 #define FORCE_OFFSET 0x80
52 #define EXTENDED_OFFSET 0xC0
56 OBJECT_DECLARE_SIMPLE_TYPE(IRQMP
, GRLIB_IRQMP
)
58 typedef struct IRQMPState IRQMPState
;
61 SysBusDevice parent_obj
;
75 uint32_t mask
[IRQMP_MAX_CPU
];
76 uint32_t force
[IRQMP_MAX_CPU
];
77 uint32_t extended
[IRQMP_MAX_CPU
];
82 static void grlib_irqmp_check_irqs(IRQMPState
*state
)
88 assert(state
!= NULL
);
89 assert(state
->parent
!= NULL
);
91 /* IRQ for CPU 0 (no SMP support) */
92 pend
= (state
->pending
| state
->force
[0])
95 level0
= pend
& ~state
->level
;
96 level1
= pend
& state
->level
;
98 trace_grlib_irqmp_check_irqs(state
->pending
, state
->force
[0],
99 state
->mask
[0], level1
, level0
);
101 /* Trigger level1 interrupt first and level0 if there is no level1 */
102 qemu_set_irq(state
->parent
->irq
, level1
?: level0
);
105 static void grlib_irqmp_ack_mask(IRQMPState
*state
, uint32_t mask
)
107 /* Clear registers */
108 state
->pending
&= ~mask
;
109 state
->force
[0] &= ~mask
; /* Only CPU 0 (No SMP support) */
111 grlib_irqmp_check_irqs(state
);
114 void grlib_irqmp_ack(DeviceState
*dev
, int intno
)
116 IRQMP
*irqmp
= GRLIB_IRQMP(dev
);
120 state
= irqmp
->state
;
121 assert(state
!= NULL
);
126 trace_grlib_irqmp_ack(intno
);
128 grlib_irqmp_ack_mask(state
, mask
);
131 static void grlib_irqmp_set_irq(void *opaque
, int irq
, int level
)
133 IRQMP
*irqmp
= GRLIB_IRQMP(opaque
);
139 assert(s
->parent
!= NULL
);
143 trace_grlib_irqmp_set_irq(irq
);
145 if (s
->broadcast
& 1 << irq
) {
146 /* Broadcasted IRQ */
147 for (i
= 0; i
< IRQMP_MAX_CPU
; i
++) {
148 s
->force
[i
] |= 1 << irq
;
151 s
->pending
|= 1 << irq
;
153 grlib_irqmp_check_irqs(s
);
158 static uint64_t grlib_irqmp_read(void *opaque
, hwaddr addr
,
161 IRQMP
*irqmp
= opaque
;
164 assert(irqmp
!= NULL
);
165 state
= irqmp
->state
;
166 assert(state
!= NULL
);
170 /* global registers */
176 return state
->pending
;
179 /* This register is an "alias" for the force register of CPU 0 */
180 return state
->force
[0];
183 case MP_STATUS_OFFSET
:
184 /* Always read as 0 */
187 case BROADCAST_OFFSET
:
188 return state
->broadcast
;
195 if (addr
>= MASK_OFFSET
&& addr
< FORCE_OFFSET
) {
196 int cpu
= (addr
- MASK_OFFSET
) / 4;
197 assert(cpu
>= 0 && cpu
< IRQMP_MAX_CPU
);
199 return state
->mask
[cpu
];
202 /* force registers */
203 if (addr
>= FORCE_OFFSET
&& addr
< EXTENDED_OFFSET
) {
204 int cpu
= (addr
- FORCE_OFFSET
) / 4;
205 assert(cpu
>= 0 && cpu
< IRQMP_MAX_CPU
);
207 return state
->force
[cpu
];
210 /* extended (not supported) */
211 if (addr
>= EXTENDED_OFFSET
&& addr
< IRQMP_REG_SIZE
) {
212 int cpu
= (addr
- EXTENDED_OFFSET
) / 4;
213 assert(cpu
>= 0 && cpu
< IRQMP_MAX_CPU
);
215 return state
->extended
[cpu
];
218 trace_grlib_irqmp_readl_unknown(addr
);
222 static void grlib_irqmp_write(void *opaque
, hwaddr addr
,
223 uint64_t value
, unsigned size
)
225 IRQMP
*irqmp
= opaque
;
228 assert(irqmp
!= NULL
);
229 state
= irqmp
->state
;
230 assert(state
!= NULL
);
234 /* global registers */
237 value
&= 0xFFFF << 1; /* clean up the value */
238 state
->level
= value
;
246 /* This register is an "alias" for the force register of CPU 0 */
248 value
&= 0xFFFE; /* clean up the value */
249 state
->force
[0] = value
;
250 grlib_irqmp_check_irqs(irqmp
->state
);
254 value
&= ~1; /* clean up the value */
255 grlib_irqmp_ack_mask(state
, value
);
258 case MP_STATUS_OFFSET
:
259 /* Read Only (no SMP support) */
262 case BROADCAST_OFFSET
:
263 value
&= 0xFFFE; /* clean up the value */
264 state
->broadcast
= value
;
272 if (addr
>= MASK_OFFSET
&& addr
< FORCE_OFFSET
) {
273 int cpu
= (addr
- MASK_OFFSET
) / 4;
274 assert(cpu
>= 0 && cpu
< IRQMP_MAX_CPU
);
276 value
&= ~1; /* clean up the value */
277 state
->mask
[cpu
] = value
;
278 grlib_irqmp_check_irqs(irqmp
->state
);
282 /* force registers */
283 if (addr
>= FORCE_OFFSET
&& addr
< EXTENDED_OFFSET
) {
284 int cpu
= (addr
- FORCE_OFFSET
) / 4;
285 assert(cpu
>= 0 && cpu
< IRQMP_MAX_CPU
);
287 uint32_t force
= value
& 0xFFFE;
288 uint32_t clear
= (value
>> 16) & 0xFFFE;
289 uint32_t old
= state
->force
[cpu
];
291 state
->force
[cpu
] = (old
| force
) & ~clear
;
292 grlib_irqmp_check_irqs(irqmp
->state
);
296 /* extended (not supported) */
297 if (addr
>= EXTENDED_OFFSET
&& addr
< IRQMP_REG_SIZE
) {
298 int cpu
= (addr
- EXTENDED_OFFSET
) / 4;
299 assert(cpu
>= 0 && cpu
< IRQMP_MAX_CPU
);
301 value
&= 0xF; /* clean up the value */
302 state
->extended
[cpu
] = value
;
306 trace_grlib_irqmp_writel_unknown(addr
, value
);
309 static const MemoryRegionOps grlib_irqmp_ops
= {
310 .read
= grlib_irqmp_read
,
311 .write
= grlib_irqmp_write
,
312 .endianness
= DEVICE_NATIVE_ENDIAN
,
314 .min_access_size
= 4,
315 .max_access_size
= 4,
319 static void grlib_irqmp_reset(DeviceState
*d
)
321 IRQMP
*irqmp
= GRLIB_IRQMP(d
);
322 assert(irqmp
->state
!= NULL
);
324 memset(irqmp
->state
, 0, sizeof *irqmp
->state
);
325 irqmp
->state
->parent
= irqmp
;
328 static void grlib_irqmp_init(Object
*obj
)
330 IRQMP
*irqmp
= GRLIB_IRQMP(obj
);
331 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
333 qdev_init_gpio_in(DEVICE(obj
), grlib_irqmp_set_irq
, MAX_PILS
);
334 qdev_init_gpio_out_named(DEVICE(obj
), &irqmp
->irq
, "grlib-irq", 1);
335 memory_region_init_io(&irqmp
->iomem
, obj
, &grlib_irqmp_ops
, irqmp
,
336 "irqmp", IRQMP_REG_SIZE
);
338 irqmp
->state
= g_malloc0(sizeof *irqmp
->state
);
340 sysbus_init_mmio(dev
, &irqmp
->iomem
);
343 static void grlib_irqmp_class_init(ObjectClass
*klass
, void *data
)
345 DeviceClass
*dc
= DEVICE_CLASS(klass
);
347 dc
->reset
= grlib_irqmp_reset
;
350 static const TypeInfo grlib_irqmp_info
= {
351 .name
= TYPE_GRLIB_IRQMP
,
352 .parent
= TYPE_SYS_BUS_DEVICE
,
353 .instance_size
= sizeof(IRQMP
),
354 .instance_init
= grlib_irqmp_init
,
355 .class_init
= grlib_irqmp_class_init
,
358 static void grlib_irqmp_register_types(void)
360 type_register_static(&grlib_irqmp_info
);
363 type_init(grlib_irqmp_register_types
)