2 * QEMU model of the LatticeMico32 timer block.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 * Specification available at:
21 * http://www.latticesemi.com/documents/mico32timer.pdf
24 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "migration/vmstate.h"
29 #include "qemu/timer.h"
30 #include "hw/ptimer.h"
31 #include "hw/qdev-properties.h"
32 #include "qemu/error-report.h"
33 #include "qemu/module.h"
35 #define DEFAULT_FREQUENCY (50*1000000)
57 #define TYPE_LM32_TIMER "lm32-timer"
58 #define LM32_TIMER(obj) OBJECT_CHECK(LM32TimerState, (obj), TYPE_LM32_TIMER)
60 struct LM32TimerState
{
61 SysBusDevice parent_obj
;
72 typedef struct LM32TimerState LM32TimerState
;
74 static void timer_update_irq(LM32TimerState
*s
)
76 int state
= (s
->regs
[R_SR
] & SR_TO
) && (s
->regs
[R_CR
] & CR_ITO
);
78 trace_lm32_timer_irq_state(state
);
79 qemu_set_irq(s
->irq
, state
);
82 static uint64_t timer_read(void *opaque
, hwaddr addr
, unsigned size
)
84 LM32TimerState
*s
= opaque
;
95 r
= (uint32_t)ptimer_get_count(s
->ptimer
);
98 error_report("lm32_timer: read access to unknown register 0x"
99 TARGET_FMT_plx
, addr
<< 2);
103 trace_lm32_timer_memory_read(addr
<< 2, r
);
107 static void timer_write(void *opaque
, hwaddr addr
,
108 uint64_t value
, unsigned size
)
110 LM32TimerState
*s
= opaque
;
112 trace_lm32_timer_memory_write(addr
, value
);
117 s
->regs
[R_SR
] &= ~SR_TO
;
120 ptimer_transaction_begin(s
->ptimer
);
121 s
->regs
[R_CR
] = value
;
122 if (s
->regs
[R_CR
] & CR_START
) {
123 ptimer_run(s
->ptimer
, 1);
125 if (s
->regs
[R_CR
] & CR_STOP
) {
126 ptimer_stop(s
->ptimer
);
128 ptimer_transaction_commit(s
->ptimer
);
131 s
->regs
[R_PERIOD
] = value
;
132 ptimer_transaction_begin(s
->ptimer
);
133 ptimer_set_count(s
->ptimer
, value
);
134 ptimer_transaction_commit(s
->ptimer
);
137 error_report("lm32_timer: write access to read only register 0x"
138 TARGET_FMT_plx
, addr
<< 2);
141 error_report("lm32_timer: write access to unknown register 0x"
142 TARGET_FMT_plx
, addr
<< 2);
148 static const MemoryRegionOps timer_ops
= {
150 .write
= timer_write
,
151 .endianness
= DEVICE_NATIVE_ENDIAN
,
153 .min_access_size
= 4,
154 .max_access_size
= 4,
158 static void timer_hit(void *opaque
)
160 LM32TimerState
*s
= opaque
;
162 trace_lm32_timer_hit();
164 s
->regs
[R_SR
] |= SR_TO
;
166 if (s
->regs
[R_CR
] & CR_CONT
) {
167 ptimer_set_count(s
->ptimer
, s
->regs
[R_PERIOD
]);
168 ptimer_run(s
->ptimer
, 1);
173 static void timer_reset(DeviceState
*d
)
175 LM32TimerState
*s
= LM32_TIMER(d
);
178 for (i
= 0; i
< R_MAX
; i
++) {
181 ptimer_transaction_begin(s
->ptimer
);
182 ptimer_stop(s
->ptimer
);
183 ptimer_transaction_commit(s
->ptimer
);
186 static void lm32_timer_init(Object
*obj
)
188 LM32TimerState
*s
= LM32_TIMER(obj
);
189 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
191 sysbus_init_irq(dev
, &s
->irq
);
193 memory_region_init_io(&s
->iomem
, obj
, &timer_ops
, s
,
195 sysbus_init_mmio(dev
, &s
->iomem
);
198 static void lm32_timer_realize(DeviceState
*dev
, Error
**errp
)
200 LM32TimerState
*s
= LM32_TIMER(dev
);
202 s
->ptimer
= ptimer_init(timer_hit
, s
, PTIMER_POLICY_DEFAULT
);
204 ptimer_transaction_begin(s
->ptimer
);
205 ptimer_set_freq(s
->ptimer
, s
->freq_hz
);
206 ptimer_transaction_commit(s
->ptimer
);
209 static const VMStateDescription vmstate_lm32_timer
= {
210 .name
= "lm32-timer",
212 .minimum_version_id
= 1,
213 .fields
= (VMStateField
[]) {
214 VMSTATE_PTIMER(ptimer
, LM32TimerState
),
215 VMSTATE_UINT32(freq_hz
, LM32TimerState
),
216 VMSTATE_UINT32_ARRAY(regs
, LM32TimerState
, R_MAX
),
217 VMSTATE_END_OF_LIST()
221 static Property lm32_timer_properties
[] = {
222 DEFINE_PROP_UINT32("frequency", LM32TimerState
, freq_hz
, DEFAULT_FREQUENCY
),
223 DEFINE_PROP_END_OF_LIST(),
226 static void lm32_timer_class_init(ObjectClass
*klass
, void *data
)
228 DeviceClass
*dc
= DEVICE_CLASS(klass
);
230 dc
->realize
= lm32_timer_realize
;
231 dc
->reset
= timer_reset
;
232 dc
->vmsd
= &vmstate_lm32_timer
;
233 dc
->props
= lm32_timer_properties
;
236 static const TypeInfo lm32_timer_info
= {
237 .name
= TYPE_LM32_TIMER
,
238 .parent
= TYPE_SYS_BUS_DEVICE
,
239 .instance_size
= sizeof(LM32TimerState
),
240 .instance_init
= lm32_timer_init
,
241 .class_init
= lm32_timer_class_init
,
244 static void lm32_timer_register_types(void)
246 type_register_static(&lm32_timer_info
);
249 type_init(lm32_timer_register_types
)