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target/arm: Honor HCR_EL2.TID1 trapping requirements
[qemu/ar7.git] / hw / riscv / spike.c
blob882368178328b60d8d0f659ea847315891852aaa
1 /*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *
9 * 0) HTIF Console and Poweroff
10 * 1) CLINT (Timer and IPI)
11 * 2) PLIC (Platform Level Interrupt Controller)
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms and conditions of the GNU General Public License,
15 * version 2 or later, as published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * You should have received a copy of the GNU General Public License along with
23 * this program. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qemu/log.h"
28 #include "qemu/error-report.h"
29 #include "qapi/error.h"
30 #include "hw/boards.h"
31 #include "hw/loader.h"
32 #include "hw/sysbus.h"
33 #include "target/riscv/cpu.h"
34 #include "hw/riscv/riscv_htif.h"
35 #include "hw/riscv/riscv_hart.h"
36 #include "hw/riscv/sifive_clint.h"
37 #include "hw/riscv/spike.h"
38 #include "hw/riscv/boot.h"
39 #include "chardev/char.h"
40 #include "sysemu/arch_init.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/qtest.h"
43 #include "sysemu/sysemu.h"
44 #include "exec/address-spaces.h"
45
46 #include <libfdt.h>
47
48 static const struct MemmapEntry {
49 hwaddr base;
50 hwaddr size;
51 } spike_memmap[] = {
52 [SPIKE_MROM] = { 0x1000, 0x11000 },
53 [SPIKE_CLINT] = { 0x2000000, 0x10000 },
54 [SPIKE_DRAM] = { 0x80000000, 0x0 },
55 };
56
57 static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
58 uint64_t mem_size, const char *cmdline)
59 {
60 void *fdt;
61 int cpu;
62 uint32_t *cells;
63 char *nodename;
64
65 fdt = s->fdt = create_device_tree(&s->fdt_size);
66 if (!fdt) {
67 error_report("create_device_tree() failed");
68 exit(1);
69 }
70
71 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
72 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
73 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
74 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
75
76 qemu_fdt_add_subnode(fdt, "/htif");
77 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
78
79 qemu_fdt_add_subnode(fdt, "/soc");
80 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
81 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
82 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
83 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
84
85 nodename = g_strdup_printf("/memory@%lx",
86 (long)memmap[SPIKE_DRAM].base);
87 qemu_fdt_add_subnode(fdt, nodename);
88 qemu_fdt_setprop_cells(fdt, nodename, "reg",
89 memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
90 mem_size >> 32, mem_size);
91 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
92 g_free(nodename);
93
94 qemu_fdt_add_subnode(fdt, "/cpus");
95 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
96 SIFIVE_CLINT_TIMEBASE_FREQ);
97 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
98 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
99
100 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
101 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
102 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
103 char *isa = riscv_isa_string(&s->soc.harts[cpu]);
104 qemu_fdt_add_subnode(fdt, nodename);
105 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
106 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
107 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
108 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
109 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
110 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
111 qemu_fdt_add_subnode(fdt, intc);
112 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
113 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
114 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
115 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
116 g_free(isa);
117 g_free(intc);
118 g_free(nodename);
119 }
120
121 cells = g_new0(uint32_t, s->soc.num_harts * 4);
122 for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
123 nodename =
124 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
125 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
126 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
127 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
128 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
129 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
130 g_free(nodename);
131 }
132 nodename = g_strdup_printf("/soc/clint@%lx",
133 (long)memmap[SPIKE_CLINT].base);
134 qemu_fdt_add_subnode(fdt, nodename);
135 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
136 qemu_fdt_setprop_cells(fdt, nodename, "reg",
137 0x0, memmap[SPIKE_CLINT].base,
138 0x0, memmap[SPIKE_CLINT].size);
139 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
140 cells, s->soc.num_harts * sizeof(uint32_t) * 4);
141 g_free(cells);
142 g_free(nodename);
143
144 if (cmdline) {
145 qemu_fdt_add_subnode(fdt, "/chosen");
146 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
147 }
148 }
149
150 static void spike_board_init(MachineState *machine)
151 {
152 const struct MemmapEntry *memmap = spike_memmap;
153
154 SpikeState *s = g_new0(SpikeState, 1);
155 MemoryRegion *system_memory = get_system_memory();
156 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
157 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
158 int i;
159 unsigned int smp_cpus = machine->smp.cpus;
160
161 /* Initialize SOC */
162 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
163 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
164 object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
165 &error_abort);
166 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
167 &error_abort);
168 object_property_set_bool(OBJECT(&s->soc), true, "realized",
169 &error_abort);
170
171 /* register system main memory (actual RAM) */
172 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
173 machine->ram_size, &error_fatal);
174 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
175 main_mem);
176
177 /* create device tree */
178 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
179
180 /* boot rom */
181 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
182 memmap[SPIKE_MROM].size, &error_fatal);
183 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
184 mask_rom);
185
186 if (machine->kernel_filename) {
187 riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
188 }
189
190 /* reset vector */
191 uint32_t reset_vec[8] = {
192 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
193 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
194 0xf1402573, /* csrr a0, mhartid */
195 #if defined(TARGET_RISCV32)
196 0x0182a283, /* lw t0, 24(t0) */
197 #elif defined(TARGET_RISCV64)
198 0x0182b283, /* ld t0, 24(t0) */
199 #endif
200 0x00028067, /* jr t0 */
201 0x00000000,
202 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
203 0x00000000,
204 /* dtb: */
205 };
206
207 /* copy in the reset vector in little_endian byte order */
208 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
209 reset_vec[i] = cpu_to_le32(reset_vec[i]);
210 }
211 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
212 memmap[SPIKE_MROM].base, &address_space_memory);
213
214 /* copy in the device tree */
215 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
216 memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
217 error_report("not enough space to store device-tree");
218 exit(1);
219 }
220 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
221 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
222 memmap[SPIKE_MROM].base + sizeof(reset_vec),
223 &address_space_memory);
224
225 /* initialize HTIF using symbols found in load_kernel */
226 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
227
228 /* Core Local Interruptor (timer and IPI) */
229 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
230 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
231 }
232
233 static void spike_v1_10_0_board_init(MachineState *machine)
234 {
235 const struct MemmapEntry *memmap = spike_memmap;
236
237 SpikeState *s = g_new0(SpikeState, 1);
238 MemoryRegion *system_memory = get_system_memory();
239 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
240 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
241 int i;
242 unsigned int smp_cpus = machine->smp.cpus;
243
244 if (!qtest_enabled()) {
245 info_report("The Spike v1.10.0 machine has been deprecated. "
246 "Please use the generic spike machine and specify the ISA "
247 "versions using -cpu.");
248 }
249
250 /* Initialize SOC */
251 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
252 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
253 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type",
254 &error_abort);
255 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
256 &error_abort);
257 object_property_set_bool(OBJECT(&s->soc), true, "realized",
258 &error_abort);
259
260 /* register system main memory (actual RAM) */
261 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
262 machine->ram_size, &error_fatal);
263 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
264 main_mem);
265
266 /* create device tree */
267 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
268
269 /* boot rom */
270 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
271 memmap[SPIKE_MROM].size, &error_fatal);
272 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
273 mask_rom);
274
275 if (machine->kernel_filename) {
276 riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
277 }
278
279 /* reset vector */
280 uint32_t reset_vec[8] = {
281 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
282 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
283 0xf1402573, /* csrr a0, mhartid */
284 #if defined(TARGET_RISCV32)
285 0x0182a283, /* lw t0, 24(t0) */
286 #elif defined(TARGET_RISCV64)
287 0x0182b283, /* ld t0, 24(t0) */
288 #endif
289 0x00028067, /* jr t0 */
290 0x00000000,
291 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
292 0x00000000,
293 /* dtb: */
294 };
295
296 /* copy in the reset vector in little_endian byte order */
297 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
298 reset_vec[i] = cpu_to_le32(reset_vec[i]);
299 }
300 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
301 memmap[SPIKE_MROM].base, &address_space_memory);
302
303 /* copy in the device tree */
304 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
305 memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
306 error_report("not enough space to store device-tree");
307 exit(1);
308 }
309 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
310 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
311 memmap[SPIKE_MROM].base + sizeof(reset_vec),
312 &address_space_memory);
313
314 /* initialize HTIF using symbols found in load_kernel */
315 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
316
317 /* Core Local Interruptor (timer and IPI) */
318 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
319 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
320 }
321
322 static void spike_v1_09_1_board_init(MachineState *machine)
323 {
324 const struct MemmapEntry *memmap = spike_memmap;
325
326 SpikeState *s = g_new0(SpikeState, 1);
327 MemoryRegion *system_memory = get_system_memory();
328 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
329 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
330 int i;
331 unsigned int smp_cpus = machine->smp.cpus;
332
333 if (!qtest_enabled()) {
334 info_report("The Spike v1.09.1 machine has been deprecated. "
335 "Please use the generic spike machine and specify the ISA "
336 "versions using -cpu.");
337 }
338
339 /* Initialize SOC */
340 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
341 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
342 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type",
343 &error_abort);
344 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
345 &error_abort);
346 object_property_set_bool(OBJECT(&s->soc), true, "realized",
347 &error_abort);
348
349 /* register system main memory (actual RAM) */
350 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
351 machine->ram_size, &error_fatal);
352 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
353 main_mem);
354
355 /* boot rom */
356 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
357 memmap[SPIKE_MROM].size, &error_fatal);
358 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
359 mask_rom);
360
361 if (machine->kernel_filename) {
362 riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
363 }
364
365 /* reset vector */
366 uint32_t reset_vec[8] = {
367 0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */
368 0x00028067, /* jump to DRAM_BASE */
369 0x00000000, /* reserved */
370 memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */
371 0, 0, 0, 0 /* trap vector */
372 };
373
374 /* part one of config string - before memory size specified */
375 const char *config_string_tmpl =
376 "platform {\n"
377 " vendor ucb;\n"
378 " arch spike;\n"
379 "};\n"
380 "rtc {\n"
381 " addr 0x%" PRIx64 "x;\n"
382 "};\n"
383 "ram {\n"
384 " 0 {\n"
385 " addr 0x%" PRIx64 "x;\n"
386 " size 0x%" PRIx64 "x;\n"
387 " };\n"
388 "};\n"
389 "core {\n"
390 " 0" " {\n"
391 " " "0 {\n"
392 " isa %s;\n"
393 " timecmp 0x%" PRIx64 "x;\n"
394 " ipi 0x%" PRIx64 "x;\n"
395 " };\n"
396 " };\n"
397 "};\n";
398
399 /* build config string with supplied memory size */
400 char *isa = riscv_isa_string(&s->soc.harts[0]);
401 char *config_string = g_strdup_printf(config_string_tmpl,
402 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE,
403 (uint64_t)memmap[SPIKE_DRAM].base,
404 (uint64_t)ram_size, isa,
405 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE,
406 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE);
407 g_free(isa);
408 size_t config_string_len = strlen(config_string);
409
410 /* copy in the reset vector in little_endian byte order */
411 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
412 reset_vec[i] = cpu_to_le32(reset_vec[i]);
413 }
414 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
415 memmap[SPIKE_MROM].base, &address_space_memory);
416
417 /* copy in the config string */
418 rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len,
419 memmap[SPIKE_MROM].base + sizeof(reset_vec),
420 &address_space_memory);
421
422 /* initialize HTIF using symbols found in load_kernel */
423 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
424
425 /* Core Local Interruptor (timer and IPI) */
426 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
427 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
428
429 g_free(config_string);
430 }
431
432 static void spike_v1_09_1_machine_init(MachineClass *mc)
433 {
434 mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
435 mc->init = spike_v1_09_1_board_init;
436 mc->max_cpus = 1;
437 }
438
439 static void spike_v1_10_0_machine_init(MachineClass *mc)
440 {
441 mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
442 mc->init = spike_v1_10_0_board_init;
443 mc->max_cpus = 1;
444 }
445
446 static void spike_machine_init(MachineClass *mc)
447 {
448 mc->desc = "RISC-V Spike Board";
449 mc->init = spike_board_init;
450 mc->max_cpus = 1;
451 mc->is_default = 1;
452 mc->default_cpu_type = SPIKE_V1_10_0_CPU;
453 }
454
455 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
456 DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
457 DEFINE_MACHINE("spike", spike_machine_init)
AR7 emulation for QEMU