target-mips/cpu.h

   1 #if !defined (__MIPS_CPU_H__)
   2 #define __MIPS_CPU_H__
   3
   4 //#define DEBUG_OP
   5
   6 #define ALIGNED_ONLY
   7
   8 #define CPUArchState struct CPUMIPSState
   9
  10 #include "qemu-common.h"
  11 #include "mips-defs.h"
  12 #include "exec/cpu-defs.h"
  13 #include "fpu/softfloat.h"
  14
  15 struct CPUMIPSState;
  16
  17 typedef struct r4k_tlb_t r4k_tlb_t;
  18 struct r4k_tlb_t {
  19     target_ulong VPN;
  20     uint32_t PageMask;
  21     uint8_t ASID;
  22     unsigned int G:1;
  23     unsigned int C0:3;
  24     unsigned int C1:3;
  25     unsigned int V0:1;
  26     unsigned int V1:1;
  27     unsigned int D0:1;
  28     unsigned int D1:1;
  29     unsigned int XI0:1;
  30     unsigned int XI1:1;
  31     unsigned int RI0:1;
  32     unsigned int RI1:1;
  33     unsigned int EHINV:1;
  34     uint64_t PFN[2];
  35 };
  36
  37 #if !defined(CONFIG_USER_ONLY)
  38 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  39 struct CPUMIPSTLBContext {
  40     uint32_t nb_tlb;
  41     uint32_t tlb_in_use;
  42     int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
  43     void (*helper_tlbwi)(struct CPUMIPSState *env);
  44     void (*helper_tlbwr)(struct CPUMIPSState *env);
  45     void (*helper_tlbp)(struct CPUMIPSState *env);
  46     void (*helper_tlbr)(struct CPUMIPSState *env);
  47     void (*helper_tlbinv)(struct CPUMIPSState *env);
  48     void (*helper_tlbinvf)(struct CPUMIPSState *env);
  49     union {
  50         struct {
  51             r4k_tlb_t tlb[MIPS_TLB_MAX];
  52         } r4k;
  53     } mmu;
  54 };
  55 #endif
  56
  57 /* MSA Context */
  58 #define MSA_WRLEN (128)
  59
  60 enum CPUMIPSMSADataFormat {
  61     DF_BYTE = 0,
  62     DF_HALF,
  63     DF_WORD,
  64     DF_DOUBLE
  65 };
  66
  67 typedef union wr_t wr_t;
  68 union wr_t {
  69     int8_t  b[MSA_WRLEN/8];
  70     int16_t h[MSA_WRLEN/16];
  71     int32_t w[MSA_WRLEN/32];
  72     int64_t d[MSA_WRLEN/64];
  73 };
  74
  75 typedef union fpr_t fpr_t;
  76 union fpr_t {
  77     float64  fd;   /* ieee double precision */
  78     float32  fs[2];/* ieee single precision */
  79     uint64_t d;    /* binary double fixed-point */
  80     uint32_t w[2]; /* binary single fixed-point */
  81 /* FPU/MSA register mapping is not tested on big-endian hosts. */
  82     wr_t     wr;   /* vector data */
  83 };
  84 /* define FP_ENDIAN_IDX to access the same location
  85  * in the fpr_t union regardless of the host endianness
  86  */
  87 #if defined(HOST_WORDS_BIGENDIAN)
  88 #  define FP_ENDIAN_IDX 1
  89 #else
  90 #  define FP_ENDIAN_IDX 0
  91 #endif
  92
  93 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  94 struct CPUMIPSFPUContext {
  95     /* Floating point registers */
  96     fpr_t fpr[32];
  97     float_status fp_status;
  98     /* fpu implementation/revision register (fir) */
  99     uint32_t fcr0;
 100 #define FCR0_FREP 29
 101 #define FCR0_UFRP 28
 102 #define FCR0_HAS2008 23
 103 #define FCR0_F64 22
 104 #define FCR0_L 21
 105 #define FCR0_W 20
 106 #define FCR0_3D 19
 107 #define FCR0_PS 18
 108 #define FCR0_D 17
 109 #define FCR0_S 16
 110 #define FCR0_PRID 8
 111 #define FCR0_REV 0
 112     /* fcsr */
 113     uint32_t fcr31;
 114 #define FCR31_ABS2008 19
 115 #define FCR31_NAN2008 18
 116 #define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 117 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 118 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
 119 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
 120 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
 121 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
 122 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
 123 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
 124 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
 125 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
 126 #define FP_INEXACT        1
 127 #define FP_UNDERFLOW      2
 128 #define FP_OVERFLOW       4
 129 #define FP_DIV0           8
 130 #define FP_INVALID        16
 131 #define FP_UNIMPLEMENTED  32
 132 };
 133
 134 #define NB_MMU_MODES 3
 135 #define TARGET_INSN_START_EXTRA_WORDS 2
 136
 137 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 138 struct CPUMIPSMVPContext {
 139     int32_t CP0_MVPControl;
 140 #define CP0MVPCo_CPA    3
 141 #define CP0MVPCo_STLB   2
 142 #define CP0MVPCo_VPC    1
 143 #define CP0MVPCo_EVP    0
 144     int32_t CP0_MVPConf0;
 145 #define CP0MVPC0_M      31
 146 #define CP0MVPC0_TLBS   29
 147 #define CP0MVPC0_GS     28
 148 #define CP0MVPC0_PCP    27
 149 #define CP0MVPC0_PTLBE  16
 150 #define CP0MVPC0_TCA    15
 151 #define CP0MVPC0_PVPE   10
 152 #define CP0MVPC0_PTC    0
 153     int32_t CP0_MVPConf1;
 154 #define CP0MVPC1_CIM    31
 155 #define CP0MVPC1_CIF    30
 156 #define CP0MVPC1_PCX    20
 157 #define CP0MVPC1_PCP2   10
 158 #define CP0MVPC1_PCP1   0
 159 };
 160
 161 typedef struct mips_def_t mips_def_t;
 162
 163 #define MIPS_SHADOW_SET_MAX 16
 164 #define MIPS_TC_MAX 5
 165 #define MIPS_FPU_MAX 1
 166 #define MIPS_DSP_ACC 4
 167 #define MIPS_KSCRATCH_NUM 6
 168
 169 typedef struct TCState TCState;
 170 struct TCState {
 171     target_ulong gpr[32];
 172     target_ulong PC;
 173     target_ulong HI[MIPS_DSP_ACC];
 174     target_ulong LO[MIPS_DSP_ACC];
 175     target_ulong ACX[MIPS_DSP_ACC];
 176     target_ulong DSPControl;
 177     int32_t CP0_TCStatus;
 178 #define CP0TCSt_TCU3    31
 179 #define CP0TCSt_TCU2    30
 180 #define CP0TCSt_TCU1    29
 181 #define CP0TCSt_TCU0    28
 182 #define CP0TCSt_TMX     27
 183 #define CP0TCSt_RNST    23
 184 #define CP0TCSt_TDS     21
 185 #define CP0TCSt_DT      20
 186 #define CP0TCSt_DA      15
 187 #define CP0TCSt_A       13
 188 #define CP0TCSt_TKSU    11
 189 #define CP0TCSt_IXMT    10
 190 #define CP0TCSt_TASID   0
 191     int32_t CP0_TCBind;
 192 #define CP0TCBd_CurTC   21
 193 #define CP0TCBd_TBE     17
 194 #define CP0TCBd_CurVPE  0
 195     target_ulong CP0_TCHalt;
 196     target_ulong CP0_TCContext;
 197     target_ulong CP0_TCSchedule;
 198     target_ulong CP0_TCScheFBack;
 199     int32_t CP0_Debug_tcstatus;
 200     target_ulong CP0_UserLocal;
 201
 202     int32_t msacsr;
 203
 204 #define MSACSR_FS       24
 205 #define MSACSR_FS_MASK  (1 << MSACSR_FS)
 206 #define MSACSR_NX       18
 207 #define MSACSR_NX_MASK  (1 << MSACSR_NX)
 208 #define MSACSR_CEF      2
 209 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
 210 #define MSACSR_RM       0
 211 #define MSACSR_RM_MASK  (0x3 << MSACSR_RM)
 212 #define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
 213         MSACSR_FS_MASK)
 214
 215     float_status msa_fp_status;
 216 };
 217
 218 typedef struct CPUMIPSState CPUMIPSState;
 219 struct CPUMIPSState {
 220     TCState active_tc;
 221     CPUMIPSFPUContext active_fpu;
 222
 223     uint32_t current_tc;
 224     uint32_t current_fpu;
 225
 226     uint32_t SEGBITS;
 227     uint32_t PABITS;
 228 #if defined(TARGET_MIPS64)
 229 # define PABITS_BASE 36
 230 #else
 231 # define PABITS_BASE 32
 232 #endif
 233     target_ulong SEGMask;
 234     uint64_t PAMask;
 235 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
 236
 237     int32_t msair;
 238 #define MSAIR_ProcID    8
 239 #define MSAIR_Rev       0
 240
 241     int32_t CP0_Index;
 242     /* CP0_MVP* are per MVP registers. */
 243     int32_t CP0_VPControl;
 244 #define CP0VPCtl_DIS    0
 245     int32_t CP0_Random;
 246     int32_t CP0_VPEControl;
 247 #define CP0VPECo_YSI    21
 248 #define CP0VPECo_GSI    20
 249 #define CP0VPECo_EXCPT  16
 250 #define CP0VPECo_TE     15
 251 #define CP0VPECo_TargTC 0
 252     int32_t CP0_VPEConf0;
 253 #define CP0VPEC0_M      31
 254 #define CP0VPEC0_XTC    21
 255 #define CP0VPEC0_TCS    19
 256 #define CP0VPEC0_SCS    18
 257 #define CP0VPEC0_DSC    17
 258 #define CP0VPEC0_ICS    16
 259 #define CP0VPEC0_MVP    1
 260 #define CP0VPEC0_VPA    0
 261     int32_t CP0_VPEConf1;
 262 #define CP0VPEC1_NCX    20
 263 #define CP0VPEC1_NCP2   10
 264 #define CP0VPEC1_NCP1   0
 265     target_ulong CP0_YQMask;
 266     target_ulong CP0_VPESchedule;
 267     target_ulong CP0_VPEScheFBack;
 268     int32_t CP0_VPEOpt;
 269 #define CP0VPEOpt_IWX7  15
 270 #define CP0VPEOpt_IWX6  14
 271 #define CP0VPEOpt_IWX5  13
 272 #define CP0VPEOpt_IWX4  12
 273 #define CP0VPEOpt_IWX3  11
 274 #define CP0VPEOpt_IWX2  10
 275 #define CP0VPEOpt_IWX1  9
 276 #define CP0VPEOpt_IWX0  8
 277 #define CP0VPEOpt_DWX7  7
 278 #define CP0VPEOpt_DWX6  6
 279 #define CP0VPEOpt_DWX5  5
 280 #define CP0VPEOpt_DWX4  4
 281 #define CP0VPEOpt_DWX3  3
 282 #define CP0VPEOpt_DWX2  2
 283 #define CP0VPEOpt_DWX1  1
 284 #define CP0VPEOpt_DWX0  0
 285     uint64_t CP0_EntryLo0;
 286     uint64_t CP0_EntryLo1;
 287 #if defined(TARGET_MIPS64)
 288 # define CP0EnLo_RI 63
 289 # define CP0EnLo_XI 62
 290 #else
 291 # define CP0EnLo_RI 31
 292 # define CP0EnLo_XI 30
 293 #endif
 294     int32_t CP0_GlobalNumber;
 295 #define CP0GN_VPId 0
 296     target_ulong CP0_Context;
 297     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
 298     int32_t CP0_PageMask;
 299     int32_t CP0_PageGrain_rw_bitmask;
 300     int32_t CP0_PageGrain;
 301 #define CP0PG_RIE 31
 302 #define CP0PG_XIE 30
 303 #define CP0PG_ELPA 29
 304 #define CP0PG_IEC 27
 305     int32_t CP0_Wired;
 306     int32_t CP0_SRSConf0_rw_bitmask;
 307     int32_t CP0_SRSConf0;
 308 #define CP0SRSC0_M      31
 309 #define CP0SRSC0_SRS3   20
 310 #define CP0SRSC0_SRS2   10
 311 #define CP0SRSC0_SRS1   0
 312     int32_t CP0_SRSConf1_rw_bitmask;
 313     int32_t CP0_SRSConf1;
 314 #define CP0SRSC1_M      31
 315 #define CP0SRSC1_SRS6   20
 316 #define CP0SRSC1_SRS5   10
 317 #define CP0SRSC1_SRS4   0
 318     int32_t CP0_SRSConf2_rw_bitmask;
 319     int32_t CP0_SRSConf2;
 320 #define CP0SRSC2_M      31
 321 #define CP0SRSC2_SRS9   20
 322 #define CP0SRSC2_SRS8   10
 323 #define CP0SRSC2_SRS7   0
 324     int32_t CP0_SRSConf3_rw_bitmask;
 325     int32_t CP0_SRSConf3;
 326 #define CP0SRSC3_M      31
 327 #define CP0SRSC3_SRS12  20
 328 #define CP0SRSC3_SRS11  10
 329 #define CP0SRSC3_SRS10  0
 330     int32_t CP0_SRSConf4_rw_bitmask;
 331     int32_t CP0_SRSConf4;
 332 #define CP0SRSC4_SRS15  20
 333 #define CP0SRSC4_SRS14  10
 334 #define CP0SRSC4_SRS13  0
 335     int32_t CP0_HWREna;
 336     target_ulong CP0_BadVAddr;
 337     uint32_t CP0_BadInstr;
 338     uint32_t CP0_BadInstrP;
 339     int32_t CP0_Count;
 340     target_ulong CP0_EntryHi;
 341 #define CP0EnHi_EHINV 10
 342     int32_t CP0_Compare;
 343     int32_t CP0_Status;
 344 #define CP0St_CU3   31
 345 #define CP0St_CU2   30
 346 #define CP0St_CU1   29
 347 #define CP0St_CU0   28
 348 #define CP0St_RP    27
 349 #define CP0St_FR    26
 350 #define CP0St_RE    25
 351 #define CP0St_MX    24
 352 #define CP0St_PX    23
 353 #define CP0St_BEV   22
 354 #define CP0St_TS    21
 355 #define CP0St_SR    20
 356 #define CP0St_NMI   19
 357 #define CP0St_IM    8
 358 #define CP0St_KX    7
 359 #define CP0St_SX    6
 360 #define CP0St_UX    5
 361 #define CP0St_KSU   3
 362 #define CP0St_ERL   2
 363 #define CP0St_EXL   1
 364 #define CP0St_IE    0
 365     int32_t CP0_IntCtl;
 366 #define CP0IntCtl_IPTI 29
 367 #define CP0IntCtl_IPPCI 26
 368 #define CP0IntCtl_VS 5
 369     int32_t CP0_SRSCtl;
 370 #define CP0SRSCtl_HSS 26
 371 #define CP0SRSCtl_EICSS 18
 372 #define CP0SRSCtl_ESS 12
 373 #define CP0SRSCtl_PSS 6
 374 #define CP0SRSCtl_CSS 0
 375     int32_t CP0_SRSMap;
 376 #define CP0SRSMap_SSV7 28
 377 #define CP0SRSMap_SSV6 24
 378 #define CP0SRSMap_SSV5 20
 379 #define CP0SRSMap_SSV4 16
 380 #define CP0SRSMap_SSV3 12
 381 #define CP0SRSMap_SSV2 8
 382 #define CP0SRSMap_SSV1 4
 383 #define CP0SRSMap_SSV0 0
 384     int32_t CP0_Cause;
 385 #define CP0Ca_BD   31
 386 #define CP0Ca_TI   30
 387 #define CP0Ca_CE   28
 388 #define CP0Ca_DC   27
 389 #define CP0Ca_PCI  26
 390 #define CP0Ca_IV   23
 391 #define CP0Ca_WP   22
 392 #define CP0Ca_IP    8
 393 #define CP0Ca_IP_mask 0x0000FF00
 394 #define CP0Ca_EC    2
 395     target_ulong CP0_EPC;
 396     int32_t CP0_PRid;
 397     int32_t CP0_EBase;
 398     int32_t CP0_Config0;
 399 #define CP0C0_M    31
 400 #define CP0C0_K23  28
 401 #define CP0C0_KU   25
 402 #define CP0C0_MDU  20
 403 #define CP0C0_MM   18
 404 #define CP0C0_BM   16
 405 #define CP0C0_BE   15
 406 #define CP0C0_AT   13
 407 #define CP0C0_AR   10
 408 #define CP0C0_MT   7
 409 #define CP0C0_VI   3
 410 #define CP0C0_K0   0
 411     int32_t CP0_Config1;
 412 #define CP0C1_M    31
 413 #define CP0C1_MMU  25
 414 #define CP0C1_IS   22
 415 #define CP0C1_IL   19
 416 #define CP0C1_IA   16
 417 #define CP0C1_DS   13
 418 #define CP0C1_DL   10
 419 #define CP0C1_DA   7
 420 #define CP0C1_C2   6
 421 #define CP0C1_MD   5
 422 #define CP0C1_PC   4
 423 #define CP0C1_WR   3
 424 #define CP0C1_CA   2
 425 #define CP0C1_EP   1
 426 #define CP0C1_FP   0
 427     int32_t CP0_Config2;
 428 #define CP0C2_M    31
 429 #define CP0C2_TU   28
 430 #define CP0C2_TS   24
 431 #define CP0C2_TL   20
 432 #define CP0C2_TA   16
 433 #define CP0C2_SU   12
 434 #define CP0C2_SS   8
 435 #define CP0C2_SL   4
 436 #define CP0C2_SA   0
 437     int32_t CP0_Config3;
 438 #define CP0C3_M    31
 439 #define CP0C3_BPG  30
 440 #define CP0C3_CMCGR 29
 441 #define CP0C3_MSAP  28
 442 #define CP0C3_BP 27
 443 #define CP0C3_BI 26
 444 #define CP0C3_IPLW 21
 445 #define CP0C3_MMAR 18
 446 #define CP0C3_MCU  17
 447 #define CP0C3_ISA_ON_EXC 16
 448 #define CP0C3_ISA  14
 449 #define CP0C3_ULRI 13
 450 #define CP0C3_RXI  12
 451 #define CP0C3_DSP2P 11
 452 #define CP0C3_DSPP 10
 453 #define CP0C3_LPA  7
 454 #define CP0C3_VEIC 6
 455 #define CP0C3_VInt 5
 456 #define CP0C3_SP   4
 457 #define CP0C3_CDMM 3
 458 #define CP0C3_MT   2
 459 #define CP0C3_SM   1
 460 #define CP0C3_TL   0
 461     int32_t CP0_Config4;
 462     int32_t CP0_Config4_rw_bitmask;
 463 #define CP0C4_M    31
 464 #define CP0C4_IE   29
 465 #define CP0C4_KScrExist 16
 466 #define CP0C4_MMUExtDef 14
 467 #define CP0C4_FTLBPageSize 8
 468 #define CP0C4_FTLBWays 4
 469 #define CP0C4_FTLBSets 0
 470 #define CP0C4_MMUSizeExt 0
 471     int32_t CP0_Config5;
 472     int32_t CP0_Config5_rw_bitmask;
 473 #define CP0C5_M          31
 474 #define CP0C5_K          30
 475 #define CP0C5_CV         29
 476 #define CP0C5_EVA        28
 477 #define CP0C5_MSAEn      27
 478 #define CP0C5_XNP        13
 479 #define CP0C5_UFE        9
 480 #define CP0C5_FRE        8
 481 #define CP0C5_VP         7
 482 #define CP0C5_SBRI       6
 483 #define CP0C5_MVH        5
 484 #define CP0C5_LLB        4
 485 #define CP0C5_UFR        2
 486 #define CP0C5_NFExists   0
 487     int32_t CP0_Config6;
 488     int32_t CP0_Config7;
 489     /* XXX: Maybe make LLAddr per-TC? */
 490     uint64_t lladdr;
 491     target_ulong llval;
 492     target_ulong llnewval;
 493     target_ulong llreg;
 494     uint64_t CP0_LLAddr_rw_bitmask;
 495     int CP0_LLAddr_shift;
 496     target_ulong CP0_WatchLo[8];
 497     int32_t CP0_WatchHi[8];
 498     target_ulong CP0_XContext;
 499     int32_t CP0_Framemask;
 500     int32_t CP0_Debug;
 501 #define CP0DB_DBD  31
 502 #define CP0DB_DM   30
 503 #define CP0DB_LSNM 28
 504 #define CP0DB_Doze 27
 505 #define CP0DB_Halt 26
 506 #define CP0DB_CNT  25
 507 #define CP0DB_IBEP 24
 508 #define CP0DB_DBEP 21
 509 #define CP0DB_IEXI 20
 510 #define CP0DB_VER  15
 511 #define CP0DB_DEC  10
 512 #define CP0DB_SSt  8
 513 #define CP0DB_DINT 5
 514 #define CP0DB_DIB  4
 515 #define CP0DB_DDBS 3
 516 #define CP0DB_DDBL 2
 517 #define CP0DB_DBp  1
 518 #define CP0DB_DSS  0
 519     target_ulong CP0_DEPC;
 520     int32_t CP0_Performance0;
 521     uint64_t CP0_TagLo;
 522     int32_t CP0_DataLo;
 523     int32_t CP0_TagHi;
 524     int32_t CP0_DataHi;
 525     target_ulong CP0_ErrorEPC;
 526     int32_t CP0_DESAVE;
 527     /* We waste some space so we can handle shadow registers like TCs. */
 528     TCState tcs[MIPS_SHADOW_SET_MAX];
 529     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 530     /* QEMU */
 531     int error_code;
 532 #define EXCP_TLB_NOMATCH   0x1
 533 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
 534     uint32_t hflags;    /* CPU State */
 535     /* TMASK defines different execution modes */
 536 #define MIPS_HFLAG_TMASK  0x75807FF
 537 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
 538     /* The KSU flags must be the lowest bits in hflags. The flag order
 539        must be the same as defined for CP0 Status. This allows to use
 540        the bits as the value of mmu_idx. */
 541 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 542 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 543 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
 544 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
 545 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
 546 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
 547 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 548 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 549 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
 550     /* True if the MIPS IV COP1X instructions can be used.  This also
 551        controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 552        and RSQRT.D.  */
 553 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 554 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 555 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
 556 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 557 #define MIPS_HFLAG_M16_SHIFT 10
 558     /* If translation is interrupted between the branch instruction and
 559      * the delay slot, record what type of branch it is so that we can
 560      * resume translation properly.  It might be possible to reduce
 561      * this from three bits to two.  */
 562 #define MIPS_HFLAG_BMASK_BASE  0x803800
 563 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
 564 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
 565 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
 566 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
 567     /* Extra flags about the current pending branch.  */
 568 #define MIPS_HFLAG_BMASK_EXT 0x7C000
 569 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
 570 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
 571 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
 572 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
 573 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
 574 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
 575     /* MIPS DSP resources access. */
 576 #define MIPS_HFLAG_DSP   0x080000  /* Enable access to MIPS DSP resources. */
 577 #define MIPS_HFLAG_DSPR2 0x100000  /* Enable access to MIPS DSPR2 resources. */
 578     /* Extra flag about HWREna register. */
 579 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
 580 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
 581 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
 582 #define MIPS_HFLAG_MSA   0x1000000
 583 #define MIPS_HFLAG_FRE   0x2000000 /* FRE enabled */
 584 #define MIPS_HFLAG_ELPA  0x4000000
 585     target_ulong btarget;        /* Jump / branch target               */
 586     target_ulong bcond;          /* Branch condition (if needed)       */
 587
 588     int SYNCI_Step; /* Address step size for SYNCI */
 589     int CCRes; /* Cycle count resolution/divisor */
 590     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
 591     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
 592     int insn_flags; /* Supported instruction set */
 593
 594     CPU_COMMON
 595
 596     /* Fields from here on are preserved across CPU reset. */
 597     CPUMIPSMVPContext *mvp;
 598 #if !defined(CONFIG_USER_ONLY)
 599     CPUMIPSTLBContext *tlb;
 600 #endif
 601
 602     const mips_def_t *cpu_model;
 603     void *irq[8];
 604     QEMUTimer *timer; /* Internal timer */
 605 };
 606
 607 #include "cpu-qom.h"
 608
 609 #if !defined(CONFIG_USER_ONLY)
 610 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 611                         target_ulong address, int rw, int access_type);
 612 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 613                            target_ulong address, int rw, int access_type);
 614 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 615                      target_ulong address, int rw, int access_type);
 616 void r4k_helper_tlbwi(CPUMIPSState *env);
 617 void r4k_helper_tlbwr(CPUMIPSState *env);
 618 void r4k_helper_tlbp(CPUMIPSState *env);
 619 void r4k_helper_tlbr(CPUMIPSState *env);
 620 void r4k_helper_tlbinv(CPUMIPSState *env);
 621 void r4k_helper_tlbinvf(CPUMIPSState *env);
 622
 623 void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 624                                 bool is_write, bool is_exec, int unused,
 625                                 unsigned size);
 626 #endif
 627
 628 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 629
 630 #define cpu_exec cpu_mips_exec
 631 #define cpu_signal_handler cpu_mips_signal_handler
 632 #define cpu_list mips_cpu_list
 633
 634 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
 635 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 636
 637 /* MMU modes definitions. We carefully match the indices with our
 638    hflags layout. */
 639 #define MMU_MODE0_SUFFIX _kernel
 640 #define MMU_MODE1_SUFFIX _super
 641 #define MMU_MODE2_SUFFIX _user
 642 #define MMU_USER_IDX 2
 643 static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
 644 {
 645     return env->hflags & MIPS_HFLAG_KSU;
 646 }
 647
 648 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 649 {
 650     return (env->CP0_Status & (1 << CP0St_IE)) &&
 651         !(env->CP0_Status & (1 << CP0St_EXL)) &&
 652         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 653         !(env->hflags & MIPS_HFLAG_DM) &&
 654         /* Note that the TCStatus IXMT field is initialized to zero,
 655            and only MT capable cores can set it to one. So we don't
 656            need to check for MT capabilities here.  */
 657         !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
 658 }
 659
 660 /* Check if there is pending and not masked out interrupt */
 661 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 662 {
 663     int32_t pending;
 664     int32_t status;
 665     bool r;
 666
 667     pending = env->CP0_Cause & CP0Ca_IP_mask;
 668     status = env->CP0_Status & CP0Ca_IP_mask;
 669
 670     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 671         /* A MIPS configured with a vectorizing external interrupt controller
 672            will feed a vector into the Cause pending lines. The core treats
 673            the status lines as a vector level, not as indiviual masks.  */
 674         r = pending > status;
 675     } else {
 676         /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
 677            treats the pending lines as individual interrupt lines, the status
 678            lines are individual masks.  */
 679         r = (pending & status) != 0;
 680     }
 681     return r;
 682 }
 683
 684 #include "exec/cpu-all.h"
 685
 686 /* Memory access type :
 687  * may be needed for precise access rights control and precise exceptions.
 688  */
 689 enum {
 690     /* 1 bit to define user level / supervisor access */
 691     ACCESS_USER  = 0x00,
 692     ACCESS_SUPER = 0x01,
 693     /* 1 bit to indicate direction */
 694     ACCESS_STORE = 0x02,
 695     /* Type of instruction that generated the access */
 696     ACCESS_CODE  = 0x10, /* Code fetch access                */
 697     ACCESS_INT   = 0x20, /* Integer load/store access        */
 698     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 699 };
 700
 701 /* Exceptions */
 702 enum {
 703     EXCP_NONE          = -1,
 704     EXCP_RESET         = 0,
 705     EXCP_SRESET,
 706     EXCP_DSS,
 707     EXCP_DINT,
 708     EXCP_DDBL,
 709     EXCP_DDBS,
 710     EXCP_NMI,
 711     EXCP_MCHECK,
 712     EXCP_EXT_INTERRUPT, /* 8 */
 713     EXCP_DFWATCH,
 714     EXCP_DIB,
 715     EXCP_IWATCH,
 716     EXCP_AdEL,
 717     EXCP_AdES,
 718     EXCP_TLBF,
 719     EXCP_IBE,
 720     EXCP_DBp, /* 16 */
 721     EXCP_SYSCALL,
 722     EXCP_BREAK,
 723     EXCP_CpU,
 724     EXCP_RI,
 725     EXCP_OVERFLOW,
 726     EXCP_TRAP,
 727     EXCP_FPE,
 728     EXCP_DWATCH, /* 24 */
 729     EXCP_LTLBL,
 730     EXCP_TLBL,
 731     EXCP_TLBS,
 732     EXCP_DBE,
 733     EXCP_THREAD,
 734     EXCP_MDMX,
 735     EXCP_C2E,
 736     EXCP_CACHE, /* 32 */
 737     EXCP_DSPDIS,
 738     EXCP_MSADIS,
 739     EXCP_MSAFPE,
 740     EXCP_TLBXI,
 741     EXCP_TLBRI,
 742
 743     EXCP_LAST = EXCP_TLBRI,
 744 };
 745 /* Dummy exception for conditional stores.  */
 746 #define EXCP_SC 0x100
 747
 748 /*
 749  * This is an interrnally generated WAKE request line.
 750  * It is driven by the CPU itself. Raised when the MT
 751  * block wants to wake a VPE from an inactive state and
 752  * cleared when VPE goes from active to inactive.
 753  */
 754 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 755
 756 int cpu_mips_exec(CPUState *cpu);
 757 void mips_tcg_init(void);
 758 MIPSCPU *cpu_mips_init(const char *cpu_model);
 759 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 760
 761 #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
 762
 763 /* TODO QOM'ify CPU reset and remove */
 764 void cpu_state_reset(CPUMIPSState *s);
 765
 766 /* mips_timer.c */
 767 uint32_t cpu_mips_get_random (CPUMIPSState *env);
 768 uint32_t cpu_mips_get_count (CPUMIPSState *env);
 769 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
 770 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
 771 void cpu_mips_start_count(CPUMIPSState *env);
 772 void cpu_mips_stop_count(CPUMIPSState *env);
 773
 774 /* mips_int.c */
 775 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
 776
 777 /* helper.c */
 778 int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 779                               int mmu_idx);
 780 #if !defined(CONFIG_USER_ONLY)
 781 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
 782 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
 783                                                int rw);
 784 #endif
 785 target_ulong exception_resume_pc (CPUMIPSState *env);
 786
 787 /* op_helper.c */
 788 extern unsigned int ieee_rm[];
 789 int ieee_ex_to_mips(int xcpt);
 790
 791 static inline void restore_rounding_mode(CPUMIPSState *env)
 792 {
 793     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
 794                             &env->active_fpu.fp_status);
 795 }
 796
 797 static inline void restore_flush_mode(CPUMIPSState *env)
 798 {
 799     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
 800                       &env->active_fpu.fp_status);
 801 }
 802
 803 static inline void restore_fp_status(CPUMIPSState *env)
 804 {
 805     restore_rounding_mode(env);
 806     restore_flush_mode(env);
 807 }
 808
 809 static inline void restore_msa_fp_status(CPUMIPSState *env)
 810 {
 811     float_status *status = &env->active_tc.msa_fp_status;
 812     int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
 813     bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
 814
 815     set_float_rounding_mode(ieee_rm[rounding_mode], status);
 816     set_flush_to_zero(flush_to_zero, status);
 817     set_flush_inputs_to_zero(flush_to_zero, status);
 818 }
 819
 820 static inline void restore_pamask(CPUMIPSState *env)
 821 {
 822     if (env->hflags & MIPS_HFLAG_ELPA) {
 823         env->PAMask = (1ULL << env->PABITS) - 1;
 824     } else {
 825         env->PAMask = PAMASK_BASE;
 826     }
 827 }
 828
 829 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
 830                                         target_ulong *cs_base, int *flags)
 831 {
 832     *pc = env->active_tc.PC;
 833     *cs_base = 0;
 834     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
 835                             MIPS_HFLAG_HWRENA_ULR);
 836 }
 837
 838 static inline int mips_vpe_active(CPUMIPSState *env)
 839 {
 840     int active = 1;
 841
 842     /* Check that the VPE is enabled.  */
 843     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 844         active = 0;
 845     }
 846     /* Check that the VPE is activated.  */
 847     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 848         active = 0;
 849     }
 850
 851     /* Now verify that there are active thread contexts in the VPE.
 852
 853        This assumes the CPU model will internally reschedule threads
 854        if the active one goes to sleep. If there are no threads available
 855        the active one will be in a sleeping state, and we can turn off
 856        the entire VPE.  */
 857     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 858         /* TC is not activated.  */
 859         active = 0;
 860     }
 861     if (env->active_tc.CP0_TCHalt & 1) {
 862         /* TC is in halt state.  */
 863         active = 0;
 864     }
 865
 866     return active;
 867 }
 868
 869 static inline int mips_vp_active(CPUMIPSState *env)
 870 {
 871     CPUState *other_cs = first_cpu;
 872
 873     /* Check if the VP disabled other VPs (which means the VP is enabled) */
 874     if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
 875         return 1;
 876     }
 877
 878     /* Check if the virtual processor is disabled due to a DVP */
 879     CPU_FOREACH(other_cs) {
 880         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
 881         if ((&other_cpu->env != env) &&
 882             ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
 883             return 0;
 884         }
 885     }
 886     return 1;
 887 }
 888
 889 #include "exec/exec-all.h"
 890
 891 static inline void compute_hflags(CPUMIPSState *env)
 892 {
 893     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 894                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 895                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
 896                      MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
 897                      MIPS_HFLAG_ELPA);
 898     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 899         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 900         !(env->hflags & MIPS_HFLAG_DM)) {
 901         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 902     }
 903 #if defined(TARGET_MIPS64)
 904     if ((env->insn_flags & ISA_MIPS3) &&
 905         (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 906          (env->CP0_Status & (1 << CP0St_PX)) ||
 907          (env->CP0_Status & (1 << CP0St_UX)))) {
 908         env->hflags |= MIPS_HFLAG_64;
 909     }
 910
 911     if (!(env->insn_flags & ISA_MIPS3)) {
 912         env->hflags |= MIPS_HFLAG_AWRAP;
 913     } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 914                !(env->CP0_Status & (1 << CP0St_UX))) {
 915         env->hflags |= MIPS_HFLAG_AWRAP;
 916     } else if (env->insn_flags & ISA_MIPS64R6) {
 917         /* Address wrapping for Supervisor and Kernel is specified in R6 */
 918         if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 919              !(env->CP0_Status & (1 << CP0St_SX))) ||
 920             (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 921              !(env->CP0_Status & (1 << CP0St_KX)))) {
 922             env->hflags |= MIPS_HFLAG_AWRAP;
 923         }
 924     }
 925 #endif
 926     if (((env->CP0_Status & (1 << CP0St_CU0)) &&
 927          !(env->insn_flags & ISA_MIPS32R6)) ||
 928         !(env->hflags & MIPS_HFLAG_KSU)) {
 929         env->hflags |= MIPS_HFLAG_CP0;
 930     }
 931     if (env->CP0_Status & (1 << CP0St_CU1)) {
 932         env->hflags |= MIPS_HFLAG_FPU;
 933     }
 934     if (env->CP0_Status & (1 << CP0St_FR)) {
 935         env->hflags |= MIPS_HFLAG_F64;
 936     }
 937     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 938         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 939         env->hflags |= MIPS_HFLAG_SBRI;
 940     }
 941     if (env->insn_flags & ASE_DSPR2) {
 942         /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
 943            so enable to access DSPR2 resources. */
 944         if (env->CP0_Status & (1 << CP0St_MX)) {
 945             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
 946         }
 947
 948     } else if (env->insn_flags & ASE_DSP) {
 949         /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
 950            so enable to access DSP resources. */
 951         if (env->CP0_Status & (1 << CP0St_MX)) {
 952             env->hflags |= MIPS_HFLAG_DSP;
 953         }
 954
 955     }
 956     if (env->insn_flags & ISA_MIPS32R2) {
 957         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 958             env->hflags |= MIPS_HFLAG_COP1X;
 959         }
 960     } else if (env->insn_flags & ISA_MIPS32) {
 961         if (env->hflags & MIPS_HFLAG_64) {
 962             env->hflags |= MIPS_HFLAG_COP1X;
 963         }
 964     } else if (env->insn_flags & ISA_MIPS4) {
 965         /* All supported MIPS IV CPUs use the XX (CU3) to enable
 966            and disable the MIPS IV extensions to the MIPS III ISA.
 967            Some other MIPS IV CPUs ignore the bit, so the check here
 968            would be too restrictive for them.  */
 969         if (env->CP0_Status & (1U << CP0St_CU3)) {
 970             env->hflags |= MIPS_HFLAG_COP1X;
 971         }
 972     }
 973     if (env->insn_flags & ASE_MSA) {
 974         if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
 975             env->hflags |= MIPS_HFLAG_MSA;
 976         }
 977     }
 978     if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
 979         if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
 980             env->hflags |= MIPS_HFLAG_FRE;
 981         }
 982     }
 983     if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
 984         if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
 985             env->hflags |= MIPS_HFLAG_ELPA;
 986         }
 987     }
 988 }
 989
 990 #ifndef CONFIG_USER_ONLY
 991 static inline void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global)
 992 {
 993     MIPSCPU *cpu = mips_env_get_cpu(env);
 994
 995     /* Flush qemu's TLB and discard all shadowed entries.  */
 996     tlb_flush(CPU(cpu), flush_global);
 997     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 998 }
 999
1000 /* Called for updates to CP0_Status.  */
1001 static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
1002 {
1003     int32_t tcstatus, *tcst;
1004     uint32_t v = cpu->CP0_Status;
1005     uint32_t cu, mx, asid, ksu;
1006     uint32_t mask = ((1 << CP0TCSt_TCU3)
1007                        | (1 << CP0TCSt_TCU2)
1008                        | (1 << CP0TCSt_TCU1)
1009                        | (1 << CP0TCSt_TCU0)
1010                        | (1 << CP0TCSt_TMX)
1011                        | (3 << CP0TCSt_TKSU)
1012                        | (0xff << CP0TCSt_TASID));
1013
1014     cu = (v >> CP0St_CU0) & 0xf;
1015     mx = (v >> CP0St_MX) & 0x1;
1016     ksu = (v >> CP0St_KSU) & 0x3;
1017     asid = env->CP0_EntryHi & 0xff;
1018
1019     tcstatus = cu << CP0TCSt_TCU0;
1020     tcstatus |= mx << CP0TCSt_TMX;
1021     tcstatus |= ksu << CP0TCSt_TKSU;
1022     tcstatus |= asid;
1023
1024     if (tc == cpu->current_tc) {
1025         tcst = &cpu->active_tc.CP0_TCStatus;
1026     } else {
1027         tcst = &cpu->tcs[tc].CP0_TCStatus;
1028     }
1029
1030     *tcst &= ~mask;
1031     *tcst |= tcstatus;
1032     compute_hflags(cpu);
1033 }
1034
1035 static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
1036 {
1037     uint32_t mask = env->CP0_Status_rw_bitmask;
1038     target_ulong old = env->CP0_Status;
1039
1040     if (env->insn_flags & ISA_MIPS32R6) {
1041         bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
1042 #if defined(TARGET_MIPS64)
1043         uint32_t ksux = (1 << CP0St_KX) & val;
1044         ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
1045         ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
1046         val = (val & ~(7 << CP0St_UX)) | ksux;
1047 #endif
1048         if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
1049             mask &= ~(3 << CP0St_KSU);
1050         }
1051         mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
1052     }
1053
1054     env->CP0_Status = (old & ~mask) | (val & mask);
1055 #if defined(TARGET_MIPS64)
1056     if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
1057         /* Access to at least one of the 64-bit segments has been disabled */
1058         cpu_mips_tlb_flush(env, 1);
1059     }
1060 #endif
1061     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1062         sync_c0_status(env, env, env->current_tc);
1063     } else {
1064         compute_hflags(env);
1065     }
1066 }
1067
1068 static inline void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
1069 {
1070     uint32_t mask = 0x00C00300;
1071     uint32_t old = env->CP0_Cause;
1072     int i;
1073
1074     if (env->insn_flags & ISA_MIPS32R2) {
1075         mask |= 1 << CP0Ca_DC;
1076     }
1077     if (env->insn_flags & ISA_MIPS32R6) {
1078         mask &= ~((1 << CP0Ca_WP) & val);
1079     }
1080
1081     env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
1082
1083     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1084         if (env->CP0_Cause & (1 << CP0Ca_DC)) {
1085             cpu_mips_stop_count(env);
1086         } else {
1087             cpu_mips_start_count(env);
1088         }
1089     }
1090
1091     /* Set/reset software interrupts */
1092     for (i = 0 ; i < 2 ; i++) {
1093         if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1094             cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
1095         }
1096     }
1097 }
1098 #endif
1099
1100 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
1101                                                         uint32_t exception,
1102                                                         int error_code,
1103                                                         uintptr_t pc)
1104 {
1105     CPUState *cs = CPU(mips_env_get_cpu(env));
1106
1107     if (exception < EXCP_SC) {
1108         qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
1109                       __func__, exception, error_code);
1110     }
1111     cs->exception_index = exception;
1112     env->error_code = error_code;
1113
1114     cpu_loop_exit_restore(cs, pc);
1115 }
1116
1117 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
1118                                                     uint32_t exception,
1119                                                     uintptr_t pc)
1120 {
1121     do_raise_exception_err(env, exception, 0, pc);
1122 }
1123
1124 #endif /* !defined (__MIPS_CPU_H__) */