hw/misc/zynq_slcr.c

   1 /*
   2  * Status and system control registers for Xilinx Zynq Platform
   3  *
   4  * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
   5  * Copyright (c) 2012 PetaLogix Pty Ltd.
   6  * Based on hw/arm_sysctl.c, written by Paul Brook
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include "qemu/osdep.h"
  18 #include "hw/hw.h"
  19 #include "qemu/timer.h"
  20 #include "hw/sysbus.h"
  21 #include "sysemu/sysemu.h"
  22
  23 #ifndef ZYNQ_SLCR_ERR_DEBUG
  24 #define ZYNQ_SLCR_ERR_DEBUG 0
  25 #endif
  26
  27 #define DB_PRINT(...) do { \
  28         if (ZYNQ_SLCR_ERR_DEBUG) { \
  29             fprintf(stderr,  ": %s: ", __func__); \
  30             fprintf(stderr, ## __VA_ARGS__); \
  31         } \
  32     } while (0);
  33
  34 #define XILINX_LOCK_KEY 0x767b
  35 #define XILINX_UNLOCK_KEY 0xdf0d
  36
  37 #define R_PSS_RST_CTRL_SOFT_RST 0x1
  38
  39 enum {
  40     SCL             = 0x000 / 4,
  41     LOCK,
  42     UNLOCK,
  43     LOCKSTA,
  44
  45     ARM_PLL_CTRL    = 0x100 / 4,
  46     DDR_PLL_CTRL,
  47     IO_PLL_CTRL,
  48     PLL_STATUS,
  49     ARM_PLL_CFG,
  50     DDR_PLL_CFG,
  51     IO_PLL_CFG,
  52
  53     ARM_CLK_CTRL    = 0x120 / 4,
  54     DDR_CLK_CTRL,
  55     DCI_CLK_CTRL,
  56     APER_CLK_CTRL,
  57     USB0_CLK_CTRL,
  58     USB1_CLK_CTRL,
  59     GEM0_RCLK_CTRL,
  60     GEM1_RCLK_CTRL,
  61     GEM0_CLK_CTRL,
  62     GEM1_CLK_CTRL,
  63     SMC_CLK_CTRL,
  64     LQSPI_CLK_CTRL,
  65     SDIO_CLK_CTRL,
  66     UART_CLK_CTRL,
  67     SPI_CLK_CTRL,
  68     CAN_CLK_CTRL,
  69     CAN_MIOCLK_CTRL,
  70     DBG_CLK_CTRL,
  71     PCAP_CLK_CTRL,
  72     TOPSW_CLK_CTRL,
  73
  74 #define FPGA_CTRL_REGS(n, start) \
  75     FPGA ## n ## _CLK_CTRL = (start) / 4, \
  76     FPGA ## n ## _THR_CTRL, \
  77     FPGA ## n ## _THR_CNT, \
  78     FPGA ## n ## _THR_STA,
  79     FPGA_CTRL_REGS(0, 0x170)
  80     FPGA_CTRL_REGS(1, 0x180)
  81     FPGA_CTRL_REGS(2, 0x190)
  82     FPGA_CTRL_REGS(3, 0x1a0)
  83
  84     BANDGAP_TRIP    = 0x1b8 / 4,
  85     PLL_PREDIVISOR  = 0x1c0 / 4,
  86     CLK_621_TRUE,
  87
  88     PSS_RST_CTRL    = 0x200 / 4,
  89     DDR_RST_CTRL,
  90     TOPSW_RESET_CTRL,
  91     DMAC_RST_CTRL,
  92     USB_RST_CTRL,
  93     GEM_RST_CTRL,
  94     SDIO_RST_CTRL,
  95     SPI_RST_CTRL,
  96     CAN_RST_CTRL,
  97     I2C_RST_CTRL,
  98     UART_RST_CTRL,
  99     GPIO_RST_CTRL,
 100     LQSPI_RST_CTRL,
 101     SMC_RST_CTRL,
 102     OCM_RST_CTRL,
 103     FPGA_RST_CTRL   = 0x240 / 4,
 104     A9_CPU_RST_CTRL,
 105
 106     RS_AWDT_CTRL    = 0x24c / 4,
 107     RST_REASON,
 108
 109     REBOOT_STATUS   = 0x258 / 4,
 110     BOOT_MODE,
 111
 112     APU_CTRL        = 0x300 / 4,
 113     WDT_CLK_SEL,
 114
 115     TZ_DMA_NS       = 0x440 / 4,
 116     TZ_DMA_IRQ_NS,
 117     TZ_DMA_PERIPH_NS,
 118
 119     PSS_IDCODE      = 0x530 / 4,
 120
 121     DDR_URGENT      = 0x600 / 4,
 122     DDR_CAL_START   = 0x60c / 4,
 123     DDR_REF_START   = 0x614 / 4,
 124     DDR_CMD_STA,
 125     DDR_URGENT_SEL,
 126     DDR_DFI_STATUS,
 127
 128     MIO             = 0x700 / 4,
 129 #define MIO_LENGTH 54
 130
 131     MIO_LOOPBACK    = 0x804 / 4,
 132     MIO_MST_TRI0,
 133     MIO_MST_TRI1,
 134
 135     SD0_WP_CD_SEL   = 0x830 / 4,
 136     SD1_WP_CD_SEL,
 137
 138     LVL_SHFTR_EN    = 0x900 / 4,
 139     OCM_CFG         = 0x910 / 4,
 140
 141     CPU_RAM         = 0xa00 / 4,
 142
 143     IOU             = 0xa30 / 4,
 144
 145     DMAC_RAM        = 0xa50 / 4,
 146
 147     AFI0            = 0xa60 / 4,
 148     AFI1 = AFI0 + 3,
 149     AFI2 = AFI1 + 3,
 150     AFI3 = AFI2 + 3,
 151 #define AFI_LENGTH 3
 152
 153     OCM             = 0xa90 / 4,
 154
 155     DEVCI_RAM       = 0xaa0 / 4,
 156
 157     CSG_RAM         = 0xab0 / 4,
 158
 159     GPIOB_CTRL      = 0xb00 / 4,
 160     GPIOB_CFG_CMOS18,
 161     GPIOB_CFG_CMOS25,
 162     GPIOB_CFG_CMOS33,
 163     GPIOB_CFG_HSTL  = 0xb14 / 4,
 164     GPIOB_DRVR_BIAS_CTRL,
 165
 166     DDRIOB          = 0xb40 / 4,
 167 #define DDRIOB_LENGTH 14
 168 };
 169
 170 #define ZYNQ_SLCR_MMIO_SIZE     0x1000
 171 #define ZYNQ_SLCR_NUM_REGS      (ZYNQ_SLCR_MMIO_SIZE / 4)
 172
 173 #define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
 174 #define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
 175
 176 typedef struct ZynqSLCRState {
 177     SysBusDevice parent_obj;
 178
 179     MemoryRegion iomem;
 180
 181     uint32_t regs[ZYNQ_SLCR_NUM_REGS];
 182 } ZynqSLCRState;
 183
 184 static void zynq_slcr_reset(DeviceState *d)
 185 {
 186     ZynqSLCRState *s = ZYNQ_SLCR(d);
 187     int i;
 188
 189     DB_PRINT("RESET\n");
 190
 191     s->regs[LOCKSTA] = 1;
 192     /* 0x100 - 0x11C */
 193     s->regs[ARM_PLL_CTRL]   = 0x0001A008;
 194     s->regs[DDR_PLL_CTRL]   = 0x0001A008;
 195     s->regs[IO_PLL_CTRL]    = 0x0001A008;
 196     s->regs[PLL_STATUS]     = 0x0000003F;
 197     s->regs[ARM_PLL_CFG]    = 0x00014000;
 198     s->regs[DDR_PLL_CFG]    = 0x00014000;
 199     s->regs[IO_PLL_CFG]     = 0x00014000;
 200
 201     /* 0x120 - 0x16C */
 202     s->regs[ARM_CLK_CTRL]   = 0x1F000400;
 203     s->regs[DDR_CLK_CTRL]   = 0x18400003;
 204     s->regs[DCI_CLK_CTRL]   = 0x01E03201;
 205     s->regs[APER_CLK_CTRL]  = 0x01FFCCCD;
 206     s->regs[USB0_CLK_CTRL]  = s->regs[USB1_CLK_CTRL]    = 0x00101941;
 207     s->regs[GEM0_RCLK_CTRL] = s->regs[GEM1_RCLK_CTRL]   = 0x00000001;
 208     s->regs[GEM0_CLK_CTRL]  = s->regs[GEM1_CLK_CTRL]    = 0x00003C01;
 209     s->regs[SMC_CLK_CTRL]   = 0x00003C01;
 210     s->regs[LQSPI_CLK_CTRL] = 0x00002821;
 211     s->regs[SDIO_CLK_CTRL]  = 0x00001E03;
 212     s->regs[UART_CLK_CTRL]  = 0x00003F03;
 213     s->regs[SPI_CLK_CTRL]   = 0x00003F03;
 214     s->regs[CAN_CLK_CTRL]   = 0x00501903;
 215     s->regs[DBG_CLK_CTRL]   = 0x00000F03;
 216     s->regs[PCAP_CLK_CTRL]  = 0x00000F01;
 217
 218     /* 0x170 - 0x1AC */
 219     s->regs[FPGA0_CLK_CTRL] = s->regs[FPGA1_CLK_CTRL] = s->regs[FPGA2_CLK_CTRL]
 220                             = s->regs[FPGA3_CLK_CTRL] = 0x00101800;
 221     s->regs[FPGA0_THR_STA] = s->regs[FPGA1_THR_STA] = s->regs[FPGA2_THR_STA]
 222                            = s->regs[FPGA3_THR_STA] = 0x00010000;
 223
 224     /* 0x1B0 - 0x1D8 */
 225     s->regs[BANDGAP_TRIP]   = 0x0000001F;
 226     s->regs[PLL_PREDIVISOR] = 0x00000001;
 227     s->regs[CLK_621_TRUE]   = 0x00000001;
 228
 229     /* 0x200 - 0x25C */
 230     s->regs[FPGA_RST_CTRL]  = 0x01F33F0F;
 231     s->regs[RST_REASON]     = 0x00000040;
 232
 233     s->regs[BOOT_MODE]      = 0x00000001;
 234
 235     /* 0x700 - 0x7D4 */
 236     for (i = 0; i < 54; i++) {
 237         s->regs[MIO + i] = 0x00001601;
 238     }
 239     for (i = 2; i <= 8; i++) {
 240         s->regs[MIO + i] = 0x00000601;
 241     }
 242
 243     s->regs[MIO_MST_TRI0] = s->regs[MIO_MST_TRI1] = 0xFFFFFFFF;
 244
 245     s->regs[CPU_RAM + 0] = s->regs[CPU_RAM + 1] = s->regs[CPU_RAM + 3]
 246                          = s->regs[CPU_RAM + 4] = s->regs[CPU_RAM + 7]
 247                          = 0x00010101;
 248     s->regs[CPU_RAM + 2] = s->regs[CPU_RAM + 5] = 0x01010101;
 249     s->regs[CPU_RAM + 6] = 0x00000001;
 250
 251     s->regs[IOU + 0] = s->regs[IOU + 1] = s->regs[IOU + 2] = s->regs[IOU + 3]
 252                      = 0x09090909;
 253     s->regs[IOU + 4] = s->regs[IOU + 5] = 0x00090909;
 254     s->regs[IOU + 6] = 0x00000909;
 255
 256     s->regs[DMAC_RAM] = 0x00000009;
 257
 258     s->regs[AFI0 + 0] = s->regs[AFI0 + 1] = 0x09090909;
 259     s->regs[AFI1 + 0] = s->regs[AFI1 + 1] = 0x09090909;
 260     s->regs[AFI2 + 0] = s->regs[AFI2 + 1] = 0x09090909;
 261     s->regs[AFI3 + 0] = s->regs[AFI3 + 1] = 0x09090909;
 262     s->regs[AFI0 + 2] = s->regs[AFI1 + 2] = s->regs[AFI2 + 2]
 263                       = s->regs[AFI3 + 2] = 0x00000909;
 264
 265     s->regs[OCM + 0]    = 0x01010101;
 266     s->regs[OCM + 1]    = s->regs[OCM + 2] = 0x09090909;
 267
 268     s->regs[DEVCI_RAM]  = 0x00000909;
 269     s->regs[CSG_RAM]    = 0x00000001;
 270
 271     s->regs[DDRIOB + 0] = s->regs[DDRIOB + 1] = s->regs[DDRIOB + 2]
 272                         = s->regs[DDRIOB + 3] = 0x00000e00;
 273     s->regs[DDRIOB + 4] = s->regs[DDRIOB + 5] = s->regs[DDRIOB + 6]
 274                         = 0x00000e00;
 275     s->regs[DDRIOB + 12] = 0x00000021;
 276 }
 277
 278
 279 static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
 280 {
 281     switch (offset) {
 282     case LOCK:
 283     case UNLOCK:
 284     case DDR_CAL_START:
 285     case DDR_REF_START:
 286         return !rnw; /* Write only */
 287     case LOCKSTA:
 288     case FPGA0_THR_STA:
 289     case FPGA1_THR_STA:
 290     case FPGA2_THR_STA:
 291     case FPGA3_THR_STA:
 292     case BOOT_MODE:
 293     case PSS_IDCODE:
 294     case DDR_CMD_STA:
 295     case DDR_DFI_STATUS:
 296     case PLL_STATUS:
 297         return rnw;/* read only */
 298     case SCL:
 299     case ARM_PLL_CTRL ... IO_PLL_CTRL:
 300     case ARM_PLL_CFG ... IO_PLL_CFG:
 301     case ARM_CLK_CTRL ... TOPSW_CLK_CTRL:
 302     case FPGA0_CLK_CTRL ... FPGA0_THR_CNT:
 303     case FPGA1_CLK_CTRL ... FPGA1_THR_CNT:
 304     case FPGA2_CLK_CTRL ... FPGA2_THR_CNT:
 305     case FPGA3_CLK_CTRL ... FPGA3_THR_CNT:
 306     case BANDGAP_TRIP:
 307     case PLL_PREDIVISOR:
 308     case CLK_621_TRUE:
 309     case PSS_RST_CTRL ... A9_CPU_RST_CTRL:
 310     case RS_AWDT_CTRL:
 311     case RST_REASON:
 312     case REBOOT_STATUS:
 313     case APU_CTRL:
 314     case WDT_CLK_SEL:
 315     case TZ_DMA_NS ... TZ_DMA_PERIPH_NS:
 316     case DDR_URGENT:
 317     case DDR_URGENT_SEL:
 318     case MIO ... MIO + MIO_LENGTH - 1:
 319     case MIO_LOOPBACK ... MIO_MST_TRI1:
 320     case SD0_WP_CD_SEL:
 321     case SD1_WP_CD_SEL:
 322     case LVL_SHFTR_EN:
 323     case OCM_CFG:
 324     case CPU_RAM:
 325     case IOU:
 326     case DMAC_RAM:
 327     case AFI0 ... AFI3 + AFI_LENGTH - 1:
 328     case OCM:
 329     case DEVCI_RAM:
 330     case CSG_RAM:
 331     case GPIOB_CTRL ... GPIOB_CFG_CMOS33:
 332     case GPIOB_CFG_HSTL:
 333     case GPIOB_DRVR_BIAS_CTRL:
 334     case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1:
 335         return true;
 336     default:
 337         return false;
 338     }
 339 }
 340
 341 static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
 342     unsigned size)
 343 {
 344     ZynqSLCRState *s = opaque;
 345     offset /= 4;
 346     uint32_t ret = s->regs[offset];
 347
 348     if (!zynq_slcr_check_offset(offset, true)) {
 349         qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to "
 350                       " addr %" HWADDR_PRIx "\n", offset * 4);
 351     }
 352
 353     DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret);
 354     return ret;
 355 }
 356
 357 static void zynq_slcr_write(void *opaque, hwaddr offset,
 358                           uint64_t val, unsigned size)
 359 {
 360     ZynqSLCRState *s = (ZynqSLCRState *)opaque;
 361     offset /= 4;
 362
 363     DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val);
 364
 365     if (!zynq_slcr_check_offset(offset, false)) {
 366         qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid write access to "
 367                       "addr %" HWADDR_PRIx "\n", offset * 4);
 368         return;
 369     }
 370
 371     switch (offset) {
 372     case SCL:
 373         s->regs[SCL] = val & 0x1;
 374         return;
 375     case LOCK:
 376         if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
 377             DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
 378                 (unsigned)val & 0xFFFF);
 379             s->regs[LOCKSTA] = 1;
 380         } else {
 381             DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
 382                 (int)offset, (unsigned)val & 0xFFFF);
 383         }
 384         return;
 385     case UNLOCK:
 386         if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
 387             DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
 388                 (unsigned)val & 0xFFFF);
 389             s->regs[LOCKSTA] = 0;
 390         } else {
 391             DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
 392                 (int)offset, (unsigned)val & 0xFFFF);
 393         }
 394         return;
 395     }
 396
 397     if (s->regs[LOCKSTA]) {
 398         qemu_log_mask(LOG_GUEST_ERROR,
 399                       "SCLR registers are locked. Unlock them first\n");
 400         return;
 401     }
 402     s->regs[offset] = val;
 403
 404     switch (offset) {
 405     case PSS_RST_CTRL:
 406         if (val & R_PSS_RST_CTRL_SOFT_RST) {
 407             qemu_system_reset_request();
 408         }
 409         break;
 410     }
 411 }
 412
 413 static const MemoryRegionOps slcr_ops = {
 414     .read = zynq_slcr_read,
 415     .write = zynq_slcr_write,
 416     .endianness = DEVICE_NATIVE_ENDIAN,
 417 };
 418
 419 static void zynq_slcr_init(Object *obj)
 420 {
 421     ZynqSLCRState *s = ZYNQ_SLCR(obj);
 422
 423     memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr",
 424                           ZYNQ_SLCR_MMIO_SIZE);
 425     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
 426 }
 427
 428 static const VMStateDescription vmstate_zynq_slcr = {
 429     .name = "zynq_slcr",
 430     .version_id = 2,
 431     .minimum_version_id = 2,
 432     .fields = (VMStateField[]) {
 433         VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS),
 434         VMSTATE_END_OF_LIST()
 435     }
 436 };
 437
 438 static void zynq_slcr_class_init(ObjectClass *klass, void *data)
 439 {
 440     DeviceClass *dc = DEVICE_CLASS(klass);
 441
 442     dc->vmsd = &vmstate_zynq_slcr;
 443     dc->reset = zynq_slcr_reset;
 444 }
 445
 446 static const TypeInfo zynq_slcr_info = {
 447     .class_init = zynq_slcr_class_init,
 448     .name  = TYPE_ZYNQ_SLCR,
 449     .parent = TYPE_SYS_BUS_DEVICE,
 450     .instance_size  = sizeof(ZynqSLCRState),
 451     .instance_init = zynq_slcr_init,
 452 };
 453
 454 static void zynq_slcr_register_types(void)
 455 {
 456     type_register_static(&zynq_slcr_info);
 457 }
 458
 459 type_init(zynq_slcr_register_types)