hw/misc/imx25_ccm.c

   1 /*
   2  * IMX25 Clock Control Module
   3  *
   4  * Copyright (C) 2012 NICTA
   5  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
   6  *
   7  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   8  * See the COPYING file in the top-level directory.
   9  *
  10  * To get the timer frequencies right, we need to emulate at least part of
  11  * the CCM.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "hw/misc/imx25_ccm.h"
  16
  17 #ifndef DEBUG_IMX25_CCM
  18 #define DEBUG_IMX25_CCM 0
  19 #endif
  20
  21 #define DPRINTF(fmt, args...) \
  22     do { \
  23         if (DEBUG_IMX25_CCM) { \
  24             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX25_CCM, \
  25                                              __func__, ##args); \
  26         } \
  27     } while (0)
  28
  29 static char const *imx25_ccm_reg_name(uint32_t reg)
  30 {
  31     static char unknown[20];
  32
  33     switch (reg) {
  34     case IMX25_CCM_MPCTL_REG:
  35         return "mpctl";
  36     case IMX25_CCM_UPCTL_REG:
  37         return "upctl";
  38     case IMX25_CCM_CCTL_REG:
  39         return "cctl";
  40     case IMX25_CCM_CGCR0_REG:
  41         return "cgcr0";
  42     case IMX25_CCM_CGCR1_REG:
  43         return "cgcr1";
  44     case IMX25_CCM_CGCR2_REG:
  45         return "cgcr2";
  46     case IMX25_CCM_PCDR0_REG:
  47         return "pcdr0";
  48     case IMX25_CCM_PCDR1_REG:
  49         return "pcdr1";
  50     case IMX25_CCM_PCDR2_REG:
  51         return "pcdr2";
  52     case IMX25_CCM_PCDR3_REG:
  53         return "pcdr3";
  54     case IMX25_CCM_RCSR_REG:
  55         return "rcsr";
  56     case IMX25_CCM_CRDR_REG:
  57         return "crdr";
  58     case IMX25_CCM_DCVR0_REG:
  59         return "dcvr0";
  60     case IMX25_CCM_DCVR1_REG:
  61         return "dcvr1";
  62     case IMX25_CCM_DCVR2_REG:
  63         return "dcvr2";
  64     case IMX25_CCM_DCVR3_REG:
  65         return "dcvr3";
  66     case IMX25_CCM_LTR0_REG:
  67         return "ltr0";
  68     case IMX25_CCM_LTR1_REG:
  69         return "ltr1";
  70     case IMX25_CCM_LTR2_REG:
  71         return "ltr2";
  72     case IMX25_CCM_LTR3_REG:
  73         return "ltr3";
  74     case IMX25_CCM_LTBR0_REG:
  75         return "ltbr0";
  76     case IMX25_CCM_LTBR1_REG:
  77         return "ltbr1";
  78     case IMX25_CCM_PMCR0_REG:
  79         return "pmcr0";
  80     case IMX25_CCM_PMCR1_REG:
  81         return "pmcr1";
  82     case IMX25_CCM_PMCR2_REG:
  83         return "pmcr2";
  84     case IMX25_CCM_MCR_REG:
  85         return "mcr";
  86     case IMX25_CCM_LPIMR0_REG:
  87         return "lpimr0";
  88     case IMX25_CCM_LPIMR1_REG:
  89         return "lpimr1";
  90     default:
  91         sprintf(unknown, "[%d ?]", reg);
  92         return unknown;
  93     }
  94 }
  95 #define CKIH_FREQ 24000000 /* 24MHz crystal input */
  96
  97 static const VMStateDescription vmstate_imx25_ccm = {
  98     .name = TYPE_IMX25_CCM,
  99     .version_id = 1,
 100     .minimum_version_id = 1,
 101     .fields = (VMStateField[]) {
 102         VMSTATE_UINT32_ARRAY(reg, IMX25CCMState, IMX25_CCM_MAX_REG),
 103         VMSTATE_END_OF_LIST()
 104     },
 105 };
 106
 107 static uint32_t imx25_ccm_get_mpll_clk(IMXCCMState *dev)
 108 {
 109     uint32_t freq;
 110     IMX25CCMState *s = IMX25_CCM(dev);
 111
 112     if (EXTRACT(s->reg[IMX25_CCM_CCTL_REG], MPLL_BYPASS)) {
 113         freq = CKIH_FREQ;
 114     } else {
 115         freq = imx_ccm_calc_pll(s->reg[IMX25_CCM_MPCTL_REG], CKIH_FREQ);
 116     }
 117
 118     DPRINTF("freq = %d\n", freq);
 119
 120     return freq;
 121 }
 122
 123 static uint32_t imx25_ccm_get_upll_clk(IMXCCMState *dev)
 124 {
 125     uint32_t freq = 0;
 126     IMX25CCMState *s = IMX25_CCM(dev);
 127
 128     if (!EXTRACT(s->reg[IMX25_CCM_CCTL_REG], UPLL_DIS)) {
 129         freq = imx_ccm_calc_pll(s->reg[IMX25_CCM_UPCTL_REG], CKIH_FREQ);
 130     }
 131
 132     DPRINTF("freq = %d\n", freq);
 133
 134     return freq;
 135 }
 136
 137 static uint32_t imx25_ccm_get_mcu_clk(IMXCCMState *dev)
 138 {
 139     uint32_t freq;
 140     IMX25CCMState *s = IMX25_CCM(dev);
 141
 142     freq = imx25_ccm_get_mpll_clk(dev);
 143
 144     if (EXTRACT(s->reg[IMX25_CCM_CCTL_REG], ARM_SRC)) {
 145         freq = (freq * 3 / 4);
 146     }
 147
 148     freq = freq / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], ARM_CLK_DIV));
 149
 150     DPRINTF("freq = %d\n", freq);
 151
 152     return freq;
 153 }
 154
 155 static uint32_t imx25_ccm_get_ahb_clk(IMXCCMState *dev)
 156 {
 157     uint32_t freq;
 158     IMX25CCMState *s = IMX25_CCM(dev);
 159
 160     freq = imx25_ccm_get_mcu_clk(dev)
 161            / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], AHB_CLK_DIV));
 162
 163     DPRINTF("freq = %d\n", freq);
 164
 165     return freq;
 166 }
 167
 168 static uint32_t imx25_ccm_get_ipg_clk(IMXCCMState *dev)
 169 {
 170     uint32_t freq;
 171
 172     freq = imx25_ccm_get_ahb_clk(dev) / 2;
 173
 174     DPRINTF("freq = %d\n", freq);
 175
 176     return freq;
 177 }
 178
 179 static uint32_t imx25_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
 180 {
 181     uint32_t freq = 0;
 182     DPRINTF("Clock = %d)\n", clock);
 183
 184     switch (clock) {
 185     case NOCLK:
 186         break;
 187     case CLK_MPLL:
 188         freq = imx25_ccm_get_mpll_clk(dev);
 189         break;
 190     case CLK_UPLL:
 191         freq = imx25_ccm_get_upll_clk(dev);
 192         break;
 193     case CLK_MCU:
 194         freq = imx25_ccm_get_mcu_clk(dev);
 195         break;
 196     case CLK_AHB:
 197         freq = imx25_ccm_get_ahb_clk(dev);
 198         break;
 199     case CLK_IPG:
 200         freq = imx25_ccm_get_ipg_clk(dev);
 201         break;
 202     case CLK_32k:
 203         freq = CKIL_FREQ;
 204         break;
 205     default:
 206         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
 207                       TYPE_IMX25_CCM, __func__, clock);
 208         break;
 209     }
 210
 211     DPRINTF("Clock = %d) = %d\n", clock, freq);
 212
 213     return freq;
 214 }
 215
 216 static void imx25_ccm_reset(DeviceState *dev)
 217 {
 218     IMX25CCMState *s = IMX25_CCM(dev);
 219
 220     DPRINTF("\n");
 221
 222     memset(s->reg, 0, IMX25_CCM_MAX_REG * sizeof(uint32_t));
 223     s->reg[IMX25_CCM_MPCTL_REG] = 0x800b2c01;
 224     s->reg[IMX25_CCM_UPCTL_REG] = 0x84042800;
 225     /*
 226      * The value below gives:
 227      * CPU = 133 MHz, AHB = 66,5 MHz, IPG = 33 MHz.
 228      */
 229     s->reg[IMX25_CCM_CCTL_REG]  = 0xd0030000;
 230     s->reg[IMX25_CCM_CGCR0_REG] = 0x028A0100;
 231     s->reg[IMX25_CCM_CGCR1_REG] = 0x04008100;
 232     s->reg[IMX25_CCM_CGCR2_REG] = 0x00000438;
 233     s->reg[IMX25_CCM_PCDR0_REG] = 0x01010101;
 234     s->reg[IMX25_CCM_PCDR1_REG] = 0x01010101;
 235     s->reg[IMX25_CCM_PCDR2_REG] = 0x01010101;
 236     s->reg[IMX25_CCM_PCDR3_REG] = 0x01010101;
 237     s->reg[IMX25_CCM_PMCR0_REG] = 0x00A00000;
 238     s->reg[IMX25_CCM_PMCR1_REG] = 0x0000A030;
 239     s->reg[IMX25_CCM_PMCR2_REG] = 0x0000A030;
 240     s->reg[IMX25_CCM_MCR_REG]   = 0x43000000;
 241
 242     /*
 243      * default boot will change the reset values to allow:
 244      * CPU = 399 MHz, AHB = 133 MHz, IPG = 66,5 MHz.
 245      * For some reason, this doesn't work. With the value below, linux
 246      * detects a 88 MHz IPG CLK instead of 66,5 MHz.
 247     s->reg[IMX25_CCM_CCTL_REG]  = 0x20032000;
 248      */
 249 }
 250
 251 static uint64_t imx25_ccm_read(void *opaque, hwaddr offset, unsigned size)
 252 {
 253     uint32_t value = 0;
 254     IMX25CCMState *s = (IMX25CCMState *)opaque;
 255
 256     if (offset < 0x70) {
 257         value = s->reg[offset >> 2];
 258     } else {
 259         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 260                       HWADDR_PRIx "\n", TYPE_IMX25_CCM, __func__, offset);
 261     }
 262
 263     DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx25_ccm_reg_name(offset >> 2),
 264             value);
 265
 266     return value;
 267 }
 268
 269 static void imx25_ccm_write(void *opaque, hwaddr offset, uint64_t value,
 270                             unsigned size)
 271 {
 272     IMX25CCMState *s = (IMX25CCMState *)opaque;
 273
 274     DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx25_ccm_reg_name(offset >> 2),
 275             (uint32_t)value);
 276
 277     if (offset < 0x70) {
 278         /*
 279          * We will do a better implementation later. In particular some bits
 280          * cannot be written to.
 281          */
 282         s->reg[offset >> 2] = value;
 283     } else {
 284         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 285                       HWADDR_PRIx "\n", TYPE_IMX25_CCM, __func__, offset);
 286     }
 287 }
 288
 289 static const struct MemoryRegionOps imx25_ccm_ops = {
 290     .read = imx25_ccm_read,
 291     .write = imx25_ccm_write,
 292     .endianness = DEVICE_NATIVE_ENDIAN,
 293     .valid = {
 294         /*
 295          * Our device would not work correctly if the guest was doing
 296          * unaligned access. This might not be a limitation on the real
 297          * device but in practice there is no reason for a guest to access
 298          * this device unaligned.
 299          */
 300         .min_access_size = 4,
 301         .max_access_size = 4,
 302         .unaligned = false,
 303     },
 304 };
 305
 306 static void imx25_ccm_init(Object *obj)
 307 {
 308     DeviceState *dev = DEVICE(obj);
 309     SysBusDevice *sd = SYS_BUS_DEVICE(obj);
 310     IMX25CCMState *s = IMX25_CCM(obj);
 311
 312     memory_region_init_io(&s->iomem, OBJECT(dev), &imx25_ccm_ops, s,
 313                           TYPE_IMX25_CCM, 0x1000);
 314     sysbus_init_mmio(sd, &s->iomem);
 315 }
 316
 317 static void imx25_ccm_class_init(ObjectClass *klass, void *data)
 318 {
 319     DeviceClass *dc = DEVICE_CLASS(klass);
 320     IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
 321
 322     dc->reset = imx25_ccm_reset;
 323     dc->vmsd = &vmstate_imx25_ccm;
 324     dc->desc = "i.MX25 Clock Control Module";
 325
 326     ccm->get_clock_frequency = imx25_ccm_get_clock_frequency;
 327 }
 328
 329 static const TypeInfo imx25_ccm_info = {
 330     .name          = TYPE_IMX25_CCM,
 331     .parent        = TYPE_IMX_CCM,
 332     .instance_size = sizeof(IMX25CCMState),
 333     .instance_init = imx25_ccm_init,
 334     .class_init    = imx25_ccm_class_init,
 335 };
 336
 337 static void imx25_ccm_register_types(void)
 338 {
 339     type_register_static(&imx25_ccm_info);
 340 }
 341
 342 type_init(imx25_ccm_register_types)