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pc: acpi: isolate FADT specific data into AcpiFadtData structure
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob1f88ed1a11609e273baeb75c530d01ac1e4a81b7
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "qemu-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "qom/cpu.h"
32 #include "target/i386/cpu.h"
33 #include "hw/misc/pvpanic.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/loader.h"
41 #include "hw/isa/isa.h"
42 #include "hw/block/fdc.h"
43 #include "hw/acpi/memory_hotplug.h"
44 #include "sysemu/tpm.h"
45 #include "hw/acpi/tpm.h"
46 #include "hw/acpi/vmgenid.h"
47 #include "sysemu/tpm_backend.h"
48 #include "hw/timer/mc146818rtc_regs.h"
49 #include "sysemu/numa.h"
50
51 /* Supported chipsets: */
52 #include "hw/acpi/piix4.h"
53 #include "hw/acpi/pcihp.h"
54 #include "hw/i386/ich9.h"
55 #include "hw/pci/pci_bus.h"
56 #include "hw/pci-host/q35.h"
57 #include "hw/i386/x86-iommu.h"
58
59 #include "hw/acpi/aml-build.h"
60
61 #include "qom/qom-qobject.h"
62 #include "hw/i386/amd_iommu.h"
63 #include "hw/i386/intel_iommu.h"
64
65 #include "hw/acpi/ipmi.h"
66
67 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
68 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
69 * a little bit, there should be plenty of free space since the DSDT
70 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
71 */
72 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
73 #define ACPI_BUILD_ALIGN_SIZE 0x1000
74
75 #define ACPI_BUILD_TABLE_SIZE 0x20000
76
77 /* #define DEBUG_ACPI_BUILD */
78 #ifdef DEBUG_ACPI_BUILD
79 #define ACPI_BUILD_DPRINTF(fmt, ...) \
80 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
81 #else
82 #define ACPI_BUILD_DPRINTF(fmt, ...)
83 #endif
84
85 /* Default IOAPIC ID */
86 #define ACPI_BUILD_IOAPIC_ID 0x0
87
88 typedef struct AcpiMcfgInfo {
89 uint64_t mcfg_base;
90 uint32_t mcfg_size;
91 } AcpiMcfgInfo;
92
93 typedef struct AcpiPmInfo {
94 bool s3_disabled;
95 bool s4_disabled;
96 bool pcihp_bridge_en;
97 uint8_t s4_val;
98 AcpiFadtData fadt;
99 uint16_t cpu_hp_io_base;
100 uint16_t pcihp_io_base;
101 uint16_t pcihp_io_len;
102 } AcpiPmInfo;
103
104 typedef struct AcpiMiscInfo {
105 bool is_piix4;
106 bool has_hpet;
107 TPMVersion tpm_version;
108 const unsigned char *dsdt_code;
109 unsigned dsdt_size;
110 uint16_t pvpanic_port;
111 uint16_t applesmc_io_base;
112 } AcpiMiscInfo;
113
114 typedef struct AcpiBuildPciBusHotplugState {
115 GArray *device_table;
116 GArray *notify_table;
117 struct AcpiBuildPciBusHotplugState *parent;
118 bool pcihp_bridge_en;
119 } AcpiBuildPciBusHotplugState;
120
121 static void init_common_fadt_data(Object *o, AcpiFadtData *data)
122 {
123 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
124 AmlAddressSpace as = AML_AS_SYSTEM_IO;
125 AcpiFadtData fadt = {
126 .rev = 3,
127 .flags =
128 (1 << ACPI_FADT_F_WBINVD) |
129 (1 << ACPI_FADT_F_PROC_C1) |
130 (1 << ACPI_FADT_F_SLP_BUTTON) |
131 (1 << ACPI_FADT_F_RTC_S4) |
132 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
133 /* APIC destination mode ("Flat Logical") has an upper limit of 8
134 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
135 * used
136 */
137 ((max_cpus > 8) ? (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
138 .int_model = 1 /* Multiple APIC */,
139 .rtc_century = RTC_CENTURY,
140 .plvl2_lat = 0xfff /* C2 state not supported */,
141 .plvl3_lat = 0xfff /* C3 state not supported */,
142 .smi_cmd = ACPI_PORT_SMI_CMD,
143 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
144 .acpi_enable_cmd =
145 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
146 .acpi_disable_cmd =
147 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
148 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
149 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
150 .address = io + 0x04 },
151 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
152 .gpe0_blk = { .space_id = as, .bit_width =
153 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
154 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
155 },
156 };
157 *data = fadt;
158 }
159
160 static void acpi_get_pm_info(AcpiPmInfo *pm)
161 {
162 Object *piix = piix4_pm_find();
163 Object *lpc = ich9_lpc_find();
164 Object *obj = piix ? piix : lpc;
165 QObject *o;
166 pm->cpu_hp_io_base = 0;
167 pm->pcihp_io_base = 0;
168 pm->pcihp_io_len = 0;
169
170 init_common_fadt_data(obj, &pm->fadt);
171 if (piix) {
172 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
173 pm->fadt.rev = 1;
174 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
175 pm->pcihp_io_base =
176 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
177 pm->pcihp_io_len =
178 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
179 }
180 if (lpc) {
181 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
182 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
183 pm->fadt.reset_reg = r;
184 pm->fadt.reset_val = 0xf;
185 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
186 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
187 }
188 assert(obj);
189
190 /* The above need not be conditional on machine type because the reset port
191 * happens to be the same on PIIX (pc) and ICH9 (q35). */
192 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
193
194 /* Fill in optional s3/s4 related properties */
195 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
196 if (o) {
197 pm->s3_disabled = qnum_get_uint(qobject_to_qnum(o));
198 } else {
199 pm->s3_disabled = false;
200 }
201 qobject_decref(o);
202 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
203 if (o) {
204 pm->s4_disabled = qnum_get_uint(qobject_to_qnum(o));
205 } else {
206 pm->s4_disabled = false;
207 }
208 qobject_decref(o);
209 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
210 if (o) {
211 pm->s4_val = qnum_get_uint(qobject_to_qnum(o));
212 } else {
213 pm->s4_val = false;
214 }
215 qobject_decref(o);
216
217 pm->pcihp_bridge_en =
218 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
219 NULL);
220 }
221
222 static void acpi_get_misc_info(AcpiMiscInfo *info)
223 {
224 Object *piix = piix4_pm_find();
225 Object *lpc = ich9_lpc_find();
226 assert(!!piix != !!lpc);
227
228 if (piix) {
229 info->is_piix4 = true;
230 }
231 if (lpc) {
232 info->is_piix4 = false;
233 }
234
235 info->has_hpet = hpet_find();
236 info->tpm_version = tpm_get_version(tpm_find());
237 info->pvpanic_port = pvpanic_port();
238 info->applesmc_io_base = applesmc_port();
239 }
240
241 /*
242 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
243 * On i386 arch we only have two pci hosts, so we can look only for them.
244 */
245 static Object *acpi_get_i386_pci_host(void)
246 {
247 PCIHostState *host;
248
249 host = OBJECT_CHECK(PCIHostState,
250 object_resolve_path("/machine/i440fx", NULL),
251 TYPE_PCI_HOST_BRIDGE);
252 if (!host) {
253 host = OBJECT_CHECK(PCIHostState,
254 object_resolve_path("/machine/q35", NULL),
255 TYPE_PCI_HOST_BRIDGE);
256 }
257
258 return OBJECT(host);
259 }
260
261 static void acpi_get_pci_holes(Range *hole, Range *hole64)
262 {
263 Object *pci_host;
264
265 pci_host = acpi_get_i386_pci_host();
266 g_assert(pci_host);
267
268 range_set_bounds1(hole,
269 object_property_get_uint(pci_host,
270 PCI_HOST_PROP_PCI_HOLE_START,
271 NULL),
272 object_property_get_uint(pci_host,
273 PCI_HOST_PROP_PCI_HOLE_END,
274 NULL));
275 range_set_bounds1(hole64,
276 object_property_get_uint(pci_host,
277 PCI_HOST_PROP_PCI_HOLE64_START,
278 NULL),
279 object_property_get_uint(pci_host,
280 PCI_HOST_PROP_PCI_HOLE64_END,
281 NULL));
282 }
283
284 static void acpi_align_size(GArray *blob, unsigned align)
285 {
286 /* Align size to multiple of given size. This reduces the chance
287 * we need to change size in the future (breaking cross version migration).
288 */
289 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
290 }
291
292 /* FACS */
293 static void
294 build_facs(GArray *table_data, BIOSLinker *linker)
295 {
296 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
297 memcpy(&facs->signature, "FACS", 4);
298 facs->length = cpu_to_le32(sizeof(*facs));
299 }
300
301 /* Load chipset information in FADT */
302 static void fadt_setup(AcpiFadtDescriptorRev3 *fadt, AcpiFadtData f)
303 {
304 fadt->model = f.int_model;
305 fadt->reserved1 = 0;
306 fadt->sci_int = cpu_to_le16(f.sci_int);
307 fadt->smi_cmd = cpu_to_le32(f.smi_cmd);
308 fadt->acpi_enable = f.acpi_enable_cmd;
309 fadt->acpi_disable = f.acpi_disable_cmd;
310 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
311 fadt->pm1a_evt_blk = cpu_to_le32(f.pm1a_evt.address);
312 fadt->pm1a_cnt_blk = cpu_to_le32(f.pm1a_cnt.address);
313 fadt->pm_tmr_blk = cpu_to_le32(f.pm_tmr.address);
314 fadt->gpe0_blk = cpu_to_le32(f.gpe0_blk.address);
315 /* EVT, CNT, TMR length matches hw/acpi/core.c */
316 fadt->pm1_evt_len = f.pm1a_evt.bit_width / 8;
317 fadt->pm1_cnt_len = f.pm1a_cnt.bit_width / 8;
318 fadt->pm_tmr_len = f.pm_tmr.bit_width / 8;
319 fadt->gpe0_blk_len = f.gpe0_blk.bit_width / 8;
320 fadt->plvl2_lat = cpu_to_le16(f.plvl2_lat);
321 fadt->plvl3_lat = cpu_to_le16(f.plvl3_lat);
322 fadt->flags = cpu_to_le32(f.flags);
323 fadt->century = f.rtc_century;
324 if (f.rev == 1) {
325 return;
326 }
327
328 fadt->reset_value = f.reset_val;
329 fadt->reset_register = f.reset_reg;
330 fadt->reset_register.address = cpu_to_le64(f.reset_reg.address);
331
332 fadt->xpm1a_event_block = f.pm1a_evt;
333 fadt->xpm1a_event_block.address = cpu_to_le64(f.pm1a_evt.address);
334
335 fadt->xpm1a_control_block = f.pm1a_cnt;
336 fadt->xpm1a_control_block.address = cpu_to_le64(f.pm1a_cnt.address);
337
338 fadt->xpm_timer_block = f.pm_tmr;
339 fadt->xpm_timer_block.address = cpu_to_le64(f.pm_tmr.address);
340
341 fadt->xgpe0_block = f.gpe0_blk;
342 fadt->xgpe0_block.address = cpu_to_le64(f.gpe0_blk.address);
343 }
344
345
346 /* FADT */
347 static void
348 build_fadt(GArray *table_data, BIOSLinker *linker, AcpiFadtData *f,
349 const char *oem_id, const char *oem_table_id)
350 {
351 AcpiFadtDescriptorRev3 *fadt = acpi_data_push(table_data, sizeof(*fadt));
352 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data;
353 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
354 unsigned xdsdt_entry_offset = (char *)&fadt->x_dsdt - table_data->data;
355 int fadt_size = sizeof(*fadt);
356
357 /* FACS address to be filled by Guest linker */
358 bios_linker_loader_add_pointer(linker,
359 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl),
360 ACPI_BUILD_TABLE_FILE, *f->facs_tbl_offset);
361
362 /* DSDT address to be filled by Guest linker */
363 fadt_setup(fadt, *f);
364 bios_linker_loader_add_pointer(linker,
365 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
366 ACPI_BUILD_TABLE_FILE, *f->dsdt_tbl_offset);
367
368 if (f->rev == 1) {
369 fadt_size = offsetof(typeof(*fadt), reset_register);
370 } else if (f->xdsdt_tbl_offset) {
371 bios_linker_loader_add_pointer(linker,
372 ACPI_BUILD_TABLE_FILE, xdsdt_entry_offset, sizeof(fadt->x_dsdt),
373 ACPI_BUILD_TABLE_FILE, *f->xdsdt_tbl_offset);
374 }
375
376 build_header(linker, table_data,
377 (void *)fadt, "FACP", fadt_size, f->rev,
378 oem_id, oem_table_id);
379 }
380
381 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
382 const CPUArchIdList *apic_ids, GArray *entry)
383 {
384 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
385
386 /* ACPI spec says that LAPIC entry for non present
387 * CPU may be omitted from MADT or it must be marked
388 * as disabled. However omitting non present CPU from
389 * MADT breaks hotplug on linux. So possible CPUs
390 * should be put in MADT but kept disabled.
391 */
392 if (apic_id < 255) {
393 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
394
395 apic->type = ACPI_APIC_PROCESSOR;
396 apic->length = sizeof(*apic);
397 apic->processor_id = uid;
398 apic->local_apic_id = apic_id;
399 if (apic_ids->cpus[uid].cpu != NULL) {
400 apic->flags = cpu_to_le32(1);
401 } else {
402 apic->flags = cpu_to_le32(0);
403 }
404 } else {
405 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
406
407 apic->type = ACPI_APIC_LOCAL_X2APIC;
408 apic->length = sizeof(*apic);
409 apic->uid = cpu_to_le32(uid);
410 apic->x2apic_id = cpu_to_le32(apic_id);
411 if (apic_ids->cpus[uid].cpu != NULL) {
412 apic->flags = cpu_to_le32(1);
413 } else {
414 apic->flags = cpu_to_le32(0);
415 }
416 }
417 }
418
419 static void
420 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
421 {
422 MachineClass *mc = MACHINE_GET_CLASS(pcms);
423 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
424 int madt_start = table_data->len;
425 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
426 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
427 bool x2apic_mode = false;
428
429 AcpiMultipleApicTable *madt;
430 AcpiMadtIoApic *io_apic;
431 AcpiMadtIntsrcovr *intsrcovr;
432 int i;
433
434 madt = acpi_data_push(table_data, sizeof *madt);
435 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
436 madt->flags = cpu_to_le32(1);
437
438 for (i = 0; i < apic_ids->len; i++) {
439 adevc->madt_cpu(adev, i, apic_ids, table_data);
440 if (apic_ids->cpus[i].arch_id > 254) {
441 x2apic_mode = true;
442 }
443 }
444
445 io_apic = acpi_data_push(table_data, sizeof *io_apic);
446 io_apic->type = ACPI_APIC_IO;
447 io_apic->length = sizeof(*io_apic);
448 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
449 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
450 io_apic->interrupt = cpu_to_le32(0);
451
452 if (pcms->apic_xrupt_override) {
453 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
454 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
455 intsrcovr->length = sizeof(*intsrcovr);
456 intsrcovr->source = 0;
457 intsrcovr->gsi = cpu_to_le32(2);
458 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
459 }
460 for (i = 1; i < 16; i++) {
461 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
462 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
463 /* No need for a INT source override structure. */
464 continue;
465 }
466 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
467 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
468 intsrcovr->length = sizeof(*intsrcovr);
469 intsrcovr->source = i;
470 intsrcovr->gsi = cpu_to_le32(i);
471 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
472 }
473
474 if (x2apic_mode) {
475 AcpiMadtLocalX2ApicNmi *local_nmi;
476
477 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
478 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
479 local_nmi->length = sizeof(*local_nmi);
480 local_nmi->uid = 0xFFFFFFFF; /* all processors */
481 local_nmi->flags = cpu_to_le16(0);
482 local_nmi->lint = 1; /* ACPI_LINT1 */
483 } else {
484 AcpiMadtLocalNmi *local_nmi;
485
486 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
487 local_nmi->type = ACPI_APIC_LOCAL_NMI;
488 local_nmi->length = sizeof(*local_nmi);
489 local_nmi->processor_id = 0xff; /* all processors */
490 local_nmi->flags = cpu_to_le16(0);
491 local_nmi->lint = 1; /* ACPI_LINT1 */
492 }
493
494 build_header(linker, table_data,
495 (void *)(table_data->data + madt_start), "APIC",
496 table_data->len - madt_start, 1, NULL, NULL);
497 }
498
499 static void build_append_pcihp_notify_entry(Aml *method, int slot)
500 {
501 Aml *if_ctx;
502 int32_t devfn = PCI_DEVFN(slot, 0);
503
504 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
505 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
506 aml_append(method, if_ctx);
507 }
508
509 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
510 bool pcihp_bridge_en)
511 {
512 Aml *dev, *notify_method, *method;
513 QObject *bsel;
514 PCIBus *sec;
515 int i;
516
517 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
518 if (bsel) {
519 uint64_t bsel_val = qnum_get_uint(qobject_to_qnum(bsel));
520
521 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
522 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
523 }
524
525 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
526 DeviceClass *dc;
527 PCIDeviceClass *pc;
528 PCIDevice *pdev = bus->devices[i];
529 int slot = PCI_SLOT(i);
530 bool hotplug_enabled_dev;
531 bool bridge_in_acpi;
532
533 if (!pdev) {
534 if (bsel) { /* add hotplug slots for non present devices */
535 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
536 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
537 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
538 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
539 aml_append(method,
540 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
541 );
542 aml_append(dev, method);
543 aml_append(parent_scope, dev);
544
545 build_append_pcihp_notify_entry(notify_method, slot);
546 }
547 continue;
548 }
549
550 pc = PCI_DEVICE_GET_CLASS(pdev);
551 dc = DEVICE_GET_CLASS(pdev);
552
553 /* When hotplug for bridges is enabled, bridges are
554 * described in ACPI separately (see build_pci_bus_end).
555 * In this case they aren't themselves hot-pluggable.
556 * Hotplugged bridges *are* hot-pluggable.
557 */
558 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
559 !DEVICE(pdev)->hotplugged;
560
561 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
562
563 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
564 continue;
565 }
566
567 /* start to compose PCI slot descriptor */
568 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
569 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
570
571 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
572 /* add VGA specific AML methods */
573 int s3d;
574
575 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
576 s3d = 3;
577 } else {
578 s3d = 0;
579 }
580
581 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
582 aml_append(method, aml_return(aml_int(0)));
583 aml_append(dev, method);
584
585 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
586 aml_append(method, aml_return(aml_int(0)));
587 aml_append(dev, method);
588
589 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
590 aml_append(method, aml_return(aml_int(s3d)));
591 aml_append(dev, method);
592 } else if (hotplug_enabled_dev) {
593 /* add _SUN/_EJ0 to make slot hotpluggable */
594 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
595
596 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
597 aml_append(method,
598 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
599 );
600 aml_append(dev, method);
601
602 if (bsel) {
603 build_append_pcihp_notify_entry(notify_method, slot);
604 }
605 } else if (bridge_in_acpi) {
606 /*
607 * device is coldplugged bridge,
608 * add child device descriptions into its scope
609 */
610 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
611
612 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
613 }
614 /* slot descriptor has been composed, add it into parent context */
615 aml_append(parent_scope, dev);
616 }
617
618 if (bsel) {
619 aml_append(parent_scope, notify_method);
620 }
621
622 /* Append PCNT method to notify about events on local and child buses.
623 * Add unconditionally for root since DSDT expects it.
624 */
625 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
626
627 /* If bus supports hotplug select it and notify about local events */
628 if (bsel) {
629 uint64_t bsel_val = qnum_get_uint(qobject_to_qnum(bsel));
630
631 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
632 aml_append(method,
633 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
634 );
635 aml_append(method,
636 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
637 );
638 }
639
640 /* Notify about child bus events in any case */
641 if (pcihp_bridge_en) {
642 QLIST_FOREACH(sec, &bus->child, sibling) {
643 int32_t devfn = sec->parent_dev->devfn;
644
645 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
646 continue;
647 }
648
649 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
650 }
651 }
652 aml_append(parent_scope, method);
653 qobject_decref(bsel);
654 }
655
656 /**
657 * build_prt_entry:
658 * @link_name: link name for PCI route entry
659 *
660 * build AML package containing a PCI route entry for @link_name
661 */
662 static Aml *build_prt_entry(const char *link_name)
663 {
664 Aml *a_zero = aml_int(0);
665 Aml *pkg = aml_package(4);
666 aml_append(pkg, a_zero);
667 aml_append(pkg, a_zero);
668 aml_append(pkg, aml_name("%s", link_name));
669 aml_append(pkg, a_zero);
670 return pkg;
671 }
672
673 /*
674 * initialize_route - Initialize the interrupt routing rule
675 * through a specific LINK:
676 * if (lnk_idx == idx)
677 * route using link 'link_name'
678 */
679 static Aml *initialize_route(Aml *route, const char *link_name,
680 Aml *lnk_idx, int idx)
681 {
682 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
683 Aml *pkg = build_prt_entry(link_name);
684
685 aml_append(if_ctx, aml_store(pkg, route));
686
687 return if_ctx;
688 }
689
690 /*
691 * build_prt - Define interrupt rounting rules
692 *
693 * Returns an array of 128 routes, one for each device,
694 * based on device location.
695 * The main goal is to equaly distribute the interrupts
696 * over the 4 existing ACPI links (works only for i440fx).
697 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
698 *
699 */
700 static Aml *build_prt(bool is_pci0_prt)
701 {
702 Aml *method, *while_ctx, *pin, *res;
703
704 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
705 res = aml_local(0);
706 pin = aml_local(1);
707 aml_append(method, aml_store(aml_package(128), res));
708 aml_append(method, aml_store(aml_int(0), pin));
709
710 /* while (pin < 128) */
711 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
712 {
713 Aml *slot = aml_local(2);
714 Aml *lnk_idx = aml_local(3);
715 Aml *route = aml_local(4);
716
717 /* slot = pin >> 2 */
718 aml_append(while_ctx,
719 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
720 /* lnk_idx = (slot + pin) & 3 */
721 aml_append(while_ctx,
722 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
723 lnk_idx));
724
725 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
726 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
727 if (is_pci0_prt) {
728 Aml *if_device_1, *if_pin_4, *else_pin_4;
729
730 /* device 1 is the power-management device, needs SCI */
731 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
732 {
733 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
734 {
735 aml_append(if_pin_4,
736 aml_store(build_prt_entry("LNKS"), route));
737 }
738 aml_append(if_device_1, if_pin_4);
739 else_pin_4 = aml_else();
740 {
741 aml_append(else_pin_4,
742 aml_store(build_prt_entry("LNKA"), route));
743 }
744 aml_append(if_device_1, else_pin_4);
745 }
746 aml_append(while_ctx, if_device_1);
747 } else {
748 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
749 }
750 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
751 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
752
753 /* route[0] = 0x[slot]FFFF */
754 aml_append(while_ctx,
755 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
756 NULL),
757 aml_index(route, aml_int(0))));
758 /* route[1] = pin & 3 */
759 aml_append(while_ctx,
760 aml_store(aml_and(pin, aml_int(3), NULL),
761 aml_index(route, aml_int(1))));
762 /* res[pin] = route */
763 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
764 /* pin++ */
765 aml_append(while_ctx, aml_increment(pin));
766 }
767 aml_append(method, while_ctx);
768 /* return res*/
769 aml_append(method, aml_return(res));
770
771 return method;
772 }
773
774 typedef struct CrsRangeEntry {
775 uint64_t base;
776 uint64_t limit;
777 } CrsRangeEntry;
778
779 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
780 {
781 CrsRangeEntry *entry;
782
783 entry = g_malloc(sizeof(*entry));
784 entry->base = base;
785 entry->limit = limit;
786
787 g_ptr_array_add(ranges, entry);
788 }
789
790 static void crs_range_free(gpointer data)
791 {
792 CrsRangeEntry *entry = (CrsRangeEntry *)data;
793 g_free(entry);
794 }
795
796 typedef struct CrsRangeSet {
797 GPtrArray *io_ranges;
798 GPtrArray *mem_ranges;
799 GPtrArray *mem_64bit_ranges;
800 } CrsRangeSet;
801
802 static void crs_range_set_init(CrsRangeSet *range_set)
803 {
804 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
805 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
806 range_set->mem_64bit_ranges =
807 g_ptr_array_new_with_free_func(crs_range_free);
808 }
809
810 static void crs_range_set_free(CrsRangeSet *range_set)
811 {
812 g_ptr_array_free(range_set->io_ranges, true);
813 g_ptr_array_free(range_set->mem_ranges, true);
814 g_ptr_array_free(range_set->mem_64bit_ranges, true);
815 }
816
817 static gint crs_range_compare(gconstpointer a, gconstpointer b)
818 {
819 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
820 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
821
822 return (int64_t)entry_a->base - (int64_t)entry_b->base;
823 }
824
825 /*
826 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
827 * interval, computes the 'free' ranges from the same interval.
828 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
829 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
830 */
831 static void crs_replace_with_free_ranges(GPtrArray *ranges,
832 uint64_t start, uint64_t end)
833 {
834 GPtrArray *free_ranges = g_ptr_array_new();
835 uint64_t free_base = start;
836 int i;
837
838 g_ptr_array_sort(ranges, crs_range_compare);
839 for (i = 0; i < ranges->len; i++) {
840 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
841
842 if (free_base < used->base) {
843 crs_range_insert(free_ranges, free_base, used->base - 1);
844 }
845
846 free_base = used->limit + 1;
847 }
848
849 if (free_base < end) {
850 crs_range_insert(free_ranges, free_base, end);
851 }
852
853 g_ptr_array_set_size(ranges, 0);
854 for (i = 0; i < free_ranges->len; i++) {
855 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
856 }
857
858 g_ptr_array_free(free_ranges, true);
859 }
860
861 /*
862 * crs_range_merge - merges adjacent ranges in the given array.
863 * Array elements are deleted and replaced with the merged ranges.
864 */
865 static void crs_range_merge(GPtrArray *range)
866 {
867 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
868 CrsRangeEntry *entry;
869 uint64_t range_base, range_limit;
870 int i;
871
872 if (!range->len) {
873 return;
874 }
875
876 g_ptr_array_sort(range, crs_range_compare);
877
878 entry = g_ptr_array_index(range, 0);
879 range_base = entry->base;
880 range_limit = entry->limit;
881 for (i = 1; i < range->len; i++) {
882 entry = g_ptr_array_index(range, i);
883 if (entry->base - 1 == range_limit) {
884 range_limit = entry->limit;
885 } else {
886 crs_range_insert(tmp, range_base, range_limit);
887 range_base = entry->base;
888 range_limit = entry->limit;
889 }
890 }
891 crs_range_insert(tmp, range_base, range_limit);
892
893 g_ptr_array_set_size(range, 0);
894 for (i = 0; i < tmp->len; i++) {
895 entry = g_ptr_array_index(tmp, i);
896 crs_range_insert(range, entry->base, entry->limit);
897 }
898 g_ptr_array_free(tmp, true);
899 }
900
901 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
902 {
903 Aml *crs = aml_resource_template();
904 CrsRangeSet temp_range_set;
905 CrsRangeEntry *entry;
906 uint8_t max_bus = pci_bus_num(host->bus);
907 uint8_t type;
908 int devfn;
909 int i;
910
911 crs_range_set_init(&temp_range_set);
912 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
913 uint64_t range_base, range_limit;
914 PCIDevice *dev = host->bus->devices[devfn];
915
916 if (!dev) {
917 continue;
918 }
919
920 for (i = 0; i < PCI_NUM_REGIONS; i++) {
921 PCIIORegion *r = &dev->io_regions[i];
922
923 range_base = r->addr;
924 range_limit = r->addr + r->size - 1;
925
926 /*
927 * Work-around for old bioses
928 * that do not support multiple root buses
929 */
930 if (!range_base || range_base > range_limit) {
931 continue;
932 }
933
934 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
935 crs_range_insert(temp_range_set.io_ranges,
936 range_base, range_limit);
937 } else { /* "memory" */
938 crs_range_insert(temp_range_set.mem_ranges,
939 range_base, range_limit);
940 }
941 }
942
943 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
944 if (type == PCI_HEADER_TYPE_BRIDGE) {
945 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
946 if (subordinate > max_bus) {
947 max_bus = subordinate;
948 }
949
950 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
951 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
952
953 /*
954 * Work-around for old bioses
955 * that do not support multiple root buses
956 */
957 if (range_base && range_base <= range_limit) {
958 crs_range_insert(temp_range_set.io_ranges,
959 range_base, range_limit);
960 }
961
962 range_base =
963 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
964 range_limit =
965 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
966
967 /*
968 * Work-around for old bioses
969 * that do not support multiple root buses
970 */
971 if (range_base && range_base <= range_limit) {
972 uint64_t length = range_limit - range_base + 1;
973 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
974 crs_range_insert(temp_range_set.mem_ranges,
975 range_base, range_limit);
976 } else {
977 crs_range_insert(temp_range_set.mem_64bit_ranges,
978 range_base, range_limit);
979 }
980 }
981
982 range_base =
983 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
984 range_limit =
985 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
986
987 /*
988 * Work-around for old bioses
989 * that do not support multiple root buses
990 */
991 if (range_base && range_base <= range_limit) {
992 uint64_t length = range_limit - range_base + 1;
993 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
994 crs_range_insert(temp_range_set.mem_ranges,
995 range_base, range_limit);
996 } else {
997 crs_range_insert(temp_range_set.mem_64bit_ranges,
998 range_base, range_limit);
999 }
1000 }
1001 }
1002 }
1003
1004 crs_range_merge(temp_range_set.io_ranges);
1005 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
1006 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
1007 aml_append(crs,
1008 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1009 AML_POS_DECODE, AML_ENTIRE_RANGE,
1010 0, entry->base, entry->limit, 0,
1011 entry->limit - entry->base + 1));
1012 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
1013 }
1014
1015 crs_range_merge(temp_range_set.mem_ranges);
1016 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
1017 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
1018 aml_append(crs,
1019 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1020 AML_MAX_FIXED, AML_NON_CACHEABLE,
1021 AML_READ_WRITE,
1022 0, entry->base, entry->limit, 0,
1023 entry->limit - entry->base + 1));
1024 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
1025 }
1026
1027 crs_range_merge(temp_range_set.mem_64bit_ranges);
1028 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
1029 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
1030 aml_append(crs,
1031 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1032 AML_MAX_FIXED, AML_NON_CACHEABLE,
1033 AML_READ_WRITE,
1034 0, entry->base, entry->limit, 0,
1035 entry->limit - entry->base + 1));
1036 crs_range_insert(range_set->mem_64bit_ranges,
1037 entry->base, entry->limit);
1038 }
1039
1040 crs_range_set_free(&temp_range_set);
1041
1042 aml_append(crs,
1043 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1044 0,
1045 pci_bus_num(host->bus),
1046 max_bus,
1047 0,
1048 max_bus - pci_bus_num(host->bus) + 1));
1049
1050 return crs;
1051 }
1052
1053 static void build_hpet_aml(Aml *table)
1054 {
1055 Aml *crs;
1056 Aml *field;
1057 Aml *method;
1058 Aml *if_ctx;
1059 Aml *scope = aml_scope("_SB");
1060 Aml *dev = aml_device("HPET");
1061 Aml *zero = aml_int(0);
1062 Aml *id = aml_local(0);
1063 Aml *period = aml_local(1);
1064
1065 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1066 aml_append(dev, aml_name_decl("_UID", zero));
1067
1068 aml_append(dev,
1069 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1070 HPET_LEN));
1071 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1072 aml_append(field, aml_named_field("VEND", 32));
1073 aml_append(field, aml_named_field("PRD", 32));
1074 aml_append(dev, field);
1075
1076 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1077 aml_append(method, aml_store(aml_name("VEND"), id));
1078 aml_append(method, aml_store(aml_name("PRD"), period));
1079 aml_append(method, aml_shiftright(id, aml_int(16), id));
1080 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1081 aml_equal(id, aml_int(0xffff))));
1082 {
1083 aml_append(if_ctx, aml_return(zero));
1084 }
1085 aml_append(method, if_ctx);
1086
1087 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1088 aml_lgreater(period, aml_int(100000000))));
1089 {
1090 aml_append(if_ctx, aml_return(zero));
1091 }
1092 aml_append(method, if_ctx);
1093
1094 aml_append(method, aml_return(aml_int(0x0F)));
1095 aml_append(dev, method);
1096
1097 crs = aml_resource_template();
1098 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1099 aml_append(dev, aml_name_decl("_CRS", crs));
1100
1101 aml_append(scope, dev);
1102 aml_append(table, scope);
1103 }
1104
1105 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1106 {
1107 Aml *dev, *fdi;
1108 uint8_t maxc, maxh, maxs;
1109
1110 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1111
1112 dev = aml_device("FLP%c", 'A' + idx);
1113
1114 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1115
1116 fdi = aml_package(16);
1117 aml_append(fdi, aml_int(idx)); /* Drive Number */
1118 aml_append(fdi,
1119 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1120 /*
1121 * the values below are the limits of the drive, and are thus independent
1122 * of the inserted media
1123 */
1124 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1125 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1126 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1127 /*
1128 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1129 * the drive type, so shall we
1130 */
1131 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1132 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1133 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1134 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1135 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1136 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1137 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1138 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1139 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1140 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1141 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1142
1143 aml_append(dev, aml_name_decl("_FDI", fdi));
1144 return dev;
1145 }
1146
1147 static Aml *build_fdc_device_aml(ISADevice *fdc)
1148 {
1149 int i;
1150 Aml *dev;
1151 Aml *crs;
1152
1153 #define ACPI_FDE_MAX_FD 4
1154 uint32_t fde_buf[5] = {
1155 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1156 cpu_to_le32(2) /* tape presence (2 == never present) */
1157 };
1158
1159 dev = aml_device("FDC0");
1160 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1161
1162 crs = aml_resource_template();
1163 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1164 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1165 aml_append(crs, aml_irq_no_flags(6));
1166 aml_append(crs,
1167 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1168 aml_append(dev, aml_name_decl("_CRS", crs));
1169
1170 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1171 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1172
1173 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1174 fde_buf[i] = cpu_to_le32(1); /* drive present */
1175 aml_append(dev, build_fdinfo_aml(i, type));
1176 }
1177 }
1178 aml_append(dev, aml_name_decl("_FDE",
1179 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1180
1181 return dev;
1182 }
1183
1184 static Aml *build_rtc_device_aml(void)
1185 {
1186 Aml *dev;
1187 Aml *crs;
1188
1189 dev = aml_device("RTC");
1190 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1191 crs = aml_resource_template();
1192 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1193 aml_append(crs, aml_irq_no_flags(8));
1194 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1195 aml_append(dev, aml_name_decl("_CRS", crs));
1196
1197 return dev;
1198 }
1199
1200 static Aml *build_kbd_device_aml(void)
1201 {
1202 Aml *dev;
1203 Aml *crs;
1204 Aml *method;
1205
1206 dev = aml_device("KBD");
1207 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1208
1209 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1210 aml_append(method, aml_return(aml_int(0x0f)));
1211 aml_append(dev, method);
1212
1213 crs = aml_resource_template();
1214 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1215 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1216 aml_append(crs, aml_irq_no_flags(1));
1217 aml_append(dev, aml_name_decl("_CRS", crs));
1218
1219 return dev;
1220 }
1221
1222 static Aml *build_mouse_device_aml(void)
1223 {
1224 Aml *dev;
1225 Aml *crs;
1226 Aml *method;
1227
1228 dev = aml_device("MOU");
1229 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1230
1231 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1232 aml_append(method, aml_return(aml_int(0x0f)));
1233 aml_append(dev, method);
1234
1235 crs = aml_resource_template();
1236 aml_append(crs, aml_irq_no_flags(12));
1237 aml_append(dev, aml_name_decl("_CRS", crs));
1238
1239 return dev;
1240 }
1241
1242 static Aml *build_lpt_device_aml(void)
1243 {
1244 Aml *dev;
1245 Aml *crs;
1246 Aml *method;
1247 Aml *if_ctx;
1248 Aml *else_ctx;
1249 Aml *zero = aml_int(0);
1250 Aml *is_present = aml_local(0);
1251
1252 dev = aml_device("LPT");
1253 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1254
1255 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1256 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1257 if_ctx = aml_if(aml_equal(is_present, zero));
1258 {
1259 aml_append(if_ctx, aml_return(aml_int(0x00)));
1260 }
1261 aml_append(method, if_ctx);
1262 else_ctx = aml_else();
1263 {
1264 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1265 }
1266 aml_append(method, else_ctx);
1267 aml_append(dev, method);
1268
1269 crs = aml_resource_template();
1270 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1271 aml_append(crs, aml_irq_no_flags(7));
1272 aml_append(dev, aml_name_decl("_CRS", crs));
1273
1274 return dev;
1275 }
1276
1277 static Aml *build_com_device_aml(uint8_t uid)
1278 {
1279 Aml *dev;
1280 Aml *crs;
1281 Aml *method;
1282 Aml *if_ctx;
1283 Aml *else_ctx;
1284 Aml *zero = aml_int(0);
1285 Aml *is_present = aml_local(0);
1286 const char *enabled_field = "CAEN";
1287 uint8_t irq = 4;
1288 uint16_t io_port = 0x03F8;
1289
1290 assert(uid == 1 || uid == 2);
1291 if (uid == 2) {
1292 enabled_field = "CBEN";
1293 irq = 3;
1294 io_port = 0x02F8;
1295 }
1296
1297 dev = aml_device("COM%d", uid);
1298 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1299 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1300
1301 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1302 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1303 if_ctx = aml_if(aml_equal(is_present, zero));
1304 {
1305 aml_append(if_ctx, aml_return(aml_int(0x00)));
1306 }
1307 aml_append(method, if_ctx);
1308 else_ctx = aml_else();
1309 {
1310 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1311 }
1312 aml_append(method, else_ctx);
1313 aml_append(dev, method);
1314
1315 crs = aml_resource_template();
1316 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1317 aml_append(crs, aml_irq_no_flags(irq));
1318 aml_append(dev, aml_name_decl("_CRS", crs));
1319
1320 return dev;
1321 }
1322
1323 static void build_isa_devices_aml(Aml *table)
1324 {
1325 ISADevice *fdc = pc_find_fdc0();
1326 bool ambiguous;
1327
1328 Aml *scope = aml_scope("_SB.PCI0.ISA");
1329 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1330
1331 aml_append(scope, build_rtc_device_aml());
1332 aml_append(scope, build_kbd_device_aml());
1333 aml_append(scope, build_mouse_device_aml());
1334 if (fdc) {
1335 aml_append(scope, build_fdc_device_aml(fdc));
1336 }
1337 aml_append(scope, build_lpt_device_aml());
1338 aml_append(scope, build_com_device_aml(1));
1339 aml_append(scope, build_com_device_aml(2));
1340
1341 if (ambiguous) {
1342 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1343 } else if (!obj) {
1344 error_report("No ISA bus, unable to define IPMI ACPI data");
1345 } else {
1346 build_acpi_ipmi_devices(scope, BUS(obj));
1347 }
1348
1349 aml_append(table, scope);
1350 }
1351
1352 static void build_dbg_aml(Aml *table)
1353 {
1354 Aml *field;
1355 Aml *method;
1356 Aml *while_ctx;
1357 Aml *scope = aml_scope("\\");
1358 Aml *buf = aml_local(0);
1359 Aml *len = aml_local(1);
1360 Aml *idx = aml_local(2);
1361
1362 aml_append(scope,
1363 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1364 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1365 aml_append(field, aml_named_field("DBGB", 8));
1366 aml_append(scope, field);
1367
1368 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1369
1370 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1371 aml_append(method, aml_to_buffer(buf, buf));
1372 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1373 aml_append(method, aml_store(aml_int(0), idx));
1374
1375 while_ctx = aml_while(aml_lless(idx, len));
1376 aml_append(while_ctx,
1377 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1378 aml_append(while_ctx, aml_increment(idx));
1379 aml_append(method, while_ctx);
1380
1381 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1382 aml_append(scope, method);
1383
1384 aml_append(table, scope);
1385 }
1386
1387 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1388 {
1389 Aml *dev;
1390 Aml *crs;
1391 Aml *method;
1392 uint32_t irqs[] = {5, 10, 11};
1393
1394 dev = aml_device("%s", name);
1395 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1396 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1397
1398 crs = aml_resource_template();
1399 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1400 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1401 aml_append(dev, aml_name_decl("_PRS", crs));
1402
1403 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1404 aml_append(method, aml_return(aml_call1("IQST", reg)));
1405 aml_append(dev, method);
1406
1407 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1408 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1409 aml_append(dev, method);
1410
1411 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1412 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1413 aml_append(dev, method);
1414
1415 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1416 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1417 aml_append(method, aml_store(aml_name("PRRI"), reg));
1418 aml_append(dev, method);
1419
1420 return dev;
1421 }
1422
1423 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1424 {
1425 Aml *dev;
1426 Aml *crs;
1427 Aml *method;
1428 uint32_t irqs;
1429
1430 dev = aml_device("%s", name);
1431 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1432 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1433
1434 crs = aml_resource_template();
1435 irqs = gsi;
1436 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1437 AML_SHARED, &irqs, 1));
1438 aml_append(dev, aml_name_decl("_PRS", crs));
1439
1440 aml_append(dev, aml_name_decl("_CRS", crs));
1441
1442 /*
1443 * _DIS can be no-op because the interrupt cannot be disabled.
1444 */
1445 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1446 aml_append(dev, method);
1447
1448 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1449 aml_append(dev, method);
1450
1451 return dev;
1452 }
1453
1454 /* _CRS method - get current settings */
1455 static Aml *build_iqcr_method(bool is_piix4)
1456 {
1457 Aml *if_ctx;
1458 uint32_t irqs;
1459 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1460 Aml *crs = aml_resource_template();
1461
1462 irqs = 0;
1463 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1464 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1465 aml_append(method, aml_name_decl("PRR0", crs));
1466
1467 aml_append(method,
1468 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1469
1470 if (is_piix4) {
1471 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1472 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1473 aml_append(method, if_ctx);
1474 } else {
1475 aml_append(method,
1476 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1477 aml_name("PRRI")));
1478 }
1479
1480 aml_append(method, aml_return(aml_name("PRR0")));
1481 return method;
1482 }
1483
1484 /* _STA method - get status */
1485 static Aml *build_irq_status_method(void)
1486 {
1487 Aml *if_ctx;
1488 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1489
1490 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1491 aml_append(if_ctx, aml_return(aml_int(0x09)));
1492 aml_append(method, if_ctx);
1493 aml_append(method, aml_return(aml_int(0x0B)));
1494 return method;
1495 }
1496
1497 static void build_piix4_pci0_int(Aml *table)
1498 {
1499 Aml *dev;
1500 Aml *crs;
1501 Aml *field;
1502 Aml *method;
1503 uint32_t irqs;
1504 Aml *sb_scope = aml_scope("_SB");
1505 Aml *pci0_scope = aml_scope("PCI0");
1506
1507 aml_append(pci0_scope, build_prt(true));
1508 aml_append(sb_scope, pci0_scope);
1509
1510 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1511 aml_append(field, aml_named_field("PRQ0", 8));
1512 aml_append(field, aml_named_field("PRQ1", 8));
1513 aml_append(field, aml_named_field("PRQ2", 8));
1514 aml_append(field, aml_named_field("PRQ3", 8));
1515 aml_append(sb_scope, field);
1516
1517 aml_append(sb_scope, build_irq_status_method());
1518 aml_append(sb_scope, build_iqcr_method(true));
1519
1520 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1521 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1522 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1523 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1524
1525 dev = aml_device("LNKS");
1526 {
1527 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1528 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1529
1530 crs = aml_resource_template();
1531 irqs = 9;
1532 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1533 AML_ACTIVE_HIGH, AML_SHARED,
1534 &irqs, 1));
1535 aml_append(dev, aml_name_decl("_PRS", crs));
1536
1537 /* The SCI cannot be disabled and is always attached to GSI 9,
1538 * so these are no-ops. We only need this link to override the
1539 * polarity to active high and match the content of the MADT.
1540 */
1541 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1542 aml_append(method, aml_return(aml_int(0x0b)));
1543 aml_append(dev, method);
1544
1545 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1546 aml_append(dev, method);
1547
1548 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1549 aml_append(method, aml_return(aml_name("_PRS")));
1550 aml_append(dev, method);
1551
1552 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1553 aml_append(dev, method);
1554 }
1555 aml_append(sb_scope, dev);
1556
1557 aml_append(table, sb_scope);
1558 }
1559
1560 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1561 {
1562 int i;
1563 int head;
1564 Aml *pkg;
1565 char base = name[3] < 'E' ? 'A' : 'E';
1566 char *s = g_strdup(name);
1567 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1568
1569 assert(strlen(s) == 4);
1570
1571 head = name[3] - base;
1572 for (i = 0; i < 4; i++) {
1573 if (head + i > 3) {
1574 head = i * -1;
1575 }
1576 s[3] = base + head + i;
1577 pkg = aml_package(4);
1578 aml_append(pkg, a_nr);
1579 aml_append(pkg, aml_int(i));
1580 aml_append(pkg, aml_name("%s", s));
1581 aml_append(pkg, aml_int(0));
1582 aml_append(ctx, pkg);
1583 }
1584 g_free(s);
1585 }
1586
1587 static Aml *build_q35_routing_table(const char *str)
1588 {
1589 int i;
1590 Aml *pkg;
1591 char *name = g_strdup_printf("%s ", str);
1592
1593 pkg = aml_package(128);
1594 for (i = 0; i < 0x18; i++) {
1595 name[3] = 'E' + (i & 0x3);
1596 append_q35_prt_entry(pkg, i, name);
1597 }
1598
1599 name[3] = 'E';
1600 append_q35_prt_entry(pkg, 0x18, name);
1601
1602 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1603 for (i = 0x0019; i < 0x1e; i++) {
1604 name[3] = 'A';
1605 append_q35_prt_entry(pkg, i, name);
1606 }
1607
1608 /* PCIe->PCI bridge. use PIRQ[E-H] */
1609 name[3] = 'E';
1610 append_q35_prt_entry(pkg, 0x1e, name);
1611 name[3] = 'A';
1612 append_q35_prt_entry(pkg, 0x1f, name);
1613
1614 g_free(name);
1615 return pkg;
1616 }
1617
1618 static void build_q35_pci0_int(Aml *table)
1619 {
1620 Aml *field;
1621 Aml *method;
1622 Aml *sb_scope = aml_scope("_SB");
1623 Aml *pci0_scope = aml_scope("PCI0");
1624
1625 /* Zero => PIC mode, One => APIC Mode */
1626 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1627 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1628 {
1629 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1630 }
1631 aml_append(table, method);
1632
1633 aml_append(pci0_scope,
1634 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1635 aml_append(pci0_scope,
1636 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1637
1638 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1639 {
1640 Aml *if_ctx;
1641 Aml *else_ctx;
1642
1643 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1644 section 6.2.8.1 */
1645 /* Note: we provide the same info as the PCI routing
1646 table of the Bochs BIOS */
1647 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1648 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1649 aml_append(method, if_ctx);
1650 else_ctx = aml_else();
1651 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1652 aml_append(method, else_ctx);
1653 }
1654 aml_append(pci0_scope, method);
1655 aml_append(sb_scope, pci0_scope);
1656
1657 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1658 aml_append(field, aml_named_field("PRQA", 8));
1659 aml_append(field, aml_named_field("PRQB", 8));
1660 aml_append(field, aml_named_field("PRQC", 8));
1661 aml_append(field, aml_named_field("PRQD", 8));
1662 aml_append(field, aml_reserved_field(0x20));
1663 aml_append(field, aml_named_field("PRQE", 8));
1664 aml_append(field, aml_named_field("PRQF", 8));
1665 aml_append(field, aml_named_field("PRQG", 8));
1666 aml_append(field, aml_named_field("PRQH", 8));
1667 aml_append(sb_scope, field);
1668
1669 aml_append(sb_scope, build_irq_status_method());
1670 aml_append(sb_scope, build_iqcr_method(false));
1671
1672 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1673 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1674 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1675 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1676 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1677 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1678 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1679 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1680
1681 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1682 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1683 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1684 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1685 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1686 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1687 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1688 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1689
1690 aml_append(table, sb_scope);
1691 }
1692
1693 static void build_q35_isa_bridge(Aml *table)
1694 {
1695 Aml *dev;
1696 Aml *scope;
1697 Aml *field;
1698
1699 scope = aml_scope("_SB.PCI0");
1700 dev = aml_device("ISA");
1701 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1702
1703 /* ICH9 PCI to ISA irq remapping */
1704 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1705 aml_int(0x60), 0x0C));
1706
1707 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1708 aml_int(0x80), 0x02));
1709 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1710 aml_append(field, aml_named_field("COMA", 3));
1711 aml_append(field, aml_reserved_field(1));
1712 aml_append(field, aml_named_field("COMB", 3));
1713 aml_append(field, aml_reserved_field(1));
1714 aml_append(field, aml_named_field("LPTD", 2));
1715 aml_append(dev, field);
1716
1717 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1718 aml_int(0x82), 0x02));
1719 /* enable bits */
1720 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1721 aml_append(field, aml_named_field("CAEN", 1));
1722 aml_append(field, aml_named_field("CBEN", 1));
1723 aml_append(field, aml_named_field("LPEN", 1));
1724 aml_append(dev, field);
1725
1726 aml_append(scope, dev);
1727 aml_append(table, scope);
1728 }
1729
1730 static void build_piix4_pm(Aml *table)
1731 {
1732 Aml *dev;
1733 Aml *scope;
1734
1735 scope = aml_scope("_SB.PCI0");
1736 dev = aml_device("PX13");
1737 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1738
1739 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1740 aml_int(0x00), 0xff));
1741 aml_append(scope, dev);
1742 aml_append(table, scope);
1743 }
1744
1745 static void build_piix4_isa_bridge(Aml *table)
1746 {
1747 Aml *dev;
1748 Aml *scope;
1749 Aml *field;
1750
1751 scope = aml_scope("_SB.PCI0");
1752 dev = aml_device("ISA");
1753 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1754
1755 /* PIIX PCI to ISA irq remapping */
1756 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1757 aml_int(0x60), 0x04));
1758 /* enable bits */
1759 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1760 /* Offset(0x5f),, 7, */
1761 aml_append(field, aml_reserved_field(0x2f8));
1762 aml_append(field, aml_reserved_field(7));
1763 aml_append(field, aml_named_field("LPEN", 1));
1764 /* Offset(0x67),, 3, */
1765 aml_append(field, aml_reserved_field(0x38));
1766 aml_append(field, aml_reserved_field(3));
1767 aml_append(field, aml_named_field("CAEN", 1));
1768 aml_append(field, aml_reserved_field(3));
1769 aml_append(field, aml_named_field("CBEN", 1));
1770 aml_append(dev, field);
1771
1772 aml_append(scope, dev);
1773 aml_append(table, scope);
1774 }
1775
1776 static void build_piix4_pci_hotplug(Aml *table)
1777 {
1778 Aml *scope;
1779 Aml *field;
1780 Aml *method;
1781
1782 scope = aml_scope("_SB.PCI0");
1783
1784 aml_append(scope,
1785 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1786 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1787 aml_append(field, aml_named_field("PCIU", 32));
1788 aml_append(field, aml_named_field("PCID", 32));
1789 aml_append(scope, field);
1790
1791 aml_append(scope,
1792 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1793 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1794 aml_append(field, aml_named_field("B0EJ", 32));
1795 aml_append(scope, field);
1796
1797 aml_append(scope,
1798 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1799 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1800 aml_append(field, aml_named_field("BNUM", 32));
1801 aml_append(scope, field);
1802
1803 aml_append(scope, aml_mutex("BLCK", 0));
1804
1805 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1806 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1807 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1808 aml_append(method,
1809 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1810 aml_append(method, aml_release(aml_name("BLCK")));
1811 aml_append(method, aml_return(aml_int(0)));
1812 aml_append(scope, method);
1813
1814 aml_append(table, scope);
1815 }
1816
1817 static Aml *build_q35_osc_method(void)
1818 {
1819 Aml *if_ctx;
1820 Aml *if_ctx2;
1821 Aml *else_ctx;
1822 Aml *method;
1823 Aml *a_cwd1 = aml_name("CDW1");
1824 Aml *a_ctrl = aml_local(0);
1825
1826 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1827 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1828
1829 if_ctx = aml_if(aml_equal(
1830 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1831 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1832 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1833
1834 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1835
1836 /*
1837 * Always allow native PME, AER (no dependencies)
1838 * Allow SHPC (PCI bridges can have SHPC controller)
1839 */
1840 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1841
1842 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1843 /* Unknown revision */
1844 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1845 aml_append(if_ctx, if_ctx2);
1846
1847 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1848 /* Capabilities bits were masked */
1849 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1850 aml_append(if_ctx, if_ctx2);
1851
1852 /* Update DWORD3 in the buffer */
1853 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1854 aml_append(method, if_ctx);
1855
1856 else_ctx = aml_else();
1857 /* Unrecognized UUID */
1858 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1859 aml_append(method, else_ctx);
1860
1861 aml_append(method, aml_return(aml_arg(3)));
1862 return method;
1863 }
1864
1865 static void
1866 build_dsdt(GArray *table_data, BIOSLinker *linker,
1867 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1868 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1869 {
1870 CrsRangeEntry *entry;
1871 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1872 CrsRangeSet crs_range_set;
1873 PCMachineState *pcms = PC_MACHINE(machine);
1874 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1875 uint32_t nr_mem = machine->ram_slots;
1876 int root_bus_limit = 0xFF;
1877 PCIBus *bus = NULL;
1878 int i;
1879
1880 dsdt = init_aml_allocator();
1881
1882 /* Reserve space for header */
1883 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1884
1885 build_dbg_aml(dsdt);
1886 if (misc->is_piix4) {
1887 sb_scope = aml_scope("_SB");
1888 dev = aml_device("PCI0");
1889 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1890 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1891 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1892 aml_append(sb_scope, dev);
1893 aml_append(dsdt, sb_scope);
1894
1895 build_hpet_aml(dsdt);
1896 build_piix4_pm(dsdt);
1897 build_piix4_isa_bridge(dsdt);
1898 build_isa_devices_aml(dsdt);
1899 build_piix4_pci_hotplug(dsdt);
1900 build_piix4_pci0_int(dsdt);
1901 } else {
1902 sb_scope = aml_scope("_SB");
1903 dev = aml_device("PCI0");
1904 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1905 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1906 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1907 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1908 aml_append(dev, build_q35_osc_method());
1909 aml_append(sb_scope, dev);
1910 aml_append(dsdt, sb_scope);
1911
1912 build_hpet_aml(dsdt);
1913 build_q35_isa_bridge(dsdt);
1914 build_isa_devices_aml(dsdt);
1915 build_q35_pci0_int(dsdt);
1916 }
1917
1918 if (pcmc->legacy_cpu_hotplug) {
1919 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1920 } else {
1921 CPUHotplugFeatures opts = {
1922 .apci_1_compatible = true, .has_legacy_cphp = true
1923 };
1924 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1925 "\\_SB.PCI0", "\\_GPE._E02");
1926 }
1927 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03");
1928
1929 scope = aml_scope("_GPE");
1930 {
1931 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1932
1933 if (misc->is_piix4) {
1934 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1935 aml_append(method,
1936 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1937 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1938 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1939 aml_append(scope, method);
1940 }
1941
1942 if (pcms->acpi_nvdimm_state.is_enabled) {
1943 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1944 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1945 aml_int(0x80)));
1946 aml_append(scope, method);
1947 }
1948 }
1949 aml_append(dsdt, scope);
1950
1951 crs_range_set_init(&crs_range_set);
1952 bus = PC_MACHINE(machine)->bus;
1953 if (bus) {
1954 QLIST_FOREACH(bus, &bus->child, sibling) {
1955 uint8_t bus_num = pci_bus_num(bus);
1956 uint8_t numa_node = pci_bus_numa_node(bus);
1957
1958 /* look only for expander root buses */
1959 if (!pci_bus_is_root(bus)) {
1960 continue;
1961 }
1962
1963 if (bus_num < root_bus_limit) {
1964 root_bus_limit = bus_num - 1;
1965 }
1966
1967 scope = aml_scope("\\_SB");
1968 dev = aml_device("PC%.02X", bus_num);
1969 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1970 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1971 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1972 if (pci_bus_is_express(bus)) {
1973 aml_append(dev, build_q35_osc_method());
1974 }
1975
1976 if (numa_node != NUMA_NODE_UNASSIGNED) {
1977 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1978 }
1979
1980 aml_append(dev, build_prt(false));
1981 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1982 aml_append(dev, aml_name_decl("_CRS", crs));
1983 aml_append(scope, dev);
1984 aml_append(dsdt, scope);
1985 }
1986 }
1987
1988 scope = aml_scope("\\_SB.PCI0");
1989 /* build PCI0._CRS */
1990 crs = aml_resource_template();
1991 aml_append(crs,
1992 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1993 0x0000, 0x0, root_bus_limit,
1994 0x0000, root_bus_limit + 1));
1995 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1996
1997 aml_append(crs,
1998 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1999 AML_POS_DECODE, AML_ENTIRE_RANGE,
2000 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2001
2002 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
2003 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
2004 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
2005 aml_append(crs,
2006 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2007 AML_POS_DECODE, AML_ENTIRE_RANGE,
2008 0x0000, entry->base, entry->limit,
2009 0x0000, entry->limit - entry->base + 1));
2010 }
2011
2012 aml_append(crs,
2013 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2014 AML_CACHEABLE, AML_READ_WRITE,
2015 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2016
2017 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
2018 range_lob(pci_hole),
2019 range_upb(pci_hole));
2020 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
2021 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
2022 aml_append(crs,
2023 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2024 AML_NON_CACHEABLE, AML_READ_WRITE,
2025 0, entry->base, entry->limit,
2026 0, entry->limit - entry->base + 1));
2027 }
2028
2029 if (!range_is_empty(pci_hole64)) {
2030 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
2031 range_lob(pci_hole64),
2032 range_upb(pci_hole64));
2033 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
2034 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
2035 aml_append(crs,
2036 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
2037 AML_MAX_FIXED,
2038 AML_CACHEABLE, AML_READ_WRITE,
2039 0, entry->base, entry->limit,
2040 0, entry->limit - entry->base + 1));
2041 }
2042 }
2043
2044 if (TPM_IS_TIS(tpm_find())) {
2045 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2046 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2047 }
2048 aml_append(scope, aml_name_decl("_CRS", crs));
2049
2050 /* reserve GPE0 block resources */
2051 dev = aml_device("GPE0");
2052 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2053 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2054 /* device present, functioning, decoding, not shown in UI */
2055 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2056 crs = aml_resource_template();
2057 aml_append(crs,
2058 aml_io(
2059 AML_DECODE16,
2060 pm->fadt.gpe0_blk.address,
2061 pm->fadt.gpe0_blk.address,
2062 1,
2063 pm->fadt.gpe0_blk.bit_width / 8)
2064 );
2065 aml_append(dev, aml_name_decl("_CRS", crs));
2066 aml_append(scope, dev);
2067
2068 crs_range_set_free(&crs_range_set);
2069
2070 /* reserve PCIHP resources */
2071 if (pm->pcihp_io_len) {
2072 dev = aml_device("PHPR");
2073 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2074 aml_append(dev,
2075 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2076 /* device present, functioning, decoding, not shown in UI */
2077 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2078 crs = aml_resource_template();
2079 aml_append(crs,
2080 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2081 pm->pcihp_io_len)
2082 );
2083 aml_append(dev, aml_name_decl("_CRS", crs));
2084 aml_append(scope, dev);
2085 }
2086 aml_append(dsdt, scope);
2087
2088 /* create S3_ / S4_ / S5_ packages if necessary */
2089 scope = aml_scope("\\");
2090 if (!pm->s3_disabled) {
2091 pkg = aml_package(4);
2092 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2093 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2094 aml_append(pkg, aml_int(0)); /* reserved */
2095 aml_append(pkg, aml_int(0)); /* reserved */
2096 aml_append(scope, aml_name_decl("_S3", pkg));
2097 }
2098
2099 if (!pm->s4_disabled) {
2100 pkg = aml_package(4);
2101 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2102 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2103 aml_append(pkg, aml_int(pm->s4_val));
2104 aml_append(pkg, aml_int(0)); /* reserved */
2105 aml_append(pkg, aml_int(0)); /* reserved */
2106 aml_append(scope, aml_name_decl("_S4", pkg));
2107 }
2108
2109 pkg = aml_package(4);
2110 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2111 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2112 aml_append(pkg, aml_int(0)); /* reserved */
2113 aml_append(pkg, aml_int(0)); /* reserved */
2114 aml_append(scope, aml_name_decl("_S5", pkg));
2115 aml_append(dsdt, scope);
2116
2117 /* create fw_cfg node, unconditionally */
2118 {
2119 /* when using port i/o, the 8-bit data register *always* overlaps
2120 * with half of the 16-bit control register. Hence, the total size
2121 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2122 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2123 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2124 "dma_enabled", NULL) ?
2125 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2126 FW_CFG_CTL_SIZE;
2127
2128 scope = aml_scope("\\_SB.PCI0");
2129 dev = aml_device("FWCF");
2130
2131 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2132
2133 /* device present, functioning, decoding, not shown in UI */
2134 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2135
2136 crs = aml_resource_template();
2137 aml_append(crs,
2138 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2139 );
2140 aml_append(dev, aml_name_decl("_CRS", crs));
2141
2142 aml_append(scope, dev);
2143 aml_append(dsdt, scope);
2144 }
2145
2146 if (misc->applesmc_io_base) {
2147 scope = aml_scope("\\_SB.PCI0.ISA");
2148 dev = aml_device("SMC");
2149
2150 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2151 /* device present, functioning, decoding, not shown in UI */
2152 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2153
2154 crs = aml_resource_template();
2155 aml_append(crs,
2156 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2157 0x01, APPLESMC_MAX_DATA_LENGTH)
2158 );
2159 aml_append(crs, aml_irq_no_flags(6));
2160 aml_append(dev, aml_name_decl("_CRS", crs));
2161
2162 aml_append(scope, dev);
2163 aml_append(dsdt, scope);
2164 }
2165
2166 if (misc->pvpanic_port) {
2167 scope = aml_scope("\\_SB.PCI0.ISA");
2168
2169 dev = aml_device("PEVT");
2170 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2171
2172 crs = aml_resource_template();
2173 aml_append(crs,
2174 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2175 );
2176 aml_append(dev, aml_name_decl("_CRS", crs));
2177
2178 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2179 aml_int(misc->pvpanic_port), 1));
2180 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2181 aml_append(field, aml_named_field("PEPT", 8));
2182 aml_append(dev, field);
2183
2184 /* device present, functioning, decoding, shown in UI */
2185 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2186
2187 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2188 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2189 aml_append(method, aml_return(aml_local(0)));
2190 aml_append(dev, method);
2191
2192 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2193 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2194 aml_append(dev, method);
2195
2196 aml_append(scope, dev);
2197 aml_append(dsdt, scope);
2198 }
2199
2200 sb_scope = aml_scope("\\_SB");
2201 {
2202 Object *pci_host;
2203 PCIBus *bus = NULL;
2204
2205 pci_host = acpi_get_i386_pci_host();
2206 if (pci_host) {
2207 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2208 }
2209
2210 if (bus) {
2211 Aml *scope = aml_scope("PCI0");
2212 /* Scan all PCI buses. Generate tables to support hotplug. */
2213 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2214
2215 if (TPM_IS_TIS(tpm_find())) {
2216 dev = aml_device("ISA.TPM");
2217 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2218 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2219 crs = aml_resource_template();
2220 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2221 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2222 /*
2223 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2224 Rewrite to take IRQ from TPM device model and
2225 fix default IRQ value there to use some unused IRQ
2226 */
2227 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2228 aml_append(dev, aml_name_decl("_CRS", crs));
2229 aml_append(scope, dev);
2230 }
2231
2232 aml_append(sb_scope, scope);
2233 }
2234 }
2235
2236 if (TPM_IS_CRB(tpm_find())) {
2237 dev = aml_device("TPM");
2238 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
2239 crs = aml_resource_template();
2240 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
2241 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
2242 aml_append(dev, aml_name_decl("_CRS", crs));
2243
2244 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
2245 aml_append(method, aml_return(aml_int(0x0f)));
2246 aml_append(dev, method);
2247
2248 aml_append(sb_scope, dev);
2249 }
2250
2251 aml_append(dsdt, sb_scope);
2252
2253 /* copy AML table into ACPI tables blob and patch header there */
2254 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2255 build_header(linker, table_data,
2256 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2257 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2258 free_aml_allocator();
2259 }
2260
2261 static void
2262 build_hpet(GArray *table_data, BIOSLinker *linker)
2263 {
2264 Acpi20Hpet *hpet;
2265
2266 hpet = acpi_data_push(table_data, sizeof(*hpet));
2267 /* Note timer_block_id value must be kept in sync with value advertised by
2268 * emulated hpet
2269 */
2270 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2271 hpet->addr.address = cpu_to_le64(HPET_BASE);
2272 build_header(linker, table_data,
2273 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2274 }
2275
2276 static void
2277 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2278 {
2279 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2280 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2281 unsigned log_addr_offset =
2282 (char *)&tcpa->log_area_start_address - table_data->data;
2283
2284 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2285 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2286 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2287
2288 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2289 false /* high memory */);
2290
2291 /* log area start address to be filled by Guest linker */
2292 bios_linker_loader_add_pointer(linker,
2293 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2294 ACPI_BUILD_TPMLOG_FILE, 0);
2295
2296 build_header(linker, table_data,
2297 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2298 }
2299
2300 static void
2301 build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2302 {
2303 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2304 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
2305 unsigned log_addr_offset =
2306 (char *)&tpm2_ptr->log_area_start_address - table_data->data;
2307
2308 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2309 if (TPM_IS_TIS(tpm_find())) {
2310 tpm2_ptr->control_area_address = cpu_to_le64(0);
2311 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2312 } else if (TPM_IS_CRB(tpm_find())) {
2313 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL);
2314 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB);
2315 } else {
2316 g_warn_if_reached();
2317 }
2318
2319 tpm2_ptr->log_area_minimum_length =
2320 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2321
2322 /* log area start address to be filled by Guest linker */
2323 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2324 log_addr_offset, log_addr_size,
2325 ACPI_BUILD_TPMLOG_FILE, 0);
2326 build_header(linker, table_data,
2327 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2328 }
2329
2330 #define HOLE_640K_START (640 * 1024)
2331 #define HOLE_640K_END (1024 * 1024)
2332
2333 static void
2334 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2335 {
2336 AcpiSystemResourceAffinityTable *srat;
2337 AcpiSratMemoryAffinity *numamem;
2338
2339 int i;
2340 int srat_start, numa_start, slots;
2341 uint64_t mem_len, mem_base, next_base;
2342 MachineClass *mc = MACHINE_GET_CLASS(machine);
2343 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2344 PCMachineState *pcms = PC_MACHINE(machine);
2345 ram_addr_t hotplugabble_address_space_size =
2346 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2347 NULL);
2348
2349 srat_start = table_data->len;
2350
2351 srat = acpi_data_push(table_data, sizeof *srat);
2352 srat->reserved1 = cpu_to_le32(1);
2353
2354 for (i = 0; i < apic_ids->len; i++) {
2355 int node_id = apic_ids->cpus[i].props.node_id;
2356 uint32_t apic_id = apic_ids->cpus[i].arch_id;
2357
2358 if (apic_id < 255) {
2359 AcpiSratProcessorAffinity *core;
2360
2361 core = acpi_data_push(table_data, sizeof *core);
2362 core->type = ACPI_SRAT_PROCESSOR_APIC;
2363 core->length = sizeof(*core);
2364 core->local_apic_id = apic_id;
2365 core->proximity_lo = node_id;
2366 memset(core->proximity_hi, 0, 3);
2367 core->local_sapic_eid = 0;
2368 core->flags = cpu_to_le32(1);
2369 } else {
2370 AcpiSratProcessorX2ApicAffinity *core;
2371
2372 core = acpi_data_push(table_data, sizeof *core);
2373 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2374 core->length = sizeof(*core);
2375 core->x2apic_id = cpu_to_le32(apic_id);
2376 core->proximity_domain = cpu_to_le32(node_id);
2377 core->flags = cpu_to_le32(1);
2378 }
2379 }
2380
2381
2382 /* the memory map is a bit tricky, it contains at least one hole
2383 * from 640k-1M and possibly another one from 3.5G-4G.
2384 */
2385 next_base = 0;
2386 numa_start = table_data->len;
2387
2388 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2389 mem_base = next_base;
2390 mem_len = pcms->node_mem[i - 1];
2391 next_base = mem_base + mem_len;
2392
2393 /* Cut out the 640K hole */
2394 if (mem_base <= HOLE_640K_START &&
2395 next_base > HOLE_640K_START) {
2396 mem_len -= next_base - HOLE_640K_START;
2397 if (mem_len > 0) {
2398 numamem = acpi_data_push(table_data, sizeof *numamem);
2399 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2400 MEM_AFFINITY_ENABLED);
2401 }
2402
2403 /* Check for the rare case: 640K < RAM < 1M */
2404 if (next_base <= HOLE_640K_END) {
2405 next_base = HOLE_640K_END;
2406 continue;
2407 }
2408 mem_base = HOLE_640K_END;
2409 mem_len = next_base - HOLE_640K_END;
2410 }
2411
2412 /* Cut out the ACPI_PCI hole */
2413 if (mem_base <= pcms->below_4g_mem_size &&
2414 next_base > pcms->below_4g_mem_size) {
2415 mem_len -= next_base - pcms->below_4g_mem_size;
2416 if (mem_len > 0) {
2417 numamem = acpi_data_push(table_data, sizeof *numamem);
2418 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2419 MEM_AFFINITY_ENABLED);
2420 }
2421 mem_base = 1ULL << 32;
2422 mem_len = next_base - pcms->below_4g_mem_size;
2423 next_base = mem_base + mem_len;
2424 }
2425 numamem = acpi_data_push(table_data, sizeof *numamem);
2426 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2427 MEM_AFFINITY_ENABLED);
2428 }
2429 slots = (table_data->len - numa_start) / sizeof *numamem;
2430 for (; slots < pcms->numa_nodes + 2; slots++) {
2431 numamem = acpi_data_push(table_data, sizeof *numamem);
2432 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2433 }
2434
2435 /*
2436 * Entry is required for Windows to enable memory hotplug in OS
2437 * and for Linux to enable SWIOTLB when booted with less than
2438 * 4G of RAM. Windows works better if the entry sets proximity
2439 * to the highest NUMA node in the machine.
2440 * Memory devices may override proximity set by this entry,
2441 * providing _PXM method if necessary.
2442 */
2443 if (hotplugabble_address_space_size) {
2444 numamem = acpi_data_push(table_data, sizeof *numamem);
2445 build_srat_memory(numamem, pcms->hotplug_memory.base,
2446 hotplugabble_address_space_size, pcms->numa_nodes - 1,
2447 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2448 }
2449
2450 build_header(linker, table_data,
2451 (void *)(table_data->data + srat_start),
2452 "SRAT",
2453 table_data->len - srat_start, 1, NULL, NULL);
2454 }
2455
2456 static void
2457 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
2458 {
2459 AcpiTableMcfg *mcfg;
2460 const char *sig;
2461 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2462
2463 mcfg = acpi_data_push(table_data, len);
2464 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2465 /* Only a single allocation so no need to play with segments */
2466 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2467 mcfg->allocation[0].start_bus_number = 0;
2468 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2469
2470 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2471 * To avoid table size changes (which create migration issues),
2472 * always create the table even if there are no allocations,
2473 * but set the signature to a reserved value in this case.
2474 * ACPI spec requires OSPMs to ignore such tables.
2475 */
2476 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2477 /* Reserved signature: ignored by OSPM */
2478 sig = "QEMU";
2479 } else {
2480 sig = "MCFG";
2481 }
2482 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2483 }
2484
2485 /*
2486 * VT-d spec 8.1 DMA Remapping Reporting Structure
2487 * (version Oct. 2014 or later)
2488 */
2489 static void
2490 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2491 {
2492 int dmar_start = table_data->len;
2493
2494 AcpiTableDmar *dmar;
2495 AcpiDmarHardwareUnit *drhd;
2496 AcpiDmarRootPortATS *atsr;
2497 uint8_t dmar_flags = 0;
2498 X86IOMMUState *iommu = x86_iommu_get_default();
2499 AcpiDmarDeviceScope *scope = NULL;
2500 /* Root complex IOAPIC use one path[0] only */
2501 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2502 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2503
2504 assert(iommu);
2505 if (iommu->intr_supported) {
2506 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2507 }
2508
2509 dmar = acpi_data_push(table_data, sizeof(*dmar));
2510 dmar->host_address_width = intel_iommu->aw_bits - 1;
2511 dmar->flags = dmar_flags;
2512
2513 /* DMAR Remapping Hardware Unit Definition structure */
2514 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2515 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2516 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2517 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2518 drhd->pci_segment = cpu_to_le16(0);
2519 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2520
2521 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2522 * 8.3.1 (version Oct. 2014 or later). */
2523 scope = &drhd->scope[0];
2524 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2525 scope->length = ioapic_scope_size;
2526 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2527 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2528 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2529 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2530
2531 if (iommu->dt_supported) {
2532 atsr = acpi_data_push(table_data, sizeof(*atsr));
2533 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2534 atsr->length = cpu_to_le16(sizeof(*atsr));
2535 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2536 atsr->pci_segment = cpu_to_le16(0);
2537 }
2538
2539 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2540 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2541 }
2542 /*
2543 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2544 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2545 */
2546 static void
2547 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2548 {
2549 int iommu_start = table_data->len;
2550 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2551
2552 /* IVRS header */
2553 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2554 /* IVinfo - IO virtualization information common to all
2555 * IOMMU units in a system
2556 */
2557 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2558 /* reserved */
2559 build_append_int_noprefix(table_data, 0, 8);
2560
2561 /* IVHD definition - type 10h */
2562 build_append_int_noprefix(table_data, 0x10, 1);
2563 /* virtualization flags */
2564 build_append_int_noprefix(table_data,
2565 (1UL << 0) | /* HtTunEn */
2566 (1UL << 4) | /* iotblSup */
2567 (1UL << 6) | /* PrefSup */
2568 (1UL << 7), /* PPRSup */
2569 1);
2570 /* IVHD length */
2571 build_append_int_noprefix(table_data, 0x24, 2);
2572 /* DeviceID */
2573 build_append_int_noprefix(table_data, s->devid, 2);
2574 /* Capability offset */
2575 build_append_int_noprefix(table_data, s->capab_offset, 2);
2576 /* IOMMU base address */
2577 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2578 /* PCI Segment Group */
2579 build_append_int_noprefix(table_data, 0, 2);
2580 /* IOMMU info */
2581 build_append_int_noprefix(table_data, 0, 2);
2582 /* IOMMU Feature Reporting */
2583 build_append_int_noprefix(table_data,
2584 (48UL << 30) | /* HATS */
2585 (48UL << 28) | /* GATS */
2586 (1UL << 2), /* GTSup */
2587 4);
2588 /*
2589 * Type 1 device entry reporting all devices
2590 * These are 4-byte device entries currently reporting the range of
2591 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2592 */
2593 build_append_int_noprefix(table_data, 0x0000001, 4);
2594
2595 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2596 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2597 }
2598
2599 static GArray *
2600 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
2601 {
2602 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2603 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2604 unsigned rsdt_pa_offset =
2605 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
2606
2607 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
2608 true /* fseg memory */);
2609
2610 memcpy(&rsdp->signature, "RSD PTR ", 8);
2611 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2612 /* Address to be filled by Guest linker */
2613 bios_linker_loader_add_pointer(linker,
2614 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
2615 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
2616
2617 /* Checksum to be filled by Guest linker */
2618 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2619 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
2620 (char *)&rsdp->checksum - rsdp_table->data);
2621
2622 return rsdp_table;
2623 }
2624
2625 typedef
2626 struct AcpiBuildState {
2627 /* Copy of table in RAM (for patching). */
2628 MemoryRegion *table_mr;
2629 /* Is table patched? */
2630 uint8_t patched;
2631 void *rsdp;
2632 MemoryRegion *rsdp_mr;
2633 MemoryRegion *linker_mr;
2634 } AcpiBuildState;
2635
2636 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2637 {
2638 Object *pci_host;
2639 QObject *o;
2640
2641 pci_host = acpi_get_i386_pci_host();
2642 g_assert(pci_host);
2643
2644 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2645 if (!o) {
2646 return false;
2647 }
2648 mcfg->mcfg_base = qnum_get_uint(qobject_to_qnum(o));
2649 qobject_decref(o);
2650
2651 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2652 assert(o);
2653 mcfg->mcfg_size = qnum_get_uint(qobject_to_qnum(o));
2654 qobject_decref(o);
2655 return true;
2656 }
2657
2658 static
2659 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2660 {
2661 PCMachineState *pcms = PC_MACHINE(machine);
2662 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2663 GArray *table_offsets;
2664 unsigned facs, dsdt, rsdt, fadt;
2665 AcpiPmInfo pm;
2666 AcpiMiscInfo misc;
2667 AcpiMcfgInfo mcfg;
2668 Range pci_hole, pci_hole64;
2669 uint8_t *u;
2670 size_t aml_len = 0;
2671 GArray *tables_blob = tables->table_data;
2672 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2673 Object *vmgenid_dev;
2674
2675 acpi_get_pm_info(&pm);
2676 acpi_get_misc_info(&misc);
2677 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2678 acpi_get_slic_oem(&slic_oem);
2679
2680 table_offsets = g_array_new(false, true /* clear */,
2681 sizeof(uint32_t));
2682 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2683
2684 bios_linker_loader_alloc(tables->linker,
2685 ACPI_BUILD_TABLE_FILE, tables_blob,
2686 64 /* Ensure FACS is aligned */,
2687 false /* high memory */);
2688
2689 /*
2690 * FACS is pointed to by FADT.
2691 * We place it first since it's the only table that has alignment
2692 * requirements.
2693 */
2694 facs = tables_blob->len;
2695 build_facs(tables_blob, tables->linker);
2696
2697 /* DSDT is pointed to by FADT */
2698 dsdt = tables_blob->len;
2699 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2700 &pci_hole, &pci_hole64, machine);
2701
2702 /* Count the size of the DSDT and SSDT, we will need it for legacy
2703 * sizing of ACPI tables.
2704 */
2705 aml_len += tables_blob->len - dsdt;
2706
2707 /* ACPI tables pointed to by RSDT */
2708 fadt = tables_blob->len;
2709 acpi_add_table(table_offsets, tables_blob);
2710 pm.fadt.facs_tbl_offset = &facs;
2711 pm.fadt.dsdt_tbl_offset = &dsdt;
2712 pm.fadt.xdsdt_tbl_offset = &dsdt;
2713 build_fadt(tables_blob, tables->linker, &pm.fadt,
2714 slic_oem.id, slic_oem.table_id);
2715 aml_len += tables_blob->len - fadt;
2716
2717 acpi_add_table(table_offsets, tables_blob);
2718 build_madt(tables_blob, tables->linker, pcms);
2719
2720 vmgenid_dev = find_vmgenid_dev();
2721 if (vmgenid_dev) {
2722 acpi_add_table(table_offsets, tables_blob);
2723 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2724 tables->vmgenid, tables->linker);
2725 }
2726
2727 if (misc.has_hpet) {
2728 acpi_add_table(table_offsets, tables_blob);
2729 build_hpet(tables_blob, tables->linker);
2730 }
2731 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2732 acpi_add_table(table_offsets, tables_blob);
2733 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2734
2735 if (misc.tpm_version == TPM_VERSION_2_0) {
2736 acpi_add_table(table_offsets, tables_blob);
2737 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
2738 }
2739 }
2740 if (pcms->numa_nodes) {
2741 acpi_add_table(table_offsets, tables_blob);
2742 build_srat(tables_blob, tables->linker, machine);
2743 if (have_numa_distance) {
2744 acpi_add_table(table_offsets, tables_blob);
2745 build_slit(tables_blob, tables->linker);
2746 }
2747 }
2748 if (acpi_get_mcfg(&mcfg)) {
2749 acpi_add_table(table_offsets, tables_blob);
2750 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2751 }
2752 if (x86_iommu_get_default()) {
2753 IommuType IOMMUType = x86_iommu_get_type();
2754 if (IOMMUType == TYPE_AMD) {
2755 acpi_add_table(table_offsets, tables_blob);
2756 build_amd_iommu(tables_blob, tables->linker);
2757 } else if (IOMMUType == TYPE_INTEL) {
2758 acpi_add_table(table_offsets, tables_blob);
2759 build_dmar_q35(tables_blob, tables->linker);
2760 }
2761 }
2762 if (pcms->acpi_nvdimm_state.is_enabled) {
2763 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2764 &pcms->acpi_nvdimm_state, machine->ram_slots);
2765 }
2766
2767 /* Add tables supplied by user (if any) */
2768 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2769 unsigned len = acpi_table_len(u);
2770
2771 acpi_add_table(table_offsets, tables_blob);
2772 g_array_append_vals(tables_blob, u, len);
2773 }
2774
2775 /* RSDT is pointed to by RSDP */
2776 rsdt = tables_blob->len;
2777 build_rsdt(tables_blob, tables->linker, table_offsets,
2778 slic_oem.id, slic_oem.table_id);
2779
2780 /* RSDP is in FSEG memory, so allocate it separately */
2781 build_rsdp(tables->rsdp, tables->linker, rsdt);
2782
2783 /* We'll expose it all to Guest so we want to reduce
2784 * chance of size changes.
2785 *
2786 * We used to align the tables to 4k, but of course this would
2787 * too simple to be enough. 4k turned out to be too small an
2788 * alignment very soon, and in fact it is almost impossible to
2789 * keep the table size stable for all (max_cpus, max_memory_slots)
2790 * combinations. So the table size is always 64k for pc-i440fx-2.1
2791 * and we give an error if the table grows beyond that limit.
2792 *
2793 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2794 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2795 * than 2.0 and we can always pad the smaller tables with zeros. We can
2796 * then use the exact size of the 2.0 tables.
2797 *
2798 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2799 */
2800 if (pcmc->legacy_acpi_table_size) {
2801 /* Subtracting aml_len gives the size of fixed tables. Then add the
2802 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2803 */
2804 int legacy_aml_len =
2805 pcmc->legacy_acpi_table_size +
2806 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit;
2807 int legacy_table_size =
2808 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2809 ACPI_BUILD_ALIGN_SIZE);
2810 if (tables_blob->len > legacy_table_size) {
2811 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2812 warn_report("ACPI table size %u exceeds %d bytes,"
2813 " migration may not work",
2814 tables_blob->len, legacy_table_size);
2815 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2816 " or PCI bridges.");
2817 }
2818 g_array_set_size(tables_blob, legacy_table_size);
2819 } else {
2820 /* Make sure we have a buffer in case we need to resize the tables. */
2821 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2822 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2823 warn_report("ACPI table size %u exceeds %d bytes,"
2824 " migration may not work",
2825 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2826 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2827 " or PCI bridges.");
2828 }
2829 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2830 }
2831
2832 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2833
2834 /* Cleanup memory that's no longer used. */
2835 g_array_free(table_offsets, true);
2836 }
2837
2838 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2839 {
2840 uint32_t size = acpi_data_len(data);
2841
2842 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2843 memory_region_ram_resize(mr, size, &error_abort);
2844
2845 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2846 memory_region_set_dirty(mr, 0, size);
2847 }
2848
2849 static void acpi_build_update(void *build_opaque)
2850 {
2851 AcpiBuildState *build_state = build_opaque;
2852 AcpiBuildTables tables;
2853
2854 /* No state to update or already patched? Nothing to do. */
2855 if (!build_state || build_state->patched) {
2856 return;
2857 }
2858 build_state->patched = 1;
2859
2860 acpi_build_tables_init(&tables);
2861
2862 acpi_build(&tables, MACHINE(qdev_get_machine()));
2863
2864 acpi_ram_update(build_state->table_mr, tables.table_data);
2865
2866 if (build_state->rsdp) {
2867 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2868 } else {
2869 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2870 }
2871
2872 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2873 acpi_build_tables_cleanup(&tables, true);
2874 }
2875
2876 static void acpi_build_reset(void *build_opaque)
2877 {
2878 AcpiBuildState *build_state = build_opaque;
2879 build_state->patched = 0;
2880 }
2881
2882 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2883 GArray *blob, const char *name,
2884 uint64_t max_size)
2885 {
2886 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2887 name, acpi_build_update, build_state, NULL, true);
2888 }
2889
2890 static const VMStateDescription vmstate_acpi_build = {
2891 .name = "acpi_build",
2892 .version_id = 1,
2893 .minimum_version_id = 1,
2894 .fields = (VMStateField[]) {
2895 VMSTATE_UINT8(patched, AcpiBuildState),
2896 VMSTATE_END_OF_LIST()
2897 },
2898 };
2899
2900 void acpi_setup(void)
2901 {
2902 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2903 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2904 AcpiBuildTables tables;
2905 AcpiBuildState *build_state;
2906 Object *vmgenid_dev;
2907
2908 if (!pcms->fw_cfg) {
2909 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2910 return;
2911 }
2912
2913 if (!pcms->acpi_build_enabled) {
2914 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2915 return;
2916 }
2917
2918 if (!acpi_enabled) {
2919 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2920 return;
2921 }
2922
2923 build_state = g_malloc0(sizeof *build_state);
2924
2925 acpi_build_tables_init(&tables);
2926 acpi_build(&tables, MACHINE(pcms));
2927
2928 /* Now expose it all to Guest */
2929 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2930 ACPI_BUILD_TABLE_FILE,
2931 ACPI_BUILD_TABLE_MAX_SIZE);
2932 assert(build_state->table_mr != NULL);
2933
2934 build_state->linker_mr =
2935 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2936 "etc/table-loader", 0);
2937
2938 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2939 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2940
2941 vmgenid_dev = find_vmgenid_dev();
2942 if (vmgenid_dev) {
2943 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg,
2944 tables.vmgenid);
2945 }
2946
2947 if (!pcmc->rsdp_in_ram) {
2948 /*
2949 * Keep for compatibility with old machine types.
2950 * Though RSDP is small, its contents isn't immutable, so
2951 * we'll update it along with the rest of tables on guest access.
2952 */
2953 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2954
2955 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2956 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2957 acpi_build_update, NULL, build_state,
2958 build_state->rsdp, rsdp_size, true);
2959 build_state->rsdp_mr = NULL;
2960 } else {
2961 build_state->rsdp = NULL;
2962 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2963 ACPI_BUILD_RSDP_FILE, 0);
2964 }
2965
2966 qemu_register_reset(acpi_build_reset, build_state);
2967 acpi_build_reset(build_state);
2968 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2969
2970 /* Cleanup tables but don't free the memory: we track it
2971 * in build_state.
2972 */
2973 acpi_build_tables_cleanup(&tables, false);
2974 }
AR7 emulation for QEMU