2 * ARM Generic Interrupt Controller using KVM in-kernel support
4 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
5 * Written by Pavel Fedin
6 * Based on vGICv2 code by Peter Maydell
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "hw/intc/arm_gicv3_common.h"
25 #include "hw/sysbus.h"
26 #include "qemu/error-report.h"
27 #include "sysemu/kvm.h"
28 #include "sysemu/sysemu.h"
30 #include "gicv3_internal.h"
31 #include "vgic_common.h"
32 #include "migration/blocker.h"
34 #ifdef DEBUG_GICV3_KVM
35 #define DPRINTF(fmt, ...) \
36 do { fprintf(stderr, "kvm_gicv3: " fmt, ## __VA_ARGS__); } while (0)
38 #define DPRINTF(fmt, ...) \
42 #define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3"
43 #define KVM_ARM_GICV3(obj) \
44 OBJECT_CHECK(GICv3State, (obj), TYPE_KVM_ARM_GICV3)
45 #define KVM_ARM_GICV3_CLASS(klass) \
46 OBJECT_CLASS_CHECK(KVMARMGICv3Class, (klass), TYPE_KVM_ARM_GICV3)
47 #define KVM_ARM_GICV3_GET_CLASS(obj) \
48 OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3)
50 #define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \
51 (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
52 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
53 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
54 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
55 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
58 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0)
59 #define ICC_BPR0_EL1 \
60 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3)
61 #define ICC_AP0R_EL1(n) \
62 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n)
63 #define ICC_AP1R_EL1(n) \
64 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n)
65 #define ICC_BPR1_EL1 \
66 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3)
67 #define ICC_CTLR_EL1 \
68 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4)
70 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5)
71 #define ICC_IGRPEN0_EL1 \
72 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6)
73 #define ICC_IGRPEN1_EL1 \
74 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7)
76 typedef struct KVMARMGICv3Class
{
77 ARMGICv3CommonClass parent_class
;
78 DeviceRealize parent_realize
;
79 void (*parent_reset
)(DeviceState
*dev
);
82 static void kvm_arm_gicv3_set_irq(void *opaque
, int irq
, int level
)
84 GICv3State
*s
= (GICv3State
*)opaque
;
86 kvm_arm_gic_set_irq(s
->num_irq
, irq
, level
);
89 #define KVM_VGIC_ATTR(reg, typer) \
90 ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg))
92 static inline void kvm_gicd_access(GICv3State
*s
, int offset
,
93 uint32_t *val
, bool write
)
95 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_DIST_REGS
,
96 KVM_VGIC_ATTR(offset
, 0),
97 val
, write
, &error_abort
);
100 static inline void kvm_gicr_access(GICv3State
*s
, int offset
, int cpu
,
101 uint32_t *val
, bool write
)
103 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
,
104 KVM_VGIC_ATTR(offset
, s
->cpu
[cpu
].gicr_typer
),
105 val
, write
, &error_abort
);
108 static inline void kvm_gicc_access(GICv3State
*s
, uint64_t reg
, int cpu
,
109 uint64_t *val
, bool write
)
111 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS
,
112 KVM_VGIC_ATTR(reg
, s
->cpu
[cpu
].gicr_typer
),
113 val
, write
, &error_abort
);
116 static inline void kvm_gic_line_level_access(GICv3State
*s
, int irq
, int cpu
,
117 uint32_t *val
, bool write
)
119 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO
,
120 KVM_VGIC_ATTR(irq
, s
->cpu
[cpu
].gicr_typer
) |
121 (VGIC_LEVEL_INFO_LINE_LEVEL
<<
122 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT
),
123 val
, write
, &error_abort
);
126 /* Loop through each distributor IRQ related register; since bits
127 * corresponding to SPIs and PPIs are RAZ/WI when affinity routing
128 * is enabled, we skip those.
130 #define for_each_dist_irq_reg(_irq, _max, _field_width) \
131 for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width))
133 static void kvm_dist_get_priority(GICv3State
*s
, uint32_t offset
, uint8_t *bmp
)
135 uint32_t reg
, *field
;
138 /* For the KVM GICv3, affinity routing is always enabled, and the first 8
139 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding
140 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to
141 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and
144 field
= (uint32_t *)(bmp
+ GIC_INTERNAL
);
145 offset
+= (GIC_INTERNAL
* 8) / 8;
146 for_each_dist_irq_reg(irq
, s
->num_irq
, 8) {
147 kvm_gicd_access(s
, offset
, ®
, false);
154 static void kvm_dist_put_priority(GICv3State
*s
, uint32_t offset
, uint8_t *bmp
)
156 uint32_t reg
, *field
;
159 /* For the KVM GICv3, affinity routing is always enabled, and the first 8
160 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding
161 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to
162 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and
165 field
= (uint32_t *)(bmp
+ GIC_INTERNAL
);
166 offset
+= (GIC_INTERNAL
* 8) / 8;
167 for_each_dist_irq_reg(irq
, s
->num_irq
, 8) {
169 kvm_gicd_access(s
, offset
, ®
, true);
175 static void kvm_dist_get_edge_trigger(GICv3State
*s
, uint32_t offset
,
181 /* For the KVM GICv3, affinity routing is always enabled, and the first 2
182 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding
183 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync
184 * them. So it should increase the offset to skip GIC_INTERNAL irqs.
185 * This matches the for_each_dist_irq_reg() macro which also skips the
186 * first GIC_INTERNAL irqs.
188 offset
+= (GIC_INTERNAL
* 2) / 8;
189 for_each_dist_irq_reg(irq
, s
->num_irq
, 2) {
190 kvm_gicd_access(s
, offset
, ®
, false);
191 reg
= half_unshuffle32(reg
>> 1);
195 *gic_bmp_ptr32(bmp
, irq
) |= reg
;
200 static void kvm_dist_put_edge_trigger(GICv3State
*s
, uint32_t offset
,
206 /* For the KVM GICv3, affinity routing is always enabled, and the first 2
207 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding
208 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync
209 * them. So it should increase the offset to skip GIC_INTERNAL irqs.
210 * This matches the for_each_dist_irq_reg() macro which also skips the
211 * first GIC_INTERNAL irqs.
213 offset
+= (GIC_INTERNAL
* 2) / 8;
214 for_each_dist_irq_reg(irq
, s
->num_irq
, 2) {
215 reg
= *gic_bmp_ptr32(bmp
, irq
);
217 reg
= (reg
& 0xffff0000) >> 16;
221 reg
= half_shuffle32(reg
) << 1;
222 kvm_gicd_access(s
, offset
, ®
, true);
227 static void kvm_gic_get_line_level_bmp(GICv3State
*s
, uint32_t *bmp
)
232 for_each_dist_irq_reg(irq
, s
->num_irq
, 1) {
233 kvm_gic_line_level_access(s
, irq
, 0, ®
, false);
234 *gic_bmp_ptr32(bmp
, irq
) = reg
;
238 static void kvm_gic_put_line_level_bmp(GICv3State
*s
, uint32_t *bmp
)
243 for_each_dist_irq_reg(irq
, s
->num_irq
, 1) {
244 reg
= *gic_bmp_ptr32(bmp
, irq
);
245 kvm_gic_line_level_access(s
, irq
, 0, ®
, true);
249 /* Read a bitmap register group from the kernel VGIC. */
250 static void kvm_dist_getbmp(GICv3State
*s
, uint32_t offset
, uint32_t *bmp
)
255 /* For the KVM GICv3, affinity routing is always enabled, and the
256 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/
257 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding
258 * functionality is replaced by the GICR registers. It doesn't need to sync
259 * them. So it should increase the offset to skip GIC_INTERNAL irqs.
260 * This matches the for_each_dist_irq_reg() macro which also skips the
261 * first GIC_INTERNAL irqs.
263 offset
+= (GIC_INTERNAL
* 1) / 8;
264 for_each_dist_irq_reg(irq
, s
->num_irq
, 1) {
265 kvm_gicd_access(s
, offset
, ®
, false);
266 *gic_bmp_ptr32(bmp
, irq
) = reg
;
271 static void kvm_dist_putbmp(GICv3State
*s
, uint32_t offset
,
272 uint32_t clroffset
, uint32_t *bmp
)
277 /* For the KVM GICv3, affinity routing is always enabled, and the
278 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/
279 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding
280 * functionality is replaced by the GICR registers. It doesn't need to sync
281 * them. So it should increase the offset and clroffset to skip GIC_INTERNAL
282 * irqs. This matches the for_each_dist_irq_reg() macro which also skips the
283 * first GIC_INTERNAL irqs.
285 offset
+= (GIC_INTERNAL
* 1) / 8;
286 if (clroffset
!= 0) {
287 clroffset
+= (GIC_INTERNAL
* 1) / 8;
290 for_each_dist_irq_reg(irq
, s
->num_irq
, 1) {
291 /* If this bitmap is a set/clear register pair, first write to the
292 * clear-reg to clear all bits before using the set-reg to write
295 if (clroffset
!= 0) {
297 kvm_gicd_access(s
, clroffset
, ®
, true);
300 reg
= *gic_bmp_ptr32(bmp
, irq
);
301 kvm_gicd_access(s
, offset
, ®
, true);
306 static void kvm_arm_gicv3_check(GICv3State
*s
)
311 /* Sanity checking s->num_irq */
312 kvm_gicd_access(s
, GICD_TYPER
, ®
, false);
313 num_irq
= ((reg
& 0x1f) + 1) * 32;
315 if (num_irq
< s
->num_irq
) {
316 error_report("Model requests %u IRQs, but kernel supports max %u",
317 s
->num_irq
, num_irq
);
322 static void kvm_arm_gicv3_put(GICv3State
*s
)
324 uint32_t regl
, regh
, reg
;
325 uint64_t reg64
, redist_typer
;
328 kvm_arm_gicv3_check(s
);
330 kvm_gicr_access(s
, GICR_TYPER
, 0, ®l
, false);
331 kvm_gicr_access(s
, GICR_TYPER
+ 4, 0, ®h
, false);
332 redist_typer
= ((uint64_t)regh
<< 32) | regl
;
335 kvm_gicd_access(s
, GICD_CTLR
, ®
, true);
337 if (redist_typer
& GICR_TYPER_PLPIS
) {
338 /* Set base addresses before LPIs are enabled by GICR_CTLR write */
339 for (ncpu
= 0; ncpu
< s
->num_cpu
; ncpu
++) {
340 GICv3CPUState
*c
= &s
->cpu
[ncpu
];
342 reg64
= c
->gicr_propbaser
;
343 regl
= (uint32_t)reg64
;
344 kvm_gicr_access(s
, GICR_PROPBASER
, ncpu
, ®l
, true);
345 regh
= (uint32_t)(reg64
>> 32);
346 kvm_gicr_access(s
, GICR_PROPBASER
+ 4, ncpu
, ®h
, true);
348 reg64
= c
->gicr_pendbaser
;
349 if (!(c
->gicr_ctlr
& GICR_CTLR_ENABLE_LPIS
)) {
350 /* Setting PTZ is advised if LPIs are disabled, to reduce
351 * GIC initialization time.
353 reg64
|= GICR_PENDBASER_PTZ
;
355 regl
= (uint32_t)reg64
;
356 kvm_gicr_access(s
, GICR_PENDBASER
, ncpu
, ®l
, true);
357 regh
= (uint32_t)(reg64
>> 32);
358 kvm_gicr_access(s
, GICR_PENDBASER
+ 4, ncpu
, ®h
, true);
362 /* Redistributor state (one per CPU) */
364 for (ncpu
= 0; ncpu
< s
->num_cpu
; ncpu
++) {
365 GICv3CPUState
*c
= &s
->cpu
[ncpu
];
368 kvm_gicr_access(s
, GICR_CTLR
, ncpu
, ®
, true);
370 reg
= c
->gicr_statusr
[GICV3_NS
];
371 kvm_gicr_access(s
, GICR_STATUSR
, ncpu
, ®
, true);
374 kvm_gicr_access(s
, GICR_WAKER
, ncpu
, ®
, true);
376 reg
= c
->gicr_igroupr0
;
377 kvm_gicr_access(s
, GICR_IGROUPR0
, ncpu
, ®
, true);
380 kvm_gicr_access(s
, GICR_ICENABLER0
, ncpu
, ®
, true);
381 reg
= c
->gicr_ienabler0
;
382 kvm_gicr_access(s
, GICR_ISENABLER0
, ncpu
, ®
, true);
384 /* Restore config before pending so we treat level/edge correctly */
385 reg
= half_shuffle32(c
->edge_trigger
>> 16) << 1;
386 kvm_gicr_access(s
, GICR_ICFGR1
, ncpu
, ®
, true);
389 kvm_gic_line_level_access(s
, 0, ncpu
, ®
, true);
392 kvm_gicr_access(s
, GICR_ICPENDR0
, ncpu
, ®
, true);
393 reg
= c
->gicr_ipendr0
;
394 kvm_gicr_access(s
, GICR_ISPENDR0
, ncpu
, ®
, true);
397 kvm_gicr_access(s
, GICR_ICACTIVER0
, ncpu
, ®
, true);
398 reg
= c
->gicr_iactiver0
;
399 kvm_gicr_access(s
, GICR_ISACTIVER0
, ncpu
, ®
, true);
401 for (i
= 0; i
< GIC_INTERNAL
; i
+= 4) {
402 reg
= c
->gicr_ipriorityr
[i
] |
403 (c
->gicr_ipriorityr
[i
+ 1] << 8) |
404 (c
->gicr_ipriorityr
[i
+ 2] << 16) |
405 (c
->gicr_ipriorityr
[i
+ 3] << 24);
406 kvm_gicr_access(s
, GICR_IPRIORITYR
+ i
, ncpu
, ®
, true);
410 /* Distributor state (shared between all CPUs */
411 reg
= s
->gicd_statusr
[GICV3_NS
];
412 kvm_gicd_access(s
, GICD_STATUSR
, ®
, true);
414 /* s->enable bitmap -> GICD_ISENABLERn */
415 kvm_dist_putbmp(s
, GICD_ISENABLER
, GICD_ICENABLER
, s
->enabled
);
417 /* s->group bitmap -> GICD_IGROUPRn */
418 kvm_dist_putbmp(s
, GICD_IGROUPR
, 0, s
->group
);
420 /* Restore targets before pending to ensure the pending state is set on
421 * the appropriate CPU interfaces in the kernel
424 /* s->gicd_irouter[irq] -> GICD_IROUTERn
425 * We can't use kvm_dist_put() here because the registers are 64-bit
427 for (i
= GIC_INTERNAL
; i
< s
->num_irq
; i
++) {
430 offset
= GICD_IROUTER
+ (sizeof(uint32_t) * i
);
431 reg
= (uint32_t)s
->gicd_irouter
[i
];
432 kvm_gicd_access(s
, offset
, ®
, true);
434 offset
= GICD_IROUTER
+ (sizeof(uint32_t) * i
) + 4;
435 reg
= (uint32_t)(s
->gicd_irouter
[i
] >> 32);
436 kvm_gicd_access(s
, offset
, ®
, true);
439 /* s->trigger bitmap -> GICD_ICFGRn
440 * (restore configuration registers before pending IRQs so we treat
441 * level/edge correctly)
443 kvm_dist_put_edge_trigger(s
, GICD_ICFGR
, s
->edge_trigger
);
445 /* s->level bitmap -> line_level */
446 kvm_gic_put_line_level_bmp(s
, s
->level
);
448 /* s->pending bitmap -> GICD_ISPENDRn */
449 kvm_dist_putbmp(s
, GICD_ISPENDR
, GICD_ICPENDR
, s
->pending
);
451 /* s->active bitmap -> GICD_ISACTIVERn */
452 kvm_dist_putbmp(s
, GICD_ISACTIVER
, GICD_ICACTIVER
, s
->active
);
454 /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */
455 kvm_dist_put_priority(s
, GICD_IPRIORITYR
, s
->gicd_ipriority
);
457 /* CPU Interface state (one per CPU) */
459 for (ncpu
= 0; ncpu
< s
->num_cpu
; ncpu
++) {
460 GICv3CPUState
*c
= &s
->cpu
[ncpu
];
463 kvm_gicc_access(s
, ICC_SRE_EL1
, ncpu
, &c
->icc_sre_el1
, true);
464 kvm_gicc_access(s
, ICC_CTLR_EL1
, ncpu
,
465 &c
->icc_ctlr_el1
[GICV3_NS
], true);
466 kvm_gicc_access(s
, ICC_IGRPEN0_EL1
, ncpu
,
467 &c
->icc_igrpen
[GICV3_G0
], true);
468 kvm_gicc_access(s
, ICC_IGRPEN1_EL1
, ncpu
,
469 &c
->icc_igrpen
[GICV3_G1NS
], true);
470 kvm_gicc_access(s
, ICC_PMR_EL1
, ncpu
, &c
->icc_pmr_el1
, true);
471 kvm_gicc_access(s
, ICC_BPR0_EL1
, ncpu
, &c
->icc_bpr
[GICV3_G0
], true);
472 kvm_gicc_access(s
, ICC_BPR1_EL1
, ncpu
, &c
->icc_bpr
[GICV3_G1NS
], true);
474 num_pri_bits
= ((c
->icc_ctlr_el1
[GICV3_NS
] &
475 ICC_CTLR_EL1_PRIBITS_MASK
) >>
476 ICC_CTLR_EL1_PRIBITS_SHIFT
) + 1;
478 switch (num_pri_bits
) {
480 reg64
= c
->icc_apr
[GICV3_G0
][3];
481 kvm_gicc_access(s
, ICC_AP0R_EL1(3), ncpu
, ®64
, true);
482 reg64
= c
->icc_apr
[GICV3_G0
][2];
483 kvm_gicc_access(s
, ICC_AP0R_EL1(2), ncpu
, ®64
, true);
485 reg64
= c
->icc_apr
[GICV3_G0
][1];
486 kvm_gicc_access(s
, ICC_AP0R_EL1(1), ncpu
, ®64
, true);
488 reg64
= c
->icc_apr
[GICV3_G0
][0];
489 kvm_gicc_access(s
, ICC_AP0R_EL1(0), ncpu
, ®64
, true);
492 switch (num_pri_bits
) {
494 reg64
= c
->icc_apr
[GICV3_G1NS
][3];
495 kvm_gicc_access(s
, ICC_AP1R_EL1(3), ncpu
, ®64
, true);
496 reg64
= c
->icc_apr
[GICV3_G1NS
][2];
497 kvm_gicc_access(s
, ICC_AP1R_EL1(2), ncpu
, ®64
, true);
499 reg64
= c
->icc_apr
[GICV3_G1NS
][1];
500 kvm_gicc_access(s
, ICC_AP1R_EL1(1), ncpu
, ®64
, true);
502 reg64
= c
->icc_apr
[GICV3_G1NS
][0];
503 kvm_gicc_access(s
, ICC_AP1R_EL1(0), ncpu
, ®64
, true);
508 static void kvm_arm_gicv3_get(GICv3State
*s
)
510 uint32_t regl
, regh
, reg
;
511 uint64_t reg64
, redist_typer
;
514 kvm_arm_gicv3_check(s
);
516 kvm_gicr_access(s
, GICR_TYPER
, 0, ®l
, false);
517 kvm_gicr_access(s
, GICR_TYPER
+ 4, 0, ®h
, false);
518 redist_typer
= ((uint64_t)regh
<< 32) | regl
;
520 kvm_gicd_access(s
, GICD_CTLR
, ®
, false);
523 /* Redistributor state (one per CPU) */
525 for (ncpu
= 0; ncpu
< s
->num_cpu
; ncpu
++) {
526 GICv3CPUState
*c
= &s
->cpu
[ncpu
];
528 kvm_gicr_access(s
, GICR_CTLR
, ncpu
, ®
, false);
531 kvm_gicr_access(s
, GICR_STATUSR
, ncpu
, ®
, false);
532 c
->gicr_statusr
[GICV3_NS
] = reg
;
534 kvm_gicr_access(s
, GICR_WAKER
, ncpu
, ®
, false);
537 kvm_gicr_access(s
, GICR_IGROUPR0
, ncpu
, ®
, false);
538 c
->gicr_igroupr0
= reg
;
539 kvm_gicr_access(s
, GICR_ISENABLER0
, ncpu
, ®
, false);
540 c
->gicr_ienabler0
= reg
;
541 kvm_gicr_access(s
, GICR_ICFGR1
, ncpu
, ®
, false);
542 c
->edge_trigger
= half_unshuffle32(reg
>> 1) << 16;
543 kvm_gic_line_level_access(s
, 0, ncpu
, ®
, false);
545 kvm_gicr_access(s
, GICR_ISPENDR0
, ncpu
, ®
, false);
546 c
->gicr_ipendr0
= reg
;
547 kvm_gicr_access(s
, GICR_ISACTIVER0
, ncpu
, ®
, false);
548 c
->gicr_iactiver0
= reg
;
550 for (i
= 0; i
< GIC_INTERNAL
; i
+= 4) {
551 kvm_gicr_access(s
, GICR_IPRIORITYR
+ i
, ncpu
, ®
, false);
552 c
->gicr_ipriorityr
[i
] = extract32(reg
, 0, 8);
553 c
->gicr_ipriorityr
[i
+ 1] = extract32(reg
, 8, 8);
554 c
->gicr_ipriorityr
[i
+ 2] = extract32(reg
, 16, 8);
555 c
->gicr_ipriorityr
[i
+ 3] = extract32(reg
, 24, 8);
559 if (redist_typer
& GICR_TYPER_PLPIS
) {
560 for (ncpu
= 0; ncpu
< s
->num_cpu
; ncpu
++) {
561 GICv3CPUState
*c
= &s
->cpu
[ncpu
];
563 kvm_gicr_access(s
, GICR_PROPBASER
, ncpu
, ®l
, false);
564 kvm_gicr_access(s
, GICR_PROPBASER
+ 4, ncpu
, ®h
, false);
565 c
->gicr_propbaser
= ((uint64_t)regh
<< 32) | regl
;
567 kvm_gicr_access(s
, GICR_PENDBASER
, ncpu
, ®l
, false);
568 kvm_gicr_access(s
, GICR_PENDBASER
+ 4, ncpu
, ®h
, false);
569 c
->gicr_pendbaser
= ((uint64_t)regh
<< 32) | regl
;
573 /* Distributor state (shared between all CPUs */
575 kvm_gicd_access(s
, GICD_STATUSR
, ®
, false);
576 s
->gicd_statusr
[GICV3_NS
] = reg
;
578 /* GICD_IGROUPRn -> s->group bitmap */
579 kvm_dist_getbmp(s
, GICD_IGROUPR
, s
->group
);
581 /* GICD_ISENABLERn -> s->enabled bitmap */
582 kvm_dist_getbmp(s
, GICD_ISENABLER
, s
->enabled
);
584 /* Line level of irq */
585 kvm_gic_get_line_level_bmp(s
, s
->level
);
586 /* GICD_ISPENDRn -> s->pending bitmap */
587 kvm_dist_getbmp(s
, GICD_ISPENDR
, s
->pending
);
589 /* GICD_ISACTIVERn -> s->active bitmap */
590 kvm_dist_getbmp(s
, GICD_ISACTIVER
, s
->active
);
592 /* GICD_ICFGRn -> s->trigger bitmap */
593 kvm_dist_get_edge_trigger(s
, GICD_ICFGR
, s
->edge_trigger
);
595 /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */
596 kvm_dist_get_priority(s
, GICD_IPRIORITYR
, s
->gicd_ipriority
);
598 /* GICD_IROUTERn -> s->gicd_irouter[irq] */
599 for (i
= GIC_INTERNAL
; i
< s
->num_irq
; i
++) {
602 offset
= GICD_IROUTER
+ (sizeof(uint32_t) * i
);
603 kvm_gicd_access(s
, offset
, ®l
, false);
604 offset
= GICD_IROUTER
+ (sizeof(uint32_t) * i
) + 4;
605 kvm_gicd_access(s
, offset
, ®h
, false);
606 s
->gicd_irouter
[i
] = ((uint64_t)regh
<< 32) | regl
;
609 /*****************************************************************
610 * CPU Interface(s) State
613 for (ncpu
= 0; ncpu
< s
->num_cpu
; ncpu
++) {
614 GICv3CPUState
*c
= &s
->cpu
[ncpu
];
617 kvm_gicc_access(s
, ICC_SRE_EL1
, ncpu
, &c
->icc_sre_el1
, false);
618 kvm_gicc_access(s
, ICC_CTLR_EL1
, ncpu
,
619 &c
->icc_ctlr_el1
[GICV3_NS
], false);
620 kvm_gicc_access(s
, ICC_IGRPEN0_EL1
, ncpu
,
621 &c
->icc_igrpen
[GICV3_G0
], false);
622 kvm_gicc_access(s
, ICC_IGRPEN1_EL1
, ncpu
,
623 &c
->icc_igrpen
[GICV3_G1NS
], false);
624 kvm_gicc_access(s
, ICC_PMR_EL1
, ncpu
, &c
->icc_pmr_el1
, false);
625 kvm_gicc_access(s
, ICC_BPR0_EL1
, ncpu
, &c
->icc_bpr
[GICV3_G0
], false);
626 kvm_gicc_access(s
, ICC_BPR1_EL1
, ncpu
, &c
->icc_bpr
[GICV3_G1NS
], false);
627 num_pri_bits
= ((c
->icc_ctlr_el1
[GICV3_NS
] &
628 ICC_CTLR_EL1_PRIBITS_MASK
) >>
629 ICC_CTLR_EL1_PRIBITS_SHIFT
) + 1;
631 switch (num_pri_bits
) {
633 kvm_gicc_access(s
, ICC_AP0R_EL1(3), ncpu
, ®64
, false);
634 c
->icc_apr
[GICV3_G0
][3] = reg64
;
635 kvm_gicc_access(s
, ICC_AP0R_EL1(2), ncpu
, ®64
, false);
636 c
->icc_apr
[GICV3_G0
][2] = reg64
;
638 kvm_gicc_access(s
, ICC_AP0R_EL1(1), ncpu
, ®64
, false);
639 c
->icc_apr
[GICV3_G0
][1] = reg64
;
641 kvm_gicc_access(s
, ICC_AP0R_EL1(0), ncpu
, ®64
, false);
642 c
->icc_apr
[GICV3_G0
][0] = reg64
;
645 switch (num_pri_bits
) {
647 kvm_gicc_access(s
, ICC_AP1R_EL1(3), ncpu
, ®64
, false);
648 c
->icc_apr
[GICV3_G1NS
][3] = reg64
;
649 kvm_gicc_access(s
, ICC_AP1R_EL1(2), ncpu
, ®64
, false);
650 c
->icc_apr
[GICV3_G1NS
][2] = reg64
;
652 kvm_gicc_access(s
, ICC_AP1R_EL1(1), ncpu
, ®64
, false);
653 c
->icc_apr
[GICV3_G1NS
][1] = reg64
;
655 kvm_gicc_access(s
, ICC_AP1R_EL1(0), ncpu
, ®64
, false);
656 c
->icc_apr
[GICV3_G1NS
][0] = reg64
;
661 static void arm_gicv3_icc_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
667 c
= (GICv3CPUState
*)env
->gicv3state
;
669 cpu
= ARM_CPU(c
->cpu
);
672 c
->icc_bpr
[GICV3_G0
] = GIC_MIN_BPR
;
673 c
->icc_bpr
[GICV3_G1
] = GIC_MIN_BPR
;
674 c
->icc_bpr
[GICV3_G1NS
] = GIC_MIN_BPR
;
676 c
->icc_sre_el1
= 0x7;
677 memset(c
->icc_apr
, 0, sizeof(c
->icc_apr
));
678 memset(c
->icc_igrpen
, 0, sizeof(c
->icc_igrpen
));
680 if (s
->migration_blocker
) {
684 /* Initialize to actual HW supported configuration */
685 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS
,
686 KVM_VGIC_ATTR(ICC_CTLR_EL1
, cpu
->mp_affinity
),
687 &c
->icc_ctlr_el1
[GICV3_NS
], false, &error_abort
);
689 c
->icc_ctlr_el1
[GICV3_S
] = c
->icc_ctlr_el1
[GICV3_NS
];
692 static void kvm_arm_gicv3_reset(DeviceState
*dev
)
694 GICv3State
*s
= ARM_GICV3_COMMON(dev
);
695 KVMARMGICv3Class
*kgc
= KVM_ARM_GICV3_GET_CLASS(s
);
699 kgc
->parent_reset(dev
);
701 if (s
->migration_blocker
) {
702 DPRINTF("Cannot put kernel gic state, no kernel interface\n");
706 kvm_arm_gicv3_put(s
);
710 * CPU interface registers of GIC needs to be reset on CPU reset.
711 * For the calling arm_gicv3_icc_reset() on CPU reset, we register
712 * below ARMCPRegInfo. As we reset the whole cpu interface under single
713 * register reset, we define only one register of CPU interface instead
714 * of defining all the registers.
716 static const ARMCPRegInfo gicv3_cpuif_reginfo
[] = {
717 { .name
= "ICC_CTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
718 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 4,
720 * If ARM_CP_NOP is used, resetfn is not called,
721 * So ARM_CP_NO_RAW is appropriate type.
723 .type
= ARM_CP_NO_RAW
,
725 .readfn
= arm_cp_read_zero
,
726 .writefn
= arm_cp_write_ignore
,
728 * We hang the whole cpu interface reset routine off here
729 * rather than parcelling it out into one little function
732 .resetfn
= arm_gicv3_icc_reset
,
738 * vm_change_state_handler - VM change state callback aiming at flushing
739 * RDIST pending tables into guest RAM
741 * The tables get flushed to guest RAM whenever the VM gets stopped.
743 static void vm_change_state_handler(void *opaque
, int running
,
746 GICv3State
*s
= (GICv3State
*)opaque
;
754 ret
= kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CTRL
,
755 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
,
758 error_report_err(err
);
760 if (ret
< 0 && ret
!= -EFAULT
) {
766 static void kvm_arm_gicv3_realize(DeviceState
*dev
, Error
**errp
)
768 GICv3State
*s
= KVM_ARM_GICV3(dev
);
769 KVMARMGICv3Class
*kgc
= KVM_ARM_GICV3_GET_CLASS(s
);
770 Error
*local_err
= NULL
;
773 DPRINTF("kvm_arm_gicv3_realize\n");
775 kgc
->parent_realize(dev
, &local_err
);
777 error_propagate(errp
, local_err
);
781 if (s
->security_extn
) {
782 error_setg(errp
, "the in-kernel VGICv3 does not implement the "
783 "security extensions");
787 gicv3_init_irqs_and_mmio(s
, kvm_arm_gicv3_set_irq
, NULL
);
789 for (i
= 0; i
< s
->num_cpu
; i
++) {
790 ARMCPU
*cpu
= ARM_CPU(qemu_get_cpu(i
));
792 define_arm_cp_regs(cpu
, gicv3_cpuif_reginfo
);
795 /* Try to create the device via the device control API */
796 s
->dev_fd
= kvm_create_device(kvm_state
, KVM_DEV_TYPE_ARM_VGIC_V3
, false);
798 error_setg_errno(errp
, -s
->dev_fd
, "error creating in-kernel VGIC");
802 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_NR_IRQS
,
803 0, &s
->num_irq
, true, &error_abort
);
805 /* Tell the kernel to complete VGIC initialization now */
806 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CTRL
,
807 KVM_DEV_ARM_VGIC_CTRL_INIT
, NULL
, true, &error_abort
);
809 kvm_arm_register_device(&s
->iomem_dist
, -1, KVM_DEV_ARM_VGIC_GRP_ADDR
,
810 KVM_VGIC_V3_ADDR_TYPE_DIST
, s
->dev_fd
);
811 kvm_arm_register_device(&s
->iomem_redist
, -1, KVM_DEV_ARM_VGIC_GRP_ADDR
,
812 KVM_VGIC_V3_ADDR_TYPE_REDIST
, s
->dev_fd
);
814 if (kvm_has_gsi_routing()) {
815 /* set up irq routing */
816 for (i
= 0; i
< s
->num_irq
- GIC_INTERNAL
; ++i
) {
817 kvm_irqchip_add_irq_route(kvm_state
, i
, 0, i
);
820 kvm_gsi_routing_allowed
= true;
822 kvm_irqchip_commit_routes(kvm_state
);
825 if (!kvm_device_check_attr(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_DIST_REGS
,
827 error_setg(&s
->migration_blocker
, "This operating system kernel does "
828 "not support vGICv3 migration");
829 migrate_add_blocker(s
->migration_blocker
, &local_err
);
831 error_propagate(errp
, local_err
);
832 error_free(s
->migration_blocker
);
836 if (kvm_device_check_attr(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CTRL
,
837 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
)) {
838 qemu_add_vm_change_state_handler(vm_change_state_handler
, s
);
842 static void kvm_arm_gicv3_class_init(ObjectClass
*klass
, void *data
)
844 DeviceClass
*dc
= DEVICE_CLASS(klass
);
845 ARMGICv3CommonClass
*agcc
= ARM_GICV3_COMMON_CLASS(klass
);
846 KVMARMGICv3Class
*kgc
= KVM_ARM_GICV3_CLASS(klass
);
848 agcc
->pre_save
= kvm_arm_gicv3_get
;
849 agcc
->post_load
= kvm_arm_gicv3_put
;
850 device_class_set_parent_realize(dc
, kvm_arm_gicv3_realize
,
851 &kgc
->parent_realize
);
852 device_class_set_parent_reset(dc
, kvm_arm_gicv3_reset
, &kgc
->parent_reset
);
855 static const TypeInfo kvm_arm_gicv3_info
= {
856 .name
= TYPE_KVM_ARM_GICV3
,
857 .parent
= TYPE_ARM_GICV3_COMMON
,
858 .instance_size
= sizeof(GICv3State
),
859 .class_init
= kvm_arm_gicv3_class_init
,
860 .class_size
= sizeof(KVMARMGICv3Class
),
863 static void kvm_arm_gicv3_register_types(void)
865 type_register_static(&kvm_arm_gicv3_info
);
868 type_init(kvm_arm_gicv3_register_types
)