2 * UniCore32 translation
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or (at your option) any
9 * later version. See the COPYING file in the top-level directory.
11 #include "qemu/osdep.h"
14 #include "disas/disas.h"
15 #include "exec/exec-all.h"
18 #include "exec/cpu_ldst.h"
20 #include "exec/helper-proto.h"
21 #include "exec/helper-gen.h"
23 #include "trace-tcg.h"
27 /* internal defines */
28 typedef struct DisasContext
{
31 /* Nonzero if this instruction has been conditionally skipped. */
33 /* The label that will be jumped to when the instruction is skipped. */
35 struct TranslationBlock
*tb
;
36 int singlestep_enabled
;
37 #ifndef CONFIG_USER_ONLY
42 #ifndef CONFIG_USER_ONLY
43 #define IS_USER(s) (s->user)
48 /* These instructions trap after executing, so defer them until after the
49 conditional executions state has been updated. */
50 #define DISAS_SYSCALL 5
52 static TCGv_env cpu_env
;
53 static TCGv_i32 cpu_R
[32];
55 /* FIXME: These should be removed. */
56 static TCGv cpu_F0s
, cpu_F1s
;
57 static TCGv_i64 cpu_F0d
, cpu_F1d
;
59 #include "exec/gen-icount.h"
61 static const char *regnames
[] = {
62 "r00", "r01", "r02", "r03", "r04", "r05", "r06", "r07",
63 "r08", "r09", "r10", "r11", "r12", "r13", "r14", "r15",
64 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
65 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "pc" };
67 /* initialize TCG globals. */
68 void uc32_translate_init(void)
72 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
73 tcg_ctx
.tcg_env
= cpu_env
;
75 for (i
= 0; i
< 32; i
++) {
76 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
77 offsetof(CPUUniCore32State
, regs
[i
]), regnames
[i
]);
83 /* Allocate a temporary variable. */
84 static TCGv_i32
new_tmp(void)
87 return tcg_temp_new_i32();
90 /* Release a temporary variable. */
91 static void dead_tmp(TCGv tmp
)
97 static inline TCGv
load_cpu_offset(int offset
)
100 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
104 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUUniCore32State, name))
106 static inline void store_cpu_offset(TCGv var
, int offset
)
108 tcg_gen_st_i32(var
, cpu_env
, offset
);
112 #define store_cpu_field(var, name) \
113 store_cpu_offset(var, offsetof(CPUUniCore32State, name))
115 /* Set a variable to the value of a CPU register. */
116 static void load_reg_var(DisasContext
*s
, TCGv var
, int reg
)
120 /* normaly, since we updated PC */
122 tcg_gen_movi_i32(var
, addr
);
124 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
128 /* Create a new temporary and set it to the value of a CPU register. */
129 static inline TCGv
load_reg(DisasContext
*s
, int reg
)
131 TCGv tmp
= new_tmp();
132 load_reg_var(s
, tmp
, reg
);
136 /* Set a CPU register. The source must be a temporary and will be
138 static void store_reg(DisasContext
*s
, int reg
, TCGv var
)
141 tcg_gen_andi_i32(var
, var
, ~3);
142 s
->is_jmp
= DISAS_JUMP
;
144 tcg_gen_mov_i32(cpu_R
[reg
], var
);
148 /* Value extensions. */
149 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
150 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
151 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
152 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
154 #define UCOP_REG_M (((insn) >> 0) & 0x1f)
155 #define UCOP_REG_N (((insn) >> 19) & 0x1f)
156 #define UCOP_REG_D (((insn) >> 14) & 0x1f)
157 #define UCOP_REG_S (((insn) >> 9) & 0x1f)
158 #define UCOP_REG_LO (((insn) >> 14) & 0x1f)
159 #define UCOP_REG_HI (((insn) >> 9) & 0x1f)
160 #define UCOP_SH_OP (((insn) >> 6) & 0x03)
161 #define UCOP_SH_IM (((insn) >> 9) & 0x1f)
162 #define UCOP_OPCODES (((insn) >> 25) & 0x0f)
163 #define UCOP_IMM_9 (((insn) >> 0) & 0x1ff)
164 #define UCOP_IMM10 (((insn) >> 0) & 0x3ff)
165 #define UCOP_IMM14 (((insn) >> 0) & 0x3fff)
166 #define UCOP_COND (((insn) >> 25) & 0x0f)
167 #define UCOP_CMOV_COND (((insn) >> 19) & 0x0f)
168 #define UCOP_CPNUM (((insn) >> 10) & 0x0f)
169 #define UCOP_UCF64_FMT (((insn) >> 24) & 0x03)
170 #define UCOP_UCF64_FUNC (((insn) >> 6) & 0x0f)
171 #define UCOP_UCF64_COND (((insn) >> 6) & 0x0f)
173 #define UCOP_SET(i) ((insn) & (1 << (i)))
174 #define UCOP_SET_P UCOP_SET(28)
175 #define UCOP_SET_U UCOP_SET(27)
176 #define UCOP_SET_B UCOP_SET(26)
177 #define UCOP_SET_W UCOP_SET(25)
178 #define UCOP_SET_L UCOP_SET(24)
179 #define UCOP_SET_S UCOP_SET(24)
181 #define ILLEGAL cpu_abort(CPU(cpu), \
182 "Illegal UniCore32 instruction %x at line %d!", \
185 #ifndef CONFIG_USER_ONLY
186 static void disas_cp0_insn(CPUUniCore32State
*env
, DisasContext
*s
,
189 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
190 TCGv tmp
, tmp2
, tmp3
;
191 if ((insn
& 0xfe000000) == 0xe0000000) {
194 tcg_gen_movi_i32(tmp2
, UCOP_REG_N
);
195 tcg_gen_movi_i32(tmp3
, UCOP_IMM10
);
198 gen_helper_cp0_get(tmp
, cpu_env
, tmp2
, tmp3
);
199 store_reg(s
, UCOP_REG_D
, tmp
);
201 tmp
= load_reg(s
, UCOP_REG_D
);
202 gen_helper_cp0_set(cpu_env
, tmp
, tmp2
, tmp3
);
212 static void disas_ocd_insn(CPUUniCore32State
*env
, DisasContext
*s
,
215 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
218 if ((insn
& 0xff003fff) == 0xe1000400) {
220 * movc rd, pp.nn, #imm9
222 * nn: UCOP_REG_N (must be 0)
225 if (UCOP_REG_N
== 0) {
227 tcg_gen_movi_i32(tmp
, 0);
228 store_reg(s
, UCOP_REG_D
, tmp
);
234 if ((insn
& 0xff003fff) == 0xe0000401) {
236 * movc pp.nn, rn, #imm9
238 * nn: UCOP_REG_N (must be 1)
241 if (UCOP_REG_N
== 1) {
242 tmp
= load_reg(s
, UCOP_REG_D
);
243 gen_helper_cp1_putc(tmp
);
254 static inline void gen_set_asr(TCGv var
, uint32_t mask
)
256 TCGv tmp_mask
= tcg_const_i32(mask
);
257 gen_helper_asr_write(cpu_env
, var
, tmp_mask
);
258 tcg_temp_free_i32(tmp_mask
);
260 /* Set NZCV flags from the high 4 bits of var. */
261 #define gen_set_nzcv(var) gen_set_asr(var, ASR_NZCV)
263 static void gen_exception(int excp
)
265 TCGv tmp
= new_tmp();
266 tcg_gen_movi_i32(tmp
, excp
);
267 gen_helper_exception(cpu_env
, tmp
);
271 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, CF))
273 /* Set CF to the top bit of var. */
274 static void gen_set_CF_bit31(TCGv var
)
276 TCGv tmp
= new_tmp();
277 tcg_gen_shri_i32(tmp
, var
, 31);
282 /* Set N and Z flags from var. */
283 static inline void gen_logic_CC(TCGv var
)
285 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUUniCore32State
, NF
));
286 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUUniCore32State
, ZF
));
289 /* dest = T0 + T1 + CF. */
290 static void gen_add_carry(TCGv dest
, TCGv t0
, TCGv t1
)
293 tcg_gen_add_i32(dest
, t0
, t1
);
294 tmp
= load_cpu_field(CF
);
295 tcg_gen_add_i32(dest
, dest
, tmp
);
299 /* dest = T0 - T1 + CF - 1. */
300 static void gen_sub_carry(TCGv dest
, TCGv t0
, TCGv t1
)
303 tcg_gen_sub_i32(dest
, t0
, t1
);
304 tmp
= load_cpu_field(CF
);
305 tcg_gen_add_i32(dest
, dest
, tmp
);
306 tcg_gen_subi_i32(dest
, dest
, 1);
310 static void shifter_out_im(TCGv var
, int shift
)
312 TCGv tmp
= new_tmp();
314 tcg_gen_andi_i32(tmp
, var
, 1);
316 tcg_gen_shri_i32(tmp
, var
, shift
);
318 tcg_gen_andi_i32(tmp
, tmp
, 1);
325 /* Shift by immediate. Includes special handling for shift == 0. */
326 static inline void gen_uc32_shift_im(TCGv var
, int shiftop
, int shift
,
333 shifter_out_im(var
, 32 - shift
);
335 tcg_gen_shli_i32(var
, var
, shift
);
341 tcg_gen_shri_i32(var
, var
, 31);
344 tcg_gen_movi_i32(var
, 0);
347 shifter_out_im(var
, shift
- 1);
349 tcg_gen_shri_i32(var
, var
, shift
);
357 shifter_out_im(var
, shift
- 1);
362 tcg_gen_sari_i32(var
, var
, shift
);
364 case 3: /* ROR/RRX */
367 shifter_out_im(var
, shift
- 1);
369 tcg_gen_rotri_i32(var
, var
, shift
); break;
371 TCGv tmp
= load_cpu_field(CF
);
373 shifter_out_im(var
, 0);
375 tcg_gen_shri_i32(var
, var
, 1);
376 tcg_gen_shli_i32(tmp
, tmp
, 31);
377 tcg_gen_or_i32(var
, var
, tmp
);
383 static inline void gen_uc32_shift_reg(TCGv var
, int shiftop
,
384 TCGv shift
, int flags
)
389 gen_helper_shl_cc(var
, cpu_env
, var
, shift
);
392 gen_helper_shr_cc(var
, cpu_env
, var
, shift
);
395 gen_helper_sar_cc(var
, cpu_env
, var
, shift
);
398 gen_helper_ror_cc(var
, cpu_env
, var
, shift
);
404 gen_helper_shl(var
, var
, shift
);
407 gen_helper_shr(var
, var
, shift
);
410 gen_helper_sar(var
, var
, shift
);
413 tcg_gen_andi_i32(shift
, shift
, 0x1f);
414 tcg_gen_rotr_i32(var
, var
, shift
);
421 static void gen_test_cc(int cc
, TCGLabel
*label
)
429 tmp
= load_cpu_field(ZF
);
430 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
433 tmp
= load_cpu_field(ZF
);
434 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
437 tmp
= load_cpu_field(CF
);
438 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
441 tmp
= load_cpu_field(CF
);
442 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
445 tmp
= load_cpu_field(NF
);
446 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
449 tmp
= load_cpu_field(NF
);
450 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
453 tmp
= load_cpu_field(VF
);
454 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
457 tmp
= load_cpu_field(VF
);
458 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
460 case 8: /* hi: C && !Z */
461 inv
= gen_new_label();
462 tmp
= load_cpu_field(CF
);
463 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
465 tmp
= load_cpu_field(ZF
);
466 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
469 case 9: /* ls: !C || Z */
470 tmp
= load_cpu_field(CF
);
471 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
473 tmp
= load_cpu_field(ZF
);
474 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
476 case 10: /* ge: N == V -> N ^ V == 0 */
477 tmp
= load_cpu_field(VF
);
478 tmp2
= load_cpu_field(NF
);
479 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
481 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
483 case 11: /* lt: N != V -> N ^ V != 0 */
484 tmp
= load_cpu_field(VF
);
485 tmp2
= load_cpu_field(NF
);
486 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
488 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
490 case 12: /* gt: !Z && N == V */
491 inv
= gen_new_label();
492 tmp
= load_cpu_field(ZF
);
493 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
495 tmp
= load_cpu_field(VF
);
496 tmp2
= load_cpu_field(NF
);
497 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
499 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
502 case 13: /* le: Z || N != V */
503 tmp
= load_cpu_field(ZF
);
504 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
506 tmp
= load_cpu_field(VF
);
507 tmp2
= load_cpu_field(NF
);
508 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
510 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
513 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
519 static const uint8_t table_logic_cc
[16] = {
520 1, /* and */ 1, /* xor */ 0, /* sub */ 0, /* rsb */
521 0, /* add */ 0, /* adc */ 0, /* sbc */ 0, /* rsc */
522 1, /* andl */ 1, /* xorl */ 0, /* cmp */ 0, /* cmn */
523 1, /* orr */ 1, /* mov */ 1, /* bic */ 1, /* mvn */
526 /* Set PC state from an immediate address. */
527 static inline void gen_bx_im(DisasContext
*s
, uint32_t addr
)
529 s
->is_jmp
= DISAS_UPDATE
;
530 tcg_gen_movi_i32(cpu_R
[31], addr
& ~3);
533 /* Set PC state from var. var is marked as dead. */
534 static inline void gen_bx(DisasContext
*s
, TCGv var
)
536 s
->is_jmp
= DISAS_UPDATE
;
537 tcg_gen_andi_i32(cpu_R
[31], var
, ~3);
541 static inline void store_reg_bx(DisasContext
*s
, int reg
, TCGv var
)
543 store_reg(s
, reg
, var
);
546 static inline TCGv
gen_ld8s(TCGv addr
, int index
)
548 TCGv tmp
= new_tmp();
549 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
553 static inline TCGv
gen_ld8u(TCGv addr
, int index
)
555 TCGv tmp
= new_tmp();
556 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
560 static inline TCGv
gen_ld16s(TCGv addr
, int index
)
562 TCGv tmp
= new_tmp();
563 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
567 static inline TCGv
gen_ld16u(TCGv addr
, int index
)
569 TCGv tmp
= new_tmp();
570 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
574 static inline TCGv
gen_ld32(TCGv addr
, int index
)
576 TCGv tmp
= new_tmp();
577 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
581 static inline void gen_st8(TCGv val
, TCGv addr
, int index
)
583 tcg_gen_qemu_st8(val
, addr
, index
);
587 static inline void gen_st16(TCGv val
, TCGv addr
, int index
)
589 tcg_gen_qemu_st16(val
, addr
, index
);
593 static inline void gen_st32(TCGv val
, TCGv addr
, int index
)
595 tcg_gen_qemu_st32(val
, addr
, index
);
599 static inline void gen_set_pc_im(uint32_t val
)
601 tcg_gen_movi_i32(cpu_R
[31], val
);
604 /* Force a TB lookup after an instruction that changes the CPU state. */
605 static inline void gen_lookup_tb(DisasContext
*s
)
607 tcg_gen_movi_i32(cpu_R
[31], s
->pc
& ~1);
608 s
->is_jmp
= DISAS_UPDATE
;
611 static inline void gen_add_data_offset(DisasContext
*s
, unsigned int insn
,
624 tcg_gen_addi_i32(var
, var
, val
);
628 offset
= load_reg(s
, UCOP_REG_M
);
629 gen_uc32_shift_im(offset
, UCOP_SH_OP
, UCOP_SH_IM
, 0);
631 tcg_gen_sub_i32(var
, var
, offset
);
633 tcg_gen_add_i32(var
, var
, offset
);
639 static inline void gen_add_datah_offset(DisasContext
*s
, unsigned int insn
,
647 val
= (insn
& 0x1f) | ((insn
>> 4) & 0x3e0);
652 tcg_gen_addi_i32(var
, var
, val
);
656 offset
= load_reg(s
, UCOP_REG_M
);
658 tcg_gen_sub_i32(var
, var
, offset
);
660 tcg_gen_add_i32(var
, var
, offset
);
666 static inline long ucf64_reg_offset(int reg
)
669 return offsetof(CPUUniCore32State
, ucf64
.regs
[reg
>> 1])
670 + offsetof(CPU_DoubleU
, l
.upper
);
672 return offsetof(CPUUniCore32State
, ucf64
.regs
[reg
>> 1])
673 + offsetof(CPU_DoubleU
, l
.lower
);
677 #define ucf64_gen_ld32(reg) load_cpu_offset(ucf64_reg_offset(reg))
678 #define ucf64_gen_st32(var, reg) store_cpu_offset(var, ucf64_reg_offset(reg))
680 /* UniCore-F64 single load/store I_offset */
681 static void do_ucf64_ldst_i(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
683 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
688 addr
= load_reg(s
, UCOP_REG_N
);
689 if (!UCOP_SET_P
&& !UCOP_SET_W
) {
694 offset
= UCOP_IMM10
<< 2;
699 tcg_gen_addi_i32(addr
, addr
, offset
);
703 if (UCOP_SET_L
) { /* load */
704 tmp
= gen_ld32(addr
, IS_USER(s
));
705 ucf64_gen_st32(tmp
, UCOP_REG_D
);
707 tmp
= ucf64_gen_ld32(UCOP_REG_D
);
708 gen_st32(tmp
, addr
, IS_USER(s
));
712 offset
= UCOP_IMM10
<< 2;
717 tcg_gen_addi_i32(addr
, addr
, offset
);
721 store_reg(s
, UCOP_REG_N
, addr
);
727 /* UniCore-F64 load/store multiple words */
728 static void do_ucf64_ldst_m(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
730 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
736 if (UCOP_REG_D
!= 0) {
739 if (UCOP_REG_N
== 31) {
742 if ((insn
<< 24) == 0) {
746 addr
= load_reg(s
, UCOP_REG_N
);
749 for (i
= 0; i
< 8; i
++) {
756 if (UCOP_SET_P
) { /* pre increment */
757 tcg_gen_addi_i32(addr
, addr
, 4);
758 } /* unnecessary to do anything when post increment */
760 if (UCOP_SET_P
) { /* pre decrement */
761 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
762 } else { /* post decrement */
764 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
769 freg
= ((insn
>> 8) & 3) << 3; /* freg should be 0, 8, 16, 24 */
771 for (i
= 0, j
= 0; i
< 8; i
++, freg
++) {
776 if (UCOP_SET_L
) { /* load */
777 tmp
= gen_ld32(addr
, IS_USER(s
));
778 ucf64_gen_st32(tmp
, freg
);
780 tmp
= ucf64_gen_ld32(freg
);
781 gen_st32(tmp
, addr
, IS_USER(s
));
785 /* unnecessary to add after the last transfer */
787 tcg_gen_addi_i32(addr
, addr
, 4);
791 if (UCOP_SET_W
) { /* write back */
793 if (!UCOP_SET_P
) { /* post increment */
794 tcg_gen_addi_i32(addr
, addr
, 4);
795 } /* unnecessary to do anything when pre increment */
800 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
804 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
807 store_reg(s
, UCOP_REG_N
, addr
);
813 /* UniCore-F64 mrc/mcr */
814 static void do_ucf64_trans(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
816 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
819 if ((insn
& 0xfe0003ff) == 0xe2000000) {
820 /* control register */
821 if ((UCOP_REG_N
!= UC32_UCF64_FPSCR
) || (UCOP_REG_D
== 31)) {
827 gen_helper_ucf64_get_fpscr(tmp
, cpu_env
);
828 store_reg(s
, UCOP_REG_D
, tmp
);
831 tmp
= load_reg(s
, UCOP_REG_D
);
832 gen_helper_ucf64_set_fpscr(cpu_env
, tmp
);
838 if ((insn
& 0xfe0003ff) == 0xe0000000) {
839 /* general register */
840 if (UCOP_REG_D
== 31) {
843 if (UCOP_SET(24)) { /* MFF */
844 tmp
= ucf64_gen_ld32(UCOP_REG_N
);
845 store_reg(s
, UCOP_REG_D
, tmp
);
847 tmp
= load_reg(s
, UCOP_REG_D
);
848 ucf64_gen_st32(tmp
, UCOP_REG_N
);
852 if ((insn
& 0xfb000000) == 0xe9000000) {
854 if (UCOP_REG_D
!= 31) {
857 if (UCOP_UCF64_COND
& 0x8) {
862 tcg_gen_movi_i32(tmp
, UCOP_UCF64_COND
);
864 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
865 tcg_gen_ld_i64(cpu_F1d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
866 gen_helper_ucf64_cmpd(cpu_F0d
, cpu_F1d
, tmp
, cpu_env
);
868 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
869 tcg_gen_ld_i32(cpu_F1s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
870 gen_helper_ucf64_cmps(cpu_F0s
, cpu_F1s
, tmp
, cpu_env
);
878 /* UniCore-F64 convert instructions */
879 static void do_ucf64_fcvt(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
881 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
883 if (UCOP_UCF64_FMT
== 3) {
886 if (UCOP_REG_N
!= 0) {
889 switch (UCOP_UCF64_FUNC
) {
891 switch (UCOP_UCF64_FMT
) {
893 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
894 gen_helper_ucf64_df2sf(cpu_F0s
, cpu_F0d
, cpu_env
);
895 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
898 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
899 gen_helper_ucf64_si2sf(cpu_F0s
, cpu_F0s
, cpu_env
);
900 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
908 switch (UCOP_UCF64_FMT
) {
910 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
911 gen_helper_ucf64_sf2df(cpu_F0d
, cpu_F0s
, cpu_env
);
912 tcg_gen_st_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
915 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
916 gen_helper_ucf64_si2df(cpu_F0d
, cpu_F0s
, cpu_env
);
917 tcg_gen_st_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
925 switch (UCOP_UCF64_FMT
) {
927 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
928 gen_helper_ucf64_sf2si(cpu_F0s
, cpu_F0s
, cpu_env
);
929 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
932 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
933 gen_helper_ucf64_df2si(cpu_F0s
, cpu_F0d
, cpu_env
);
934 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
946 /* UniCore-F64 compare instructions */
947 static void do_ucf64_fcmp(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
949 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
954 if (UCOP_REG_D
!= 0) {
960 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
961 tcg_gen_ld_i64(cpu_F1d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
962 /* gen_helper_ucf64_cmpd(cpu_F0d, cpu_F1d, cpu_env); */
964 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
965 tcg_gen_ld_i32(cpu_F1s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
966 /* gen_helper_ucf64_cmps(cpu_F0s, cpu_F1s, cpu_env); */
970 #define gen_helper_ucf64_movs(x, y) do { } while (0)
971 #define gen_helper_ucf64_movd(x, y) do { } while (0)
973 #define UCF64_OP1(name) do { \
974 if (UCOP_REG_N != 0) { \
977 switch (UCOP_UCF64_FMT) { \
979 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
980 ucf64_reg_offset(UCOP_REG_M)); \
981 gen_helper_ucf64_##name##s(cpu_F0s, cpu_F0s); \
982 tcg_gen_st_i32(cpu_F0s, cpu_env, \
983 ucf64_reg_offset(UCOP_REG_D)); \
986 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
987 ucf64_reg_offset(UCOP_REG_M)); \
988 gen_helper_ucf64_##name##d(cpu_F0d, cpu_F0d); \
989 tcg_gen_st_i64(cpu_F0d, cpu_env, \
990 ucf64_reg_offset(UCOP_REG_D)); \
998 #define UCF64_OP2(name) do { \
999 switch (UCOP_UCF64_FMT) { \
1001 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
1002 ucf64_reg_offset(UCOP_REG_N)); \
1003 tcg_gen_ld_i32(cpu_F1s, cpu_env, \
1004 ucf64_reg_offset(UCOP_REG_M)); \
1005 gen_helper_ucf64_##name##s(cpu_F0s, \
1006 cpu_F0s, cpu_F1s, cpu_env); \
1007 tcg_gen_st_i32(cpu_F0s, cpu_env, \
1008 ucf64_reg_offset(UCOP_REG_D)); \
1011 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
1012 ucf64_reg_offset(UCOP_REG_N)); \
1013 tcg_gen_ld_i64(cpu_F1d, cpu_env, \
1014 ucf64_reg_offset(UCOP_REG_M)); \
1015 gen_helper_ucf64_##name##d(cpu_F0d, \
1016 cpu_F0d, cpu_F1d, cpu_env); \
1017 tcg_gen_st_i64(cpu_F0d, cpu_env, \
1018 ucf64_reg_offset(UCOP_REG_D)); \
1026 /* UniCore-F64 data processing */
1027 static void do_ucf64_datap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1029 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1031 if (UCOP_UCF64_FMT
== 3) {
1034 switch (UCOP_UCF64_FUNC
) {
1061 /* Disassemble an F64 instruction */
1062 static void disas_ucf64_insn(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1064 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1066 if (!UCOP_SET(29)) {
1068 do_ucf64_ldst_m(env
, s
, insn
);
1070 do_ucf64_ldst_i(env
, s
, insn
);
1074 switch ((insn
>> 26) & 0x3) {
1076 do_ucf64_datap(env
, s
, insn
);
1082 do_ucf64_fcvt(env
, s
, insn
);
1085 do_ucf64_fcmp(env
, s
, insn
);
1089 do_ucf64_trans(env
, s
, insn
);
1094 static inline bool use_goto_tb(DisasContext
*s
, uint32_t dest
)
1096 #ifndef CONFIG_USER_ONLY
1097 return (s
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
1103 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint32_t dest
)
1105 if (use_goto_tb(s
, dest
)) {
1107 gen_set_pc_im(dest
);
1108 tcg_gen_exit_tb((uintptr_t)s
->tb
+ n
);
1110 gen_set_pc_im(dest
);
1115 static inline void gen_jmp(DisasContext
*s
, uint32_t dest
)
1117 if (unlikely(s
->singlestep_enabled
)) {
1118 /* An indirect jump so that we still trigger the debug exception. */
1121 gen_goto_tb(s
, 0, dest
);
1122 s
->is_jmp
= DISAS_TB_JUMP
;
1126 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
1127 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int bsr
, TCGv t0
)
1131 /* ??? This is also undefined in system mode. */
1136 tmp
= load_cpu_field(bsr
);
1137 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
1138 tcg_gen_andi_i32(t0
, t0
, mask
);
1139 tcg_gen_or_i32(tmp
, tmp
, t0
);
1140 store_cpu_field(tmp
, bsr
);
1142 gen_set_asr(t0
, mask
);
1149 /* Generate an old-style exception return. Marks pc as dead. */
1150 static void gen_exception_return(DisasContext
*s
, TCGv pc
)
1153 store_reg(s
, 31, pc
);
1154 tmp
= load_cpu_field(bsr
);
1155 gen_set_asr(tmp
, 0xffffffff);
1157 s
->is_jmp
= DISAS_UPDATE
;
1160 static void disas_coproc_insn(CPUUniCore32State
*env
, DisasContext
*s
,
1163 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1165 switch (UCOP_CPNUM
) {
1166 #ifndef CONFIG_USER_ONLY
1168 disas_cp0_insn(env
, s
, insn
);
1171 disas_ocd_insn(env
, s
, insn
);
1175 disas_ucf64_insn(env
, s
, insn
);
1178 /* Unknown coprocessor. */
1179 cpu_abort(CPU(cpu
), "Unknown coprocessor!");
1183 /* data processing instructions */
1184 static void do_datap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1186 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1191 if (UCOP_OPCODES
== 0x0f || UCOP_OPCODES
== 0x0d) {
1192 if (UCOP_SET(23)) { /* CMOV instructions */
1193 if ((UCOP_CMOV_COND
== 0xe) || (UCOP_CMOV_COND
== 0xf)) {
1196 /* if not always execute, we generate a conditional jump to
1198 s
->condlabel
= gen_new_label();
1199 gen_test_cc(UCOP_CMOV_COND
^ 1, s
->condlabel
);
1204 logic_cc
= table_logic_cc
[UCOP_OPCODES
] & (UCOP_SET_S
>> 24);
1208 /* immediate operand */
1211 val
= (val
>> UCOP_SH_IM
) | (val
<< (32 - UCOP_SH_IM
));
1214 tcg_gen_movi_i32(tmp2
, val
);
1215 if (logic_cc
&& UCOP_SH_IM
) {
1216 gen_set_CF_bit31(tmp2
);
1220 tmp2
= load_reg(s
, UCOP_REG_M
);
1222 tmp
= load_reg(s
, UCOP_REG_S
);
1223 gen_uc32_shift_reg(tmp2
, UCOP_SH_OP
, tmp
, logic_cc
);
1225 gen_uc32_shift_im(tmp2
, UCOP_SH_OP
, UCOP_SH_IM
, logic_cc
);
1229 if (UCOP_OPCODES
!= 0x0f && UCOP_OPCODES
!= 0x0d) {
1230 tmp
= load_reg(s
, UCOP_REG_N
);
1235 switch (UCOP_OPCODES
) {
1237 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1241 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1244 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
1248 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1251 if (UCOP_SET_S
&& UCOP_REG_D
== 31) {
1252 /* SUBS r31, ... is used for exception return. */
1256 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1257 gen_exception_return(s
, tmp
);
1260 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1262 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
1264 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1269 gen_helper_sub_cc(tmp
, cpu_env
, tmp2
, tmp
);
1271 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
1273 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1277 gen_helper_add_cc(tmp
, cpu_env
, tmp
, tmp2
);
1279 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
1281 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1285 gen_helper_adc_cc(tmp
, cpu_env
, tmp
, tmp2
);
1287 gen_add_carry(tmp
, tmp
, tmp2
);
1289 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1293 gen_helper_sbc_cc(tmp
, cpu_env
, tmp
, tmp2
);
1295 gen_sub_carry(tmp
, tmp
, tmp2
);
1297 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1301 gen_helper_sbc_cc(tmp
, cpu_env
, tmp2
, tmp
);
1303 gen_sub_carry(tmp
, tmp2
, tmp
);
1305 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1309 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1316 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
1323 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1329 gen_helper_add_cc(tmp
, cpu_env
, tmp
, tmp2
);
1334 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1338 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1341 if (logic_cc
&& UCOP_REG_D
== 31) {
1342 /* MOVS r31, ... is used for exception return. */
1346 gen_exception_return(s
, tmp2
);
1351 store_reg_bx(s
, UCOP_REG_D
, tmp2
);
1355 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
1359 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1363 tcg_gen_not_i32(tmp2
, tmp2
);
1367 store_reg_bx(s
, UCOP_REG_D
, tmp2
);
1370 if (UCOP_OPCODES
!= 0x0f && UCOP_OPCODES
!= 0x0d) {
1376 static void do_mult(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1378 TCGv tmp
, tmp2
, tmp3
, tmp4
;
1382 tmp
= load_reg(s
, UCOP_REG_M
);
1383 tmp2
= load_reg(s
, UCOP_REG_N
);
1385 tcg_gen_muls2_i32(tmp
, tmp2
, tmp
, tmp2
);
1387 tcg_gen_mulu2_i32(tmp
, tmp2
, tmp
, tmp2
);
1389 if (UCOP_SET(25)) { /* mult accumulate */
1390 tmp3
= load_reg(s
, UCOP_REG_LO
);
1391 tmp4
= load_reg(s
, UCOP_REG_HI
);
1392 tcg_gen_add2_i32(tmp
, tmp2
, tmp
, tmp2
, tmp3
, tmp4
);
1396 store_reg(s
, UCOP_REG_LO
, tmp
);
1397 store_reg(s
, UCOP_REG_HI
, tmp2
);
1400 tmp
= load_reg(s
, UCOP_REG_M
);
1401 tmp2
= load_reg(s
, UCOP_REG_N
);
1402 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
1406 tmp2
= load_reg(s
, UCOP_REG_S
);
1407 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
1413 store_reg(s
, UCOP_REG_D
, tmp
);
1417 /* miscellaneous instructions */
1418 static void do_misc(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1420 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1424 if ((insn
& 0xffffffe0) == 0x10ffc120) {
1425 /* Trivial implementation equivalent to bx. */
1426 tmp
= load_reg(s
, UCOP_REG_M
);
1431 if ((insn
& 0xfbffc000) == 0x30ffc000) {
1432 /* PSR = immediate */
1435 val
= (val
>> UCOP_SH_IM
) | (val
<< (32 - UCOP_SH_IM
));
1438 tcg_gen_movi_i32(tmp
, val
);
1439 if (gen_set_psr(s
, ~ASR_RESERVED
, UCOP_SET_B
, tmp
)) {
1445 if ((insn
& 0xfbffffe0) == 0x12ffc020) {
1446 /* PSR.flag = reg */
1447 tmp
= load_reg(s
, UCOP_REG_M
);
1448 if (gen_set_psr(s
, ASR_NZCV
, UCOP_SET_B
, tmp
)) {
1454 if ((insn
& 0xfbffffe0) == 0x10ffc020) {
1456 tmp
= load_reg(s
, UCOP_REG_M
);
1457 if (gen_set_psr(s
, ~ASR_RESERVED
, UCOP_SET_B
, tmp
)) {
1463 if ((insn
& 0xfbf83fff) == 0x10f80000) {
1469 tmp
= load_cpu_field(bsr
);
1472 gen_helper_asr_read(tmp
, cpu_env
);
1474 store_reg(s
, UCOP_REG_D
, tmp
);
1478 if ((insn
& 0xfbf83fe0) == 0x12f80120) {
1480 tmp
= load_reg(s
, UCOP_REG_M
);
1483 tcg_gen_not_i32(tmp
, tmp
);
1485 tcg_gen_clzi_i32(tmp
, tmp
, 32);
1486 store_reg(s
, UCOP_REG_D
, tmp
);
1494 /* load/store I_offset and R_offset */
1495 static void do_ldst_ir(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1497 unsigned int mmu_idx
;
1501 tmp2
= load_reg(s
, UCOP_REG_N
);
1502 mmu_idx
= (IS_USER(s
) || (!UCOP_SET_P
&& UCOP_SET_W
));
1506 gen_add_data_offset(s
, insn
, tmp2
);
1512 tmp
= gen_ld8u(tmp2
, mmu_idx
);
1514 tmp
= gen_ld32(tmp2
, mmu_idx
);
1518 tmp
= load_reg(s
, UCOP_REG_D
);
1520 gen_st8(tmp
, tmp2
, mmu_idx
);
1522 gen_st32(tmp
, tmp2
, mmu_idx
);
1526 gen_add_data_offset(s
, insn
, tmp2
);
1527 store_reg(s
, UCOP_REG_N
, tmp2
);
1528 } else if (UCOP_SET_W
) {
1529 store_reg(s
, UCOP_REG_N
, tmp2
);
1534 /* Complete the load. */
1535 if (UCOP_REG_D
== 31) {
1538 store_reg(s
, UCOP_REG_D
, tmp
);
1543 /* SWP instruction */
1544 static void do_swap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1546 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1551 if ((insn
& 0xff003fe0) != 0x40000120) {
1555 /* ??? This is not really atomic. However we know
1556 we never have multiple CPUs running in parallel,
1557 so it is good enough. */
1558 addr
= load_reg(s
, UCOP_REG_N
);
1559 tmp
= load_reg(s
, UCOP_REG_M
);
1561 tmp2
= gen_ld8u(addr
, IS_USER(s
));
1562 gen_st8(tmp
, addr
, IS_USER(s
));
1564 tmp2
= gen_ld32(addr
, IS_USER(s
));
1565 gen_st32(tmp
, addr
, IS_USER(s
));
1568 store_reg(s
, UCOP_REG_D
, tmp2
);
1571 /* load/store hw/sb */
1572 static void do_ldst_hwsb(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1574 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1578 if (UCOP_SH_OP
== 0) {
1579 do_swap(env
, s
, insn
);
1583 addr
= load_reg(s
, UCOP_REG_N
);
1585 gen_add_datah_offset(s
, insn
, addr
);
1588 if (UCOP_SET_L
) { /* load */
1589 switch (UCOP_SH_OP
) {
1591 tmp
= gen_ld16u(addr
, IS_USER(s
));
1594 tmp
= gen_ld8s(addr
, IS_USER(s
));
1596 default: /* see do_swap */
1598 tmp
= gen_ld16s(addr
, IS_USER(s
));
1601 } else { /* store */
1602 if (UCOP_SH_OP
!= 1) {
1605 tmp
= load_reg(s
, UCOP_REG_D
);
1606 gen_st16(tmp
, addr
, IS_USER(s
));
1608 /* Perform base writeback before the loaded value to
1609 ensure correct behavior with overlapping index registers. */
1611 gen_add_datah_offset(s
, insn
, addr
);
1612 store_reg(s
, UCOP_REG_N
, addr
);
1613 } else if (UCOP_SET_W
) {
1614 store_reg(s
, UCOP_REG_N
, addr
);
1619 /* Complete the load. */
1620 store_reg(s
, UCOP_REG_D
, tmp
);
1624 /* load/store multiple words */
1625 static void do_ldst_m(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1627 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1628 unsigned int val
, i
, mmu_idx
;
1629 int j
, n
, reg
, user
, loaded_base
;
1638 /* XXX: store correct base if write back */
1640 if (UCOP_SET_B
) { /* S bit in instruction table */
1642 ILLEGAL
; /* only usable in supervisor mode */
1644 if (UCOP_SET(18) == 0) { /* pc reg */
1649 mmu_idx
= (IS_USER(s
) || (!UCOP_SET_P
&& UCOP_SET_W
));
1650 addr
= load_reg(s
, UCOP_REG_N
);
1652 /* compute total size */
1654 TCGV_UNUSED(loaded_var
);
1656 for (i
= 0; i
< 6; i
++) {
1661 for (i
= 9; i
< 19; i
++) {
1666 /* XXX: test invalid n == 0 case ? */
1670 tcg_gen_addi_i32(addr
, addr
, 4);
1672 /* post increment */
1677 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
1679 /* post decrement */
1681 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
1687 reg
= UCOP_SET(6) ? 16 : 0;
1688 for (i
= 0; i
< 19; i
++, reg
++) {
1693 if (UCOP_SET_L
) { /* load */
1694 tmp
= gen_ld32(addr
, mmu_idx
);
1698 tmp2
= tcg_const_i32(reg
);
1699 gen_helper_set_user_reg(cpu_env
, tmp2
, tmp
);
1700 tcg_temp_free_i32(tmp2
);
1702 } else if (reg
== UCOP_REG_N
) {
1706 store_reg(s
, reg
, tmp
);
1708 } else { /* store */
1710 /* special case: r31 = PC + 4 */
1713 tcg_gen_movi_i32(tmp
, val
);
1716 tmp2
= tcg_const_i32(reg
);
1717 gen_helper_get_user_reg(tmp
, cpu_env
, tmp2
);
1718 tcg_temp_free_i32(tmp2
);
1720 tmp
= load_reg(s
, reg
);
1722 gen_st32(tmp
, addr
, mmu_idx
);
1725 /* no need to add after the last transfer */
1727 tcg_gen_addi_i32(addr
, addr
, 4);
1731 if (UCOP_SET_W
) { /* write back */
1736 /* post increment */
1737 tcg_gen_addi_i32(addr
, addr
, 4);
1743 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
1746 /* post decrement */
1747 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
1750 store_reg(s
, UCOP_REG_N
, addr
);
1755 store_reg(s
, UCOP_REG_N
, loaded_var
);
1757 if (UCOP_SET_B
&& !user
) {
1758 /* Restore ASR from BSR. */
1759 tmp
= load_cpu_field(bsr
);
1760 gen_set_asr(tmp
, 0xffffffff);
1762 s
->is_jmp
= DISAS_UPDATE
;
1766 /* branch (and link) */
1767 static void do_branch(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1769 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1774 if (UCOP_COND
== 0xf) {
1778 if (UCOP_COND
!= 0xe) {
1779 /* if not always execute, we generate a conditional jump to
1781 s
->condlabel
= gen_new_label();
1782 gen_test_cc(UCOP_COND
^ 1, s
->condlabel
);
1786 val
= (int32_t)s
->pc
;
1789 tcg_gen_movi_i32(tmp
, val
);
1790 store_reg(s
, 30, tmp
);
1792 offset
= (((int32_t)insn
<< 8) >> 8);
1793 val
+= (offset
<< 2); /* unicore is pc+4 */
1797 static void disas_uc32_insn(CPUUniCore32State
*env
, DisasContext
*s
)
1799 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1802 insn
= cpu_ldl_code(env
, s
->pc
);
1805 /* UniCore instructions class:
1806 * AAAB BBBC xxxx xxxx xxxx xxxD xxEx xxxx
1807 * AAA : see switch case
1808 * BBBB : opcodes or cond or PUBW
1813 switch (insn
>> 29) {
1815 if (UCOP_SET(5) && UCOP_SET(8) && !UCOP_SET(28)) {
1816 do_mult(env
, s
, insn
);
1821 do_misc(env
, s
, insn
);
1825 if (((UCOP_OPCODES
>> 2) == 2) && !UCOP_SET_S
) {
1826 do_misc(env
, s
, insn
);
1829 do_datap(env
, s
, insn
);
1833 if (UCOP_SET(8) && UCOP_SET(5)) {
1834 do_ldst_hwsb(env
, s
, insn
);
1837 if (UCOP_SET(8) || UCOP_SET(5)) {
1841 do_ldst_ir(env
, s
, insn
);
1846 ILLEGAL
; /* extended instructions */
1848 do_ldst_m(env
, s
, insn
);
1851 do_branch(env
, s
, insn
);
1855 disas_coproc_insn(env
, s
, insn
);
1858 if (!UCOP_SET(28)) {
1859 disas_coproc_insn(env
, s
, insn
);
1862 if ((insn
& 0xff000000) == 0xff000000) { /* syscall */
1863 gen_set_pc_im(s
->pc
);
1864 s
->is_jmp
= DISAS_SYSCALL
;
1871 /* generate intermediate code for basic block 'tb'. */
1872 void gen_intermediate_code(CPUUniCore32State
*env
, TranslationBlock
*tb
)
1874 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1875 CPUState
*cs
= CPU(cpu
);
1876 DisasContext dc1
, *dc
= &dc1
;
1877 target_ulong pc_start
;
1878 uint32_t next_page_start
;
1882 /* generate intermediate code */
1889 dc
->is_jmp
= DISAS_NEXT
;
1891 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
1893 cpu_F0s
= tcg_temp_new_i32();
1894 cpu_F1s
= tcg_temp_new_i32();
1895 cpu_F0d
= tcg_temp_new_i64();
1896 cpu_F1d
= tcg_temp_new_i64();
1897 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1899 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1900 if (max_insns
== 0) {
1901 max_insns
= CF_COUNT_MASK
;
1903 if (max_insns
> TCG_MAX_INSNS
) {
1904 max_insns
= TCG_MAX_INSNS
;
1907 #ifndef CONFIG_USER_ONLY
1908 if ((env
->uncached_asr
& ASR_M
) == ASR_MODE_USER
) {
1917 tcg_gen_insn_start(dc
->pc
);
1920 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
1921 gen_set_pc_im(dc
->pc
);
1922 gen_exception(EXCP_DEBUG
);
1923 dc
->is_jmp
= DISAS_JUMP
;
1924 /* The address covered by the breakpoint must be included in
1925 [tb->pc, tb->pc + tb->size) in order to for it to be
1926 properly cleared -- thus we increment the PC here so that
1927 the logic setting tb->size below does the right thing. */
1929 goto done_generating
;
1932 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
1936 disas_uc32_insn(env
, dc
);
1939 fprintf(stderr
, "Internal resource leak before %08x\n", dc
->pc
);
1943 if (dc
->condjmp
&& !dc
->is_jmp
) {
1944 gen_set_label(dc
->condlabel
);
1947 /* Translation stops when a conditional branch is encountered.
1948 * Otherwise the subsequent code could get translated several times.
1949 * Also stop translation when a page boundary is reached. This
1950 * ensures prefetch aborts occur at the right place. */
1951 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
1952 !cs
->singlestep_enabled
&&
1954 dc
->pc
< next_page_start
&&
1955 num_insns
< max_insns
);
1957 if (tb
->cflags
& CF_LAST_IO
) {
1959 /* FIXME: This can theoretically happen with self-modifying
1961 cpu_abort(cs
, "IO on conditional branch instruction");
1966 /* At this stage dc->condjmp will only be set when the skipped
1967 instruction was a conditional branch or trap, and the PC has
1968 already been written. */
1969 if (unlikely(cs
->singlestep_enabled
)) {
1970 /* Make sure the pc is updated, and raise a debug exception. */
1972 if (dc
->is_jmp
== DISAS_SYSCALL
) {
1973 gen_exception(UC32_EXCP_PRIV
);
1975 gen_exception(EXCP_DEBUG
);
1977 gen_set_label(dc
->condlabel
);
1979 if (dc
->condjmp
|| !dc
->is_jmp
) {
1980 gen_set_pc_im(dc
->pc
);
1983 if (dc
->is_jmp
== DISAS_SYSCALL
&& !dc
->condjmp
) {
1984 gen_exception(UC32_EXCP_PRIV
);
1986 gen_exception(EXCP_DEBUG
);
1989 /* While branches must always occur at the end of an IT block,
1990 there are a few other things that can cause us to terminate
1991 the TB in the middel of an IT block:
1992 - Exception generating instructions (bkpt, swi, undefined).
1994 - Hardware watchpoints.
1995 Hardware breakpoints have already been handled and skip this code.
1997 switch (dc
->is_jmp
) {
1999 gen_goto_tb(dc
, 1, dc
->pc
);
2004 /* indicate that the hash table must be used to find the next TB */
2008 /* nothing more to generate */
2011 gen_exception(UC32_EXCP_PRIV
);
2015 gen_set_label(dc
->condlabel
);
2016 gen_goto_tb(dc
, 1, dc
->pc
);
2022 gen_tb_end(tb
, num_insns
);
2025 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
2026 && qemu_log_in_addr_range(pc_start
)) {
2028 qemu_log("----------------\n");
2029 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
2030 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
, 0);
2035 tb
->size
= dc
->pc
- pc_start
;
2036 tb
->icount
= num_insns
;
2039 static const char *cpu_mode_names
[16] = {
2040 "USER", "REAL", "INTR", "PRIV", "UM14", "UM15", "UM16", "TRAP",
2041 "UM18", "UM19", "UM1A", "EXTN", "UM1C", "UM1D", "UM1E", "SUSR"
2044 #undef UCF64_DUMP_STATE
2045 #ifdef UCF64_DUMP_STATE
2046 static void cpu_dump_state_ucf64(CPUUniCore32State
*env
, FILE *f
,
2047 fprintf_function cpu_fprintf
, int flags
)
2055 /* ??? This assumes float64 and double have the same layout.
2056 Oh well, it's only debug dumps. */
2062 for (i
= 0; i
< 16; i
++) {
2063 d
.d
= env
->ucf64
.regs
[i
];
2067 cpu_fprintf(f
, "s%02d=%08x(%8g) s%02d=%08x(%8g)",
2068 i
* 2, (int)s0
.i
, s0
.s
,
2069 i
* 2 + 1, (int)s1
.i
, s1
.s
);
2070 cpu_fprintf(f
, " d%02d=%" PRIx64
"(%8g)\n",
2071 i
, (uint64_t)d0
.f64
, d0
.d
);
2073 cpu_fprintf(f
, "FPSCR: %08x\n", (int)env
->ucf64
.xregs
[UC32_UCF64_FPSCR
]);
2076 #define cpu_dump_state_ucf64(env, file, pr, flags) do { } while (0)
2079 void uc32_cpu_dump_state(CPUState
*cs
, FILE *f
,
2080 fprintf_function cpu_fprintf
, int flags
)
2082 UniCore32CPU
*cpu
= UNICORE32_CPU(cs
);
2083 CPUUniCore32State
*env
= &cpu
->env
;
2087 for (i
= 0; i
< 32; i
++) {
2088 cpu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
2090 cpu_fprintf(f
, "\n");
2092 cpu_fprintf(f
, " ");
2095 psr
= cpu_asr_read(env
);
2096 cpu_fprintf(f
, "PSR=%08x %c%c%c%c %s\n",
2098 psr
& (1 << 31) ? 'N' : '-',
2099 psr
& (1 << 30) ? 'Z' : '-',
2100 psr
& (1 << 29) ? 'C' : '-',
2101 psr
& (1 << 28) ? 'V' : '-',
2102 cpu_mode_names
[psr
& 0xf]);
2104 cpu_dump_state_ucf64(env
, f
, cpu_fprintf
, flags
);
2107 void restore_state_to_opc(CPUUniCore32State
*env
, TranslationBlock
*tb
,
2110 env
->regs
[31] = data
[0];