ehci: Use uframe precision for interrupt threshold checking (v2)
[qemu/ar7.git] / hw / apic.h
blob1d48e027c3c17c88f1c9e4f894ef72f78d903f59
1 #ifndef APIC_H
2 #define APIC_H
4 #include "qemu-common.h"
6 /* apic.c */
7 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
8 uint8_t vector_num, uint8_t trigger_mode);
9 int apic_accept_pic_intr(DeviceState *s);
10 void apic_deliver_pic_intr(DeviceState *s, int level);
11 void apic_deliver_nmi(DeviceState *d);
12 int apic_get_interrupt(DeviceState *s);
13 void apic_reset_irq_delivered(void);
14 int apic_get_irq_delivered(void);
15 void cpu_set_apic_base(DeviceState *s, uint64_t val);
16 uint64_t cpu_get_apic_base(DeviceState *s);
17 void cpu_set_apic_tpr(DeviceState *s, uint8_t val);
18 uint8_t cpu_get_apic_tpr(DeviceState *s);
19 void apic_init_reset(DeviceState *s);
20 void apic_sipi(DeviceState *s);
21 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
22 TPRAccess access);
23 void apic_poll_irq(DeviceState *d);
24 void apic_designate_bsp(DeviceState *d);
26 /* pc.c */
27 DeviceState *cpu_get_current_apic(void);
29 /* cpu.c */
30 bool cpu_is_bsp(X86CPU *cpu);
32 #endif