tests/libqos/ahci.h

   1 #ifndef __libqos_ahci_h
   2 #define __libqos_ahci_h
   3
   4 /*
   5  * AHCI qtest library functions and definitions
   6  *
   7  * Copyright (c) 2014 John Snow <jsnow@redhat.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include <stdint.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include "libqos/libqos.h"
  32 #include "libqos/pci.h"
  33 #include "libqos/malloc-pc.h"
  34
  35 /*** Supplementary PCI Config Space IDs & Masks ***/
  36 #define PCI_DEVICE_ID_INTEL_Q35_AHCI   (0x2922)
  37 #define PCI_MSI_FLAGS_RESERVED         (0xFF00)
  38 #define PCI_PM_CTRL_RESERVED             (0xFC)
  39 #define PCI_BCC(REG32)          ((REG32) >> 24)
  40 #define PCI_PI(REG32)   (((REG32) >> 8) & 0xFF)
  41 #define PCI_SCC(REG32) (((REG32) >> 16) & 0xFF)
  42
  43 /*** Recognized AHCI Device Types ***/
  44 #define AHCI_INTEL_ICH9 (PCI_DEVICE_ID_INTEL_Q35_AHCI << 16 | \
  45                          PCI_VENDOR_ID_INTEL)
  46
  47 /*** AHCI/HBA Register Offsets and Bitmasks ***/
  48 #define AHCI_CAP                          (0)
  49 #define AHCI_CAP_NP                    (0x1F)
  50 #define AHCI_CAP_SXS                   (0x20)
  51 #define AHCI_CAP_EMS                   (0x40)
  52 #define AHCI_CAP_CCCS                  (0x80)
  53 #define AHCI_CAP_NCS                 (0x1F00)
  54 #define AHCI_CAP_PSC                 (0x2000)
  55 #define AHCI_CAP_SSC                 (0x4000)
  56 #define AHCI_CAP_PMD                 (0x8000)
  57 #define AHCI_CAP_FBSS               (0x10000)
  58 #define AHCI_CAP_SPM                (0x20000)
  59 #define AHCI_CAP_SAM                (0x40000)
  60 #define AHCI_CAP_RESERVED           (0x80000)
  61 #define AHCI_CAP_ISS               (0xF00000)
  62 #define AHCI_CAP_SCLO             (0x1000000)
  63 #define AHCI_CAP_SAL              (0x2000000)
  64 #define AHCI_CAP_SALP             (0x4000000)
  65 #define AHCI_CAP_SSS              (0x8000000)
  66 #define AHCI_CAP_SMPS            (0x10000000)
  67 #define AHCI_CAP_SSNTF           (0x20000000)
  68 #define AHCI_CAP_SNCQ            (0x40000000)
  69 #define AHCI_CAP_S64A            (0x80000000)
  70
  71 #define AHCI_GHC                          (1)
  72 #define AHCI_GHC_HR                    (0x01)
  73 #define AHCI_GHC_IE                    (0x02)
  74 #define AHCI_GHC_MRSM                  (0x04)
  75 #define AHCI_GHC_RESERVED        (0x7FFFFFF8)
  76 #define AHCI_GHC_AE              (0x80000000)
  77
  78 #define AHCI_IS                           (2)
  79 #define AHCI_PI                           (3)
  80 #define AHCI_VS                           (4)
  81
  82 #define AHCI_CCCCTL                       (5)
  83 #define AHCI_CCCCTL_EN                 (0x01)
  84 #define AHCI_CCCCTL_RESERVED           (0x06)
  85 #define AHCI_CCCCTL_CC               (0xFF00)
  86 #define AHCI_CCCCTL_TV           (0xFFFF0000)
  87
  88 #define AHCI_CCCPORTS                     (6)
  89 #define AHCI_EMLOC                        (7)
  90
  91 #define AHCI_EMCTL                        (8)
  92 #define AHCI_EMCTL_STSMR               (0x01)
  93 #define AHCI_EMCTL_CTLTM              (0x100)
  94 #define AHCI_EMCTL_CTLRST             (0x200)
  95 #define AHCI_EMCTL_RESERVED      (0xF0F0FCFE)
  96
  97 #define AHCI_CAP2                         (9)
  98 #define AHCI_CAP2_BOH                  (0x01)
  99 #define AHCI_CAP2_NVMP                 (0x02)
 100 #define AHCI_CAP2_APST                 (0x04)
 101 #define AHCI_CAP2_RESERVED       (0xFFFFFFF8)
 102
 103 #define AHCI_BOHC                        (10)
 104 #define AHCI_RESERVED                    (11)
 105 #define AHCI_NVMHCI                      (24)
 106 #define AHCI_VENDOR                      (40)
 107 #define AHCI_PORTS                       (64)
 108
 109 /*** Port Memory Offsets & Bitmasks ***/
 110 #define AHCI_PX_CLB                       (0)
 111 #define AHCI_PX_CLB_RESERVED          (0x1FF)
 112
 113 #define AHCI_PX_CLBU                      (1)
 114
 115 #define AHCI_PX_FB                        (2)
 116 #define AHCI_PX_FB_RESERVED            (0xFF)
 117
 118 #define AHCI_PX_FBU                       (3)
 119
 120 #define AHCI_PX_IS                        (4)
 121 #define AHCI_PX_IS_DHRS                 (0x1)
 122 #define AHCI_PX_IS_PSS                  (0x2)
 123 #define AHCI_PX_IS_DSS                  (0x4)
 124 #define AHCI_PX_IS_SDBS                 (0x8)
 125 #define AHCI_PX_IS_UFS                 (0x10)
 126 #define AHCI_PX_IS_DPS                 (0x20)
 127 #define AHCI_PX_IS_PCS                 (0x40)
 128 #define AHCI_PX_IS_DMPS                (0x80)
 129 #define AHCI_PX_IS_RESERVED       (0x23FFF00)
 130 #define AHCI_PX_IS_PRCS            (0x400000)
 131 #define AHCI_PX_IS_IPMS            (0x800000)
 132 #define AHCI_PX_IS_OFS            (0x1000000)
 133 #define AHCI_PX_IS_INFS           (0x4000000)
 134 #define AHCI_PX_IS_IFS            (0x8000000)
 135 #define AHCI_PX_IS_HBDS          (0x10000000)
 136 #define AHCI_PX_IS_HBFS          (0x20000000)
 137 #define AHCI_PX_IS_TFES          (0x40000000)
 138 #define AHCI_PX_IS_CPDS          (0x80000000)
 139
 140 #define AHCI_PX_IE                        (5)
 141 #define AHCI_PX_IE_DHRE                 (0x1)
 142 #define AHCI_PX_IE_PSE                  (0x2)
 143 #define AHCI_PX_IE_DSE                  (0x4)
 144 #define AHCI_PX_IE_SDBE                 (0x8)
 145 #define AHCI_PX_IE_UFE                 (0x10)
 146 #define AHCI_PX_IE_DPE                 (0x20)
 147 #define AHCI_PX_IE_PCE                 (0x40)
 148 #define AHCI_PX_IE_DMPE                (0x80)
 149 #define AHCI_PX_IE_RESERVED       (0x23FFF00)
 150 #define AHCI_PX_IE_PRCE            (0x400000)
 151 #define AHCI_PX_IE_IPME            (0x800000)
 152 #define AHCI_PX_IE_OFE            (0x1000000)
 153 #define AHCI_PX_IE_INFE           (0x4000000)
 154 #define AHCI_PX_IE_IFE            (0x8000000)
 155 #define AHCI_PX_IE_HBDE          (0x10000000)
 156 #define AHCI_PX_IE_HBFE          (0x20000000)
 157 #define AHCI_PX_IE_TFEE          (0x40000000)
 158 #define AHCI_PX_IE_CPDE          (0x80000000)
 159
 160 #define AHCI_PX_CMD                       (6)
 161 #define AHCI_PX_CMD_ST                  (0x1)
 162 #define AHCI_PX_CMD_SUD                 (0x2)
 163 #define AHCI_PX_CMD_POD                 (0x4)
 164 #define AHCI_PX_CMD_CLO                 (0x8)
 165 #define AHCI_PX_CMD_FRE                (0x10)
 166 #define AHCI_PX_CMD_RESERVED           (0xE0)
 167 #define AHCI_PX_CMD_CCS              (0x1F00)
 168 #define AHCI_PX_CMD_MPSS             (0x2000)
 169 #define AHCI_PX_CMD_FR               (0x4000)
 170 #define AHCI_PX_CMD_CR               (0x8000)
 171 #define AHCI_PX_CMD_CPS             (0x10000)
 172 #define AHCI_PX_CMD_PMA             (0x20000)
 173 #define AHCI_PX_CMD_HPCP            (0x40000)
 174 #define AHCI_PX_CMD_MPSP            (0x80000)
 175 #define AHCI_PX_CMD_CPD            (0x100000)
 176 #define AHCI_PX_CMD_ESP            (0x200000)
 177 #define AHCI_PX_CMD_FBSCP          (0x400000)
 178 #define AHCI_PX_CMD_APSTE          (0x800000)
 179 #define AHCI_PX_CMD_ATAPI         (0x1000000)
 180 #define AHCI_PX_CMD_DLAE          (0x2000000)
 181 #define AHCI_PX_CMD_ALPE          (0x4000000)
 182 #define AHCI_PX_CMD_ASP           (0x8000000)
 183 #define AHCI_PX_CMD_ICC          (0xF0000000)
 184
 185 #define AHCI_PX_RES1                      (7)
 186
 187 #define AHCI_PX_TFD                       (8)
 188 #define AHCI_PX_TFD_STS                (0xFF)
 189 #define AHCI_PX_TFD_STS_ERR            (0x01)
 190 #define AHCI_PX_TFD_STS_CS1            (0x06)
 191 #define AHCI_PX_TFD_STS_DRQ            (0x08)
 192 #define AHCI_PX_TFD_STS_CS2            (0x70)
 193 #define AHCI_PX_TFD_STS_BSY            (0x80)
 194 #define AHCI_PX_TFD_ERR              (0xFF00)
 195 #define AHCI_PX_TFD_RESERVED     (0xFFFF0000)
 196
 197 #define AHCI_PX_SIG                       (9)
 198 #define AHCI_PX_SIG_SECTOR_COUNT       (0xFF)
 199 #define AHCI_PX_SIG_LBA_LOW          (0xFF00)
 200 #define AHCI_PX_SIG_LBA_MID        (0xFF0000)
 201 #define AHCI_PX_SIG_LBA_HIGH     (0xFF000000)
 202
 203 #define AHCI_PX_SSTS                     (10)
 204 #define AHCI_PX_SSTS_DET               (0x0F)
 205 #define AHCI_PX_SSTS_SPD               (0xF0)
 206 #define AHCI_PX_SSTS_IPM              (0xF00)
 207 #define AHCI_PX_SSTS_RESERVED    (0xFFFFF000)
 208 #define SSTS_DET_NO_DEVICE             (0x00)
 209 #define SSTS_DET_PRESENT               (0x01)
 210 #define SSTS_DET_ESTABLISHED           (0x03)
 211 #define SSTS_DET_OFFLINE               (0x04)
 212
 213 #define AHCI_PX_SCTL                     (11)
 214
 215 #define AHCI_PX_SERR                     (12)
 216 #define AHCI_PX_SERR_ERR             (0xFFFF)
 217 #define AHCI_PX_SERR_DIAG        (0xFFFF0000)
 218 #define AHCI_PX_SERR_DIAG_X      (0x04000000)
 219
 220 #define AHCI_PX_SACT                     (13)
 221 #define AHCI_PX_CI                       (14)
 222 #define AHCI_PX_SNTF                     (15)
 223
 224 #define AHCI_PX_FBS                      (16)
 225 #define AHCI_PX_FBS_EN                  (0x1)
 226 #define AHCI_PX_FBS_DEC                 (0x2)
 227 #define AHCI_PX_FBS_SDE                 (0x4)
 228 #define AHCI_PX_FBS_DEV               (0xF00)
 229 #define AHCI_PX_FBS_ADO              (0xF000)
 230 #define AHCI_PX_FBS_DWE             (0xF0000)
 231 #define AHCI_PX_FBS_RESERVED     (0xFFF000F8)
 232
 233 #define AHCI_PX_RES2                     (17)
 234 #define AHCI_PX_VS                       (28)
 235
 236 #define HBA_DATA_REGION_SIZE            (256)
 237 #define HBA_PORT_DATA_SIZE              (128)
 238 #define HBA_PORT_NUM_REG (HBA_PORT_DATA_SIZE/4)
 239
 240 #define AHCI_VERSION_0_95        (0x00000905)
 241 #define AHCI_VERSION_1_0         (0x00010000)
 242 #define AHCI_VERSION_1_1         (0x00010100)
 243 #define AHCI_VERSION_1_2         (0x00010200)
 244 #define AHCI_VERSION_1_3         (0x00010300)
 245
 246 #define AHCI_SECTOR_SIZE                (512)
 247 #define ATAPI_SECTOR_SIZE              (2048)
 248
 249 #define AHCI_SIGNATURE_CDROM     (0xeb140101)
 250 #define AHCI_SIGNATURE_DISK      (0x00000101)
 251
 252 /* FIS types */
 253 enum {
 254     REG_H2D_FIS = 0x27,
 255     REG_D2H_FIS = 0x34,
 256     DMA_ACTIVATE_FIS = 0x39,
 257     DMA_SETUP_FIS = 0x41,
 258     DATA_FIS = 0x46,
 259     BIST_ACTIVATE_FIS = 0x58,
 260     PIO_SETUP_FIS = 0x5F,
 261     SDB_FIS = 0xA1
 262 };
 263
 264 /* FIS flags */
 265 #define REG_H2D_FIS_CMD  0x80
 266
 267 /* ATA Commands */
 268 enum {
 269     /* DMA */
 270     CMD_READ_DMA       = 0xC8,
 271     CMD_READ_DMA_EXT   = 0x25,
 272     CMD_WRITE_DMA      = 0xCA,
 273     CMD_WRITE_DMA_EXT  = 0x35,
 274     /* PIO */
 275     CMD_READ_PIO       = 0x20,
 276     CMD_READ_PIO_EXT   = 0x24,
 277     CMD_WRITE_PIO      = 0x30,
 278     CMD_WRITE_PIO_EXT  = 0x34,
 279     /* Misc */
 280     CMD_READ_MAX       = 0xF8,
 281     CMD_READ_MAX_EXT   = 0x27,
 282     CMD_FLUSH_CACHE    = 0xE7,
 283     CMD_IDENTIFY       = 0xEC,
 284     CMD_PACKET         = 0xA0,
 285     CMD_PACKET_ID      = 0xA1,
 286     /* NCQ */
 287     READ_FPDMA_QUEUED  = 0x60,
 288     WRITE_FPDMA_QUEUED = 0x61,
 289 };
 290
 291 /* ATAPI Commands */
 292 enum {
 293     CMD_ATAPI_READ_10 = 0x28,
 294 };
 295
 296 /* AHCI Command Header Flags & Masks*/
 297 #define CMDH_CFL        (0x1F)
 298 #define CMDH_ATAPI      (0x20)
 299 #define CMDH_WRITE      (0x40)
 300 #define CMDH_PREFETCH   (0x80)
 301 #define CMDH_RESET     (0x100)
 302 #define CMDH_BIST      (0x200)
 303 #define CMDH_CLR_BSY   (0x400)
 304 #define CMDH_RES       (0x800)
 305 #define CMDH_PMP      (0xF000)
 306
 307 /* ATA device register masks */
 308 #define ATA_DEVICE_MAGIC 0xA0 /* used in ata1-3 */
 309 #define ATA_DEVICE_LBA   0x40
 310 #define NCQ_DEVICE_MAGIC 0x40 /* for ncq device registers */
 311 #define ATA_DEVICE_DRIVE 0x10
 312 #define ATA_DEVICE_HEAD  0x0F
 313
 314 /*** Structures ***/
 315
 316 typedef struct AHCIPortQState {
 317     uint64_t fb;
 318     uint64_t clb;
 319     uint64_t ctba[32];
 320     uint16_t prdtl[32];
 321     uint8_t next; /** Next Command Slot to Use **/
 322 } AHCIPortQState;
 323
 324 typedef struct AHCIQState {
 325     QOSState *parent;
 326     QPCIDevice *dev;
 327     void *hba_base;
 328     uint64_t barsize;
 329     uint32_t fingerprint;
 330     uint32_t cap;
 331     uint32_t cap2;
 332     AHCIPortQState port[32];
 333 } AHCIQState;
 334
 335 /**
 336  * Generic FIS structure.
 337  */
 338 typedef struct FIS {
 339     uint8_t fis_type;
 340     uint8_t flags;
 341     char data[0];
 342 } __attribute__((__packed__)) FIS;
 343
 344 /**
 345  * Register device-to-host FIS structure.
 346  */
 347 typedef struct RegD2HFIS {
 348     /* DW0 */
 349     uint8_t fis_type;
 350     uint8_t flags;
 351     uint8_t status;
 352     uint8_t error;
 353     /* DW1 */
 354     uint8_t lba_lo[3];
 355     uint8_t device;
 356     /* DW2 */
 357     uint8_t lba_hi[3];
 358     uint8_t res0;
 359     /* DW3 */
 360     uint16_t count;
 361     uint16_t res1;
 362     /* DW4 */
 363     uint32_t res2;
 364 } __attribute__((__packed__)) RegD2HFIS;
 365
 366 /**
 367  * Register device-to-host FIS structure;
 368  * PIO Setup variety.
 369  */
 370 typedef struct PIOSetupFIS {
 371     /* DW0 */
 372     uint8_t fis_type;
 373     uint8_t flags;
 374     uint8_t status;
 375     uint8_t error;
 376     /* DW1 */
 377     uint8_t lba_lo[3];
 378     uint8_t device;
 379     /* DW2 */
 380     uint8_t lba_hi[3];
 381     uint8_t res0;
 382     /* DW3 */
 383     uint16_t count;
 384     uint8_t res1;
 385     uint8_t e_status;
 386     /* DW4 */
 387     uint16_t tx_count;
 388     uint16_t res2;
 389 } __attribute__((__packed__)) PIOSetupFIS;
 390
 391 /**
 392  * Register host-to-device FIS structure.
 393  */
 394 typedef struct RegH2DFIS {
 395     /* DW0 */
 396     uint8_t fis_type;
 397     uint8_t flags;
 398     uint8_t command;
 399     uint8_t feature_low;
 400     /* DW1 */
 401     uint8_t lba_lo[3];
 402     uint8_t device;
 403     /* DW2 */
 404     uint8_t lba_hi[3];
 405     uint8_t feature_high;
 406     /* DW3 */
 407     uint16_t count;
 408     uint8_t icc;
 409     uint8_t control;
 410     /* DW4 */
 411     uint8_t aux[4];
 412 } __attribute__((__packed__)) RegH2DFIS;
 413
 414 /**
 415  * Register host-to-device FIS structure, for NCQ commands.
 416  * Actually just a RegH2DFIS, but with fields repurposed.
 417  * Repurposed fields are annotated below.
 418  */
 419 typedef struct NCQFIS {
 420     /* DW0 */
 421     uint8_t fis_type;
 422     uint8_t flags;
 423     uint8_t command;
 424     uint8_t sector_low; /* H2D: Feature 7:0 */
 425     /* DW1 */
 426     uint8_t lba_lo[3];
 427     uint8_t device;
 428     /* DW2 */
 429     uint8_t lba_hi[3];
 430     uint8_t sector_hi; /* H2D: Feature 15:8 */
 431     /* DW3 */
 432     uint8_t tag;       /* H2D: Count 0:7 */
 433     uint8_t prio;      /* H2D: Count 15:8 */
 434     uint8_t icc;
 435     uint8_t control;
 436     /* DW4 */
 437     uint8_t aux[4];
 438 } __attribute__((__packed__)) NCQFIS;
 439
 440 /**
 441  * Command List entry structure.
 442  * The command list contains between 1-32 of these structures.
 443  */
 444 typedef struct AHCICommandHeader {
 445     uint16_t flags; /* Cmd-Fis-Len, PMP#, and flags. */
 446     uint16_t prdtl; /* Phys Region Desc. Table Length */
 447     uint32_t prdbc; /* Phys Region Desc. Byte Count */
 448     uint64_t ctba;  /* Command Table Descriptor Base Address */
 449     uint32_t res[4];
 450 } __attribute__((__packed__)) AHCICommandHeader;
 451
 452 /**
 453  * Physical Region Descriptor; pointed to by the Command List Header,
 454  * struct ahci_command.
 455  */
 456 typedef struct PRD {
 457     uint64_t dba;  /* Data Base Address */
 458     uint32_t res;  /* Reserved */
 459     uint32_t dbc;  /* Data Byte Count (0-indexed) & Interrupt Flag (bit 2^31) */
 460 } __attribute__((__packed__)) PRD;
 461
 462 /* Opaque, defined within ahci.c */
 463 typedef struct AHCICommand AHCICommand;
 464
 465 /* Options to ahci_exec */
 466 typedef struct AHCIOpts {
 467     size_t size;
 468     unsigned prd_size;
 469     uint64_t lba;
 470     uint64_t buffer;
 471     bool atapi;
 472     bool atapi_dma;
 473     bool error;
 474     int (*pre_cb)(AHCIQState*, AHCICommand*, const struct AHCIOpts *);
 475     int (*mid_cb)(AHCIQState*, AHCICommand*, const struct AHCIOpts *);
 476     int (*post_cb)(AHCIQState*, AHCICommand*, const struct AHCIOpts *);
 477     void *opaque;
 478 } AHCIOpts;
 479
 480 /*** Macro Utilities ***/
 481 #define BITANY(data, mask) (((data) & (mask)) != 0)
 482 #define BITSET(data, mask) (((data) & (mask)) == (mask))
 483 #define BITCLR(data, mask) (((data) & (mask)) == 0)
 484 #define ASSERT_BIT_SET(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
 485 #define ASSERT_BIT_CLEAR(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
 486
 487 /* For calculating how big the PRD table needs to be: */
 488 #define CMD_TBL_SIZ(n) ((0x80 + ((n) * sizeof(PRD)) + 0x7F) & ~0x7F)
 489
 490 /* Helpers for reading/writing AHCI HBA register values */
 491
 492 static inline uint32_t ahci_mread(AHCIQState *ahci, size_t offset)
 493 {
 494     return qpci_io_readl(ahci->dev, ahci->hba_base + offset);
 495 }
 496
 497 static inline void ahci_mwrite(AHCIQState *ahci, size_t offset, uint32_t value)
 498 {
 499     qpci_io_writel(ahci->dev, ahci->hba_base + offset, value);
 500 }
 501
 502 static inline uint32_t ahci_rreg(AHCIQState *ahci, uint32_t reg_num)
 503 {
 504     return ahci_mread(ahci, 4 * reg_num);
 505 }
 506
 507 static inline void ahci_wreg(AHCIQState *ahci, uint32_t reg_num, uint32_t value)
 508 {
 509     ahci_mwrite(ahci, 4 * reg_num, value);
 510 }
 511
 512 static inline void ahci_set(AHCIQState *ahci, uint32_t reg_num, uint32_t mask)
 513 {
 514     ahci_wreg(ahci, reg_num, ahci_rreg(ahci, reg_num) | mask);
 515 }
 516
 517 static inline void ahci_clr(AHCIQState *ahci, uint32_t reg_num, uint32_t mask)
 518 {
 519     ahci_wreg(ahci, reg_num, ahci_rreg(ahci, reg_num) & ~mask);
 520 }
 521
 522 static inline size_t ahci_px_offset(uint8_t port, uint32_t reg_num)
 523 {
 524     return AHCI_PORTS + (HBA_PORT_NUM_REG * port) + reg_num;
 525 }
 526
 527 static inline uint32_t ahci_px_rreg(AHCIQState *ahci, uint8_t port,
 528                                     uint32_t reg_num)
 529 {
 530     return ahci_rreg(ahci, ahci_px_offset(port, reg_num));
 531 }
 532
 533 static inline void ahci_px_wreg(AHCIQState *ahci, uint8_t port,
 534                                 uint32_t reg_num, uint32_t value)
 535 {
 536     ahci_wreg(ahci, ahci_px_offset(port, reg_num), value);
 537 }
 538
 539 static inline void ahci_px_set(AHCIQState *ahci, uint8_t port,
 540                                uint32_t reg_num, uint32_t mask)
 541 {
 542     ahci_px_wreg(ahci, port, reg_num,
 543                  ahci_px_rreg(ahci, port, reg_num) | mask);
 544 }
 545
 546 static inline void ahci_px_clr(AHCIQState *ahci, uint8_t port,
 547                                uint32_t reg_num, uint32_t mask)
 548 {
 549     ahci_px_wreg(ahci, port, reg_num,
 550                  ahci_px_rreg(ahci, port, reg_num) & ~mask);
 551 }
 552
 553 /*** Prototypes ***/
 554 uint64_t ahci_alloc(AHCIQState *ahci, size_t bytes);
 555 void ahci_free(AHCIQState *ahci, uint64_t addr);
 556 QPCIDevice *get_ahci_device(uint32_t *fingerprint);
 557 void free_ahci_device(QPCIDevice *dev);
 558 void ahci_clean_mem(AHCIQState *ahci);
 559 void ahci_pci_enable(AHCIQState *ahci);
 560 void start_ahci_device(AHCIQState *ahci);
 561 void ahci_hba_enable(AHCIQState *ahci);
 562 unsigned ahci_port_select(AHCIQState *ahci);
 563 void ahci_port_clear(AHCIQState *ahci, uint8_t port);
 564 void ahci_port_check_error(AHCIQState *ahci, uint8_t port);
 565 void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port,
 566                                 uint32_t intr_mask);
 567 void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot);
 568 void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot);
 569 void ahci_port_check_pio_sanity(AHCIQState *ahci, uint8_t port,
 570                                 uint8_t slot, size_t buffsize);
 571 void ahci_port_check_cmd_sanity(AHCIQState *ahci, AHCICommand *cmd);
 572 void ahci_get_command_header(AHCIQState *ahci, uint8_t port,
 573                              uint8_t slot, AHCICommandHeader *cmd);
 574 void ahci_set_command_header(AHCIQState *ahci, uint8_t port,
 575                              uint8_t slot, AHCICommandHeader *cmd);
 576 void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot);
 577 void ahci_write_fis(AHCIQState *ahci, AHCICommand *cmd);
 578 unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port);
 579 unsigned size_to_prdtl(unsigned bytes, unsigned bytes_per_prd);
 580 void ahci_guest_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
 581                    uint64_t gbuffer, size_t size, uint64_t sector);
 582 AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
 583                                 uint64_t gbuffer, size_t size, uint64_t sector);
 584 void ahci_guest_io_resume(AHCIQState *ahci, AHCICommand *cmd);
 585 void ahci_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
 586              void *buffer, size_t bufsize, uint64_t sector);
 587 void ahci_exec(AHCIQState *ahci, uint8_t port,
 588                uint8_t op, const AHCIOpts *opts);
 589
 590 /* Command Lifecycle */
 591 AHCICommand *ahci_command_create(uint8_t command_name);
 592 AHCICommand *ahci_atapi_command_create(uint8_t scsi_cmd);
 593 void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port);
 594 void ahci_command_issue(AHCIQState *ahci, AHCICommand *cmd);
 595 void ahci_command_issue_async(AHCIQState *ahci, AHCICommand *cmd);
 596 void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd);
 597 void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd);
 598 void ahci_command_free(AHCICommand *cmd);
 599
 600 /* Command adjustments */
 601 void ahci_command_set_flags(AHCICommand *cmd, uint16_t cmdh_flags);
 602 void ahci_command_clr_flags(AHCICommand *cmd, uint16_t cmdh_flags);
 603 void ahci_command_set_offset(AHCICommand *cmd, uint64_t lba_sect);
 604 void ahci_command_set_buffer(AHCICommand *cmd, uint64_t buffer);
 605 void ahci_command_set_size(AHCICommand *cmd, uint64_t xbytes);
 606 void ahci_command_set_prd_size(AHCICommand *cmd, unsigned prd_size);
 607 void ahci_command_set_sizes(AHCICommand *cmd, uint64_t xbytes,
 608                             unsigned prd_size);
 609 void ahci_command_set_acmd(AHCICommand *cmd, void *acmd);
 610 void ahci_command_enable_atapi_dma(AHCICommand *cmd);
 611 void ahci_command_adjust(AHCICommand *cmd, uint64_t lba_sect, uint64_t gbuffer,
 612                          uint64_t xbytes, unsigned prd_size);
 613
 614 /* Command Misc */
 615 uint8_t ahci_command_slot(AHCICommand *cmd);
 616 bool is_atapi(AHCIQState *ahci, uint8_t port);
 617
 618 #endif