hw/arm/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu-common.h"
  27 #include "cpu.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/arm/boot.h"
  30 #include "hw/arm/primecell.h"
  31 #include "hw/net/lan9118.h"
  32 #include "hw/i2c/i2c.h"
  33 #include "net/net.h"
  34 #include "sysemu/sysemu.h"
  35 #include "hw/boards.h"
  36 #include "hw/loader.h"
  37 #include "exec/address-spaces.h"
  38 #include "hw/block/flash.h"
  39 #include "sysemu/device_tree.h"
  40 #include "qemu/error-report.h"
  41 #include <libfdt.h>
  42 #include "hw/char/pl011.h"
  43 #include "hw/cpu/a9mpcore.h"
  44 #include "hw/cpu/a15mpcore.h"
  45
  46 #define VEXPRESS_BOARD_ID 0x8e0
  47 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
  48 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
  49
  50 /* Number of virtio transports to create (0..8; limited by
  51  * number of available IRQ lines).
  52  */
  53 #define NUM_VIRTIO_TRANSPORTS 4
  54
  55 /* Address maps for peripherals:
  56  * the Versatile Express motherboard has two possible maps,
  57  * the "legacy" one (used for A9) and the "Cortex-A Series"
  58  * map (used for newer cores).
  59  * Individual daughterboards can also have different maps for
  60  * their peripherals.
  61  */
  62
  63 enum {
  64     VE_SYSREGS,
  65     VE_SP810,
  66     VE_SERIALPCI,
  67     VE_PL041,
  68     VE_MMCI,
  69     VE_KMI0,
  70     VE_KMI1,
  71     VE_UART0,
  72     VE_UART1,
  73     VE_UART2,
  74     VE_UART3,
  75     VE_WDT,
  76     VE_TIMER01,
  77     VE_TIMER23,
  78     VE_SERIALDVI,
  79     VE_RTC,
  80     VE_COMPACTFLASH,
  81     VE_CLCD,
  82     VE_NORFLASH0,
  83     VE_NORFLASH1,
  84     VE_NORFLASHALIAS,
  85     VE_SRAM,
  86     VE_VIDEORAM,
  87     VE_ETHERNET,
  88     VE_USB,
  89     VE_DAPROM,
  90     VE_VIRTIO,
  91 };
  92
  93 static hwaddr motherboard_legacy_map[] = {
  94     [VE_NORFLASHALIAS] = 0,
  95     /* CS7: 0x10000000 .. 0x10020000 */
  96     [VE_SYSREGS] = 0x10000000,
  97     [VE_SP810] = 0x10001000,
  98     [VE_SERIALPCI] = 0x10002000,
  99     [VE_PL041] = 0x10004000,
 100     [VE_MMCI] = 0x10005000,
 101     [VE_KMI0] = 0x10006000,
 102     [VE_KMI1] = 0x10007000,
 103     [VE_UART0] = 0x10009000,
 104     [VE_UART1] = 0x1000a000,
 105     [VE_UART2] = 0x1000b000,
 106     [VE_UART3] = 0x1000c000,
 107     [VE_WDT] = 0x1000f000,
 108     [VE_TIMER01] = 0x10011000,
 109     [VE_TIMER23] = 0x10012000,
 110     [VE_VIRTIO] = 0x10013000,
 111     [VE_SERIALDVI] = 0x10016000,
 112     [VE_RTC] = 0x10017000,
 113     [VE_COMPACTFLASH] = 0x1001a000,
 114     [VE_CLCD] = 0x1001f000,
 115     /* CS0: 0x40000000 .. 0x44000000 */
 116     [VE_NORFLASH0] = 0x40000000,
 117     /* CS1: 0x44000000 .. 0x48000000 */
 118     [VE_NORFLASH1] = 0x44000000,
 119     /* CS2: 0x48000000 .. 0x4a000000 */
 120     [VE_SRAM] = 0x48000000,
 121     /* CS3: 0x4c000000 .. 0x50000000 */
 122     [VE_VIDEORAM] = 0x4c000000,
 123     [VE_ETHERNET] = 0x4e000000,
 124     [VE_USB] = 0x4f000000,
 125 };
 126
 127 static hwaddr motherboard_aseries_map[] = {
 128     [VE_NORFLASHALIAS] = 0,
 129     /* CS0: 0x08000000 .. 0x0c000000 */
 130     [VE_NORFLASH0] = 0x08000000,
 131     /* CS4: 0x0c000000 .. 0x10000000 */
 132     [VE_NORFLASH1] = 0x0c000000,
 133     /* CS5: 0x10000000 .. 0x14000000 */
 134     /* CS1: 0x14000000 .. 0x18000000 */
 135     [VE_SRAM] = 0x14000000,
 136     /* CS2: 0x18000000 .. 0x1c000000 */
 137     [VE_VIDEORAM] = 0x18000000,
 138     [VE_ETHERNET] = 0x1a000000,
 139     [VE_USB] = 0x1b000000,
 140     /* CS3: 0x1c000000 .. 0x20000000 */
 141     [VE_DAPROM] = 0x1c000000,
 142     [VE_SYSREGS] = 0x1c010000,
 143     [VE_SP810] = 0x1c020000,
 144     [VE_SERIALPCI] = 0x1c030000,
 145     [VE_PL041] = 0x1c040000,
 146     [VE_MMCI] = 0x1c050000,
 147     [VE_KMI0] = 0x1c060000,
 148     [VE_KMI1] = 0x1c070000,
 149     [VE_UART0] = 0x1c090000,
 150     [VE_UART1] = 0x1c0a0000,
 151     [VE_UART2] = 0x1c0b0000,
 152     [VE_UART3] = 0x1c0c0000,
 153     [VE_WDT] = 0x1c0f0000,
 154     [VE_TIMER01] = 0x1c110000,
 155     [VE_TIMER23] = 0x1c120000,
 156     [VE_VIRTIO] = 0x1c130000,
 157     [VE_SERIALDVI] = 0x1c160000,
 158     [VE_RTC] = 0x1c170000,
 159     [VE_COMPACTFLASH] = 0x1c1a0000,
 160     [VE_CLCD] = 0x1c1f0000,
 161 };
 162
 163 /* Structure defining the peculiarities of a specific daughterboard */
 164
 165 typedef struct VEDBoardInfo VEDBoardInfo;
 166
 167 typedef struct {
 168     MachineClass parent;
 169     VEDBoardInfo *daughterboard;
 170 } VexpressMachineClass;
 171
 172 typedef struct {
 173     MachineState parent;
 174     bool secure;
 175     bool virt;
 176 } VexpressMachineState;
 177
 178 #define TYPE_VEXPRESS_MACHINE   "vexpress"
 179 #define TYPE_VEXPRESS_A9_MACHINE   MACHINE_TYPE_NAME("vexpress-a9")
 180 #define TYPE_VEXPRESS_A15_MACHINE   MACHINE_TYPE_NAME("vexpress-a15")
 181 #define VEXPRESS_MACHINE(obj) \
 182     OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE)
 183 #define VEXPRESS_MACHINE_GET_CLASS(obj) \
 184     OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE)
 185 #define VEXPRESS_MACHINE_CLASS(klass) \
 186     OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE)
 187
 188 typedef void DBoardInitFn(const VexpressMachineState *machine,
 189                           ram_addr_t ram_size,
 190                           const char *cpu_type,
 191                           qemu_irq *pic);
 192
 193 struct VEDBoardInfo {
 194     struct arm_boot_info bootinfo;
 195     const hwaddr *motherboard_map;
 196     hwaddr loader_start;
 197     const hwaddr gic_cpu_if_addr;
 198     uint32_t proc_id;
 199     uint32_t num_voltage_sensors;
 200     const uint32_t *voltages;
 201     uint32_t num_clocks;
 202     const uint32_t *clocks;
 203     DBoardInitFn *init;
 204 };
 205
 206 static void init_cpus(MachineState *ms, const char *cpu_type,
 207                       const char *privdev, hwaddr periphbase,
 208                       qemu_irq *pic, bool secure, bool virt)
 209 {
 210     DeviceState *dev;
 211     SysBusDevice *busdev;
 212     int n;
 213     unsigned int smp_cpus = ms->smp.cpus;
 214
 215     /* Create the actual CPUs */
 216     for (n = 0; n < smp_cpus; n++) {
 217         Object *cpuobj = object_new(cpu_type);
 218
 219         if (!secure) {
 220             object_property_set_bool(cpuobj, false, "has_el3", NULL);
 221         }
 222         if (!virt) {
 223             if (object_property_find(cpuobj, "has_el2", NULL)) {
 224                 object_property_set_bool(cpuobj, false, "has_el2", NULL);
 225             }
 226         }
 227
 228         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 229             object_property_set_int(cpuobj, periphbase,
 230                                     "reset-cbar", &error_abort);
 231         }
 232         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 233     }
 234
 235     /* Create the private peripheral devices (including the GIC);
 236      * this must happen after the CPUs are created because a15mpcore_priv
 237      * wires itself up to the CPU's generic_timer gpio out lines.
 238      */
 239     dev = qdev_new(privdev);
 240     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 241     busdev = SYS_BUS_DEVICE(dev);
 242     sysbus_realize_and_unref(busdev, &error_fatal);
 243     sysbus_mmio_map(busdev, 0, periphbase);
 244
 245     /* Interrupts [42:0] are from the motherboard;
 246      * [47:43] are reserved; [63:48] are daughterboard
 247      * peripherals. Note that some documentation numbers
 248      * external interrupts starting from 32 (because there
 249      * are internal interrupts 0..31).
 250      */
 251     for (n = 0; n < 64; n++) {
 252         pic[n] = qdev_get_gpio_in(dev, n);
 253     }
 254
 255     /* Connect the CPUs to the GIC */
 256     for (n = 0; n < smp_cpus; n++) {
 257         DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
 258
 259         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 260         sysbus_connect_irq(busdev, n + smp_cpus,
 261                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 262         sysbus_connect_irq(busdev, n + 2 * smp_cpus,
 263                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
 264         sysbus_connect_irq(busdev, n + 3 * smp_cpus,
 265                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
 266     }
 267 }
 268
 269 static void a9_daughterboard_init(const VexpressMachineState *vms,
 270                                   ram_addr_t ram_size,
 271                                   const char *cpu_type,
 272                                   qemu_irq *pic)
 273 {
 274     MachineState *machine = MACHINE(vms);
 275     MemoryRegion *sysmem = get_system_memory();
 276     MemoryRegion *lowram = g_new(MemoryRegion, 1);
 277     ram_addr_t low_ram_size;
 278
 279     if (ram_size > 0x40000000) {
 280         /* 1GB is the maximum the address space permits */
 281         error_report("vexpress-a9: cannot model more than 1GB RAM");
 282         exit(1);
 283     }
 284
 285     low_ram_size = ram_size;
 286     if (low_ram_size > 0x4000000) {
 287         low_ram_size = 0x4000000;
 288     }
 289     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
 290      * address space should in theory be remappable to various
 291      * things including ROM or RAM; we always map the RAM there.
 292      */
 293     memory_region_init_alias(lowram, NULL, "vexpress.lowmem", machine->ram,
 294                              0, low_ram_size);
 295     memory_region_add_subregion(sysmem, 0x0, lowram);
 296     memory_region_add_subregion(sysmem, 0x60000000, machine->ram);
 297
 298     /* 0x1e000000 A9MPCore (SCU) private memory region */
 299     init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
 300               vms->secure, vms->virt);
 301
 302     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 303
 304     /* 0x10020000 PL111 CLCD (daughterboard) */
 305     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 306
 307     /* 0x10060000 AXI RAM */
 308     /* 0x100e0000 PL341 Dynamic Memory Controller */
 309     /* 0x100e1000 PL354 Static Memory Controller */
 310     /* 0x100e2000 System Configuration Controller */
 311
 312     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 313     /* 0x100e5000 SP805 Watchdog module */
 314     /* 0x100e6000 BP147 TrustZone Protection Controller */
 315     /* 0x100e9000 PL301 'Fast' AXI matrix */
 316     /* 0x100ea000 PL301 'Slow' AXI matrix */
 317     /* 0x100ec000 TrustZone Address Space Controller */
 318     /* 0x10200000 CoreSight debug APB */
 319     /* 0x1e00a000 PL310 L2 Cache Controller */
 320     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 321 }
 322
 323 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
 324  * values are in microvolts.
 325  */
 326 static const uint32_t a9_voltages[] = {
 327     1000000, /* VD10 : 1.0V : SoC internal logic voltage */
 328     1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
 329     1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
 330     1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
 331     900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
 332     3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
 333 };
 334
 335 /* Reset values for daughterboard oscillators (in Hz) */
 336 static const uint32_t a9_clocks[] = {
 337     45000000, /* AMBA AXI ACLK: 45MHz */
 338     23750000, /* daughterboard CLCD clock: 23.75MHz */
 339     66670000, /* Test chip reference clock: 66.67MHz */
 340 };
 341
 342 static VEDBoardInfo a9_daughterboard = {
 343     .motherboard_map = motherboard_legacy_map,
 344     .loader_start = 0x60000000,
 345     .gic_cpu_if_addr = 0x1e000100,
 346     .proc_id = 0x0c000191,
 347     .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
 348     .voltages = a9_voltages,
 349     .num_clocks = ARRAY_SIZE(a9_clocks),
 350     .clocks = a9_clocks,
 351     .init = a9_daughterboard_init,
 352 };
 353
 354 static void a15_daughterboard_init(const VexpressMachineState *vms,
 355                                    ram_addr_t ram_size,
 356                                    const char *cpu_type,
 357                                    qemu_irq *pic)
 358 {
 359     MachineState *machine = MACHINE(vms);
 360     MemoryRegion *sysmem = get_system_memory();
 361     MemoryRegion *sram = g_new(MemoryRegion, 1);
 362
 363     {
 364         /* We have to use a separate 64 bit variable here to avoid the gcc
 365          * "comparison is always false due to limited range of data type"
 366          * warning if we are on a host where ram_addr_t is 32 bits.
 367          */
 368         uint64_t rsz = ram_size;
 369         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
 370             error_report("vexpress-a15: cannot model more than 30GB RAM");
 371             exit(1);
 372         }
 373     }
 374
 375     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
 376     memory_region_add_subregion(sysmem, 0x80000000, machine->ram);
 377
 378     /* 0x2c000000 A15MPCore private memory region (GIC) */
 379     init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV,
 380               0x2c000000, pic, vms->secure, vms->virt);
 381
 382     /* A15 daughterboard peripherals: */
 383
 384     /* 0x20000000: CoreSight interfaces: not modelled */
 385     /* 0x2a000000: PL301 AXI interconnect: not modelled */
 386     /* 0x2a420000: SCC: not modelled */
 387     /* 0x2a430000: system counter: not modelled */
 388     /* 0x2b000000: HDLCD controller: not modelled */
 389     /* 0x2b060000: SP805 watchdog: not modelled */
 390     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
 391     /* 0x2e000000: system SRAM */
 392     memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000,
 393                            &error_fatal);
 394     memory_region_add_subregion(sysmem, 0x2e000000, sram);
 395
 396     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
 397     /* 0x7ffd0000: PL354 static memory controller: not modelled */
 398 }
 399
 400 static const uint32_t a15_voltages[] = {
 401     900000, /* Vcore: 0.9V : CPU core voltage */
 402 };
 403
 404 static const uint32_t a15_clocks[] = {
 405     60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
 406     0, /* OSCCLK1: reserved */
 407     0, /* OSCCLK2: reserved */
 408     0, /* OSCCLK3: reserved */
 409     40000000, /* OSCCLK4: 40MHz : external AXI master clock */
 410     23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
 411     50000000, /* OSCCLK6: 50MHz : static memory controller clock */
 412     60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
 413     40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
 414 };
 415
 416 static VEDBoardInfo a15_daughterboard = {
 417     .motherboard_map = motherboard_aseries_map,
 418     .loader_start = 0x80000000,
 419     .gic_cpu_if_addr = 0x2c002000,
 420     .proc_id = 0x14000237,
 421     .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
 422     .voltages = a15_voltages,
 423     .num_clocks = ARRAY_SIZE(a15_clocks),
 424     .clocks = a15_clocks,
 425     .init = a15_daughterboard_init,
 426 };
 427
 428 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
 429                                 hwaddr addr, hwaddr size, uint32_t intc,
 430                                 int irq)
 431 {
 432     /* Add a virtio_mmio node to the device tree blob:
 433      *   virtio_mmio@ADDRESS {
 434      *       compatible = "virtio,mmio";
 435      *       reg = <ADDRESS, SIZE>;
 436      *       interrupt-parent = <&intc>;
 437      *       interrupts = <0, irq, 1>;
 438      *   }
 439      * (Note that the format of the interrupts property is dependent on the
 440      * interrupt controller that interrupt-parent points to; these are for
 441      * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
 442      */
 443     int rc;
 444     char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
 445
 446     rc = qemu_fdt_add_subnode(fdt, nodename);
 447     rc |= qemu_fdt_setprop_string(fdt, nodename,
 448                                   "compatible", "virtio,mmio");
 449     rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
 450                                        acells, addr, scells, size);
 451     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
 452     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
 453     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
 454     g_free(nodename);
 455     if (rc) {
 456         return -1;
 457     }
 458     return 0;
 459 }
 460
 461 static uint32_t find_int_controller(void *fdt)
 462 {
 463     /* Find the FDT node corresponding to the interrupt controller
 464      * for virtio-mmio devices. We do this by scanning the fdt for
 465      * a node with the right compatibility, since we know there is
 466      * only one GIC on a vexpress board.
 467      * We return the phandle of the node, or 0 if none was found.
 468      */
 469     const char *compat = "arm,cortex-a9-gic";
 470     int offset;
 471
 472     offset = fdt_node_offset_by_compatible(fdt, -1, compat);
 473     if (offset >= 0) {
 474         return fdt_get_phandle(fdt, offset);
 475     }
 476     return 0;
 477 }
 478
 479 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
 480 {
 481     uint32_t acells, scells, intc;
 482     const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
 483
 484     acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
 485                                    NULL, &error_fatal);
 486     scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
 487                                    NULL, &error_fatal);
 488     intc = find_int_controller(fdt);
 489     if (!intc) {
 490         /* Not fatal, we just won't provide virtio. This will
 491          * happen with older device tree blobs.
 492          */
 493         warn_report("couldn't find interrupt controller in "
 494                     "dtb; will not include virtio-mmio devices in the dtb");
 495     } else {
 496         int i;
 497         const hwaddr *map = daughterboard->motherboard_map;
 498
 499         /* We iterate backwards here because adding nodes
 500          * to the dtb puts them in last-first.
 501          */
 502         for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
 503             add_virtio_mmio_node(fdt, acells, scells,
 504                                  map[VE_VIRTIO] + 0x200 * i,
 505                                  0x200, intc, 40 + i);
 506         }
 507     }
 508 }
 509
 510
 511 /* Open code a private version of pflash registration since we
 512  * need to set non-default device width for VExpress platform.
 513  */
 514 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
 515                                              DriveInfo *di)
 516 {
 517     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
 518
 519     if (di) {
 520         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di));
 521     }
 522
 523     qdev_prop_set_uint32(dev, "num-blocks",
 524                          VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
 525     qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
 526     qdev_prop_set_uint8(dev, "width", 4);
 527     qdev_prop_set_uint8(dev, "device-width", 2);
 528     qdev_prop_set_bit(dev, "big-endian", false);
 529     qdev_prop_set_uint16(dev, "id0", 0x89);
 530     qdev_prop_set_uint16(dev, "id1", 0x18);
 531     qdev_prop_set_uint16(dev, "id2", 0x00);
 532     qdev_prop_set_uint16(dev, "id3", 0x00);
 533     qdev_prop_set_string(dev, "name", name);
 534     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 535
 536     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 537     return PFLASH_CFI01(dev);
 538 }
 539
 540 static void vexpress_common_init(MachineState *machine)
 541 {
 542     VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
 543     VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
 544     VEDBoardInfo *daughterboard = vmc->daughterboard;
 545     DeviceState *dev, *sysctl, *pl041;
 546     qemu_irq pic[64];
 547     uint32_t sys_id;
 548     DriveInfo *dinfo;
 549     PFlashCFI01 *pflash0;
 550     I2CBus *i2c;
 551     ram_addr_t vram_size, sram_size;
 552     MemoryRegion *sysmem = get_system_memory();
 553     MemoryRegion *vram = g_new(MemoryRegion, 1);
 554     MemoryRegion *sram = g_new(MemoryRegion, 1);
 555     MemoryRegion *flashalias = g_new(MemoryRegion, 1);
 556     MemoryRegion *flash0mem;
 557     const hwaddr *map = daughterboard->motherboard_map;
 558     int i;
 559
 560     daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
 561
 562     /*
 563      * If a bios file was provided, attempt to map it into memory
 564      */
 565     if (bios_name) {
 566         char *fn;
 567         int image_size;
 568
 569         if (drive_get(IF_PFLASH, 0, 0)) {
 570             error_report("The contents of the first flash device may be "
 571                          "specified with -bios or with -drive if=pflash... "
 572                          "but you cannot use both options at once");
 573             exit(1);
 574         }
 575         fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 576         if (!fn) {
 577             error_report("Could not find ROM image '%s'", bios_name);
 578             exit(1);
 579         }
 580         image_size = load_image_targphys(fn, map[VE_NORFLASH0],
 581                                          VEXPRESS_FLASH_SIZE);
 582         g_free(fn);
 583         if (image_size < 0) {
 584             error_report("Could not load ROM image '%s'", bios_name);
 585             exit(1);
 586         }
 587     }
 588
 589     /* Motherboard peripherals: the wiring is the same but the
 590      * addresses vary between the legacy and A-Series memory maps.
 591      */
 592
 593     sys_id = 0x1190f500;
 594
 595     sysctl = qdev_new("realview_sysctl");
 596     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 597     qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
 598     qdev_prop_set_uint32(sysctl, "len-db-voltage",
 599                          daughterboard->num_voltage_sensors);
 600     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
 601         char *propname = g_strdup_printf("db-voltage[%d]", i);
 602         qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
 603         g_free(propname);
 604     }
 605     qdev_prop_set_uint32(sysctl, "len-db-clock",
 606                          daughterboard->num_clocks);
 607     for (i = 0; i < daughterboard->num_clocks; i++) {
 608         char *propname = g_strdup_printf("db-clock[%d]", i);
 609         qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
 610         g_free(propname);
 611     }
 612     sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
 613     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
 614
 615     /* VE_SP810: not modelled */
 616     /* VE_SERIALPCI: not modelled */
 617
 618     pl041 = qdev_new("pl041");
 619     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 620     sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
 621     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
 622     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
 623
 624     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
 625     /* Wire up MMC card detect and read-only signals */
 626     qdev_connect_gpio_out(dev, 0,
 627                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 628     qdev_connect_gpio_out(dev, 1,
 629                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 630
 631     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
 632     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
 633
 634     pl011_create(map[VE_UART0], pic[5], serial_hd(0));
 635     pl011_create(map[VE_UART1], pic[6], serial_hd(1));
 636     pl011_create(map[VE_UART2], pic[7], serial_hd(2));
 637     pl011_create(map[VE_UART3], pic[8], serial_hd(3));
 638
 639     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
 640     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 641
 642     dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL);
 643     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 644     i2c_create_slave(i2c, "sii9022", 0x39);
 645
 646     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 647
 648     /* VE_COMPACTFLASH: not modelled */
 649
 650     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 651
 652     dinfo = drive_get_next(IF_PFLASH);
 653     pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
 654                                        dinfo);
 655     if (!pflash0) {
 656         error_report("vexpress: error registering flash 0");
 657         exit(1);
 658     }
 659
 660     if (map[VE_NORFLASHALIAS] != -1) {
 661         /* Map flash 0 as an alias into low memory */
 662         flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
 663         memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
 664                                  flash0mem, 0, VEXPRESS_FLASH_SIZE);
 665         memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
 666     }
 667
 668     dinfo = drive_get_next(IF_PFLASH);
 669     if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
 670                                   dinfo)) {
 671         error_report("vexpress: error registering flash 1");
 672         exit(1);
 673     }
 674
 675     sram_size = 0x2000000;
 676     memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
 677                            &error_fatal);
 678     memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
 679
 680     vram_size = 0x800000;
 681     memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size,
 682                            &error_fatal);
 683     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
 684
 685     /* 0x4e000000 LAN9118 Ethernet */
 686     if (nd_table[0].used) {
 687         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
 688     }
 689
 690     /* VE_USB: not modelled */
 691
 692     /* VE_DAPROM: not modelled */
 693
 694     /* Create mmio transports, so the user can create virtio backends
 695      * (which will be automatically plugged in to the transports). If
 696      * no backend is created the transport will just sit harmlessly idle.
 697      */
 698     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
 699         sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
 700                              pic[40 + i]);
 701     }
 702
 703     daughterboard->bootinfo.ram_size = machine->ram_size;
 704     daughterboard->bootinfo.nb_cpus = machine->smp.cpus;
 705     daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
 706     daughterboard->bootinfo.loader_start = daughterboard->loader_start;
 707     daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
 708     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
 709     daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
 710     daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
 711     /* When booting Linux we should be in secure state if the CPU has one. */
 712     daughterboard->bootinfo.secure_boot = vms->secure;
 713     arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo);
 714 }
 715
 716 static bool vexpress_get_secure(Object *obj, Error **errp)
 717 {
 718     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 719
 720     return vms->secure;
 721 }
 722
 723 static void vexpress_set_secure(Object *obj, bool value, Error **errp)
 724 {
 725     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 726
 727     vms->secure = value;
 728 }
 729
 730 static bool vexpress_get_virt(Object *obj, Error **errp)
 731 {
 732     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 733
 734     return vms->virt;
 735 }
 736
 737 static void vexpress_set_virt(Object *obj, bool value, Error **errp)
 738 {
 739     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 740
 741     vms->virt = value;
 742 }
 743
 744 static void vexpress_instance_init(Object *obj)
 745 {
 746     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 747
 748     /* EL3 is enabled by default on vexpress */
 749     vms->secure = true;
 750     object_property_add_bool(obj, "secure", vexpress_get_secure,
 751                              vexpress_set_secure);
 752     object_property_set_description(obj, "secure",
 753                                     "Set on/off to enable/disable the ARM "
 754                                     "Security Extensions (TrustZone)");
 755 }
 756
 757 static void vexpress_a15_instance_init(Object *obj)
 758 {
 759     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 760
 761     /*
 762      * For the vexpress-a15, EL2 is by default enabled if EL3 is,
 763      * but can also be specifically set to on or off.
 764      */
 765     vms->virt = true;
 766     object_property_add_bool(obj, "virtualization", vexpress_get_virt,
 767                              vexpress_set_virt);
 768     object_property_set_description(obj, "virtualization",
 769                                     "Set on/off to enable/disable the ARM "
 770                                     "Virtualization Extensions "
 771                                     "(defaults to same as 'secure')");
 772 }
 773
 774 static void vexpress_a9_instance_init(Object *obj)
 775 {
 776     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 777
 778     /* The A9 doesn't have the virt extensions */
 779     vms->virt = false;
 780 }
 781
 782 static void vexpress_class_init(ObjectClass *oc, void *data)
 783 {
 784     MachineClass *mc = MACHINE_CLASS(oc);
 785
 786     mc->desc = "ARM Versatile Express";
 787     mc->init = vexpress_common_init;
 788     mc->max_cpus = 4;
 789     mc->ignore_memory_transaction_failures = true;
 790     mc->default_ram_id = "vexpress.highmem";
 791 }
 792
 793 static void vexpress_a9_class_init(ObjectClass *oc, void *data)
 794 {
 795     MachineClass *mc = MACHINE_CLASS(oc);
 796     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 797
 798     mc->desc = "ARM Versatile Express for Cortex-A9";
 799     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 800
 801     vmc->daughterboard = &a9_daughterboard;
 802 }
 803
 804 static void vexpress_a15_class_init(ObjectClass *oc, void *data)
 805 {
 806     MachineClass *mc = MACHINE_CLASS(oc);
 807     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 808
 809     mc->desc = "ARM Versatile Express for Cortex-A15";
 810     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
 811
 812     vmc->daughterboard = &a15_daughterboard;
 813 }
 814
 815 static const TypeInfo vexpress_info = {
 816     .name = TYPE_VEXPRESS_MACHINE,
 817     .parent = TYPE_MACHINE,
 818     .abstract = true,
 819     .instance_size = sizeof(VexpressMachineState),
 820     .instance_init = vexpress_instance_init,
 821     .class_size = sizeof(VexpressMachineClass),
 822     .class_init = vexpress_class_init,
 823 };
 824
 825 static const TypeInfo vexpress_a9_info = {
 826     .name = TYPE_VEXPRESS_A9_MACHINE,
 827     .parent = TYPE_VEXPRESS_MACHINE,
 828     .class_init = vexpress_a9_class_init,
 829     .instance_init = vexpress_a9_instance_init,
 830 };
 831
 832 static const TypeInfo vexpress_a15_info = {
 833     .name = TYPE_VEXPRESS_A15_MACHINE,
 834     .parent = TYPE_VEXPRESS_MACHINE,
 835     .class_init = vexpress_a15_class_init,
 836     .instance_init = vexpress_a15_instance_init,
 837 };
 838
 839 static void vexpress_machine_init(void)
 840 {
 841     type_register_static(&vexpress_info);
 842     type_register_static(&vexpress_a9_info);
 843     type_register_static(&vexpress_a15_info);
 844 }
 845
 846 type_init(vexpress_machine_init);