target-tilegx/cpu.c

   1 /*
   2  * QEMU TILE-Gx CPU
   3  *
   4  *  Copyright (c) 2015 Chen Gang
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "migration/vmstate.h"
  26 #include "linux-user/syscall_defs.h"
  27
  28 static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
  29                                   fprintf_function cpu_fprintf, int flags)
  30 {
  31     static const char * const reg_names[TILEGX_R_COUNT] = {
  32          "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
  33          "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  34         "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  35         "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
  36         "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  37         "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
  38         "r48", "r49", "r50", "r51",  "bp",  "tp",  "sp",  "lr"
  39     };
  40
  41     TileGXCPU *cpu = TILEGX_CPU(cs);
  42     CPUTLGState *env = &cpu->env;
  43     int i;
  44
  45     for (i = 0; i < TILEGX_R_COUNT; i++) {
  46         cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
  47                     reg_names[i], env->regs[i],
  48                     (i % 4) == 3 ? "\n" : " ");
  49     }
  50     cpu_fprintf(f, "PC  " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
  51                 env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
  52 }
  53
  54 TileGXCPU *cpu_tilegx_init(const char *cpu_model)
  55 {
  56     TileGXCPU *cpu;
  57
  58     cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
  59
  60     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
  61
  62     return cpu;
  63 }
  64
  65 static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
  66 {
  67     TileGXCPU *cpu = TILEGX_CPU(cs);
  68
  69     cpu->env.pc = value;
  70 }
  71
  72 static bool tilegx_cpu_has_work(CPUState *cs)
  73 {
  74     return true;
  75 }
  76
  77 static void tilegx_cpu_reset(CPUState *s)
  78 {
  79     TileGXCPU *cpu = TILEGX_CPU(s);
  80     TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
  81     CPUTLGState *env = &cpu->env;
  82
  83     tcc->parent_reset(s);
  84
  85     memset(env, 0, sizeof(CPUTLGState));
  86     tlb_flush(s, 1);
  87 }
  88
  89 static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
  90 {
  91     CPUState *cs = CPU(dev);
  92     TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
  93
  94     cpu_reset(cs);
  95     qemu_init_vcpu(cs);
  96
  97     tcc->parent_realize(dev, errp);
  98 }
  99
 100 static void tilegx_cpu_initfn(Object *obj)
 101 {
 102     CPUState *cs = CPU(obj);
 103     TileGXCPU *cpu = TILEGX_CPU(obj);
 104     CPUTLGState *env = &cpu->env;
 105     static bool tcg_initialized;
 106
 107     cs->env_ptr = env;
 108     cpu_exec_init(cs, &error_abort);
 109
 110     if (tcg_enabled() && !tcg_initialized) {
 111         tcg_initialized = true;
 112         tilegx_tcg_init();
 113     }
 114 }
 115
 116 static void tilegx_cpu_do_interrupt(CPUState *cs)
 117 {
 118     cs->exception_index = -1;
 119 }
 120
 121 static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 122                                        int mmu_idx)
 123 {
 124     TileGXCPU *cpu = TILEGX_CPU(cs);
 125
 126     /* The sigcode field will be filled in by do_signal in main.c.  */
 127     cs->exception_index = TILEGX_EXCP_SIGNAL;
 128     cpu->env.excaddr = address;
 129     cpu->env.signo = TARGET_SIGSEGV;
 130     cpu->env.sigcode = 0;
 131
 132     return 1;
 133 }
 134
 135 static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 136 {
 137     if (interrupt_request & CPU_INTERRUPT_HARD) {
 138         tilegx_cpu_do_interrupt(cs);
 139         return true;
 140     }
 141     return false;
 142 }
 143
 144 static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
 145 {
 146     DeviceClass *dc = DEVICE_CLASS(oc);
 147     CPUClass *cc = CPU_CLASS(oc);
 148     TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
 149
 150     tcc->parent_realize = dc->realize;
 151     dc->realize = tilegx_cpu_realizefn;
 152
 153     tcc->parent_reset = cc->reset;
 154     cc->reset = tilegx_cpu_reset;
 155
 156     cc->has_work = tilegx_cpu_has_work;
 157     cc->do_interrupt = tilegx_cpu_do_interrupt;
 158     cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
 159     cc->dump_state = tilegx_cpu_dump_state;
 160     cc->set_pc = tilegx_cpu_set_pc;
 161     cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
 162     cc->gdb_num_core_regs = 0;
 163
 164     /*
 165      * Reason: tilegx_cpu_initfn() calls cpu_exec_init(), which saves
 166      * the object in cpus -> dangling pointer after final
 167      * object_unref().
 168      */
 169     dc->cannot_destroy_with_object_finalize_yet = true;
 170 }
 171
 172 static const TypeInfo tilegx_cpu_type_info = {
 173     .name = TYPE_TILEGX_CPU,
 174     .parent = TYPE_CPU,
 175     .instance_size = sizeof(TileGXCPU),
 176     .instance_init = tilegx_cpu_initfn,
 177     .class_size = sizeof(TileGXCPUClass),
 178     .class_init = tilegx_cpu_class_init,
 179 };
 180
 181 static void tilegx_cpu_register_types(void)
 182 {
 183     type_register_static(&tilegx_cpu_type_info);
 184 }
 185
 186 type_init(tilegx_cpu_register_types)