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nbd: always query export list in fixed new style protocol
[qemu/ar7.git] / hw / sparc / sun4m.c
blob20dc3417109a8d6407da49ee5392bd8ea5e5d3ce
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "hw/sysbus.h"
26 #include "qemu/error-report.h"
27 #include "qemu/timer.h"
28 #include "hw/sparc/sun4m.h"
29 #include "hw/timer/m48t59.h"
30 #include "hw/sparc/sparc32_dma.h"
31 #include "hw/block/fdc.h"
32 #include "sysemu/sysemu.h"
33 #include "net/net.h"
34 #include "hw/boards.h"
35 #include "hw/nvram/openbios_firmware_abi.h"
36 #include "hw/scsi/esp.h"
37 #include "hw/i386/pc.h"
38 #include "hw/isa/isa.h"
39 #include "hw/nvram/fw_cfg.h"
40 #include "hw/char/escc.h"
41 #include "hw/empty_slot.h"
42 #include "hw/loader.h"
43 #include "elf.h"
44 #include "sysemu/block-backend.h"
45 #include "trace.h"
46
47 /*
48 * Sun4m architecture was used in the following machines:
49 *
50 * SPARCserver 6xxMP/xx
51 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
52 * SPARCclassic X (4/10)
53 * SPARCstation LX/ZX (4/30)
54 * SPARCstation Voyager
55 * SPARCstation 10/xx, SPARCserver 10/xx
56 * SPARCstation 5, SPARCserver 5
57 * SPARCstation 20/xx, SPARCserver 20
58 * SPARCstation 4
59 *
60 * See for example: http://www.sunhelp.org/faq/sunref1.html
61 */
62
63 #define KERNEL_LOAD_ADDR 0x00004000
64 #define CMDLINE_ADDR 0x007ff000
65 #define INITRD_LOAD_ADDR 0x00800000
66 #define PROM_SIZE_MAX (1024 * 1024)
67 #define PROM_VADDR 0xffd00000
68 #define PROM_FILENAME "openbios-sparc32"
69 #define CFG_ADDR 0xd00000510ULL
70 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
71 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
72 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
73
74 #define MAX_CPUS 16
75 #define MAX_PILS 16
76 #define MAX_VSIMMS 4
77
78 #define ESCC_CLOCK 4915200
79
80 struct sun4m_hwdef {
81 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
82 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
83 hwaddr serial_base, fd_base;
84 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
85 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
86 hwaddr bpp_base, dbri_base, sx_base;
87 struct {
88 hwaddr reg_base, vram_base;
89 } vsimm[MAX_VSIMMS];
90 hwaddr ecc_base;
91 uint64_t max_mem;
92 const char * const default_cpu_model;
93 uint32_t ecc_version;
94 uint32_t iommu_version;
95 uint16_t machine_id;
96 uint8_t nvram_machine_id;
97 };
98
99 void DMA_init(ISABus *bus, int high_page_enable)
100 {
101 }
102
103 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
104 Error **errp)
105 {
106 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
107 }
108
109 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
110 const char *cmdline, const char *boot_devices,
111 ram_addr_t RAM_size, uint32_t kernel_size,
112 int width, int height, int depth,
113 int nvram_machine_id, const char *arch)
114 {
115 unsigned int i;
116 uint32_t start, end;
117 uint8_t image[0x1ff0];
118 struct OpenBIOS_nvpart_v1 *part_header;
119 NvramClass *k = NVRAM_GET_CLASS(nvram);
120
121 memset(image, '\0', sizeof(image));
122
123 start = 0;
124
125 // OpenBIOS nvram variables
126 // Variable partition
127 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
128 part_header->signature = OPENBIOS_PART_SYSTEM;
129 pstrcpy(part_header->name, sizeof(part_header->name), "system");
130
131 end = start + sizeof(struct OpenBIOS_nvpart_v1);
132 for (i = 0; i < nb_prom_envs; i++)
133 end = OpenBIOS_set_var(image, end, prom_envs[i]);
134
135 // End marker
136 image[end++] = '\0';
137
138 end = start + ((end - start + 15) & ~15);
139 OpenBIOS_finish_partition(part_header, end - start);
140
141 // free partition
142 start = end;
143 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
144 part_header->signature = OPENBIOS_PART_FREE;
145 pstrcpy(part_header->name, sizeof(part_header->name), "free");
146
147 end = 0x1fd0;
148 OpenBIOS_finish_partition(part_header, end - start);
149
150 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
151 nvram_machine_id);
152
153 for (i = 0; i < sizeof(image); i++) {
154 (k->write)(nvram, i, image[i]);
155 }
156 }
157
158 static DeviceState *slavio_intctl;
159
160 void sun4m_hmp_info_pic(Monitor *mon, const QDict *qdict)
161 {
162 if (slavio_intctl)
163 slavio_pic_info(mon, slavio_intctl);
164 }
165
166 void sun4m_hmp_info_irq(Monitor *mon, const QDict *qdict)
167 {
168 if (slavio_intctl)
169 slavio_irq_info(mon, slavio_intctl);
170 }
171
172 void cpu_check_irqs(CPUSPARCState *env)
173 {
174 CPUState *cs;
175
176 if (env->pil_in && (env->interrupt_index == 0 ||
177 (env->interrupt_index & ~15) == TT_EXTINT)) {
178 unsigned int i;
179
180 for (i = 15; i > 0; i--) {
181 if (env->pil_in & (1 << i)) {
182 int old_interrupt = env->interrupt_index;
183
184 env->interrupt_index = TT_EXTINT | i;
185 if (old_interrupt != env->interrupt_index) {
186 cs = CPU(sparc_env_get_cpu(env));
187 trace_sun4m_cpu_interrupt(i);
188 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
189 }
190 break;
191 }
192 }
193 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
194 cs = CPU(sparc_env_get_cpu(env));
195 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
196 env->interrupt_index = 0;
197 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
198 }
199 }
200
201 static void cpu_kick_irq(SPARCCPU *cpu)
202 {
203 CPUSPARCState *env = &cpu->env;
204 CPUState *cs = CPU(cpu);
205
206 cs->halted = 0;
207 cpu_check_irqs(env);
208 qemu_cpu_kick(cs);
209 }
210
211 static void cpu_set_irq(void *opaque, int irq, int level)
212 {
213 SPARCCPU *cpu = opaque;
214 CPUSPARCState *env = &cpu->env;
215
216 if (level) {
217 trace_sun4m_cpu_set_irq_raise(irq);
218 env->pil_in |= 1 << irq;
219 cpu_kick_irq(cpu);
220 } else {
221 trace_sun4m_cpu_set_irq_lower(irq);
222 env->pil_in &= ~(1 << irq);
223 cpu_check_irqs(env);
224 }
225 }
226
227 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
228 {
229 }
230
231 static void main_cpu_reset(void *opaque)
232 {
233 SPARCCPU *cpu = opaque;
234 CPUState *cs = CPU(cpu);
235
236 cpu_reset(cs);
237 cs->halted = 0;
238 }
239
240 static void secondary_cpu_reset(void *opaque)
241 {
242 SPARCCPU *cpu = opaque;
243 CPUState *cs = CPU(cpu);
244
245 cpu_reset(cs);
246 cs->halted = 1;
247 }
248
249 static void cpu_halt_signal(void *opaque, int irq, int level)
250 {
251 if (level && current_cpu) {
252 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
253 }
254 }
255
256 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
257 {
258 return addr - 0xf0000000ULL;
259 }
260
261 static unsigned long sun4m_load_kernel(const char *kernel_filename,
262 const char *initrd_filename,
263 ram_addr_t RAM_size)
264 {
265 int linux_boot;
266 unsigned int i;
267 long initrd_size, kernel_size;
268 uint8_t *ptr;
269
270 linux_boot = (kernel_filename != NULL);
271
272 kernel_size = 0;
273 if (linux_boot) {
274 int bswap_needed;
275
276 #ifdef BSWAP_NEEDED
277 bswap_needed = 1;
278 #else
279 bswap_needed = 0;
280 #endif
281 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
282 NULL, NULL, NULL, 1, EM_SPARC, 0);
283 if (kernel_size < 0)
284 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
285 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
286 TARGET_PAGE_SIZE);
287 if (kernel_size < 0)
288 kernel_size = load_image_targphys(kernel_filename,
289 KERNEL_LOAD_ADDR,
290 RAM_size - KERNEL_LOAD_ADDR);
291 if (kernel_size < 0) {
292 fprintf(stderr, "qemu: could not load kernel '%s'\n",
293 kernel_filename);
294 exit(1);
295 }
296
297 /* load initrd */
298 initrd_size = 0;
299 if (initrd_filename) {
300 initrd_size = load_image_targphys(initrd_filename,
301 INITRD_LOAD_ADDR,
302 RAM_size - INITRD_LOAD_ADDR);
303 if (initrd_size < 0) {
304 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
305 initrd_filename);
306 exit(1);
307 }
308 }
309 if (initrd_size > 0) {
310 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
311 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
312 if (ldl_p(ptr) == 0x48647253) { // HdrS
313 stl_p(ptr + 16, INITRD_LOAD_ADDR);
314 stl_p(ptr + 20, initrd_size);
315 break;
316 }
317 }
318 }
319 }
320 return kernel_size;
321 }
322
323 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
324 {
325 DeviceState *dev;
326 SysBusDevice *s;
327
328 dev = qdev_create(NULL, "iommu");
329 qdev_prop_set_uint32(dev, "version", version);
330 qdev_init_nofail(dev);
331 s = SYS_BUS_DEVICE(dev);
332 sysbus_connect_irq(s, 0, irq);
333 sysbus_mmio_map(s, 0, addr);
334
335 return s;
336 }
337
338 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
339 void *iommu, qemu_irq *dev_irq, int is_ledma)
340 {
341 DeviceState *dev;
342 SysBusDevice *s;
343
344 dev = qdev_create(NULL, "sparc32_dma");
345 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
346 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
347 qdev_init_nofail(dev);
348 s = SYS_BUS_DEVICE(dev);
349 sysbus_connect_irq(s, 0, parent_irq);
350 *dev_irq = qdev_get_gpio_in(dev, 0);
351 sysbus_mmio_map(s, 0, daddr);
352
353 return s;
354 }
355
356 static void lance_init(NICInfo *nd, hwaddr leaddr,
357 void *dma_opaque, qemu_irq irq)
358 {
359 DeviceState *dev;
360 SysBusDevice *s;
361 qemu_irq reset;
362
363 qemu_check_nic_model(&nd_table[0], "lance");
364
365 dev = qdev_create(NULL, "lance");
366 qdev_set_nic_properties(dev, nd);
367 qdev_prop_set_ptr(dev, "dma", dma_opaque);
368 qdev_init_nofail(dev);
369 s = SYS_BUS_DEVICE(dev);
370 sysbus_mmio_map(s, 0, leaddr);
371 sysbus_connect_irq(s, 0, irq);
372 reset = qdev_get_gpio_in(dev, 0);
373 qdev_connect_gpio_out(dma_opaque, 0, reset);
374 }
375
376 static DeviceState *slavio_intctl_init(hwaddr addr,
377 hwaddr addrg,
378 qemu_irq **parent_irq)
379 {
380 DeviceState *dev;
381 SysBusDevice *s;
382 unsigned int i, j;
383
384 dev = qdev_create(NULL, "slavio_intctl");
385 qdev_init_nofail(dev);
386
387 s = SYS_BUS_DEVICE(dev);
388
389 for (i = 0; i < MAX_CPUS; i++) {
390 for (j = 0; j < MAX_PILS; j++) {
391 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
392 }
393 }
394 sysbus_mmio_map(s, 0, addrg);
395 for (i = 0; i < MAX_CPUS; i++) {
396 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
397 }
398
399 return dev;
400 }
401
402 #define SYS_TIMER_OFFSET 0x10000ULL
403 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
404
405 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
406 qemu_irq *cpu_irqs, unsigned int num_cpus)
407 {
408 DeviceState *dev;
409 SysBusDevice *s;
410 unsigned int i;
411
412 dev = qdev_create(NULL, "slavio_timer");
413 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
414 qdev_init_nofail(dev);
415 s = SYS_BUS_DEVICE(dev);
416 sysbus_connect_irq(s, 0, master_irq);
417 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
418
419 for (i = 0; i < MAX_CPUS; i++) {
420 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
421 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
422 }
423 }
424
425 static qemu_irq slavio_system_powerdown;
426
427 static void slavio_powerdown_req(Notifier *n, void *opaque)
428 {
429 qemu_irq_raise(slavio_system_powerdown);
430 }
431
432 static Notifier slavio_system_powerdown_notifier = {
433 .notify = slavio_powerdown_req
434 };
435
436 #define MISC_LEDS 0x01600000
437 #define MISC_CFG 0x01800000
438 #define MISC_DIAG 0x01a00000
439 #define MISC_MDM 0x01b00000
440 #define MISC_SYS 0x01f00000
441
442 static void slavio_misc_init(hwaddr base,
443 hwaddr aux1_base,
444 hwaddr aux2_base, qemu_irq irq,
445 qemu_irq fdc_tc)
446 {
447 DeviceState *dev;
448 SysBusDevice *s;
449
450 dev = qdev_create(NULL, "slavio_misc");
451 qdev_init_nofail(dev);
452 s = SYS_BUS_DEVICE(dev);
453 if (base) {
454 /* 8 bit registers */
455 /* Slavio control */
456 sysbus_mmio_map(s, 0, base + MISC_CFG);
457 /* Diagnostics */
458 sysbus_mmio_map(s, 1, base + MISC_DIAG);
459 /* Modem control */
460 sysbus_mmio_map(s, 2, base + MISC_MDM);
461 /* 16 bit registers */
462 /* ss600mp diag LEDs */
463 sysbus_mmio_map(s, 3, base + MISC_LEDS);
464 /* 32 bit registers */
465 /* System control */
466 sysbus_mmio_map(s, 4, base + MISC_SYS);
467 }
468 if (aux1_base) {
469 /* AUX 1 (Misc System Functions) */
470 sysbus_mmio_map(s, 5, aux1_base);
471 }
472 if (aux2_base) {
473 /* AUX 2 (Software Powerdown Control) */
474 sysbus_mmio_map(s, 6, aux2_base);
475 }
476 sysbus_connect_irq(s, 0, irq);
477 sysbus_connect_irq(s, 1, fdc_tc);
478 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
479 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
480 }
481
482 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
483 {
484 DeviceState *dev;
485 SysBusDevice *s;
486
487 dev = qdev_create(NULL, "eccmemctl");
488 qdev_prop_set_uint32(dev, "version", version);
489 qdev_init_nofail(dev);
490 s = SYS_BUS_DEVICE(dev);
491 sysbus_connect_irq(s, 0, irq);
492 sysbus_mmio_map(s, 0, base);
493 if (version == 0) { // SS-600MP only
494 sysbus_mmio_map(s, 1, base + 0x1000);
495 }
496 }
497
498 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
499 {
500 DeviceState *dev;
501 SysBusDevice *s;
502
503 dev = qdev_create(NULL, "apc");
504 qdev_init_nofail(dev);
505 s = SYS_BUS_DEVICE(dev);
506 /* Power management (APC) XXX: not a Slavio device */
507 sysbus_mmio_map(s, 0, power_base);
508 sysbus_connect_irq(s, 0, cpu_halt);
509 }
510
511 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
512 int height, int depth)
513 {
514 DeviceState *dev;
515 SysBusDevice *s;
516
517 dev = qdev_create(NULL, "SUNW,tcx");
518 qdev_prop_set_uint32(dev, "vram_size", vram_size);
519 qdev_prop_set_uint16(dev, "width", width);
520 qdev_prop_set_uint16(dev, "height", height);
521 qdev_prop_set_uint16(dev, "depth", depth);
522 qdev_prop_set_uint64(dev, "prom_addr", addr);
523 qdev_init_nofail(dev);
524 s = SYS_BUS_DEVICE(dev);
525
526 /* 10/ROM : FCode ROM */
527 sysbus_mmio_map(s, 0, addr);
528 /* 2/STIP : Stipple */
529 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
530 /* 3/BLIT : Blitter */
531 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
532 /* 5/RSTIP : Raw Stipple */
533 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
534 /* 6/RBLIT : Raw Blitter */
535 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
536 /* 7/TEC : Transform Engine */
537 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
538 /* 8/CMAP : DAC */
539 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
540 /* 9/THC : */
541 if (depth == 8) {
542 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
543 } else {
544 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
545 }
546 /* 11/DHC : */
547 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
548 /* 12/ALT : */
549 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
550 /* 0/DFB8 : 8-bit plane */
551 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
552 /* 1/DFB24 : 24bit plane */
553 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
554 /* 4/RDFB32: Raw framebuffer. Control plane */
555 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
556 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
557 if (depth == 8) {
558 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
559 }
560
561 sysbus_connect_irq(s, 0, irq);
562 }
563
564 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
565 int height, int depth)
566 {
567 DeviceState *dev;
568 SysBusDevice *s;
569
570 dev = qdev_create(NULL, "cgthree");
571 qdev_prop_set_uint32(dev, "vram-size", vram_size);
572 qdev_prop_set_uint16(dev, "width", width);
573 qdev_prop_set_uint16(dev, "height", height);
574 qdev_prop_set_uint16(dev, "depth", depth);
575 qdev_prop_set_uint64(dev, "prom-addr", addr);
576 qdev_init_nofail(dev);
577 s = SYS_BUS_DEVICE(dev);
578
579 /* FCode ROM */
580 sysbus_mmio_map(s, 0, addr);
581 /* DAC */
582 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
583 /* 8-bit plane */
584 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
585
586 sysbus_connect_irq(s, 0, irq);
587 }
588
589 /* NCR89C100/MACIO Internal ID register */
590
591 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
592
593 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
594
595 static void idreg_init(hwaddr addr)
596 {
597 DeviceState *dev;
598 SysBusDevice *s;
599
600 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
601 qdev_init_nofail(dev);
602 s = SYS_BUS_DEVICE(dev);
603
604 sysbus_mmio_map(s, 0, addr);
605 cpu_physical_memory_write_rom(&address_space_memory,
606 addr, idreg_data, sizeof(idreg_data));
607 }
608
609 #define MACIO_ID_REGISTER(obj) \
610 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
611
612 typedef struct IDRegState {
613 SysBusDevice parent_obj;
614
615 MemoryRegion mem;
616 } IDRegState;
617
618 static int idreg_init1(SysBusDevice *dev)
619 {
620 IDRegState *s = MACIO_ID_REGISTER(dev);
621
622 memory_region_init_ram(&s->mem, OBJECT(s),
623 "sun4m.idreg", sizeof(idreg_data), &error_fatal);
624 vmstate_register_ram_global(&s->mem);
625 memory_region_set_readonly(&s->mem, true);
626 sysbus_init_mmio(dev, &s->mem);
627 return 0;
628 }
629
630 static void idreg_class_init(ObjectClass *klass, void *data)
631 {
632 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
633
634 k->init = idreg_init1;
635 }
636
637 static const TypeInfo idreg_info = {
638 .name = TYPE_MACIO_ID_REGISTER,
639 .parent = TYPE_SYS_BUS_DEVICE,
640 .instance_size = sizeof(IDRegState),
641 .class_init = idreg_class_init,
642 };
643
644 #define TYPE_TCX_AFX "tcx_afx"
645 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
646
647 typedef struct AFXState {
648 SysBusDevice parent_obj;
649
650 MemoryRegion mem;
651 } AFXState;
652
653 /* SS-5 TCX AFX register */
654 static void afx_init(hwaddr addr)
655 {
656 DeviceState *dev;
657 SysBusDevice *s;
658
659 dev = qdev_create(NULL, TYPE_TCX_AFX);
660 qdev_init_nofail(dev);
661 s = SYS_BUS_DEVICE(dev);
662
663 sysbus_mmio_map(s, 0, addr);
664 }
665
666 static int afx_init1(SysBusDevice *dev)
667 {
668 AFXState *s = TCX_AFX(dev);
669
670 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_fatal);
671 vmstate_register_ram_global(&s->mem);
672 sysbus_init_mmio(dev, &s->mem);
673 return 0;
674 }
675
676 static void afx_class_init(ObjectClass *klass, void *data)
677 {
678 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
679
680 k->init = afx_init1;
681 }
682
683 static const TypeInfo afx_info = {
684 .name = TYPE_TCX_AFX,
685 .parent = TYPE_SYS_BUS_DEVICE,
686 .instance_size = sizeof(AFXState),
687 .class_init = afx_class_init,
688 };
689
690 #define TYPE_OPENPROM "openprom"
691 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
692
693 typedef struct PROMState {
694 SysBusDevice parent_obj;
695
696 MemoryRegion prom;
697 } PROMState;
698
699 /* Boot PROM (OpenBIOS) */
700 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
701 {
702 hwaddr *base_addr = (hwaddr *)opaque;
703 return addr + *base_addr - PROM_VADDR;
704 }
705
706 static void prom_init(hwaddr addr, const char *bios_name)
707 {
708 DeviceState *dev;
709 SysBusDevice *s;
710 char *filename;
711 int ret;
712
713 dev = qdev_create(NULL, TYPE_OPENPROM);
714 qdev_init_nofail(dev);
715 s = SYS_BUS_DEVICE(dev);
716
717 sysbus_mmio_map(s, 0, addr);
718
719 /* load boot prom */
720 if (bios_name == NULL) {
721 bios_name = PROM_FILENAME;
722 }
723 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
724 if (filename) {
725 ret = load_elf(filename, translate_prom_address, &addr, NULL,
726 NULL, NULL, 1, EM_SPARC, 0);
727 if (ret < 0 || ret > PROM_SIZE_MAX) {
728 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
729 }
730 g_free(filename);
731 } else {
732 ret = -1;
733 }
734 if (ret < 0 || ret > PROM_SIZE_MAX) {
735 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
736 exit(1);
737 }
738 }
739
740 static int prom_init1(SysBusDevice *dev)
741 {
742 PROMState *s = OPENPROM(dev);
743
744 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX,
745 &error_fatal);
746 vmstate_register_ram_global(&s->prom);
747 memory_region_set_readonly(&s->prom, true);
748 sysbus_init_mmio(dev, &s->prom);
749 return 0;
750 }
751
752 static Property prom_properties[] = {
753 {/* end of property list */},
754 };
755
756 static void prom_class_init(ObjectClass *klass, void *data)
757 {
758 DeviceClass *dc = DEVICE_CLASS(klass);
759 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
760
761 k->init = prom_init1;
762 dc->props = prom_properties;
763 }
764
765 static const TypeInfo prom_info = {
766 .name = TYPE_OPENPROM,
767 .parent = TYPE_SYS_BUS_DEVICE,
768 .instance_size = sizeof(PROMState),
769 .class_init = prom_class_init,
770 };
771
772 #define TYPE_SUN4M_MEMORY "memory"
773 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
774
775 typedef struct RamDevice {
776 SysBusDevice parent_obj;
777
778 MemoryRegion ram;
779 uint64_t size;
780 } RamDevice;
781
782 /* System RAM */
783 static int ram_init1(SysBusDevice *dev)
784 {
785 RamDevice *d = SUN4M_RAM(dev);
786
787 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
788 d->size);
789 sysbus_init_mmio(dev, &d->ram);
790 return 0;
791 }
792
793 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
794 uint64_t max_mem)
795 {
796 DeviceState *dev;
797 SysBusDevice *s;
798 RamDevice *d;
799
800 /* allocate RAM */
801 if ((uint64_t)RAM_size > max_mem) {
802 fprintf(stderr,
803 "qemu: Too much memory for this machine: %d, maximum %d\n",
804 (unsigned int)(RAM_size / (1024 * 1024)),
805 (unsigned int)(max_mem / (1024 * 1024)));
806 exit(1);
807 }
808 dev = qdev_create(NULL, "memory");
809 s = SYS_BUS_DEVICE(dev);
810
811 d = SUN4M_RAM(dev);
812 d->size = RAM_size;
813 qdev_init_nofail(dev);
814
815 sysbus_mmio_map(s, 0, addr);
816 }
817
818 static Property ram_properties[] = {
819 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
820 DEFINE_PROP_END_OF_LIST(),
821 };
822
823 static void ram_class_init(ObjectClass *klass, void *data)
824 {
825 DeviceClass *dc = DEVICE_CLASS(klass);
826 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
827
828 k->init = ram_init1;
829 dc->props = ram_properties;
830 }
831
832 static const TypeInfo ram_info = {
833 .name = TYPE_SUN4M_MEMORY,
834 .parent = TYPE_SYS_BUS_DEVICE,
835 .instance_size = sizeof(RamDevice),
836 .class_init = ram_class_init,
837 };
838
839 static void cpu_devinit(const char *cpu_model, unsigned int id,
840 uint64_t prom_addr, qemu_irq **cpu_irqs)
841 {
842 CPUState *cs;
843 SPARCCPU *cpu;
844 CPUSPARCState *env;
845
846 cpu = cpu_sparc_init(cpu_model);
847 if (cpu == NULL) {
848 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
849 exit(1);
850 }
851 env = &cpu->env;
852
853 cpu_sparc_set_id(env, id);
854 if (id == 0) {
855 qemu_register_reset(main_cpu_reset, cpu);
856 } else {
857 qemu_register_reset(secondary_cpu_reset, cpu);
858 cs = CPU(cpu);
859 cs->halted = 1;
860 }
861 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
862 env->prom_addr = prom_addr;
863 }
864
865 static void dummy_fdc_tc(void *opaque, int irq, int level)
866 {
867 }
868
869 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
870 MachineState *machine)
871 {
872 const char *cpu_model = machine->cpu_model;
873 unsigned int i;
874 void *iommu, *espdma, *ledma, *nvram;
875 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
876 espdma_irq, ledma_irq;
877 qemu_irq esp_reset, dma_enable;
878 qemu_irq fdc_tc;
879 unsigned long kernel_size;
880 DriveInfo *fd[MAX_FD];
881 FWCfgState *fw_cfg;
882 unsigned int num_vsimms;
883
884 /* init CPUs */
885 if (!cpu_model)
886 cpu_model = hwdef->default_cpu_model;
887
888 for(i = 0; i < smp_cpus; i++) {
889 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
890 }
891
892 for (i = smp_cpus; i < MAX_CPUS; i++)
893 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
894
895
896 /* set up devices */
897 ram_init(0, machine->ram_size, hwdef->max_mem);
898 /* models without ECC don't trap when missing ram is accessed */
899 if (!hwdef->ecc_base) {
900 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
901 }
902
903 prom_init(hwdef->slavio_base, bios_name);
904
905 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
906 hwdef->intctl_base + 0x10000ULL,
907 cpu_irqs);
908
909 for (i = 0; i < 32; i++) {
910 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
911 }
912 for (i = 0; i < MAX_CPUS; i++) {
913 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
914 }
915
916 if (hwdef->idreg_base) {
917 idreg_init(hwdef->idreg_base);
918 }
919
920 if (hwdef->afx_base) {
921 afx_init(hwdef->afx_base);
922 }
923
924 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
925 slavio_irq[30]);
926
927 if (hwdef->iommu_pad_base) {
928 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
929 Software shouldn't use aliased addresses, neither should it crash
930 when does. Using empty_slot instead of aliasing can help with
931 debugging such accesses */
932 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
933 }
934
935 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
936 iommu, &espdma_irq, 0);
937
938 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
939 slavio_irq[16], iommu, &ledma_irq, 1);
940
941 if (graphic_depth != 8 && graphic_depth != 24) {
942 error_report("Unsupported depth: %d", graphic_depth);
943 exit (1);
944 }
945 num_vsimms = 0;
946 if (num_vsimms == 0) {
947 if (vga_interface_type == VGA_CG3) {
948 if (graphic_depth != 8) {
949 error_report("Unsupported depth: %d", graphic_depth);
950 exit(1);
951 }
952
953 if (!(graphic_width == 1024 && graphic_height == 768) &&
954 !(graphic_width == 1152 && graphic_height == 900)) {
955 error_report("Unsupported resolution: %d x %d", graphic_width,
956 graphic_height);
957 exit(1);
958 }
959
960 /* sbus irq 5 */
961 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
962 graphic_width, graphic_height, graphic_depth);
963 } else {
964 /* If no display specified, default to TCX */
965 if (graphic_depth != 8 && graphic_depth != 24) {
966 error_report("Unsupported depth: %d", graphic_depth);
967 exit(1);
968 }
969
970 if (!(graphic_width == 1024 && graphic_height == 768)) {
971 error_report("Unsupported resolution: %d x %d",
972 graphic_width, graphic_height);
973 exit(1);
974 }
975
976 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
977 graphic_width, graphic_height, graphic_depth);
978 }
979 }
980
981 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
982 /* vsimm registers probed by OBP */
983 if (hwdef->vsimm[i].reg_base) {
984 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
985 }
986 }
987
988 if (hwdef->sx_base) {
989 empty_slot_init(hwdef->sx_base, 0x2000);
990 }
991
992 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
993
994 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
995
996 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
997
998 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
999 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1000 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1001 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1002 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
1003 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1004
1005 if (hwdef->apc_base) {
1006 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1007 }
1008
1009 if (hwdef->fd_base) {
1010 /* there is zero or one floppy drive */
1011 memset(fd, 0, sizeof(fd));
1012 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1013 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1014 &fdc_tc);
1015 } else {
1016 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1017 }
1018
1019 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1020 slavio_irq[30], fdc_tc);
1021
1022 if (drive_get_max_bus(IF_SCSI) > 0) {
1023 fprintf(stderr, "qemu: too many SCSI bus\n");
1024 exit(1);
1025 }
1026
1027 esp_init(hwdef->esp_base, 2,
1028 espdma_memory_read, espdma_memory_write,
1029 espdma, espdma_irq, &esp_reset, &dma_enable);
1030
1031 qdev_connect_gpio_out(espdma, 0, esp_reset);
1032 qdev_connect_gpio_out(espdma, 1, dma_enable);
1033
1034 if (hwdef->cs_base) {
1035 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1036 slavio_irq[5]);
1037 }
1038
1039 if (hwdef->dbri_base) {
1040 /* ISDN chip with attached CS4215 audio codec */
1041 /* prom space */
1042 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1043 /* reg space */
1044 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1045 }
1046
1047 if (hwdef->bpp_base) {
1048 /* parallel port */
1049 empty_slot_init(hwdef->bpp_base, 0x20);
1050 }
1051
1052 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1053 machine->initrd_filename,
1054 machine->ram_size);
1055
1056 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1057 machine->boot_order, machine->ram_size, kernel_size,
1058 graphic_width, graphic_height, graphic_depth,
1059 hwdef->nvram_machine_id, "Sun4m");
1060
1061 if (hwdef->ecc_base)
1062 ecc_init(hwdef->ecc_base, slavio_irq[28],
1063 hwdef->ecc_version);
1064
1065 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
1066 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1067 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1068 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1069 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1070 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1071 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1072 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1073 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1074 if (machine->kernel_cmdline) {
1075 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1076 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1077 machine->kernel_cmdline);
1078 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1079 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1080 strlen(machine->kernel_cmdline) + 1);
1081 } else {
1082 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1083 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1084 }
1085 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1086 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1087 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1088 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1089 }
1090
1091 enum {
1092 ss5_id = 32,
1093 vger_id,
1094 lx_id,
1095 ss4_id,
1096 scls_id,
1097 sbook_id,
1098 ss10_id = 64,
1099 ss20_id,
1100 ss600mp_id,
1101 };
1102
1103 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1104 /* SS-5 */
1105 {
1106 .iommu_base = 0x10000000,
1107 .iommu_pad_base = 0x10004000,
1108 .iommu_pad_len = 0x0fffb000,
1109 .tcx_base = 0x50000000,
1110 .cs_base = 0x6c000000,
1111 .slavio_base = 0x70000000,
1112 .ms_kb_base = 0x71000000,
1113 .serial_base = 0x71100000,
1114 .nvram_base = 0x71200000,
1115 .fd_base = 0x71400000,
1116 .counter_base = 0x71d00000,
1117 .intctl_base = 0x71e00000,
1118 .idreg_base = 0x78000000,
1119 .dma_base = 0x78400000,
1120 .esp_base = 0x78800000,
1121 .le_base = 0x78c00000,
1122 .apc_base = 0x6a000000,
1123 .afx_base = 0x6e000000,
1124 .aux1_base = 0x71900000,
1125 .aux2_base = 0x71910000,
1126 .nvram_machine_id = 0x80,
1127 .machine_id = ss5_id,
1128 .iommu_version = 0x05000000,
1129 .max_mem = 0x10000000,
1130 .default_cpu_model = "Fujitsu MB86904",
1131 },
1132 /* SS-10 */
1133 {
1134 .iommu_base = 0xfe0000000ULL,
1135 .tcx_base = 0xe20000000ULL,
1136 .slavio_base = 0xff0000000ULL,
1137 .ms_kb_base = 0xff1000000ULL,
1138 .serial_base = 0xff1100000ULL,
1139 .nvram_base = 0xff1200000ULL,
1140 .fd_base = 0xff1700000ULL,
1141 .counter_base = 0xff1300000ULL,
1142 .intctl_base = 0xff1400000ULL,
1143 .idreg_base = 0xef0000000ULL,
1144 .dma_base = 0xef0400000ULL,
1145 .esp_base = 0xef0800000ULL,
1146 .le_base = 0xef0c00000ULL,
1147 .apc_base = 0xefa000000ULL, // XXX should not exist
1148 .aux1_base = 0xff1800000ULL,
1149 .aux2_base = 0xff1a01000ULL,
1150 .ecc_base = 0xf00000000ULL,
1151 .ecc_version = 0x10000000, // version 0, implementation 1
1152 .nvram_machine_id = 0x72,
1153 .machine_id = ss10_id,
1154 .iommu_version = 0x03000000,
1155 .max_mem = 0xf00000000ULL,
1156 .default_cpu_model = "TI SuperSparc II",
1157 },
1158 /* SS-600MP */
1159 {
1160 .iommu_base = 0xfe0000000ULL,
1161 .tcx_base = 0xe20000000ULL,
1162 .slavio_base = 0xff0000000ULL,
1163 .ms_kb_base = 0xff1000000ULL,
1164 .serial_base = 0xff1100000ULL,
1165 .nvram_base = 0xff1200000ULL,
1166 .counter_base = 0xff1300000ULL,
1167 .intctl_base = 0xff1400000ULL,
1168 .dma_base = 0xef0081000ULL,
1169 .esp_base = 0xef0080000ULL,
1170 .le_base = 0xef0060000ULL,
1171 .apc_base = 0xefa000000ULL, // XXX should not exist
1172 .aux1_base = 0xff1800000ULL,
1173 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1174 .ecc_base = 0xf00000000ULL,
1175 .ecc_version = 0x00000000, // version 0, implementation 0
1176 .nvram_machine_id = 0x71,
1177 .machine_id = ss600mp_id,
1178 .iommu_version = 0x01000000,
1179 .max_mem = 0xf00000000ULL,
1180 .default_cpu_model = "TI SuperSparc II",
1181 },
1182 /* SS-20 */
1183 {
1184 .iommu_base = 0xfe0000000ULL,
1185 .tcx_base = 0xe20000000ULL,
1186 .slavio_base = 0xff0000000ULL,
1187 .ms_kb_base = 0xff1000000ULL,
1188 .serial_base = 0xff1100000ULL,
1189 .nvram_base = 0xff1200000ULL,
1190 .fd_base = 0xff1700000ULL,
1191 .counter_base = 0xff1300000ULL,
1192 .intctl_base = 0xff1400000ULL,
1193 .idreg_base = 0xef0000000ULL,
1194 .dma_base = 0xef0400000ULL,
1195 .esp_base = 0xef0800000ULL,
1196 .le_base = 0xef0c00000ULL,
1197 .bpp_base = 0xef4800000ULL,
1198 .apc_base = 0xefa000000ULL, // XXX should not exist
1199 .aux1_base = 0xff1800000ULL,
1200 .aux2_base = 0xff1a01000ULL,
1201 .dbri_base = 0xee0000000ULL,
1202 .sx_base = 0xf80000000ULL,
1203 .vsimm = {
1204 {
1205 .reg_base = 0x9c000000ULL,
1206 .vram_base = 0xfc000000ULL
1207 }, {
1208 .reg_base = 0x90000000ULL,
1209 .vram_base = 0xf0000000ULL
1210 }, {
1211 .reg_base = 0x94000000ULL
1212 }, {
1213 .reg_base = 0x98000000ULL
1214 }
1215 },
1216 .ecc_base = 0xf00000000ULL,
1217 .ecc_version = 0x20000000, // version 0, implementation 2
1218 .nvram_machine_id = 0x72,
1219 .machine_id = ss20_id,
1220 .iommu_version = 0x13000000,
1221 .max_mem = 0xf00000000ULL,
1222 .default_cpu_model = "TI SuperSparc II",
1223 },
1224 /* Voyager */
1225 {
1226 .iommu_base = 0x10000000,
1227 .tcx_base = 0x50000000,
1228 .slavio_base = 0x70000000,
1229 .ms_kb_base = 0x71000000,
1230 .serial_base = 0x71100000,
1231 .nvram_base = 0x71200000,
1232 .fd_base = 0x71400000,
1233 .counter_base = 0x71d00000,
1234 .intctl_base = 0x71e00000,
1235 .idreg_base = 0x78000000,
1236 .dma_base = 0x78400000,
1237 .esp_base = 0x78800000,
1238 .le_base = 0x78c00000,
1239 .apc_base = 0x71300000, // pmc
1240 .aux1_base = 0x71900000,
1241 .aux2_base = 0x71910000,
1242 .nvram_machine_id = 0x80,
1243 .machine_id = vger_id,
1244 .iommu_version = 0x05000000,
1245 .max_mem = 0x10000000,
1246 .default_cpu_model = "Fujitsu MB86904",
1247 },
1248 /* LX */
1249 {
1250 .iommu_base = 0x10000000,
1251 .iommu_pad_base = 0x10004000,
1252 .iommu_pad_len = 0x0fffb000,
1253 .tcx_base = 0x50000000,
1254 .slavio_base = 0x70000000,
1255 .ms_kb_base = 0x71000000,
1256 .serial_base = 0x71100000,
1257 .nvram_base = 0x71200000,
1258 .fd_base = 0x71400000,
1259 .counter_base = 0x71d00000,
1260 .intctl_base = 0x71e00000,
1261 .idreg_base = 0x78000000,
1262 .dma_base = 0x78400000,
1263 .esp_base = 0x78800000,
1264 .le_base = 0x78c00000,
1265 .aux1_base = 0x71900000,
1266 .aux2_base = 0x71910000,
1267 .nvram_machine_id = 0x80,
1268 .machine_id = lx_id,
1269 .iommu_version = 0x04000000,
1270 .max_mem = 0x10000000,
1271 .default_cpu_model = "TI MicroSparc I",
1272 },
1273 /* SS-4 */
1274 {
1275 .iommu_base = 0x10000000,
1276 .tcx_base = 0x50000000,
1277 .cs_base = 0x6c000000,
1278 .slavio_base = 0x70000000,
1279 .ms_kb_base = 0x71000000,
1280 .serial_base = 0x71100000,
1281 .nvram_base = 0x71200000,
1282 .fd_base = 0x71400000,
1283 .counter_base = 0x71d00000,
1284 .intctl_base = 0x71e00000,
1285 .idreg_base = 0x78000000,
1286 .dma_base = 0x78400000,
1287 .esp_base = 0x78800000,
1288 .le_base = 0x78c00000,
1289 .apc_base = 0x6a000000,
1290 .aux1_base = 0x71900000,
1291 .aux2_base = 0x71910000,
1292 .nvram_machine_id = 0x80,
1293 .machine_id = ss4_id,
1294 .iommu_version = 0x05000000,
1295 .max_mem = 0x10000000,
1296 .default_cpu_model = "Fujitsu MB86904",
1297 },
1298 /* SPARCClassic */
1299 {
1300 .iommu_base = 0x10000000,
1301 .tcx_base = 0x50000000,
1302 .slavio_base = 0x70000000,
1303 .ms_kb_base = 0x71000000,
1304 .serial_base = 0x71100000,
1305 .nvram_base = 0x71200000,
1306 .fd_base = 0x71400000,
1307 .counter_base = 0x71d00000,
1308 .intctl_base = 0x71e00000,
1309 .idreg_base = 0x78000000,
1310 .dma_base = 0x78400000,
1311 .esp_base = 0x78800000,
1312 .le_base = 0x78c00000,
1313 .apc_base = 0x6a000000,
1314 .aux1_base = 0x71900000,
1315 .aux2_base = 0x71910000,
1316 .nvram_machine_id = 0x80,
1317 .machine_id = scls_id,
1318 .iommu_version = 0x05000000,
1319 .max_mem = 0x10000000,
1320 .default_cpu_model = "TI MicroSparc I",
1321 },
1322 /* SPARCbook */
1323 {
1324 .iommu_base = 0x10000000,
1325 .tcx_base = 0x50000000, // XXX
1326 .slavio_base = 0x70000000,
1327 .ms_kb_base = 0x71000000,
1328 .serial_base = 0x71100000,
1329 .nvram_base = 0x71200000,
1330 .fd_base = 0x71400000,
1331 .counter_base = 0x71d00000,
1332 .intctl_base = 0x71e00000,
1333 .idreg_base = 0x78000000,
1334 .dma_base = 0x78400000,
1335 .esp_base = 0x78800000,
1336 .le_base = 0x78c00000,
1337 .apc_base = 0x6a000000,
1338 .aux1_base = 0x71900000,
1339 .aux2_base = 0x71910000,
1340 .nvram_machine_id = 0x80,
1341 .machine_id = sbook_id,
1342 .iommu_version = 0x05000000,
1343 .max_mem = 0x10000000,
1344 .default_cpu_model = "TI MicroSparc I",
1345 },
1346 };
1347
1348 /* SPARCstation 5 hardware initialisation */
1349 static void ss5_init(MachineState *machine)
1350 {
1351 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1352 }
1353
1354 /* SPARCstation 10 hardware initialisation */
1355 static void ss10_init(MachineState *machine)
1356 {
1357 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1358 }
1359
1360 /* SPARCserver 600MP hardware initialisation */
1361 static void ss600mp_init(MachineState *machine)
1362 {
1363 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1364 }
1365
1366 /* SPARCstation 20 hardware initialisation */
1367 static void ss20_init(MachineState *machine)
1368 {
1369 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1370 }
1371
1372 /* SPARCstation Voyager hardware initialisation */
1373 static void vger_init(MachineState *machine)
1374 {
1375 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1376 }
1377
1378 /* SPARCstation LX hardware initialisation */
1379 static void ss_lx_init(MachineState *machine)
1380 {
1381 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1382 }
1383
1384 /* SPARCstation 4 hardware initialisation */
1385 static void ss4_init(MachineState *machine)
1386 {
1387 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1388 }
1389
1390 /* SPARCClassic hardware initialisation */
1391 static void scls_init(MachineState *machine)
1392 {
1393 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1394 }
1395
1396 /* SPARCbook hardware initialisation */
1397 static void sbook_init(MachineState *machine)
1398 {
1399 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1400 }
1401
1402 static void ss5_class_init(ObjectClass *oc, void *data)
1403 {
1404 MachineClass *mc = MACHINE_CLASS(oc);
1405
1406 mc->desc = "Sun4m platform, SPARCstation 5";
1407 mc->init = ss5_init;
1408 mc->block_default_type = IF_SCSI;
1409 mc->is_default = 1;
1410 mc->default_boot_order = "c";
1411 }
1412
1413 static const TypeInfo ss5_type = {
1414 .name = MACHINE_TYPE_NAME("SS-5"),
1415 .parent = TYPE_MACHINE,
1416 .class_init = ss5_class_init,
1417 };
1418
1419 static void ss10_class_init(ObjectClass *oc, void *data)
1420 {
1421 MachineClass *mc = MACHINE_CLASS(oc);
1422
1423 mc->desc = "Sun4m platform, SPARCstation 10";
1424 mc->init = ss10_init;
1425 mc->block_default_type = IF_SCSI;
1426 mc->max_cpus = 4;
1427 mc->default_boot_order = "c";
1428 }
1429
1430 static const TypeInfo ss10_type = {
1431 .name = MACHINE_TYPE_NAME("SS-10"),
1432 .parent = TYPE_MACHINE,
1433 .class_init = ss10_class_init,
1434 };
1435
1436 static void ss600mp_class_init(ObjectClass *oc, void *data)
1437 {
1438 MachineClass *mc = MACHINE_CLASS(oc);
1439
1440 mc->desc = "Sun4m platform, SPARCserver 600MP";
1441 mc->init = ss600mp_init;
1442 mc->block_default_type = IF_SCSI;
1443 mc->max_cpus = 4;
1444 mc->default_boot_order = "c";
1445 }
1446
1447 static const TypeInfo ss600mp_type = {
1448 .name = MACHINE_TYPE_NAME("SS-600MP"),
1449 .parent = TYPE_MACHINE,
1450 .class_init = ss600mp_class_init,
1451 };
1452
1453 static void ss20_class_init(ObjectClass *oc, void *data)
1454 {
1455 MachineClass *mc = MACHINE_CLASS(oc);
1456
1457 mc->desc = "Sun4m platform, SPARCstation 20";
1458 mc->init = ss20_init;
1459 mc->block_default_type = IF_SCSI;
1460 mc->max_cpus = 4;
1461 mc->default_boot_order = "c";
1462 }
1463
1464 static const TypeInfo ss20_type = {
1465 .name = MACHINE_TYPE_NAME("SS-20"),
1466 .parent = TYPE_MACHINE,
1467 .class_init = ss20_class_init,
1468 };
1469
1470 static void voyager_class_init(ObjectClass *oc, void *data)
1471 {
1472 MachineClass *mc = MACHINE_CLASS(oc);
1473
1474 mc->desc = "Sun4m platform, SPARCstation Voyager";
1475 mc->init = vger_init;
1476 mc->block_default_type = IF_SCSI;
1477 mc->default_boot_order = "c";
1478 }
1479
1480 static const TypeInfo voyager_type = {
1481 .name = MACHINE_TYPE_NAME("Voyager"),
1482 .parent = TYPE_MACHINE,
1483 .class_init = voyager_class_init,
1484 };
1485
1486 static void ss_lx_class_init(ObjectClass *oc, void *data)
1487 {
1488 MachineClass *mc = MACHINE_CLASS(oc);
1489
1490 mc->desc = "Sun4m platform, SPARCstation LX";
1491 mc->init = ss_lx_init;
1492 mc->block_default_type = IF_SCSI;
1493 mc->default_boot_order = "c";
1494 }
1495
1496 static const TypeInfo ss_lx_type = {
1497 .name = MACHINE_TYPE_NAME("LX"),
1498 .parent = TYPE_MACHINE,
1499 .class_init = ss_lx_class_init,
1500 };
1501
1502 static void ss4_class_init(ObjectClass *oc, void *data)
1503 {
1504 MachineClass *mc = MACHINE_CLASS(oc);
1505
1506 mc->desc = "Sun4m platform, SPARCstation 4";
1507 mc->init = ss4_init;
1508 mc->block_default_type = IF_SCSI;
1509 mc->default_boot_order = "c";
1510 }
1511
1512 static const TypeInfo ss4_type = {
1513 .name = MACHINE_TYPE_NAME("SS-4"),
1514 .parent = TYPE_MACHINE,
1515 .class_init = ss4_class_init,
1516 };
1517
1518 static void scls_class_init(ObjectClass *oc, void *data)
1519 {
1520 MachineClass *mc = MACHINE_CLASS(oc);
1521
1522 mc->desc = "Sun4m platform, SPARCClassic";
1523 mc->init = scls_init;
1524 mc->block_default_type = IF_SCSI;
1525 mc->default_boot_order = "c";
1526 }
1527
1528 static const TypeInfo scls_type = {
1529 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1530 .parent = TYPE_MACHINE,
1531 .class_init = scls_class_init,
1532 };
1533
1534 static void sbook_class_init(ObjectClass *oc, void *data)
1535 {
1536 MachineClass *mc = MACHINE_CLASS(oc);
1537
1538 mc->desc = "Sun4m platform, SPARCbook";
1539 mc->init = sbook_init;
1540 mc->block_default_type = IF_SCSI;
1541 mc->default_boot_order = "c";
1542 }
1543
1544 static const TypeInfo sbook_type = {
1545 .name = MACHINE_TYPE_NAME("SPARCbook"),
1546 .parent = TYPE_MACHINE,
1547 .class_init = sbook_class_init,
1548 };
1549
1550 static void sun4m_register_types(void)
1551 {
1552 type_register_static(&idreg_info);
1553 type_register_static(&afx_info);
1554 type_register_static(&prom_info);
1555 type_register_static(&ram_info);
1556 }
1557
1558 static void sun4m_machine_init(void)
1559 {
1560 type_register_static(&ss5_type);
1561 type_register_static(&ss10_type);
1562 type_register_static(&ss600mp_type);
1563 type_register_static(&ss20_type);
1564 type_register_static(&voyager_type);
1565 type_register_static(&ss_lx_type);
1566 type_register_static(&ss4_type);
1567 type_register_static(&scls_type);
1568 type_register_static(&sbook_type);
1569 }
1570
1571 type_init(sun4m_register_types)
1572 machine_init(sun4m_machine_init)
AR7 emulation for QEMU