hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30
  31 #include "qemu/osdep.h"
  32 #include "qemu/units.h"
  33 #include "hw/hw.h"
  34 #include "hw/loader.h"
  35 #include "sysemu/arch_init.h"
  36 #include "hw/i2c/smbus_eeprom.h"
  37 #include "hw/boards.h"
  38 #include "hw/timer/mc146818rtc.h"
  39 #include "hw/xen/xen.h"
  40 #include "sysemu/kvm.h"
  41 #include "kvm_i386.h"
  42 #include "hw/kvm/clock.h"
  43 #include "hw/pci-host/q35.h"
  44 #include "exec/address-spaces.h"
  45 #include "hw/i386/pc.h"
  46 #include "hw/i386/ich9.h"
  47 #include "hw/i386/amd_iommu.h"
  48 #include "hw/i386/intel_iommu.h"
  49 #include "hw/display/ramfb.h"
  50 #include "hw/firmware/smbios.h"
  51 #include "hw/ide/pci.h"
  52 #include "hw/ide/ahci.h"
  53 #include "hw/usb.h"
  54 #include "qapi/error.h"
  55 #include "qemu/error-report.h"
  56 #include "sysemu/numa.h"
  57
  58 /* ICH9 AHCI has 6 ports */
  59 #define MAX_SATA_PORTS     6
  60
  61 struct ehci_companions {
  62     const char *name;
  63     int func;
  64     int port;
  65 };
  66
  67 static const struct ehci_companions ich9_1d[] = {
  68     { .name = "ich9-usb-uhci1", .func = 0, .port = 0 },
  69     { .name = "ich9-usb-uhci2", .func = 1, .port = 2 },
  70     { .name = "ich9-usb-uhci3", .func = 2, .port = 4 },
  71 };
  72
  73 static const struct ehci_companions ich9_1a[] = {
  74     { .name = "ich9-usb-uhci4", .func = 0, .port = 0 },
  75     { .name = "ich9-usb-uhci5", .func = 1, .port = 2 },
  76     { .name = "ich9-usb-uhci6", .func = 2, .port = 4 },
  77 };
  78
  79 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
  80 {
  81     const struct ehci_companions *comp;
  82     PCIDevice *ehci, *uhci;
  83     BusState *usbbus;
  84     const char *name;
  85     int i;
  86
  87     switch (slot) {
  88     case 0x1d:
  89         name = "ich9-usb-ehci1";
  90         comp = ich9_1d;
  91         break;
  92     case 0x1a:
  93         name = "ich9-usb-ehci2";
  94         comp = ich9_1a;
  95         break;
  96     default:
  97         return -1;
  98     }
  99
 100     ehci = pci_create_multifunction(bus, PCI_DEVFN(slot, 7), true, name);
 101     qdev_init_nofail(&ehci->qdev);
 102     usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
 103
 104     for (i = 0; i < 3; i++) {
 105         uhci = pci_create_multifunction(bus, PCI_DEVFN(slot, comp[i].func),
 106                                         true, comp[i].name);
 107         qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
 108         qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
 109         qdev_init_nofail(&uhci->qdev);
 110     }
 111     return 0;
 112 }
 113
 114 /* PC hardware initialisation */
 115 static void pc_q35_init(MachineState *machine)
 116 {
 117     PCMachineState *pcms = PC_MACHINE(machine);
 118     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
 119     Q35PCIHost *q35_host;
 120     PCIHostState *phb;
 121     PCIBus *host_bus;
 122     PCIDevice *lpc;
 123     DeviceState *lpc_dev;
 124     BusState *idebus[MAX_SATA_PORTS];
 125     ISADevice *rtc_state;
 126     MemoryRegion *system_io = get_system_io();
 127     MemoryRegion *pci_memory;
 128     MemoryRegion *rom_memory;
 129     MemoryRegion *ram_memory;
 130     GSIState *gsi_state;
 131     ISABus *isa_bus;
 132     qemu_irq *i8259;
 133     int i;
 134     ICH9LPCState *ich9_lpc;
 135     PCIDevice *ahci;
 136     ram_addr_t lowmem;
 137     DriveInfo *hd[MAX_SATA_PORTS];
 138     MachineClass *mc = MACHINE_GET_CLASS(machine);
 139
 140     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
 141      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
 142      * also known as MMCFG).
 143      * If it doesn't, we need to split it in chunks below and above 4G.
 144      * In any case, try to make sure that guest addresses aligned at
 145      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
 146      */
 147     if (machine->ram_size >= 0xb0000000) {
 148         lowmem = 0x80000000;
 149     } else {
 150         lowmem = 0xb0000000;
 151     }
 152
 153     /* Handle the machine opt max-ram-below-4g.  It is basically doing
 154      * min(qemu limit, user limit).
 155      */
 156     if (!pcms->max_ram_below_4g) {
 157         pcms->max_ram_below_4g = 1ULL << 32; /* default: 4G */;
 158     }
 159     if (lowmem > pcms->max_ram_below_4g) {
 160         lowmem = pcms->max_ram_below_4g;
 161         if (machine->ram_size - lowmem > lowmem &&
 162             lowmem & (1 * GiB - 1)) {
 163             warn_report("There is possibly poor performance as the ram size "
 164                         " (0x%" PRIx64 ") is more then twice the size of"
 165                         " max-ram-below-4g (%"PRIu64") and"
 166                         " max-ram-below-4g is not a multiple of 1G.",
 167                         (uint64_t)machine->ram_size, pcms->max_ram_below_4g);
 168         }
 169     }
 170
 171     if (machine->ram_size >= lowmem) {
 172         pcms->above_4g_mem_size = machine->ram_size - lowmem;
 173         pcms->below_4g_mem_size = lowmem;
 174     } else {
 175         pcms->above_4g_mem_size = 0;
 176         pcms->below_4g_mem_size = machine->ram_size;
 177     }
 178
 179     if (xen_enabled()) {
 180         xen_hvm_init(pcms, &ram_memory);
 181     }
 182
 183     pc_cpus_init(pcms);
 184
 185     kvmclock_create();
 186
 187     /* pci enabled */
 188     if (pcmc->pci_enabled) {
 189         pci_memory = g_new(MemoryRegion, 1);
 190         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 191         rom_memory = pci_memory;
 192     } else {
 193         pci_memory = NULL;
 194         rom_memory = get_system_memory();
 195     }
 196
 197     pc_guest_info_init(pcms);
 198
 199     if (pcmc->smbios_defaults) {
 200         /* These values are guest ABI, do not change */
 201         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 202                             mc->name, pcmc->smbios_legacy_mode,
 203                             pcmc->smbios_uuid_encoded,
 204                             SMBIOS_ENTRY_POINT_21);
 205     }
 206
 207     /* allocate ram and load rom/bios */
 208     if (!xen_enabled()) {
 209         pc_memory_init(pcms, get_system_memory(),
 210                        rom_memory, &ram_memory);
 211     }
 212
 213     /* irq lines */
 214     gsi_state = g_malloc0(sizeof(*gsi_state));
 215     if (kvm_ioapic_in_kernel()) {
 216         kvm_pc_setup_irq_routing(pcmc->pci_enabled);
 217         pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 218                                        GSI_NUM_PINS);
 219     } else {
 220         pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 221     }
 222
 223     /* create pci host bus */
 224     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 225
 226     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 227     object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory),
 228                              MCH_HOST_PROP_RAM_MEM, NULL);
 229     object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory),
 230                              MCH_HOST_PROP_PCI_MEM, NULL);
 231     object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()),
 232                              MCH_HOST_PROP_SYSTEM_MEM, NULL);
 233     object_property_set_link(OBJECT(q35_host), OBJECT(system_io),
 234                              MCH_HOST_PROP_IO_MEM, NULL);
 235     object_property_set_int(OBJECT(q35_host), pcms->below_4g_mem_size,
 236                             PCI_HOST_BELOW_4G_MEM_SIZE, NULL);
 237     object_property_set_int(OBJECT(q35_host), pcms->above_4g_mem_size,
 238                             PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
 239     /* pci */
 240     qdev_init_nofail(DEVICE(q35_host));
 241     phb = PCI_HOST_BRIDGE(q35_host);
 242     host_bus = phb->bus;
 243     /* create ISA bus */
 244     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 245                                           ICH9_LPC_FUNC), true,
 246                                           TYPE_ICH9_LPC_DEVICE);
 247
 248     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 249                              TYPE_HOTPLUG_HANDLER,
 250                              (Object **)&pcms->acpi_dev,
 251                              object_property_allow_set_link,
 252                              OBJ_PROP_LINK_STRONG, &error_abort);
 253     object_property_set_link(OBJECT(machine), OBJECT(lpc),
 254                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 255
 256     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 257     lpc_dev = DEVICE(lpc);
 258     for (i = 0; i < GSI_NUM_PINS; i++) {
 259         qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, pcms->gsi[i]);
 260     }
 261     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 262                  ICH9_LPC_NB_PIRQS);
 263     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 264     isa_bus = ich9_lpc->isa_bus;
 265
 266     if (kvm_pic_in_kernel()) {
 267         i8259 = kvm_i8259_init(isa_bus);
 268     } else if (xen_enabled()) {
 269         i8259 = xen_interrupt_controller_init();
 270     } else {
 271         i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
 272     }
 273
 274     for (i = 0; i < ISA_NUM_IRQS; i++) {
 275         gsi_state->i8259_irq[i] = i8259[i];
 276     }
 277     g_free(i8259);
 278
 279     if (pcmc->pci_enabled) {
 280         ioapic_init_gsi(gsi_state, "q35");
 281     }
 282
 283     pc_register_ferr_irq(pcms->gsi[13]);
 284
 285     assert(pcms->vmport != ON_OFF_AUTO__MAX);
 286     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 287         pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
 288     }
 289
 290     /* init basic PC hardware */
 291     pc_basic_device_init(isa_bus, pcms->gsi, &rtc_state, !mc->no_floppy,
 292                          (pcms->vmport != ON_OFF_AUTO_ON), pcms->pit_enabled,
 293                          0xff0104);
 294
 295     /* connect pm stuff to lpc */
 296     ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms));
 297
 298     if (pcms->sata_enabled) {
 299         /* ahci and SATA device, for q35 1 ahci controller is built-in */
 300         ahci = pci_create_simple_multifunction(host_bus,
 301                                                PCI_DEVFN(ICH9_SATA1_DEV,
 302                                                          ICH9_SATA1_FUNC),
 303                                                true, "ich9-ahci");
 304         idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 305         idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 306         g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
 307         ide_drive_get(hd, ahci_get_num_ports(ahci));
 308         ahci_ide_create_devs(ahci, hd);
 309     } else {
 310         idebus[0] = idebus[1] = NULL;
 311     }
 312
 313     if (machine_usb(machine)) {
 314         /* Should we create 6 UHCI according to ich9 spec? */
 315         ehci_create_ich9_with_companions(host_bus, 0x1d);
 316     }
 317
 318     if (pcms->smbus_enabled) {
 319         /* TODO: Populate SPD eeprom data.  */
 320         smbus_eeprom_init(ich9_smb_init(host_bus,
 321                                         PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 322                                         0xb100),
 323                           8, NULL, 0);
 324     }
 325
 326     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 327
 328     /* the rest devices to which pci devfn is automatically assigned */
 329     pc_vga_init(isa_bus, host_bus);
 330     pc_nic_init(pcmc, isa_bus, host_bus);
 331
 332     if (pcms->acpi_nvdimm_state.is_enabled) {
 333         nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io,
 334                                pcms->fw_cfg, OBJECT(pcms));
 335     }
 336 }
 337
 338 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 339     static void pc_init_##suffix(MachineState *machine) \
 340     { \
 341         void (*compat)(MachineState *m) = (compatfn); \
 342         if (compat) { \
 343             compat(machine); \
 344         } \
 345         pc_q35_init(machine); \
 346     } \
 347     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 348
 349
 350 static void pc_q35_machine_options(MachineClass *m)
 351 {
 352     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 353     pcmc->default_nic_model = "e1000e";
 354
 355     m->family = "pc_q35";
 356     m->desc = "Standard PC (Q35 + ICH9, 2009)";
 357     m->units_per_default_bus = 1;
 358     m->default_machine_opts = "firmware=bios-256k.bin";
 359     m->default_display = "std";
 360     m->default_kernel_irqchip_split = true;
 361     m->no_floppy = 1;
 362     machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
 363     machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
 364     machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
 365     m->max_cpus = 288;
 366 }
 367
 368 static void pc_q35_4_0_machine_options(MachineClass *m)
 369 {
 370     pc_q35_machine_options(m);
 371     m->alias = "q35";
 372 }
 373
 374 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
 375                    pc_q35_4_0_machine_options);
 376
 377 static void pc_q35_3_1_machine_options(MachineClass *m)
 378 {
 379     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 380
 381     pc_q35_4_0_machine_options(m);
 382     m->default_kernel_irqchip_split = false;
 383     m->alias = NULL;
 384     pcmc->pvh_enabled = false;
 385     compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
 386     compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
 387 }
 388
 389 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
 390                    pc_q35_3_1_machine_options);
 391
 392 static void pc_q35_3_0_machine_options(MachineClass *m)
 393 {
 394     pc_q35_3_1_machine_options(m);
 395     compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
 396     compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
 397 }
 398
 399 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
 400                     pc_q35_3_0_machine_options);
 401
 402 static void pc_q35_2_12_machine_options(MachineClass *m)
 403 {
 404     pc_q35_3_0_machine_options(m);
 405     compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
 406     compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
 407 }
 408
 409 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
 410                    pc_q35_2_12_machine_options);
 411
 412 static void pc_q35_2_11_machine_options(MachineClass *m)
 413 {
 414     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 415
 416     pc_q35_2_12_machine_options(m);
 417     pcmc->default_nic_model = "e1000";
 418     compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
 419     compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
 420 }
 421
 422 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
 423                    pc_q35_2_11_machine_options);
 424
 425 static void pc_q35_2_10_machine_options(MachineClass *m)
 426 {
 427     pc_q35_2_11_machine_options(m);
 428     compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
 429     compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
 430     m->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
 431     m->auto_enable_numa_with_memhp = false;
 432 }
 433
 434 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
 435                    pc_q35_2_10_machine_options);
 436
 437 static void pc_q35_2_9_machine_options(MachineClass *m)
 438 {
 439     pc_q35_2_10_machine_options(m);
 440     compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
 441     compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
 442 }
 443
 444 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
 445                    pc_q35_2_9_machine_options);
 446
 447 static void pc_q35_2_8_machine_options(MachineClass *m)
 448 {
 449     pc_q35_2_9_machine_options(m);
 450     compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
 451     compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
 452 }
 453
 454 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
 455                    pc_q35_2_8_machine_options);
 456
 457 static void pc_q35_2_7_machine_options(MachineClass *m)
 458 {
 459     pc_q35_2_8_machine_options(m);
 460     m->max_cpus = 255;
 461     compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
 462     compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
 463 }
 464
 465 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
 466                    pc_q35_2_7_machine_options);
 467
 468 static void pc_q35_2_6_machine_options(MachineClass *m)
 469 {
 470     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 471
 472     pc_q35_2_7_machine_options(m);
 473     pcmc->legacy_cpu_hotplug = true;
 474     pcmc->linuxboot_dma_enabled = false;
 475     compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
 476     compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
 477 }
 478
 479 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
 480                    pc_q35_2_6_machine_options);
 481
 482 static void pc_q35_2_5_machine_options(MachineClass *m)
 483 {
 484     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 485
 486     pc_q35_2_6_machine_options(m);
 487     pcmc->save_tsc_khz = false;
 488     m->legacy_fw_cfg_order = 1;
 489     compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
 490     compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
 491 }
 492
 493 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 494                    pc_q35_2_5_machine_options);
 495
 496 static void pc_q35_2_4_machine_options(MachineClass *m)
 497 {
 498     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 499
 500     pc_q35_2_5_machine_options(m);
 501     m->hw_version = "2.4.0";
 502     pcmc->broken_reserved_end = true;
 503     compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
 504     compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
 505 }
 506
 507 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 508                    pc_q35_2_4_machine_options);