target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c

   1 /* Xtensa configuration-specific ISA information.
   2
   3    Copyright (c) 2003-2019 Tensilica Inc.
   4
   5    Permission is hereby granted, free of charge, to any person obtaining
   6    a copy of this software and associated documentation files (the
   7    "Software"), to deal in the Software without restriction, including
   8    without limitation the rights to use, copy, modify, merge, publish,
   9    distribute, sublicense, and/or sell copies of the Software, and to
  10    permit persons to whom the Software is furnished to do so, subject to
  11    the following conditions:
  12
  13    The above copyright notice and this permission notice shall be included
  14    in all copies or substantial portions of the Software.
  15
  16    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  19    IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
  20    CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21    TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22    SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
  23
  24 #include "xtensa-isa.h"
  25 #include "xtensa-isa-internal.h"
  26
  27 \f
  28 /* Sysregs.  */
  29
  30 static xtensa_sysreg_internal sysregs[] = {
  31   { "LBEG", 0, 0 },
  32   { "LEND", 1, 0 },
  33   { "LCOUNT", 2, 0 },
  34   { "BR", 4, 0 },
  35   { "PTEVADDR", 83, 0 },
  36   { "DDR", 104, 0 },
  37   { "CONFIGID0", 176, 0 },
  38   { "CONFIGID1", 208, 0 },
  39   { "INTERRUPT", 226, 0 },
  40   { "INTCLEAR", 227, 0 },
  41   { "CCOUNT", 234, 0 },
  42   { "PRID", 235, 0 },
  43   { "ICOUNT", 236, 0 },
  44   { "CCOMPARE0", 240, 0 },
  45   { "CCOMPARE1", 241, 0 },
  46   { "VECBASE", 231, 0 },
  47   { "EPC1", 177, 0 },
  48   { "EPC2", 178, 0 },
  49   { "EXCSAVE1", 209, 0 },
  50   { "EXCSAVE2", 210, 0 },
  51   { "EPS2", 194, 0 },
  52   { "EXCCAUSE", 232, 0 },
  53   { "DEPC", 192, 0 },
  54   { "EXCVADDR", 238, 0 },
  55   { "WINDOWBASE", 72, 0 },
  56   { "WINDOWSTART", 73, 0 },
  57   { "SAR", 3, 0 },
  58   { "LITBASE", 5, 0 },
  59   { "PS", 230, 0 },
  60   { "MISC0", 244, 0 },
  61   { "MISC1", 245, 0 },
  62   { "INTENABLE", 228, 0 },
  63   { "ICOUNTLEVEL", 237, 0 },
  64   { "DEBUGCAUSE", 233, 0 },
  65   { "RASID", 90, 0 },
  66   { "ITLBCFG", 91, 0 },
  67   { "DTLBCFG", 92, 0 },
  68   { "CPENABLE", 224, 0 },
  69   { "SCOMPARE1", 12, 0 },
  70   { "ATOMCTL", 99, 0 },
  71   { "THREADPTR", 231, 1 },
  72   { "AE_OVF_SAR", 240, 1 },
  73   { "AE_BITHEAD", 241, 1 },
  74   { "AE_TS_FTS_BU_BP", 242, 1 },
  75   { "AE_SD_NO", 243, 1 }
  76 };
  77
  78 #define NUM_SYSREGS 45
  79 #define MAX_SPECIAL_REG 245
  80 #define MAX_USER_REG 243
  81
  82 \f
  83 /* Processor states.  */
  84
  85 static xtensa_state_internal states[] = {
  86   { "LCOUNT", 32, 0 },
  87   { "PC", 32, 0 },
  88   { "ICOUNT", 32, 0 },
  89   { "DDR", 32, 0 },
  90   { "INTERRUPT", 12, 0 },
  91   { "CCOUNT", 32, 0 },
  92   { "XTSYNC", 1, 0 },
  93   { "VECBASE", 22, 0 },
  94   { "EPC1", 32, 0 },
  95   { "EPC2", 32, 0 },
  96   { "EXCSAVE1", 32, 0 },
  97   { "EXCSAVE2", 32, 0 },
  98   { "EPS2", 15, 0 },
  99   { "EXCCAUSE", 6, 0 },
 100   { "PSINTLEVEL", 4, 0 },
 101   { "PSUM", 1, 0 },
 102   { "PSWOE", 1, 0 },
 103   { "PSRING", 2, 0 },
 104   { "PSEXCM", 1, 0 },
 105   { "DEPC", 32, 0 },
 106   { "EXCVADDR", 32, 0 },
 107   { "WindowBase", 3, 0 },
 108   { "WindowStart", 8, 0 },
 109   { "PSCALLINC", 2, 0 },
 110   { "PSOWB", 4, 0 },
 111   { "LBEG", 32, 0 },
 112   { "LEND", 32, 0 },
 113   { "SAR", 6, 0 },
 114   { "THREADPTR", 32, 0 },
 115   { "LITBADDR", 20, 0 },
 116   { "LITBEN", 1, 0 },
 117   { "MISC0", 32, 0 },
 118   { "MISC1", 32, 0 },
 119   { "InOCDMode", 1, 0 },
 120   { "INTENABLE", 12, 0 },
 121   { "ICOUNTLEVEL", 4, 0 },
 122   { "DEBUGCAUSE", 6, 0 },
 123   { "DBNUM", 4, 0 },
 124   { "CCOMPARE0", 32, 0 },
 125   { "CCOMPARE1", 32, 0 },
 126   { "ASID3", 8, 0 },
 127   { "ASID2", 8, 0 },
 128   { "ASID1", 8, 0 },
 129   { "INSTPGSZID4", 2, 0 },
 130   { "DATAPGSZID4", 2, 0 },
 131   { "PTBASE", 10, 0 },
 132   { "CPENABLE", 2, 0 },
 133   { "SCOMPARE1", 32, 0 },
 134   { "ATOMCTL", 6, 0 },
 135   { "CCON", 1, XTENSA_STATE_IS_EXPORTED },
 136   { "MPSCORE", 16, XTENSA_STATE_IS_EXPORTED },
 137   { "WMPINT_ADDR", 12, XTENSA_STATE_IS_EXPORTED },
 138   { "WMPINT_DATA", 32, XTENSA_STATE_IS_EXPORTED },
 139   { "WMPINT_TOGGLEEN", 1, XTENSA_STATE_IS_EXPORTED },
 140   { "AE_OVERFLOW", 1, 0 },
 141   { "AE_SAR", 6, 0 },
 142   { "AE_BITHEAD", 32, 0 },
 143   { "AE_BITPTR", 4, 0 },
 144   { "AE_BITSUSED", 4, 0 },
 145   { "AE_TABLESIZE", 4, 0 },
 146   { "AE_FIRST_TS", 4, 0 },
 147   { "AE_NEXTOFFSET", 27, 0 },
 148   { "AE_SEARCHDONE", 1, 0 }
 149 };
 150
 151 #define NUM_STATES 63
 152
 153 enum xtensa_state_id {
 154   STATE_LCOUNT,
 155   STATE_PC,
 156   STATE_ICOUNT,
 157   STATE_DDR,
 158   STATE_INTERRUPT,
 159   STATE_CCOUNT,
 160   STATE_XTSYNC,
 161   STATE_VECBASE,
 162   STATE_EPC1,
 163   STATE_EPC2,
 164   STATE_EXCSAVE1,
 165   STATE_EXCSAVE2,
 166   STATE_EPS2,
 167   STATE_EXCCAUSE,
 168   STATE_PSINTLEVEL,
 169   STATE_PSUM,
 170   STATE_PSWOE,
 171   STATE_PSRING,
 172   STATE_PSEXCM,
 173   STATE_DEPC,
 174   STATE_EXCVADDR,
 175   STATE_WindowBase,
 176   STATE_WindowStart,
 177   STATE_PSCALLINC,
 178   STATE_PSOWB,
 179   STATE_LBEG,
 180   STATE_LEND,
 181   STATE_SAR,
 182   STATE_THREADPTR,
 183   STATE_LITBADDR,
 184   STATE_LITBEN,
 185   STATE_MISC0,
 186   STATE_MISC1,
 187   STATE_InOCDMode,
 188   STATE_INTENABLE,
 189   STATE_ICOUNTLEVEL,
 190   STATE_DEBUGCAUSE,
 191   STATE_DBNUM,
 192   STATE_CCOMPARE0,
 193   STATE_CCOMPARE1,
 194   STATE_ASID3,
 195   STATE_ASID2,
 196   STATE_ASID1,
 197   STATE_INSTPGSZID4,
 198   STATE_DATAPGSZID4,
 199   STATE_PTBASE,
 200   STATE_CPENABLE,
 201   STATE_SCOMPARE1,
 202   STATE_ATOMCTL,
 203   STATE_CCON,
 204   STATE_MPSCORE,
 205   STATE_WMPINT_ADDR,
 206   STATE_WMPINT_DATA,
 207   STATE_WMPINT_TOGGLEEN,
 208   STATE_AE_OVERFLOW,
 209   STATE_AE_SAR,
 210   STATE_AE_BITHEAD,
 211   STATE_AE_BITPTR,
 212   STATE_AE_BITSUSED,
 213   STATE_AE_TABLESIZE,
 214   STATE_AE_FIRST_TS,
 215   STATE_AE_NEXTOFFSET,
 216   STATE_AE_SEARCHDONE
 217 };
 218
 219 \f
 220 /* Field definitions.  */
 221
 222 static unsigned
 223 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
 224 {
 225   unsigned tie_t = 0;
 226   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 227   return tie_t;
 228 }
 229
 230 static void
 231 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 232 {
 233   uint32 tie_t;
 234   tie_t = (val << 28) >> 28;
 235   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 236 }
 237
 238 static unsigned
 239 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
 240 {
 241   unsigned tie_t = 0;
 242   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 243   return tie_t;
 244 }
 245
 246 static void
 247 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 248 {
 249   uint32 tie_t;
 250   tie_t = (val << 28) >> 28;
 251   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 252 }
 253
 254 static unsigned
 255 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
 256 {
 257   unsigned tie_t = 0;
 258   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 259   return tie_t;
 260 }
 261
 262 static void
 263 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 264 {
 265   uint32 tie_t;
 266   tie_t = (val << 28) >> 28;
 267   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 268 }
 269
 270 static unsigned
 271 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
 272 {
 273   unsigned tie_t = 0;
 274   tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
 275   return tie_t;
 276 }
 277
 278 static void
 279 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 280 {
 281   uint32 tie_t;
 282   tie_t = (val << 28) >> 28;
 283   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
 284 }
 285
 286 static unsigned
 287 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
 288 {
 289   unsigned tie_t = 0;
 290   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 291   return tie_t;
 292 }
 293
 294 static void
 295 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 296 {
 297   uint32 tie_t;
 298   tie_t = (val << 28) >> 28;
 299   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 300 }
 301
 302 static unsigned
 303 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
 304 {
 305   unsigned tie_t = 0;
 306   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 307   return tie_t;
 308 }
 309
 310 static void
 311 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 312 {
 313   uint32 tie_t;
 314   tie_t = (val << 28) >> 28;
 315   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 316 }
 317
 318 static unsigned
 319 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
 320 {
 321   unsigned tie_t = 0;
 322   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
 323   return tie_t;
 324 }
 325
 326 static void
 327 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 328 {
 329   uint32 tie_t;
 330   tie_t = (val << 30) >> 30;
 331   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
 332 }
 333
 334 static unsigned
 335 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
 336 {
 337   unsigned tie_t = 0;
 338   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
 339   return tie_t;
 340 }
 341
 342 static void
 343 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 344 {
 345   uint32 tie_t;
 346   tie_t = (val << 30) >> 30;
 347   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
 348 }
 349
 350 static unsigned
 351 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
 352 {
 353   unsigned tie_t = 0;
 354   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 355   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 356   return tie_t;
 357 }
 358
 359 static void
 360 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 361 {
 362   uint32 tie_t;
 363   tie_t = (val << 28) >> 28;
 364   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 365   tie_t = (val << 24) >> 28;
 366   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 367 }
 368
 369 static unsigned
 370 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
 371 {
 372   unsigned tie_t = 0;
 373   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 374   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 375   return tie_t;
 376 }
 377
 378 static void
 379 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 380 {
 381   uint32 tie_t;
 382   tie_t = (val << 28) >> 28;
 383   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 384   tie_t = (val << 24) >> 28;
 385   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 386 }
 387
 388 static unsigned
 389 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
 390 {
 391   unsigned tie_t = 0;
 392   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
 393   return tie_t;
 394 }
 395
 396 static void
 397 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 398 {
 399   uint32 tie_t;
 400   tie_t = (val << 29) >> 29;
 401   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
 402 }
 403
 404 static unsigned
 405 Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn)
 406 {
 407   unsigned tie_t = 0;
 408   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
 409   return tie_t;
 410 }
 411
 412 static void
 413 Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 414 {
 415   uint32 tie_t;
 416   tie_t = (val << 31) >> 31;
 417   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
 418 }
 419
 420 static unsigned
 421 Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn)
 422 {
 423   unsigned tie_t = 0;
 424   tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
 425   return tie_t;
 426 }
 427
 428 static void
 429 Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 430 {
 431   uint32 tie_t;
 432   tie_t = (val << 30) >> 30;
 433   insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
 434 }
 435
 436 static unsigned
 437 Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn)
 438 {
 439   unsigned tie_t = 0;
 440   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
 441   return tie_t;
 442 }
 443
 444 static void
 445 Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 446 {
 447   uint32 tie_t;
 448   tie_t = (val << 30) >> 30;
 449   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
 450 }
 451
 452 static unsigned
 453 Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn)
 454 {
 455   unsigned tie_t = 0;
 456   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
 457   return tie_t;
 458 }
 459
 460 static void
 461 Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 462 {
 463   uint32 tie_t;
 464   tie_t = (val << 31) >> 31;
 465   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
 466 }
 467
 468 static unsigned
 469 Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn)
 470 {
 471   unsigned tie_t = 0;
 472   tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
 473   return tie_t;
 474 }
 475
 476 static void
 477 Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 478 {
 479   uint32 tie_t;
 480   tie_t = (val << 30) >> 30;
 481   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
 482 }
 483
 484 static unsigned
 485 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
 486 {
 487   unsigned tie_t = 0;
 488   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 489   return tie_t;
 490 }
 491
 492 static void
 493 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 494 {
 495   uint32 tie_t;
 496   tie_t = (val << 28) >> 28;
 497   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 498 }
 499
 500 static unsigned
 501 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
 502 {
 503   unsigned tie_t = 0;
 504   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 505   return tie_t;
 506 }
 507
 508 static void
 509 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 510 {
 511   uint32 tie_t;
 512   tie_t = (val << 28) >> 28;
 513   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 514 }
 515
 516 static unsigned
 517 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
 518 {
 519   unsigned tie_t = 0;
 520   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 521   return tie_t;
 522 }
 523
 524 static void
 525 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 526 {
 527   uint32 tie_t;
 528   tie_t = (val << 28) >> 28;
 529   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 530 }
 531
 532 static unsigned
 533 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
 534 {
 535   unsigned tie_t = 0;
 536   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 537   return tie_t;
 538 }
 539
 540 static void
 541 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 542 {
 543   uint32 tie_t;
 544   tie_t = (val << 28) >> 28;
 545   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 546 }
 547
 548 static unsigned
 549 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
 550 {
 551   unsigned tie_t = 0;
 552   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
 553   return tie_t;
 554 }
 555
 556 static void
 557 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 558 {
 559   uint32 tie_t;
 560   tie_t = (val << 31) >> 31;
 561   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
 562 }
 563
 564 static unsigned
 565 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
 566 {
 567   unsigned tie_t = 0;
 568   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
 569   return tie_t;
 570 }
 571
 572 static void
 573 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 574 {
 575   uint32 tie_t;
 576   tie_t = (val << 31) >> 31;
 577   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
 578 }
 579
 580 static unsigned
 581 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
 582 {
 583   unsigned tie_t = 0;
 584   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 585   return tie_t;
 586 }
 587
 588 static void
 589 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 590 {
 591   uint32 tie_t;
 592   tie_t = (val << 28) >> 28;
 593   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 594 }
 595
 596 static unsigned
 597 Field_ftsf61ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 598 {
 599   unsigned tie_t = 0;
 600   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
 601   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
 602   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 603   return tie_t;
 604 }
 605
 606 static void
 607 Field_ftsf61ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 608 {
 609   uint32 tie_t;
 610   tie_t = (val << 28) >> 28;
 611   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 612   tie_t = (val << 27) >> 31;
 613   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
 614   tie_t = (val << 22) >> 27;
 615   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
 616 }
 617
 618 static unsigned
 619 Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 620 {
 621   unsigned tie_t = 0;
 622   tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
 623   return tie_t;
 624 }
 625
 626 static void
 627 Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 628 {
 629   uint32 tie_t;
 630   tie_t = (val << 25) >> 25;
 631   insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
 632 }
 633
 634 static unsigned
 635 Field_ftsf330ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 636 {
 637   unsigned tie_t = 0;
 638   tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
 639   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 640   return tie_t;
 641 }
 642
 643 static void
 644 Field_ftsf330ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 645 {
 646   uint32 tie_t;
 647   tie_t = (val << 28) >> 28;
 648   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 649   tie_t = (val << 26) >> 30;
 650   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
 651 }
 652
 653 static unsigned
 654 Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 655 {
 656   unsigned tie_t = 0;
 657   tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
 658   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
 659   return tie_t;
 660 }
 661
 662 static void
 663 Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 664 {
 665   uint32 tie_t;
 666   tie_t = (val << 31) >> 31;
 667   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
 668   tie_t = (val << 22) >> 23;
 669   insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
 670 }
 671
 672 static unsigned
 673 Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 674 {
 675   unsigned tie_t = 0;
 676   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
 677   return tie_t;
 678 }
 679
 680 static void
 681 Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 682 {
 683   uint32 tie_t;
 684   tie_t = (val << 29) >> 29;
 685   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
 686 }
 687
 688 static unsigned
 689 Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 690 {
 691   unsigned tie_t = 0;
 692   tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
 693   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
 694   return tie_t;
 695 }
 696
 697 static void
 698 Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 699 {
 700   uint32 tie_t;
 701   tie_t = (val << 31) >> 31;
 702   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
 703   tie_t = (val << 22) >> 23;
 704   insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
 705 }
 706
 707 static unsigned
 708 Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 709 {
 710   unsigned tie_t = 0;
 711   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
 712   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
 713   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
 714   return tie_t;
 715 }
 716
 717 static void
 718 Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 719 {
 720   uint32 tie_t;
 721   tie_t = (val << 31) >> 31;
 722   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
 723   tie_t = (val << 27) >> 28;
 724   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
 725   tie_t = (val << 25) >> 30;
 726   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
 727 }
 728
 729 static unsigned
 730 Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 731 {
 732   unsigned tie_t = 0;
 733   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
 734   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
 735   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
 736   return tie_t;
 737 }
 738
 739 static void
 740 Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 741 {
 742   uint32 tie_t;
 743   tie_t = (val << 31) >> 31;
 744   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
 745   tie_t = (val << 27) >> 28;
 746   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
 747   tie_t = (val << 25) >> 30;
 748   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
 749 }
 750
 751 static unsigned
 752 Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 753 {
 754   unsigned tie_t = 0;
 755   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
 756   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
 757   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
 758   return tie_t;
 759 }
 760
 761 static void
 762 Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 763 {
 764   uint32 tie_t;
 765   tie_t = (val << 31) >> 31;
 766   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
 767   tie_t = (val << 27) >> 28;
 768   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
 769   tie_t = (val << 25) >> 30;
 770   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
 771 }
 772
 773 static unsigned
 774 Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 775 {
 776   unsigned tie_t = 0;
 777   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
 778   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
 779   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
 780   return tie_t;
 781 }
 782
 783 static void
 784 Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 785 {
 786   uint32 tie_t;
 787   tie_t = (val << 31) >> 31;
 788   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
 789   tie_t = (val << 27) >> 28;
 790   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
 791   tie_t = (val << 25) >> 30;
 792   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
 793 }
 794
 795 static unsigned
 796 Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 797 {
 798   unsigned tie_t = 0;
 799   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
 800   tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
 801   return tie_t;
 802 }
 803
 804 static void
 805 Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 806 {
 807   uint32 tie_t;
 808   tie_t = (val << 30) >> 30;
 809   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
 810   tie_t = (val << 28) >> 30;
 811   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
 812 }
 813
 814 static unsigned
 815 Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 816 {
 817   unsigned tie_t = 0;
 818   tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
 819   return tie_t;
 820 }
 821
 822 static void
 823 Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 824 {
 825   uint32 tie_t;
 826   tie_t = (val << 29) >> 29;
 827   insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
 828 }
 829
 830 static unsigned
 831 Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 832 {
 833   unsigned tie_t = 0;
 834   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
 835   tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
 836   tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31);
 837   return tie_t;
 838 }
 839
 840 static void
 841 Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 842 {
 843   uint32 tie_t;
 844   tie_t = (val << 31) >> 31;
 845   insn[0] = (insn[0] & ~0x4) | (tie_t << 2);
 846   tie_t = (val << 29) >> 30;
 847   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
 848   tie_t = (val << 27) >> 30;
 849   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
 850 }
 851
 852 static unsigned
 853 Field_ftsf347_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 854 {
 855   unsigned tie_t = 0;
 856   tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
 857   return tie_t;
 858 }
 859
 860 static void
 861 Field_ftsf347_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 862 {
 863   uint32 tie_t;
 864   tie_t = (val << 30) >> 30;
 865   insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
 866 }
 867
 868 static unsigned
 869 Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 870 {
 871   unsigned tie_t = 0;
 872   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
 873   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
 874   return tie_t;
 875 }
 876
 877 static void
 878 Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 879 {
 880   uint32 tie_t;
 881   tie_t = (val << 28) >> 28;
 882   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
 883   tie_t = (val << 26) >> 30;
 884   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
 885 }
 886
 887 static unsigned
 888 Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 889 {
 890   unsigned tie_t = 0;
 891   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
 892   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
 893   return tie_t;
 894 }
 895
 896 static void
 897 Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 898 {
 899   uint32 tie_t;
 900   tie_t = (val << 28) >> 28;
 901   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
 902   tie_t = (val << 26) >> 30;
 903   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
 904 }
 905
 906 static unsigned
 907 Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 908 {
 909   unsigned tie_t = 0;
 910   tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
 911   return tie_t;
 912 }
 913
 914 static void
 915 Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 916 {
 917   uint32 tie_t;
 918   tie_t = (val << 30) >> 30;
 919   insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
 920 }
 921
 922 static unsigned
 923 Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 924 {
 925   unsigned tie_t = 0;
 926   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
 927   tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
 928   return tie_t;
 929 }
 930
 931 static void
 932 Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 933 {
 934   uint32 tie_t;
 935   tie_t = (val << 28) >> 28;
 936   insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
 937   tie_t = (val << 25) >> 29;
 938   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
 939 }
 940
 941 static unsigned
 942 Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 943 {
 944   unsigned tie_t = 0;
 945   tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
 946   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
 947   return tie_t;
 948 }
 949
 950 static void
 951 Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 952 {
 953   uint32 tie_t;
 954   tie_t = (val << 31) >> 31;
 955   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
 956   tie_t = (val << 22) >> 23;
 957   insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
 958 }
 959
 960 static unsigned
 961 Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 962 {
 963   unsigned tie_t = 0;
 964   tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
 965   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
 966   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
 967   return tie_t;
 968 }
 969
 970 static void
 971 Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 972 {
 973   uint32 tie_t;
 974   tie_t = (val << 31) >> 31;
 975   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
 976   tie_t = (val << 30) >> 31;
 977   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
 978   tie_t = (val << 23) >> 25;
 979   insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
 980 }
 981
 982 static unsigned
 983 Field_ftsf340_Slot_ae_slot1_get (const xtensa_insnbuf insn)
 984 {
 985   unsigned tie_t = 0;
 986   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
 987   return tie_t;
 988 }
 989
 990 static void
 991 Field_ftsf340_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
 992 {
 993   uint32 tie_t;
 994   tie_t = (val << 30) >> 30;
 995   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
 996 }
 997
 998 static unsigned
 999 Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1000 {
1001   unsigned tie_t = 0;
1002   tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
1003   tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
1004   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1005   return tie_t;
1006 }
1007
1008 static void
1009 Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1010 {
1011   uint32 tie_t;
1012   tie_t = (val << 31) >> 31;
1013   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1014   tie_t = (val << 29) >> 30;
1015   insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
1016   tie_t = (val << 22) >> 25;
1017   insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
1018 }
1019
1020 static unsigned
1021 Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1022 {
1023   unsigned tie_t = 0;
1024   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1025   return tie_t;
1026 }
1027
1028 static void
1029 Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1030 {
1031   uint32 tie_t;
1032   tie_t = (val << 31) >> 31;
1033   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1034 }
1035
1036 static unsigned
1037 Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1038 {
1039   unsigned tie_t = 0;
1040   tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
1041   tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
1042   return tie_t;
1043 }
1044
1045 static void
1046 Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1047 {
1048   uint32 tie_t;
1049   tie_t = (val << 28) >> 28;
1050   insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
1051   tie_t = (val << 21) >> 25;
1052   insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
1053 }
1054
1055 static unsigned
1056 Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1057 {
1058   unsigned tie_t = 0;
1059   tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
1060   tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
1061   return tie_t;
1062 }
1063
1064 static void
1065 Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1066 {
1067   uint32 tie_t;
1068   tie_t = (val << 28) >> 28;
1069   insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
1070   tie_t = (val << 21) >> 25;
1071   insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
1072 }
1073
1074 static unsigned
1075 Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1076 {
1077   unsigned tie_t = 0;
1078   tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
1079   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1080   return tie_t;
1081 }
1082
1083 static void
1084 Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1085 {
1086   uint32 tie_t;
1087   tie_t = (val << 31) >> 31;
1088   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1089   tie_t = (val << 22) >> 23;
1090   insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
1091 }
1092
1093 static unsigned
1094 Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1095 {
1096   unsigned tie_t = 0;
1097   tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
1098   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1099   return tie_t;
1100 }
1101
1102 static void
1103 Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1104 {
1105   uint32 tie_t;
1106   tie_t = (val << 31) >> 31;
1107   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1108   tie_t = (val << 22) >> 23;
1109   insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
1110 }
1111
1112 static unsigned
1113 Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1114 {
1115   unsigned tie_t = 0;
1116   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1117   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
1118   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1119   return tie_t;
1120 }
1121
1122 static void
1123 Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1124 {
1125   uint32 tie_t;
1126   tie_t = (val << 28) >> 28;
1127   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1128   tie_t = (val << 26) >> 30;
1129   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
1130   tie_t = (val << 21) >> 27;
1131   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1132 }
1133
1134 static unsigned
1135 Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1136 {
1137   unsigned tie_t = 0;
1138   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1139   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1140   return tie_t;
1141 }
1142
1143 static void
1144 Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1145 {
1146   uint32 tie_t;
1147   tie_t = (val << 25) >> 25;
1148   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1149   tie_t = (val << 20) >> 27;
1150   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1151 }
1152
1153 static unsigned
1154 Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1155 {
1156   unsigned tie_t = 0;
1157   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1158   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1159   return tie_t;
1160 }
1161
1162 static void
1163 Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1164 {
1165   uint32 tie_t;
1166   tie_t = (val << 28) >> 28;
1167   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1168   tie_t = (val << 23) >> 27;
1169   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1170 }
1171
1172 static unsigned
1173 Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1174 {
1175   unsigned tie_t = 0;
1176   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
1177   return tie_t;
1178 }
1179
1180 static void
1181 Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1182 {
1183   uint32 tie_t;
1184   tie_t = (val << 30) >> 30;
1185   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
1186 }
1187
1188 static unsigned
1189 Field_ftsf59ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1190 {
1191   unsigned tie_t = 0;
1192   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1193   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
1194   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1195   return tie_t;
1196 }
1197
1198 static void
1199 Field_ftsf59ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1200 {
1201   uint32 tie_t;
1202   tie_t = (val << 28) >> 28;
1203   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1204   tie_t = (val << 26) >> 30;
1205   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
1206   tie_t = (val << 21) >> 27;
1207   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1208 }
1209
1210 static unsigned
1211 Field_ftsf119ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1212 {
1213   unsigned tie_t = 0;
1214   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1215   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1216   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1217   return tie_t;
1218 }
1219
1220 static void
1221 Field_ftsf119ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1222 {
1223   uint32 tie_t;
1224   tie_t = (val << 25) >> 25;
1225   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1226   tie_t = (val << 24) >> 31;
1227   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1228   tie_t = (val << 21) >> 29;
1229   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1230 }
1231
1232 static unsigned
1233 Field_ftsf338_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1234 {
1235   unsigned tie_t = 0;
1236   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1237   return tie_t;
1238 }
1239
1240 static void
1241 Field_ftsf338_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1242 {
1243   uint32 tie_t;
1244   tie_t = (val << 31) >> 31;
1245   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1246 }
1247
1248 static unsigned
1249 Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1250 {
1251   unsigned tie_t = 0;
1252   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1253   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1254   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1255   return tie_t;
1256 }
1257
1258 static void
1259 Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1260 {
1261   uint32 tie_t;
1262   tie_t = (val << 28) >> 28;
1263   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1264   tie_t = (val << 27) >> 31;
1265   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1266   tie_t = (val << 22) >> 27;
1267   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1268 }
1269
1270 static unsigned
1271 Field_ftsf67ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1272 {
1273   unsigned tie_t = 0;
1274   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1275   tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
1276   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1277   return tie_t;
1278 }
1279
1280 static void
1281 Field_ftsf67ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1282 {
1283   uint32 tie_t;
1284   tie_t = (val << 28) >> 28;
1285   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1286   tie_t = (val << 26) >> 30;
1287   insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
1288   tie_t = (val << 21) >> 27;
1289   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1290 }
1291
1292 static unsigned
1293 Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1294 {
1295   unsigned tie_t = 0;
1296   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1297   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1298   return tie_t;
1299 }
1300
1301 static void
1302 Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1303 {
1304   uint32 tie_t;
1305   tie_t = (val << 25) >> 25;
1306   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1307   tie_t = (val << 20) >> 27;
1308   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1309 }
1310
1311 static unsigned
1312 Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1313 {
1314   unsigned tie_t = 0;
1315   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1316   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1317   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1318   return tie_t;
1319 }
1320
1321 static void
1322 Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1323 {
1324   uint32 tie_t;
1325   tie_t = (val << 31) >> 31;
1326   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1327   tie_t = (val << 27) >> 28;
1328   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1329   tie_t = (val << 25) >> 30;
1330   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1331 }
1332
1333 static unsigned
1334 Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1335 {
1336   unsigned tie_t = 0;
1337   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1338   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1339   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1340   return tie_t;
1341 }
1342
1343 static void
1344 Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1345 {
1346   uint32 tie_t;
1347   tie_t = (val << 31) >> 31;
1348   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1349   tie_t = (val << 27) >> 28;
1350   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1351   tie_t = (val << 25) >> 30;
1352   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1353 }
1354
1355 static unsigned
1356 Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1357 {
1358   unsigned tie_t = 0;
1359   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1360   tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
1361   return tie_t;
1362 }
1363
1364 static void
1365 Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1366 {
1367   uint32 tie_t;
1368   tie_t = (val << 30) >> 30;
1369   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
1370   tie_t = (val << 28) >> 30;
1371   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1372 }
1373
1374 static unsigned
1375 Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1376 {
1377   unsigned tie_t = 0;
1378   tie_t = (tie_t << 6) | ((insn[0] << 23) >> 26);
1379   return tie_t;
1380 }
1381
1382 static void
1383 Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1384 {
1385   uint32 tie_t;
1386   tie_t = (val << 26) >> 26;
1387   insn[0] = (insn[0] & ~0x1f8) | (tie_t << 3);
1388 }
1389
1390 static unsigned
1391 Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1392 {
1393   unsigned tie_t = 0;
1394   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1395   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1396   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1397   return tie_t;
1398 }
1399
1400 static void
1401 Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1402 {
1403   uint32 tie_t;
1404   tie_t = (val << 31) >> 31;
1405   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1406   tie_t = (val << 27) >> 28;
1407   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1408   tie_t = (val << 25) >> 30;
1409   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1410 }
1411
1412 static unsigned
1413 Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1414 {
1415   unsigned tie_t = 0;
1416   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1417   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1418   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1419   return tie_t;
1420 }
1421
1422 static void
1423 Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1424 {
1425   uint32 tie_t;
1426   tie_t = (val << 31) >> 31;
1427   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1428   tie_t = (val << 27) >> 28;
1429   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1430   tie_t = (val << 25) >> 30;
1431   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1432 }
1433
1434 static unsigned
1435 Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1436 {
1437   unsigned tie_t = 0;
1438   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1439   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1440   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1441   return tie_t;
1442 }
1443
1444 static void
1445 Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1446 {
1447   uint32 tie_t;
1448   tie_t = (val << 31) >> 31;
1449   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1450   tie_t = (val << 27) >> 28;
1451   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1452   tie_t = (val << 25) >> 30;
1453   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1454 }
1455
1456 static unsigned
1457 Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1458 {
1459   unsigned tie_t = 0;
1460   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1461   tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
1462   return tie_t;
1463 }
1464
1465 static void
1466 Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1467 {
1468   uint32 tie_t;
1469   tie_t = (val << 30) >> 30;
1470   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
1471   tie_t = (val << 28) >> 30;
1472   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1473 }
1474
1475 static unsigned
1476 Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1477 {
1478   unsigned tie_t = 0;
1479   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1480   tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
1481   return tie_t;
1482 }
1483
1484 static void
1485 Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1486 {
1487   uint32 tie_t;
1488   tie_t = (val << 30) >> 30;
1489   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
1490   tie_t = (val << 28) >> 30;
1491   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1492 }
1493
1494 static unsigned
1495 Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1496 {
1497   unsigned tie_t = 0;
1498   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1499   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1500   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1501   return tie_t;
1502 }
1503
1504 static void
1505 Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1506 {
1507   uint32 tie_t;
1508   tie_t = (val << 31) >> 31;
1509   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1510   tie_t = (val << 27) >> 28;
1511   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1512   tie_t = (val << 25) >> 30;
1513   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1514 }
1515
1516 static unsigned
1517 Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1518 {
1519   unsigned tie_t = 0;
1520   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1521   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1522   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1523   return tie_t;
1524 }
1525
1526 static void
1527 Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1528 {
1529   uint32 tie_t;
1530   tie_t = (val << 31) >> 31;
1531   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1532   tie_t = (val << 27) >> 28;
1533   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1534   tie_t = (val << 25) >> 30;
1535   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1536 }
1537
1538 static unsigned
1539 Field_ftsf100ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1540 {
1541   unsigned tie_t = 0;
1542   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1543   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1544   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1545   return tie_t;
1546 }
1547
1548 static void
1549 Field_ftsf100ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1550 {
1551   uint32 tie_t;
1552   tie_t = (val << 31) >> 31;
1553   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1554   tie_t = (val << 27) >> 28;
1555   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1556   tie_t = (val << 25) >> 30;
1557   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1558 }
1559
1560 static unsigned
1561 Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1562 {
1563   unsigned tie_t = 0;
1564   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1565   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1566   return tie_t;
1567 }
1568
1569 static void
1570 Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1571 {
1572   uint32 tie_t;
1573   tie_t = (val << 29) >> 29;
1574   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1575   tie_t = (val << 27) >> 30;
1576   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1577 }
1578
1579 static unsigned
1580 Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1581 {
1582   unsigned tie_t = 0;
1583   tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27);
1584   return tie_t;
1585 }
1586
1587 static void
1588 Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1589 {
1590   uint32 tie_t;
1591   tie_t = (val << 27) >> 27;
1592   insn[0] = (insn[0] & ~0xf8) | (tie_t << 3);
1593 }
1594
1595 static unsigned
1596 Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1597 {
1598   unsigned tie_t = 0;
1599   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1600   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1601   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1602   return tie_t;
1603 }
1604
1605 static void
1606 Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1607 {
1608   uint32 tie_t;
1609   tie_t = (val << 31) >> 31;
1610   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1611   tie_t = (val << 27) >> 28;
1612   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1613   tie_t = (val << 25) >> 30;
1614   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1615 }
1616
1617 static unsigned
1618 Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1619 {
1620   unsigned tie_t = 0;
1621   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1622   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1623   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1624   return tie_t;
1625 }
1626
1627 static void
1628 Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1629 {
1630   uint32 tie_t;
1631   tie_t = (val << 31) >> 31;
1632   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1633   tie_t = (val << 27) >> 28;
1634   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1635   tie_t = (val << 25) >> 30;
1636   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1637 }
1638
1639 static unsigned
1640 Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1641 {
1642   unsigned tie_t = 0;
1643   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1644   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1645   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1646   return tie_t;
1647 }
1648
1649 static void
1650 Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1651 {
1652   uint32 tie_t;
1653   tie_t = (val << 31) >> 31;
1654   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1655   tie_t = (val << 27) >> 28;
1656   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1657   tie_t = (val << 25) >> 30;
1658   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1659 }
1660
1661 static unsigned
1662 Field_ftsf98ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1663 {
1664   unsigned tie_t = 0;
1665   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1666   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1667   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1668   return tie_t;
1669 }
1670
1671 static void
1672 Field_ftsf98ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1673 {
1674   uint32 tie_t;
1675   tie_t = (val << 31) >> 31;
1676   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1677   tie_t = (val << 27) >> 28;
1678   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1679   tie_t = (val << 25) >> 30;
1680   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1681 }
1682
1683 static unsigned
1684 Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1685 {
1686   unsigned tie_t = 0;
1687   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1688   tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
1689   tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30);
1690   return tie_t;
1691 }
1692
1693 static void
1694 Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1695 {
1696   uint32 tie_t;
1697   tie_t = (val << 30) >> 30;
1698   insn[0] = (insn[0] & ~0x6) | (tie_t << 1);
1699   tie_t = (val << 28) >> 30;
1700   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
1701   tie_t = (val << 26) >> 30;
1702   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1703 }
1704
1705 static unsigned
1706 Field_ftsf208_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1707 {
1708   unsigned tie_t = 0;
1709   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
1710   return tie_t;
1711 }
1712
1713 static void
1714 Field_ftsf208_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1715 {
1716   uint32 tie_t;
1717   tie_t = (val << 31) >> 31;
1718   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
1719 }
1720
1721 static unsigned
1722 Field_ftsf91ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1723 {
1724   unsigned tie_t = 0;
1725   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1726   tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
1727   tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
1728   return tie_t;
1729 }
1730
1731 static void
1732 Field_ftsf91ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1733 {
1734   uint32 tie_t;
1735   tie_t = (val << 29) >> 29;
1736   insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
1737   tie_t = (val << 27) >> 30;
1738   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
1739   tie_t = (val << 25) >> 30;
1740   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1741 }
1742
1743 static unsigned
1744 Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1745 {
1746   unsigned tie_t = 0;
1747   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1748   tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
1749   tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
1750   return tie_t;
1751 }
1752
1753 static void
1754 Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1755 {
1756   uint32 tie_t;
1757   tie_t = (val << 29) >> 29;
1758   insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
1759   tie_t = (val << 27) >> 30;
1760   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
1761   tie_t = (val << 25) >> 30;
1762   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1763 }
1764
1765 static unsigned
1766 Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1767 {
1768   unsigned tie_t = 0;
1769   tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31);
1770   return tie_t;
1771 }
1772
1773 static void
1774 Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1775 {
1776   uint32 tie_t;
1777   tie_t = (val << 31) >> 31;
1778   insn[0] = (insn[0] & ~0x2000) | (tie_t << 13);
1779 }
1780
1781 static unsigned
1782 Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1783 {
1784   unsigned tie_t = 0;
1785   tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30);
1786   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1787   return tie_t;
1788 }
1789
1790 static void
1791 Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1792 {
1793   uint32 tie_t;
1794   tie_t = (val << 25) >> 25;
1795   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1796   tie_t = (val << 23) >> 30;
1797   insn[0] = (insn[0] & ~0x1800) | (tie_t << 11);
1798 }
1799
1800 static unsigned
1801 Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1802 {
1803   unsigned tie_t = 0;
1804   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1805   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1806   return tie_t;
1807 }
1808
1809 static void
1810 Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1811 {
1812   uint32 tie_t;
1813   tie_t = (val << 25) >> 25;
1814   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1815   tie_t = (val << 22) >> 29;
1816   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1817 }
1818
1819 static unsigned
1820 Field_ftsf122ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1821 {
1822   unsigned tie_t = 0;
1823   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1824   tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27);
1825   return tie_t;
1826 }
1827
1828 static void
1829 Field_ftsf122ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1830 {
1831   uint32 tie_t;
1832   tie_t = (val << 27) >> 27;
1833   insn[0] = (insn[0] & ~0x7c) | (tie_t << 2);
1834   tie_t = (val << 24) >> 29;
1835   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1836 }
1837
1838 static unsigned
1839 Field_ftsf346ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1840 {
1841   unsigned tie_t = 0;
1842   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
1843   tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
1844   return tie_t;
1845 }
1846
1847 static void
1848 Field_ftsf346ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1849 {
1850   uint32 tie_t;
1851   tie_t = (val << 30) >> 30;
1852   insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
1853   tie_t = (val << 28) >> 30;
1854   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
1855 }
1856
1857 static unsigned
1858 Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1859 {
1860   unsigned tie_t = 0;
1861   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1862   tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23);
1863   return tie_t;
1864 }
1865
1866 static void
1867 Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1868 {
1869   uint32 tie_t;
1870   tie_t = (val << 23) >> 23;
1871   insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0);
1872   tie_t = (val << 20) >> 29;
1873   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1874 }
1875
1876 static unsigned
1877 Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1878 {
1879   unsigned tie_t = 0;
1880   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1881   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1882   return tie_t;
1883 }
1884
1885 static void
1886 Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1887 {
1888   uint32 tie_t;
1889   tie_t = (val << 25) >> 25;
1890   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1891   tie_t = (val << 22) >> 29;
1892   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1893 }
1894
1895 static unsigned
1896 Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1897 {
1898   unsigned tie_t = 0;
1899   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1900   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1901   return tie_t;
1902 }
1903
1904 static void
1905 Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1906 {
1907   uint32 tie_t;
1908   tie_t = (val << 25) >> 25;
1909   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1910   tie_t = (val << 22) >> 29;
1911   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1912 }
1913
1914 static unsigned
1915 Field_ftsf104ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1916 {
1917   unsigned tie_t = 0;
1918   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1919   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1920   return tie_t;
1921 }
1922
1923 static void
1924 Field_ftsf104ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1925 {
1926   uint32 tie_t;
1927   tie_t = (val << 29) >> 29;
1928   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1929   tie_t = (val << 26) >> 29;
1930   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1931 }
1932
1933 static unsigned
1934 Field_ftsf105ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1935 {
1936   unsigned tie_t = 0;
1937   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1938   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1939   return tie_t;
1940 }
1941
1942 static void
1943 Field_ftsf105ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1944 {
1945   uint32 tie_t;
1946   tie_t = (val << 29) >> 29;
1947   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1948   tie_t = (val << 26) >> 29;
1949   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1950 }
1951
1952 static unsigned
1953 Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1954 {
1955   unsigned tie_t = 0;
1956   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1957   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1958   return tie_t;
1959 }
1960
1961 static void
1962 Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1963 {
1964   uint32 tie_t;
1965   tie_t = (val << 25) >> 25;
1966   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1967   tie_t = (val << 22) >> 29;
1968   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1969 }
1970
1971 static unsigned
1972 Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1973 {
1974   unsigned tie_t = 0;
1975   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1976   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1977   return tie_t;
1978 }
1979
1980 static void
1981 Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1982 {
1983   uint32 tie_t;
1984   tie_t = (val << 25) >> 25;
1985   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1986   tie_t = (val << 22) >> 29;
1987   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1988 }
1989
1990 static unsigned
1991 Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1992 {
1993   unsigned tie_t = 0;
1994   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1995   tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23);
1996   return tie_t;
1997 }
1998
1999 static void
2000 Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2001 {
2002   uint32 tie_t;
2003   tie_t = (val << 23) >> 23;
2004   insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0);
2005   tie_t = (val << 20) >> 29;
2006   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2007 }
2008
2009 static unsigned
2010 Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2011 {
2012   unsigned tie_t = 0;
2013   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2014   tie_t = (tie_t << 6) | ((insn[0] << 25) >> 26);
2015   return tie_t;
2016 }
2017
2018 static void
2019 Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2020 {
2021   uint32 tie_t;
2022   tie_t = (val << 26) >> 26;
2023   insn[0] = (insn[0] & ~0x7e) | (tie_t << 1);
2024   tie_t = (val << 23) >> 29;
2025   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2026 }
2027
2028 static unsigned
2029 Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2030 {
2031   unsigned tie_t = 0;
2032   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2033   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
2034   return tie_t;
2035 }
2036
2037 static void
2038 Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2039 {
2040   uint32 tie_t;
2041   tie_t = (val << 31) >> 31;
2042   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
2043   tie_t = (val << 29) >> 30;
2044   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2045 }
2046
2047 static unsigned
2048 Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2049 {
2050   unsigned tie_t = 0;
2051   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2052   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
2053   return tie_t;
2054 }
2055
2056 static void
2057 Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2058 {
2059   uint32 tie_t;
2060   tie_t = (val << 25) >> 25;
2061   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
2062   tie_t = (val << 22) >> 29;
2063   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2064 }
2065
2066 static unsigned
2067 Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2068 {
2069   unsigned tie_t = 0;
2070   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2071   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
2072   return tie_t;
2073 }
2074
2075 static void
2076 Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2077 {
2078   uint32 tie_t;
2079   tie_t = (val << 25) >> 25;
2080   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
2081   tie_t = (val << 22) >> 29;
2082   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2083 }
2084
2085 static unsigned
2086 Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2087 {
2088   unsigned tie_t = 0;
2089   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2090   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
2091   return tie_t;
2092 }
2093
2094 static void
2095 Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2096 {
2097   uint32 tie_t;
2098   tie_t = (val << 25) >> 25;
2099   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
2100   tie_t = (val << 22) >> 29;
2101   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2102 }
2103
2104 static unsigned
2105 Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2106 {
2107   unsigned tie_t = 0;
2108   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2109   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
2110   return tie_t;
2111 }
2112
2113 static void
2114 Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2115 {
2116   uint32 tie_t;
2117   tie_t = (val << 25) >> 25;
2118   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
2119   tie_t = (val << 22) >> 29;
2120   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2121 }
2122
2123 static unsigned
2124 Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2125 {
2126   unsigned tie_t = 0;
2127   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
2128   return tie_t;
2129 }
2130
2131 static void
2132 Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2133 {
2134   uint32 tie_t;
2135   tie_t = (val << 27) >> 27;
2136   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
2137 }
2138
2139 static unsigned
2140 Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2141 {
2142   unsigned tie_t = 0;
2143   tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
2144   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
2145   return tie_t;
2146 }
2147
2148 static void
2149 Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2150 {
2151   uint32 tie_t;
2152   tie_t = (val << 31) >> 31;
2153   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
2154   tie_t = (val << 22) >> 23;
2155   insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
2156 }
2157
2158 static unsigned
2159 Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2160 {
2161   unsigned tie_t = 0;
2162   tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
2163   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
2164   return tie_t;
2165 }
2166
2167 static void
2168 Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2169 {
2170   uint32 tie_t;
2171   tie_t = (val << 31) >> 31;
2172   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
2173   tie_t = (val << 22) >> 23;
2174   insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
2175 }
2176
2177 static unsigned
2178 Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2179 {
2180   unsigned tie_t = 0;
2181   tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
2182   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
2183   return tie_t;
2184 }
2185
2186 static void
2187 Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2188 {
2189   uint32 tie_t;
2190   tie_t = (val << 31) >> 31;
2191   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
2192   tie_t = (val << 22) >> 23;
2193   insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
2194 }
2195
2196 static unsigned
2197 Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2198 {
2199   unsigned tie_t = 0;
2200   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2201   return tie_t;
2202 }
2203
2204 static void
2205 Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2206 {
2207   uint32 tie_t;
2208   tie_t = (val << 30) >> 30;
2209   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2210 }
2211
2212 static unsigned
2213 Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2214 {
2215   unsigned tie_t = 0;
2216   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2217   return tie_t;
2218 }
2219
2220 static void
2221 Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2222 {
2223   uint32 tie_t;
2224   tie_t = (val << 29) >> 29;
2225   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2226 }
2227
2228 static unsigned
2229 Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2230 {
2231   unsigned tie_t = 0;
2232   tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
2233   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
2234   return tie_t;
2235 }
2236
2237 static void
2238 Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2239 {
2240   uint32 tie_t;
2241   tie_t = (val << 31) >> 31;
2242   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
2243   tie_t = (val << 24) >> 25;
2244   insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
2245 }
2246
2247 static unsigned
2248 Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2249 {
2250   unsigned tie_t = 0;
2251   tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
2252   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2253   return tie_t;
2254 }
2255
2256 static void
2257 Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2258 {
2259   uint32 tie_t;
2260   tie_t = (val << 29) >> 29;
2261   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2262   tie_t = (val << 27) >> 30;
2263   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
2264 }
2265
2266 static unsigned
2267 Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2268 {
2269   unsigned tie_t = 0;
2270   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2271   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2272   return tie_t;
2273 }
2274
2275 static void
2276 Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2277 {
2278   uint32 tie_t;
2279   tie_t = (val << 31) >> 31;
2280   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2281   tie_t = (val << 28) >> 29;
2282   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2283 }
2284
2285 static unsigned
2286 Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2287 {
2288   unsigned tie_t = 0;
2289   tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
2290   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2291   return tie_t;
2292 }
2293
2294 static void
2295 Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2296 {
2297   uint32 tie_t;
2298   tie_t = (val << 30) >> 30;
2299   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2300   tie_t = (val << 28) >> 30;
2301   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
2302 }
2303
2304 static unsigned
2305 Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2306 {
2307   unsigned tie_t = 0;
2308   tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2309   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2310   return tie_t;
2311 }
2312
2313 static void
2314 Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2315 {
2316   uint32 tie_t;
2317   tie_t = (val << 29) >> 29;
2318   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2319   tie_t = (val << 26) >> 29;
2320   insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2321 }
2322
2323 static unsigned
2324 Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2325 {
2326   unsigned tie_t = 0;
2327   tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
2328   return tie_t;
2329 }
2330
2331 static void
2332 Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2333 {
2334   uint32 tie_t;
2335   tie_t = (val << 30) >> 30;
2336   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
2337 }
2338
2339 static unsigned
2340 Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2341 {
2342   unsigned tie_t = 0;
2343   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2344   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2345   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2346   return tie_t;
2347 }
2348
2349 static void
2350 Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2351 {
2352   uint32 tie_t;
2353   tie_t = (val << 28) >> 28;
2354   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2355   tie_t = (val << 26) >> 30;
2356   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2357   tie_t = (val << 24) >> 30;
2358   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2359 }
2360
2361 static unsigned
2362 Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2363 {
2364   unsigned tie_t = 0;
2365   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2366   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2367   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2368   return tie_t;
2369 }
2370
2371 static void
2372 Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2373 {
2374   uint32 tie_t;
2375   tie_t = (val << 28) >> 28;
2376   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2377   tie_t = (val << 26) >> 30;
2378   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2379   tie_t = (val << 24) >> 30;
2380   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2381 }
2382
2383 static unsigned
2384 Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2385 {
2386   unsigned tie_t = 0;
2387   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2388   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2389   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2390   return tie_t;
2391 }
2392
2393 static void
2394 Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2395 {
2396   uint32 tie_t;
2397   tie_t = (val << 28) >> 28;
2398   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2399   tie_t = (val << 26) >> 30;
2400   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2401   tie_t = (val << 24) >> 30;
2402   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2403 }
2404
2405 static unsigned
2406 Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2407 {
2408   unsigned tie_t = 0;
2409   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2410   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2411   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2412   return tie_t;
2413 }
2414
2415 static void
2416 Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2417 {
2418   uint32 tie_t;
2419   tie_t = (val << 28) >> 28;
2420   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2421   tie_t = (val << 26) >> 30;
2422   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2423   tie_t = (val << 24) >> 30;
2424   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2425 }
2426
2427 static unsigned
2428 Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2429 {
2430   unsigned tie_t = 0;
2431   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2432   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2433   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2434   return tie_t;
2435 }
2436
2437 static void
2438 Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2439 {
2440   uint32 tie_t;
2441   tie_t = (val << 28) >> 28;
2442   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2443   tie_t = (val << 26) >> 30;
2444   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2445   tie_t = (val << 24) >> 30;
2446   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2447 }
2448
2449 static unsigned
2450 Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2451 {
2452   unsigned tie_t = 0;
2453   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2454   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2455   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2456   return tie_t;
2457 }
2458
2459 static void
2460 Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2461 {
2462   uint32 tie_t;
2463   tie_t = (val << 28) >> 28;
2464   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2465   tie_t = (val << 26) >> 30;
2466   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2467   tie_t = (val << 24) >> 30;
2468   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2469 }
2470
2471 static unsigned
2472 Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2473 {
2474   unsigned tie_t = 0;
2475   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2476   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2477   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2478   return tie_t;
2479 }
2480
2481 static void
2482 Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2483 {
2484   uint32 tie_t;
2485   tie_t = (val << 28) >> 28;
2486   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2487   tie_t = (val << 26) >> 30;
2488   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2489   tie_t = (val << 24) >> 30;
2490   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2491 }
2492
2493 static unsigned
2494 Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2495 {
2496   unsigned tie_t = 0;
2497   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2498   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2499   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2500   return tie_t;
2501 }
2502
2503 static void
2504 Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2505 {
2506   uint32 tie_t;
2507   tie_t = (val << 28) >> 28;
2508   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2509   tie_t = (val << 26) >> 30;
2510   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2511   tie_t = (val << 24) >> 30;
2512   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2513 }
2514
2515 static unsigned
2516 Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2517 {
2518   unsigned tie_t = 0;
2519   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2520   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2521   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2522   return tie_t;
2523 }
2524
2525 static void
2526 Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2527 {
2528   uint32 tie_t;
2529   tie_t = (val << 28) >> 28;
2530   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2531   tie_t = (val << 26) >> 30;
2532   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2533   tie_t = (val << 24) >> 30;
2534   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2535 }
2536
2537 static unsigned
2538 Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2539 {
2540   unsigned tie_t = 0;
2541   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2542   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2543   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2544   return tie_t;
2545 }
2546
2547 static void
2548 Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2549 {
2550   uint32 tie_t;
2551   tie_t = (val << 28) >> 28;
2552   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2553   tie_t = (val << 26) >> 30;
2554   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2555   tie_t = (val << 24) >> 30;
2556   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2557 }
2558
2559 static unsigned
2560 Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2561 {
2562   unsigned tie_t = 0;
2563   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2564   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2565   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2566   return tie_t;
2567 }
2568
2569 static void
2570 Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2571 {
2572   uint32 tie_t;
2573   tie_t = (val << 28) >> 28;
2574   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2575   tie_t = (val << 26) >> 30;
2576   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2577   tie_t = (val << 24) >> 30;
2578   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2579 }
2580
2581 static unsigned
2582 Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2583 {
2584   unsigned tie_t = 0;
2585   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2586   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2587   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2588   return tie_t;
2589 }
2590
2591 static void
2592 Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2593 {
2594   uint32 tie_t;
2595   tie_t = (val << 28) >> 28;
2596   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2597   tie_t = (val << 26) >> 30;
2598   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2599   tie_t = (val << 24) >> 30;
2600   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2601 }
2602
2603 static unsigned
2604 Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2605 {
2606   unsigned tie_t = 0;
2607   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2608   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2609   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2610   return tie_t;
2611 }
2612
2613 static void
2614 Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2615 {
2616   uint32 tie_t;
2617   tie_t = (val << 28) >> 28;
2618   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2619   tie_t = (val << 26) >> 30;
2620   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2621   tie_t = (val << 24) >> 30;
2622   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2623 }
2624
2625 static unsigned
2626 Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2627 {
2628   unsigned tie_t = 0;
2629   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2630   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2631   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2632   return tie_t;
2633 }
2634
2635 static void
2636 Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2637 {
2638   uint32 tie_t;
2639   tie_t = (val << 28) >> 28;
2640   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2641   tie_t = (val << 26) >> 30;
2642   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2643   tie_t = (val << 24) >> 30;
2644   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2645 }
2646
2647 static unsigned
2648 Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2649 {
2650   unsigned tie_t = 0;
2651   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2652   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2653   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2654   return tie_t;
2655 }
2656
2657 static void
2658 Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2659 {
2660   uint32 tie_t;
2661   tie_t = (val << 28) >> 28;
2662   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2663   tie_t = (val << 26) >> 30;
2664   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2665   tie_t = (val << 24) >> 30;
2666   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2667 }
2668
2669 static unsigned
2670 Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2671 {
2672   unsigned tie_t = 0;
2673   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2674   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2675   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2676   return tie_t;
2677 }
2678
2679 static void
2680 Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2681 {
2682   uint32 tie_t;
2683   tie_t = (val << 28) >> 28;
2684   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2685   tie_t = (val << 26) >> 30;
2686   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2687   tie_t = (val << 24) >> 30;
2688   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2689 }
2690
2691 static unsigned
2692 Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2693 {
2694   unsigned tie_t = 0;
2695   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2696   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2697   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2698   return tie_t;
2699 }
2700
2701 static void
2702 Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2703 {
2704   uint32 tie_t;
2705   tie_t = (val << 28) >> 28;
2706   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2707   tie_t = (val << 26) >> 30;
2708   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2709   tie_t = (val << 24) >> 30;
2710   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2711 }
2712
2713 static unsigned
2714 Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2715 {
2716   unsigned tie_t = 0;
2717   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2718   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2719   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2720   return tie_t;
2721 }
2722
2723 static void
2724 Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2725 {
2726   uint32 tie_t;
2727   tie_t = (val << 28) >> 28;
2728   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2729   tie_t = (val << 26) >> 30;
2730   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2731   tie_t = (val << 24) >> 30;
2732   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2733 }
2734
2735 static unsigned
2736 Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2737 {
2738   unsigned tie_t = 0;
2739   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2740   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2741   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2742   return tie_t;
2743 }
2744
2745 static void
2746 Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2747 {
2748   uint32 tie_t;
2749   tie_t = (val << 28) >> 28;
2750   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2751   tie_t = (val << 26) >> 30;
2752   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2753   tie_t = (val << 24) >> 30;
2754   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2755 }
2756
2757 static unsigned
2758 Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2759 {
2760   unsigned tie_t = 0;
2761   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2762   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2763   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2764   return tie_t;
2765 }
2766
2767 static void
2768 Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2769 {
2770   uint32 tie_t;
2771   tie_t = (val << 28) >> 28;
2772   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2773   tie_t = (val << 26) >> 30;
2774   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2775   tie_t = (val << 24) >> 30;
2776   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2777 }
2778
2779 static unsigned
2780 Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2781 {
2782   unsigned tie_t = 0;
2783   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2784   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2785   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2786   return tie_t;
2787 }
2788
2789 static void
2790 Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2791 {
2792   uint32 tie_t;
2793   tie_t = (val << 28) >> 28;
2794   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2795   tie_t = (val << 26) >> 30;
2796   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2797   tie_t = (val << 24) >> 30;
2798   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2799 }
2800
2801 static unsigned
2802 Field_ftsf211ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2803 {
2804   unsigned tie_t = 0;
2805   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2806   return tie_t;
2807 }
2808
2809 static void
2810 Field_ftsf211ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2811 {
2812   uint32 tie_t;
2813   tie_t = (val << 31) >> 31;
2814   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2815 }
2816
2817 static unsigned
2818 Field_ftsf332ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2819 {
2820   unsigned tie_t = 0;
2821   tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
2822   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2823   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2824   return tie_t;
2825 }
2826
2827 static void
2828 Field_ftsf332ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2829 {
2830   uint32 tie_t;
2831   tie_t = (val << 28) >> 28;
2832   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2833   tie_t = (val << 26) >> 30;
2834   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2835   tie_t = (val << 25) >> 31;
2836   insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
2837 }
2838
2839 static unsigned
2840 Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2841 {
2842   unsigned tie_t = 0;
2843   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2844   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2845   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2846   return tie_t;
2847 }
2848
2849 static void
2850 Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2851 {
2852   uint32 tie_t;
2853   tie_t = (val << 28) >> 28;
2854   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2855   tie_t = (val << 26) >> 30;
2856   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2857   tie_t = (val << 24) >> 30;
2858   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2859 }
2860
2861 static unsigned
2862 Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2863 {
2864   unsigned tie_t = 0;
2865   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2866   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2867   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2868   return tie_t;
2869 }
2870
2871 static void
2872 Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2873 {
2874   uint32 tie_t;
2875   tie_t = (val << 28) >> 28;
2876   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2877   tie_t = (val << 26) >> 30;
2878   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2879   tie_t = (val << 24) >> 30;
2880   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2881 }
2882
2883 static unsigned
2884 Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2885 {
2886   unsigned tie_t = 0;
2887   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2888   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2889   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2890   return tie_t;
2891 }
2892
2893 static void
2894 Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2895 {
2896   uint32 tie_t;
2897   tie_t = (val << 28) >> 28;
2898   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2899   tie_t = (val << 26) >> 30;
2900   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2901   tie_t = (val << 24) >> 30;
2902   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2903 }
2904
2905 static unsigned
2906 Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2907 {
2908   unsigned tie_t = 0;
2909   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2910   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2911   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2912   return tie_t;
2913 }
2914
2915 static void
2916 Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2917 {
2918   uint32 tie_t;
2919   tie_t = (val << 28) >> 28;
2920   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2921   tie_t = (val << 26) >> 30;
2922   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2923   tie_t = (val << 24) >> 30;
2924   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2925 }
2926
2927 static unsigned
2928 Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2929 {
2930   unsigned tie_t = 0;
2931   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2932   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2933   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2934   return tie_t;
2935 }
2936
2937 static void
2938 Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2939 {
2940   uint32 tie_t;
2941   tie_t = (val << 28) >> 28;
2942   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2943   tie_t = (val << 26) >> 30;
2944   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2945   tie_t = (val << 24) >> 30;
2946   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2947 }
2948
2949 static unsigned
2950 Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2951 {
2952   unsigned tie_t = 0;
2953   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2954   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2955   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2956   return tie_t;
2957 }
2958
2959 static void
2960 Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2961 {
2962   uint32 tie_t;
2963   tie_t = (val << 28) >> 28;
2964   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2965   tie_t = (val << 26) >> 30;
2966   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2967   tie_t = (val << 24) >> 30;
2968   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2969 }
2970
2971 static unsigned
2972 Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2973 {
2974   unsigned tie_t = 0;
2975   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2976   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2977   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2978   return tie_t;
2979 }
2980
2981 static void
2982 Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2983 {
2984   uint32 tie_t;
2985   tie_t = (val << 28) >> 28;
2986   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2987   tie_t = (val << 26) >> 30;
2988   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2989   tie_t = (val << 24) >> 30;
2990   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2991 }
2992
2993 static unsigned
2994 Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2995 {
2996   unsigned tie_t = 0;
2997   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2998   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2999   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3000   return tie_t;
3001 }
3002
3003 static void
3004 Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3005 {
3006   uint32 tie_t;
3007   tie_t = (val << 28) >> 28;
3008   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3009   tie_t = (val << 26) >> 30;
3010   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3011   tie_t = (val << 24) >> 30;
3012   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3013 }
3014
3015 static unsigned
3016 Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3017 {
3018   unsigned tie_t = 0;
3019   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3020   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3021   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3022   return tie_t;
3023 }
3024
3025 static void
3026 Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3027 {
3028   uint32 tie_t;
3029   tie_t = (val << 28) >> 28;
3030   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3031   tie_t = (val << 26) >> 30;
3032   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3033   tie_t = (val << 24) >> 30;
3034   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3035 }
3036
3037 static unsigned
3038 Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3039 {
3040   unsigned tie_t = 0;
3041   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3042   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3043   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3044   return tie_t;
3045 }
3046
3047 static void
3048 Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3049 {
3050   uint32 tie_t;
3051   tie_t = (val << 28) >> 28;
3052   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3053   tie_t = (val << 26) >> 30;
3054   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3055   tie_t = (val << 24) >> 30;
3056   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3057 }
3058
3059 static unsigned
3060 Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3061 {
3062   unsigned tie_t = 0;
3063   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3064   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3065   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3066   return tie_t;
3067 }
3068
3069 static void
3070 Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3071 {
3072   uint32 tie_t;
3073   tie_t = (val << 28) >> 28;
3074   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3075   tie_t = (val << 26) >> 30;
3076   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3077   tie_t = (val << 24) >> 30;
3078   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3079 }
3080
3081 static unsigned
3082 Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3083 {
3084   unsigned tie_t = 0;
3085   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3086   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3087   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3088   return tie_t;
3089 }
3090
3091 static void
3092 Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3093 {
3094   uint32 tie_t;
3095   tie_t = (val << 28) >> 28;
3096   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3097   tie_t = (val << 26) >> 30;
3098   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3099   tie_t = (val << 24) >> 30;
3100   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3101 }
3102
3103 static unsigned
3104 Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3105 {
3106   unsigned tie_t = 0;
3107   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3108   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3109   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3110   return tie_t;
3111 }
3112
3113 static void
3114 Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3115 {
3116   uint32 tie_t;
3117   tie_t = (val << 28) >> 28;
3118   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3119   tie_t = (val << 26) >> 30;
3120   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3121   tie_t = (val << 24) >> 30;
3122   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3123 }
3124
3125 static unsigned
3126 Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3127 {
3128   unsigned tie_t = 0;
3129   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3130   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3131   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3132   return tie_t;
3133 }
3134
3135 static void
3136 Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3137 {
3138   uint32 tie_t;
3139   tie_t = (val << 28) >> 28;
3140   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3141   tie_t = (val << 26) >> 30;
3142   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3143   tie_t = (val << 24) >> 30;
3144   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3145 }
3146
3147 static unsigned
3148 Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3149 {
3150   unsigned tie_t = 0;
3151   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3152   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3153   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3154   return tie_t;
3155 }
3156
3157 static void
3158 Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3159 {
3160   uint32 tie_t;
3161   tie_t = (val << 28) >> 28;
3162   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3163   tie_t = (val << 26) >> 30;
3164   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3165   tie_t = (val << 24) >> 30;
3166   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3167 }
3168
3169 static unsigned
3170 Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3171 {
3172   unsigned tie_t = 0;
3173   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3174   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3175   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3176   return tie_t;
3177 }
3178
3179 static void
3180 Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3181 {
3182   uint32 tie_t;
3183   tie_t = (val << 28) >> 28;
3184   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3185   tie_t = (val << 26) >> 30;
3186   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3187   tie_t = (val << 24) >> 30;
3188   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3189 }
3190
3191 static unsigned
3192 Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3193 {
3194   unsigned tie_t = 0;
3195   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3196   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3197   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3198   return tie_t;
3199 }
3200
3201 static void
3202 Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3203 {
3204   uint32 tie_t;
3205   tie_t = (val << 28) >> 28;
3206   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3207   tie_t = (val << 26) >> 30;
3208   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3209   tie_t = (val << 24) >> 30;
3210   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3211 }
3212
3213 static unsigned
3214 Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3215 {
3216   unsigned tie_t = 0;
3217   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3218   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3219   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3220   return tie_t;
3221 }
3222
3223 static void
3224 Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3225 {
3226   uint32 tie_t;
3227   tie_t = (val << 28) >> 28;
3228   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3229   tie_t = (val << 26) >> 30;
3230   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3231   tie_t = (val << 24) >> 30;
3232   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3233 }
3234
3235 static unsigned
3236 Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3237 {
3238   unsigned tie_t = 0;
3239   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3240   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3241   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3242   return tie_t;
3243 }
3244
3245 static void
3246 Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3247 {
3248   uint32 tie_t;
3249   tie_t = (val << 28) >> 28;
3250   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3251   tie_t = (val << 26) >> 30;
3252   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3253   tie_t = (val << 24) >> 30;
3254   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3255 }
3256
3257 static unsigned
3258 Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3259 {
3260   unsigned tie_t = 0;
3261   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3262   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3263   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3264   return tie_t;
3265 }
3266
3267 static void
3268 Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3269 {
3270   uint32 tie_t;
3271   tie_t = (val << 28) >> 28;
3272   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3273   tie_t = (val << 26) >> 30;
3274   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3275   tie_t = (val << 24) >> 30;
3276   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3277 }
3278
3279 static unsigned
3280 Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3281 {
3282   unsigned tie_t = 0;
3283   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3284   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3285   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3286   return tie_t;
3287 }
3288
3289 static void
3290 Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3291 {
3292   uint32 tie_t;
3293   tie_t = (val << 28) >> 28;
3294   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3295   tie_t = (val << 26) >> 30;
3296   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3297   tie_t = (val << 24) >> 30;
3298   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3299 }
3300
3301 static unsigned
3302 Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3303 {
3304   unsigned tie_t = 0;
3305   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3306   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3307   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3308   return tie_t;
3309 }
3310
3311 static void
3312 Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3313 {
3314   uint32 tie_t;
3315   tie_t = (val << 28) >> 28;
3316   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3317   tie_t = (val << 26) >> 30;
3318   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3319   tie_t = (val << 24) >> 30;
3320   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3321 }
3322
3323 static unsigned
3324 Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3325 {
3326   unsigned tie_t = 0;
3327   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3328   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3329   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3330   return tie_t;
3331 }
3332
3333 static void
3334 Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3335 {
3336   uint32 tie_t;
3337   tie_t = (val << 28) >> 28;
3338   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3339   tie_t = (val << 26) >> 30;
3340   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3341   tie_t = (val << 24) >> 30;
3342   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3343 }
3344
3345 static unsigned
3346 Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3347 {
3348   unsigned tie_t = 0;
3349   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3350   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3351   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3352   return tie_t;
3353 }
3354
3355 static void
3356 Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3357 {
3358   uint32 tie_t;
3359   tie_t = (val << 28) >> 28;
3360   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3361   tie_t = (val << 26) >> 30;
3362   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3363   tie_t = (val << 24) >> 30;
3364   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3365 }
3366
3367 static unsigned
3368 Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3369 {
3370   unsigned tie_t = 0;
3371   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3372   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3373   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3374   return tie_t;
3375 }
3376
3377 static void
3378 Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3379 {
3380   uint32 tie_t;
3381   tie_t = (val << 28) >> 28;
3382   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3383   tie_t = (val << 26) >> 30;
3384   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3385   tie_t = (val << 24) >> 30;
3386   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3387 }
3388
3389 static unsigned
3390 Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3391 {
3392   unsigned tie_t = 0;
3393   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3394   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3395   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3396   return tie_t;
3397 }
3398
3399 static void
3400 Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3401 {
3402   uint32 tie_t;
3403   tie_t = (val << 28) >> 28;
3404   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3405   tie_t = (val << 26) >> 30;
3406   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3407   tie_t = (val << 24) >> 30;
3408   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3409 }
3410
3411 static unsigned
3412 Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3413 {
3414   unsigned tie_t = 0;
3415   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3416   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3417   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3418   return tie_t;
3419 }
3420
3421 static void
3422 Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3423 {
3424   uint32 tie_t;
3425   tie_t = (val << 28) >> 28;
3426   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3427   tie_t = (val << 26) >> 30;
3428   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3429   tie_t = (val << 24) >> 30;
3430   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3431 }
3432
3433 static unsigned
3434 Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3435 {
3436   unsigned tie_t = 0;
3437   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3438   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3439   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3440   return tie_t;
3441 }
3442
3443 static void
3444 Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3445 {
3446   uint32 tie_t;
3447   tie_t = (val << 28) >> 28;
3448   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3449   tie_t = (val << 26) >> 30;
3450   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3451   tie_t = (val << 24) >> 30;
3452   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3453 }
3454
3455 static unsigned
3456 Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3457 {
3458   unsigned tie_t = 0;
3459   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3460   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3461   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3462   return tie_t;
3463 }
3464
3465 static void
3466 Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3467 {
3468   uint32 tie_t;
3469   tie_t = (val << 28) >> 28;
3470   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3471   tie_t = (val << 26) >> 30;
3472   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3473   tie_t = (val << 24) >> 30;
3474   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3475 }
3476
3477 static unsigned
3478 Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3479 {
3480   unsigned tie_t = 0;
3481   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3482   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3483   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3484   return tie_t;
3485 }
3486
3487 static void
3488 Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3489 {
3490   uint32 tie_t;
3491   tie_t = (val << 28) >> 28;
3492   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3493   tie_t = (val << 26) >> 30;
3494   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3495   tie_t = (val << 24) >> 30;
3496   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3497 }
3498
3499 static unsigned
3500 Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3501 {
3502   unsigned tie_t = 0;
3503   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3504   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3505   return tie_t;
3506 }
3507
3508 static void
3509 Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3510 {
3511   uint32 tie_t;
3512   tie_t = (val << 28) >> 28;
3513   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3514   tie_t = (val << 23) >> 27;
3515   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3516 }
3517
3518 static unsigned
3519 Field_ftsf44ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3520 {
3521   unsigned tie_t = 0;
3522   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3523   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3524   return tie_t;
3525 }
3526
3527 static void
3528 Field_ftsf44ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3529 {
3530   uint32 tie_t;
3531   tie_t = (val << 28) >> 28;
3532   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3533   tie_t = (val << 23) >> 27;
3534   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3535 }
3536
3537 static unsigned
3538 Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3539 {
3540   unsigned tie_t = 0;
3541   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3542   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3543   return tie_t;
3544 }
3545
3546 static void
3547 Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3548 {
3549   uint32 tie_t;
3550   tie_t = (val << 28) >> 28;
3551   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3552   tie_t = (val << 23) >> 27;
3553   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3554 }
3555
3556 static unsigned
3557 Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3558 {
3559   unsigned tie_t = 0;
3560   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3561   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3562   return tie_t;
3563 }
3564
3565 static void
3566 Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3567 {
3568   uint32 tie_t;
3569   tie_t = (val << 28) >> 28;
3570   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3571   tie_t = (val << 23) >> 27;
3572   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3573 }
3574
3575 static unsigned
3576 Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3577 {
3578   unsigned tie_t = 0;
3579   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3580   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3581   return tie_t;
3582 }
3583
3584 static void
3585 Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3586 {
3587   uint32 tie_t;
3588   tie_t = (val << 28) >> 28;
3589   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3590   tie_t = (val << 23) >> 27;
3591   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3592 }
3593
3594 static unsigned
3595 Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3596 {
3597   unsigned tie_t = 0;
3598   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3599   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3600   return tie_t;
3601 }
3602
3603 static void
3604 Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3605 {
3606   uint32 tie_t;
3607   tie_t = (val << 28) >> 28;
3608   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3609   tie_t = (val << 23) >> 27;
3610   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3611 }
3612
3613 static unsigned
3614 Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3615 {
3616   unsigned tie_t = 0;
3617   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3618   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3619   return tie_t;
3620 }
3621
3622 static void
3623 Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3624 {
3625   uint32 tie_t;
3626   tie_t = (val << 28) >> 28;
3627   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3628   tie_t = (val << 23) >> 27;
3629   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3630 }
3631
3632 static unsigned
3633 Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3634 {
3635   unsigned tie_t = 0;
3636   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3637   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3638   return tie_t;
3639 }
3640
3641 static void
3642 Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3643 {
3644   uint32 tie_t;
3645   tie_t = (val << 28) >> 28;
3646   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3647   tie_t = (val << 23) >> 27;
3648   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3649 }
3650
3651 static unsigned
3652 Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3653 {
3654   unsigned tie_t = 0;
3655   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3656   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3657   return tie_t;
3658 }
3659
3660 static void
3661 Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3662 {
3663   uint32 tie_t;
3664   tie_t = (val << 28) >> 28;
3665   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3666   tie_t = (val << 23) >> 27;
3667   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3668 }
3669
3670 static unsigned
3671 Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3672 {
3673   unsigned tie_t = 0;
3674   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3675   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3676   return tie_t;
3677 }
3678
3679 static void
3680 Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3681 {
3682   uint32 tie_t;
3683   tie_t = (val << 28) >> 28;
3684   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3685   tie_t = (val << 23) >> 27;
3686   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3687 }
3688
3689 static unsigned
3690 Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3691 {
3692   unsigned tie_t = 0;
3693   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3694   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3695   return tie_t;
3696 }
3697
3698 static void
3699 Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3700 {
3701   uint32 tie_t;
3702   tie_t = (val << 28) >> 28;
3703   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3704   tie_t = (val << 23) >> 27;
3705   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3706 }
3707
3708 static unsigned
3709 Field_ftsf39ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3710 {
3711   unsigned tie_t = 0;
3712   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3713   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3714   return tie_t;
3715 }
3716
3717 static void
3718 Field_ftsf39ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3719 {
3720   uint32 tie_t;
3721   tie_t = (val << 28) >> 28;
3722   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3723   tie_t = (val << 23) >> 27;
3724   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3725 }
3726
3727 static unsigned
3728 Field_ftsf46ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3729 {
3730   unsigned tie_t = 0;
3731   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3732   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3733   return tie_t;
3734 }
3735
3736 static void
3737 Field_ftsf46ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3738 {
3739   uint32 tie_t;
3740   tie_t = (val << 28) >> 28;
3741   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3742   tie_t = (val << 23) >> 27;
3743   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3744 }
3745
3746 static unsigned
3747 Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3748 {
3749   unsigned tie_t = 0;
3750   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3751   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3752   return tie_t;
3753 }
3754
3755 static void
3756 Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3757 {
3758   uint32 tie_t;
3759   tie_t = (val << 28) >> 28;
3760   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3761   tie_t = (val << 23) >> 27;
3762   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3763 }
3764
3765 static unsigned
3766 Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3767 {
3768   unsigned tie_t = 0;
3769   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3770   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3771   return tie_t;
3772 }
3773
3774 static void
3775 Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3776 {
3777   uint32 tie_t;
3778   tie_t = (val << 28) >> 28;
3779   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3780   tie_t = (val << 23) >> 27;
3781   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3782 }
3783
3784 static unsigned
3785 Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3786 {
3787   unsigned tie_t = 0;
3788   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3789   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3790   return tie_t;
3791 }
3792
3793 static void
3794 Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3795 {
3796   uint32 tie_t;
3797   tie_t = (val << 28) >> 28;
3798   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3799   tie_t = (val << 23) >> 27;
3800   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3801 }
3802
3803 static unsigned
3804 Field_ftsf55ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3805 {
3806   unsigned tie_t = 0;
3807   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3808   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3809   return tie_t;
3810 }
3811
3812 static void
3813 Field_ftsf55ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3814 {
3815   uint32 tie_t;
3816   tie_t = (val << 28) >> 28;
3817   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3818   tie_t = (val << 23) >> 27;
3819   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3820 }
3821
3822 static unsigned
3823 Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3824 {
3825   unsigned tie_t = 0;
3826   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3827   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3828   return tie_t;
3829 }
3830
3831 static void
3832 Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3833 {
3834   uint32 tie_t;
3835   tie_t = (val << 28) >> 28;
3836   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3837   tie_t = (val << 23) >> 27;
3838   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3839 }
3840
3841 static unsigned
3842 Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3843 {
3844   unsigned tie_t = 0;
3845   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3846   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3847   return tie_t;
3848 }
3849
3850 static void
3851 Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3852 {
3853   uint32 tie_t;
3854   tie_t = (val << 28) >> 28;
3855   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3856   tie_t = (val << 23) >> 27;
3857   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3858 }
3859
3860 static unsigned
3861 Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3862 {
3863   unsigned tie_t = 0;
3864   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3865   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3866   return tie_t;
3867 }
3868
3869 static void
3870 Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3871 {
3872   uint32 tie_t;
3873   tie_t = (val << 28) >> 28;
3874   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3875   tie_t = (val << 23) >> 27;
3876   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3877 }
3878
3879 static unsigned
3880 Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3881 {
3882   unsigned tie_t = 0;
3883   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3884   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
3885   return tie_t;
3886 }
3887
3888 static void
3889 Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3890 {
3891   uint32 tie_t;
3892   tie_t = (val << 31) >> 31;
3893   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
3894   tie_t = (val << 26) >> 27;
3895   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3896 }
3897
3898 static unsigned
3899 Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3900 {
3901   unsigned tie_t = 0;
3902   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3903   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
3904   return tie_t;
3905 }
3906
3907 static void
3908 Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3909 {
3910   uint32 tie_t;
3911   tie_t = (val << 31) >> 31;
3912   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
3913   tie_t = (val << 26) >> 27;
3914   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3915 }
3916
3917 static unsigned
3918 Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3919 {
3920   unsigned tie_t = 0;
3921   tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3922   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3923   return tie_t;
3924 }
3925
3926 static void
3927 Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3928 {
3929   uint32 tie_t;
3930   tie_t = (val << 28) >> 28;
3931   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3932   tie_t = (val << 23) >> 27;
3933   insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3934 }
3935
3936 static unsigned
3937 Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3938 {
3939   unsigned tie_t = 0;
3940   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
3941   return tie_t;
3942 }
3943
3944 static void
3945 Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3946 {
3947   uint32 tie_t;
3948   tie_t = (val << 28) >> 28;
3949   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
3950 }
3951
3952 static unsigned
3953 Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3954 {
3955   unsigned tie_t = 0;
3956   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3957   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3958   return tie_t;
3959 }
3960
3961 static void
3962 Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3963 {
3964   uint32 tie_t;
3965   tie_t = (val << 28) >> 28;
3966   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3967   tie_t = (val << 27) >> 31;
3968   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3969 }
3970
3971 static unsigned
3972 Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3973 {
3974   unsigned tie_t = 0;
3975   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3976   return tie_t;
3977 }
3978
3979 static void
3980 Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3981 {
3982   uint32 tie_t;
3983   tie_t = (val << 28) >> 28;
3984   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3985 }
3986
3987 static unsigned
3988 Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3989 {
3990   unsigned tie_t = 0;
3991   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3992   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3993   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3994   return tie_t;
3995 }
3996
3997 static void
3998 Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3999 {
4000   uint32 tie_t;
4001   tie_t = (val << 28) >> 28;
4002   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4003   tie_t = (val << 26) >> 30;
4004   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4005   tie_t = (val << 24) >> 30;
4006   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4007 }
4008
4009 static unsigned
4010 Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4011 {
4012   unsigned tie_t = 0;
4013   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4014   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4015   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
4016   return tie_t;
4017 }
4018
4019 static void
4020 Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4021 {
4022   uint32 tie_t;
4023   tie_t = (val << 31) >> 31;
4024   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
4025   tie_t = (val << 29) >> 30;
4026   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4027   tie_t = (val << 27) >> 30;
4028   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4029 }
4030
4031 static unsigned
4032 Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4033 {
4034   unsigned tie_t = 0;
4035   tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
4036   return tie_t;
4037 }
4038
4039 static void
4040 Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4041 {
4042   uint32 tie_t;
4043   tie_t = (val << 29) >> 29;
4044   insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
4045 }
4046
4047 static unsigned
4048 Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4049 {
4050   unsigned tie_t = 0;
4051   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4052   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4053   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4054   return tie_t;
4055 }
4056
4057 static void
4058 Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4059 {
4060   uint32 tie_t;
4061   tie_t = (val << 28) >> 28;
4062   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4063   tie_t = (val << 26) >> 30;
4064   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4065   tie_t = (val << 24) >> 30;
4066   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4067 }
4068
4069 static unsigned
4070 Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4071 {
4072   unsigned tie_t = 0;
4073   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4074   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
4075   return tie_t;
4076 }
4077
4078 static void
4079 Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4080 {
4081   uint32 tie_t;
4082   tie_t = (val << 31) >> 31;
4083   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
4084   tie_t = (val << 29) >> 30;
4085   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4086 }
4087
4088 static unsigned
4089 Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4090 {
4091   unsigned tie_t = 0;
4092   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4093   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4094   return tie_t;
4095 }
4096
4097 static void
4098 Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4099 {
4100   uint32 tie_t;
4101   tie_t = (val << 28) >> 28;
4102   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4103   tie_t = (val << 27) >> 31;
4104   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4105 }
4106
4107 static unsigned
4108 Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4109 {
4110   unsigned tie_t = 0;
4111   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4112   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4113   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4114   return tie_t;
4115 }
4116
4117 static void
4118 Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4119 {
4120   uint32 tie_t;
4121   tie_t = (val << 28) >> 28;
4122   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4123   tie_t = (val << 26) >> 30;
4124   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4125   tie_t = (val << 24) >> 30;
4126   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4127 }
4128
4129 static unsigned
4130 Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4131 {
4132   unsigned tie_t = 0;
4133   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4134   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4135   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4136   return tie_t;
4137 }
4138
4139 static void
4140 Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4141 {
4142   uint32 tie_t;
4143   tie_t = (val << 28) >> 28;
4144   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4145   tie_t = (val << 26) >> 30;
4146   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4147   tie_t = (val << 24) >> 30;
4148   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4149 }
4150
4151 static unsigned
4152 Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4153 {
4154   unsigned tie_t = 0;
4155   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4156   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4157   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4158   return tie_t;
4159 }
4160
4161 static void
4162 Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4163 {
4164   uint32 tie_t;
4165   tie_t = (val << 28) >> 28;
4166   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4167   tie_t = (val << 26) >> 30;
4168   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4169   tie_t = (val << 24) >> 30;
4170   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4171 }
4172
4173 static unsigned
4174 Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4175 {
4176   unsigned tie_t = 0;
4177   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4178   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4179   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4180   return tie_t;
4181 }
4182
4183 static void
4184 Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4185 {
4186   uint32 tie_t;
4187   tie_t = (val << 28) >> 28;
4188   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4189   tie_t = (val << 26) >> 30;
4190   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4191   tie_t = (val << 24) >> 30;
4192   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4193 }
4194
4195 static unsigned
4196 Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4197 {
4198   unsigned tie_t = 0;
4199   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4200   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4201   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4202   return tie_t;
4203 }
4204
4205 static void
4206 Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4207 {
4208   uint32 tie_t;
4209   tie_t = (val << 28) >> 28;
4210   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4211   tie_t = (val << 26) >> 30;
4212   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4213   tie_t = (val << 24) >> 30;
4214   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4215 }
4216
4217 static unsigned
4218 Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4219 {
4220   unsigned tie_t = 0;
4221   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4222   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4223   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4224   return tie_t;
4225 }
4226
4227 static void
4228 Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4229 {
4230   uint32 tie_t;
4231   tie_t = (val << 28) >> 28;
4232   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4233   tie_t = (val << 26) >> 30;
4234   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4235   tie_t = (val << 24) >> 30;
4236   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4237 }
4238
4239 static unsigned
4240 Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4241 {
4242   unsigned tie_t = 0;
4243   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4244   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4245   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4246   return tie_t;
4247 }
4248
4249 static void
4250 Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4251 {
4252   uint32 tie_t;
4253   tie_t = (val << 28) >> 28;
4254   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4255   tie_t = (val << 26) >> 30;
4256   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4257   tie_t = (val << 24) >> 30;
4258   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4259 }
4260
4261 static unsigned
4262 Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4263 {
4264   unsigned tie_t = 0;
4265   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4266   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4267   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4268   return tie_t;
4269 }
4270
4271 static void
4272 Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4273 {
4274   uint32 tie_t;
4275   tie_t = (val << 28) >> 28;
4276   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4277   tie_t = (val << 26) >> 30;
4278   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4279   tie_t = (val << 24) >> 30;
4280   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4281 }
4282
4283 static unsigned
4284 Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4285 {
4286   unsigned tie_t = 0;
4287   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4288   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4289   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4290   return tie_t;
4291 }
4292
4293 static void
4294 Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4295 {
4296   uint32 tie_t;
4297   tie_t = (val << 28) >> 28;
4298   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4299   tie_t = (val << 26) >> 30;
4300   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4301   tie_t = (val << 24) >> 30;
4302   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4303 }
4304
4305 static unsigned
4306 Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4307 {
4308   unsigned tie_t = 0;
4309   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4310   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4311   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4312   return tie_t;
4313 }
4314
4315 static void
4316 Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4317 {
4318   uint32 tie_t;
4319   tie_t = (val << 28) >> 28;
4320   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4321   tie_t = (val << 26) >> 30;
4322   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4323   tie_t = (val << 24) >> 30;
4324   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4325 }
4326
4327 static unsigned
4328 Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4329 {
4330   unsigned tie_t = 0;
4331   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4332   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4333   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4334   return tie_t;
4335 }
4336
4337 static void
4338 Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4339 {
4340   uint32 tie_t;
4341   tie_t = (val << 28) >> 28;
4342   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4343   tie_t = (val << 26) >> 30;
4344   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4345   tie_t = (val << 24) >> 30;
4346   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4347 }
4348
4349 static unsigned
4350 Field_ftsf209ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4351 {
4352   unsigned tie_t = 0;
4353   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4354   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4355   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
4356   return tie_t;
4357 }
4358
4359 static void
4360 Field_ftsf209ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4361 {
4362   uint32 tie_t;
4363   tie_t = (val << 31) >> 31;
4364   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
4365   tie_t = (val << 29) >> 30;
4366   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4367   tie_t = (val << 27) >> 30;
4368   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4369 }
4370
4371 static unsigned
4372 Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4373 {
4374   unsigned tie_t = 0;
4375   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4376   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4377   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4378   return tie_t;
4379 }
4380
4381 static void
4382 Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4383 {
4384   uint32 tie_t;
4385   tie_t = (val << 28) >> 28;
4386   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4387   tie_t = (val << 26) >> 30;
4388   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4389   tie_t = (val << 24) >> 30;
4390   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4391 }
4392
4393 static unsigned
4394 Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4395 {
4396   unsigned tie_t = 0;
4397   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4398   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4399   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4400   return tie_t;
4401 }
4402
4403 static void
4404 Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4405 {
4406   uint32 tie_t;
4407   tie_t = (val << 28) >> 28;
4408   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4409   tie_t = (val << 26) >> 30;
4410   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4411   tie_t = (val << 24) >> 30;
4412   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4413 }
4414
4415 static unsigned
4416 Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4417 {
4418   unsigned tie_t = 0;
4419   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4420   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4421   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4422   return tie_t;
4423 }
4424
4425 static void
4426 Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4427 {
4428   uint32 tie_t;
4429   tie_t = (val << 28) >> 28;
4430   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4431   tie_t = (val << 26) >> 30;
4432   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4433   tie_t = (val << 24) >> 30;
4434   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4435 }
4436
4437 static unsigned
4438 Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4439 {
4440   unsigned tie_t = 0;
4441   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4442   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4443   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4444   return tie_t;
4445 }
4446
4447 static void
4448 Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4449 {
4450   uint32 tie_t;
4451   tie_t = (val << 28) >> 28;
4452   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4453   tie_t = (val << 26) >> 30;
4454   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4455   tie_t = (val << 24) >> 30;
4456   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4457 }
4458
4459 static unsigned
4460 Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4461 {
4462   unsigned tie_t = 0;
4463   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4464   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4465   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4466   return tie_t;
4467 }
4468
4469 static void
4470 Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4471 {
4472   uint32 tie_t;
4473   tie_t = (val << 28) >> 28;
4474   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4475   tie_t = (val << 26) >> 30;
4476   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4477   tie_t = (val << 24) >> 30;
4478   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4479 }
4480
4481 static unsigned
4482 Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4483 {
4484   unsigned tie_t = 0;
4485   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4486   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4487   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4488   return tie_t;
4489 }
4490
4491 static void
4492 Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4493 {
4494   uint32 tie_t;
4495   tie_t = (val << 28) >> 28;
4496   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4497   tie_t = (val << 26) >> 30;
4498   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4499   tie_t = (val << 24) >> 30;
4500   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4501 }
4502
4503 static unsigned
4504 Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4505 {
4506   unsigned tie_t = 0;
4507   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4508   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4509   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4510   return tie_t;
4511 }
4512
4513 static void
4514 Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4515 {
4516   uint32 tie_t;
4517   tie_t = (val << 28) >> 28;
4518   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4519   tie_t = (val << 26) >> 30;
4520   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4521   tie_t = (val << 24) >> 30;
4522   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4523 }
4524
4525 static unsigned
4526 Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4527 {
4528   unsigned tie_t = 0;
4529   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4530   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4531   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4532   return tie_t;
4533 }
4534
4535 static void
4536 Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4537 {
4538   uint32 tie_t;
4539   tie_t = (val << 28) >> 28;
4540   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4541   tie_t = (val << 26) >> 30;
4542   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4543   tie_t = (val << 24) >> 30;
4544   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4545 }
4546
4547 static unsigned
4548 Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4549 {
4550   unsigned tie_t = 0;
4551   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4552   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4553   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4554   return tie_t;
4555 }
4556
4557 static void
4558 Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4559 {
4560   uint32 tie_t;
4561   tie_t = (val << 28) >> 28;
4562   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4563   tie_t = (val << 26) >> 30;
4564   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4565   tie_t = (val << 24) >> 30;
4566   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4567 }
4568
4569 static unsigned
4570 Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4571 {
4572   unsigned tie_t = 0;
4573   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4574   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4575   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4576   return tie_t;
4577 }
4578
4579 static void
4580 Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4581 {
4582   uint32 tie_t;
4583   tie_t = (val << 28) >> 28;
4584   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4585   tie_t = (val << 26) >> 30;
4586   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4587   tie_t = (val << 24) >> 30;
4588   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4589 }
4590
4591 static unsigned
4592 Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4593 {
4594   unsigned tie_t = 0;
4595   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4596   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4597   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4598   return tie_t;
4599 }
4600
4601 static void
4602 Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4603 {
4604   uint32 tie_t;
4605   tie_t = (val << 28) >> 28;
4606   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4607   tie_t = (val << 26) >> 30;
4608   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4609   tie_t = (val << 24) >> 30;
4610   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4611 }
4612
4613 static unsigned
4614 Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4615 {
4616   unsigned tie_t = 0;
4617   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4618   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4619   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4620   return tie_t;
4621 }
4622
4623 static void
4624 Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4625 {
4626   uint32 tie_t;
4627   tie_t = (val << 28) >> 28;
4628   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4629   tie_t = (val << 26) >> 30;
4630   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4631   tie_t = (val << 24) >> 30;
4632   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4633 }
4634
4635 static unsigned
4636 Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4637 {
4638   unsigned tie_t = 0;
4639   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4640   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4641   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4642   return tie_t;
4643 }
4644
4645 static void
4646 Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4647 {
4648   uint32 tie_t;
4649   tie_t = (val << 28) >> 28;
4650   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4651   tie_t = (val << 26) >> 30;
4652   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4653   tie_t = (val << 24) >> 30;
4654   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4655 }
4656
4657 static unsigned
4658 Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4659 {
4660   unsigned tie_t = 0;
4661   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4662   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4663   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4664   return tie_t;
4665 }
4666
4667 static void
4668 Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4669 {
4670   uint32 tie_t;
4671   tie_t = (val << 28) >> 28;
4672   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4673   tie_t = (val << 26) >> 30;
4674   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4675   tie_t = (val << 24) >> 30;
4676   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4677 }
4678
4679 static unsigned
4680 Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4681 {
4682   unsigned tie_t = 0;
4683   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4684   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4685   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4686   return tie_t;
4687 }
4688
4689 static void
4690 Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4691 {
4692   uint32 tie_t;
4693   tie_t = (val << 28) >> 28;
4694   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4695   tie_t = (val << 26) >> 30;
4696   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4697   tie_t = (val << 24) >> 30;
4698   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4699 }
4700
4701 static unsigned
4702 Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4703 {
4704   unsigned tie_t = 0;
4705   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4706   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4707   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4708   return tie_t;
4709 }
4710
4711 static void
4712 Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4713 {
4714   uint32 tie_t;
4715   tie_t = (val << 28) >> 28;
4716   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4717   tie_t = (val << 26) >> 30;
4718   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4719   tie_t = (val << 24) >> 30;
4720   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4721 }
4722
4723 static unsigned
4724 Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4725 {
4726   unsigned tie_t = 0;
4727   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
4728   return tie_t;
4729 }
4730
4731 static void
4732 Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4733 {
4734   uint32 tie_t;
4735   tie_t = (val << 28) >> 28;
4736   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
4737 }
4738
4739 static unsigned
4740 Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4741 {
4742   unsigned tie_t = 0;
4743   tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25);
4744   return tie_t;
4745 }
4746
4747 static void
4748 Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4749 {
4750   uint32 tie_t;
4751   tie_t = (val << 25) >> 25;
4752   insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20);
4753 }
4754
4755 static unsigned
4756 Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4757 {
4758   unsigned tie_t = 0;
4759   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
4760   return tie_t;
4761 }
4762
4763 static void
4764 Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4765 {
4766   uint32 tie_t;
4767   tie_t = (val << 24) >> 24;
4768   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
4769 }
4770
4771 static unsigned
4772 Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4773 {
4774   unsigned tie_t = 0;
4775   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4776   return tie_t;
4777 }
4778
4779 static void
4780 Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4781 {
4782   uint32 tie_t;
4783   tie_t = (val << 28) >> 28;
4784   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4785 }
4786
4787 static unsigned
4788 Field_ftsf293_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4789 {
4790   unsigned tie_t = 0;
4791   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
4792   return tie_t;
4793 }
4794
4795 static void
4796 Field_ftsf293_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4797 {
4798   uint32 tie_t;
4799   tie_t = (val << 29) >> 29;
4800   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
4801 }
4802
4803 static unsigned
4804 Field_ftsf321_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4805 {
4806   unsigned tie_t = 0;
4807   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
4808   return tie_t;
4809 }
4810
4811 static void
4812 Field_ftsf321_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4813 {
4814   uint32 tie_t;
4815   tie_t = (val << 31) >> 31;
4816   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
4817 }
4818
4819 static unsigned
4820 Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4821 {
4822   unsigned tie_t = 0;
4823   tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
4824   return tie_t;
4825 }
4826
4827 static void
4828 Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4829 {
4830   uint32 tie_t;
4831   tie_t = (val << 29) >> 29;
4832   insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
4833 }
4834
4835 static unsigned
4836 Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4837 {
4838   unsigned tie_t = 0;
4839   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
4840   return tie_t;
4841 }
4842
4843 static void
4844 Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4845 {
4846   uint32 tie_t;
4847   tie_t = (val << 28) >> 28;
4848   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
4849 }
4850
4851 static unsigned
4852 Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4853 {
4854   unsigned tie_t = 0;
4855   tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
4856   return tie_t;
4857 }
4858
4859 static void
4860 Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4861 {
4862   uint32 tie_t;
4863   tie_t = (val << 29) >> 29;
4864   insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
4865 }
4866
4867 static unsigned
4868 Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4869 {
4870   unsigned tie_t = 0;
4871   tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
4872   return tie_t;
4873 }
4874
4875 static void
4876 Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4877 {
4878   uint32 tie_t;
4879   tie_t = (val << 30) >> 30;
4880   insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
4881 }
4882
4883 static unsigned
4884 Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4885 {
4886   unsigned tie_t = 0;
4887   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
4888   tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
4889   return tie_t;
4890 }
4891
4892 static void
4893 Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4894 {
4895   uint32 tie_t;
4896   tie_t = (val << 24) >> 24;
4897   insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
4898   tie_t = (val << 16) >> 24;
4899   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
4900 }
4901
4902 static unsigned
4903 Field_ftsf217_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4904 {
4905   unsigned tie_t = 0;
4906   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4907   return tie_t;
4908 }
4909
4910 static void
4911 Field_ftsf217_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4912 {
4913   uint32 tie_t;
4914   tie_t = (val << 31) >> 31;
4915   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4916 }
4917
4918 static unsigned
4919 Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4920 {
4921   unsigned tie_t = 0;
4922   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
4923   return tie_t;
4924 }
4925
4926 static void
4927 Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4928 {
4929   uint32 tie_t;
4930   tie_t = (val << 29) >> 29;
4931   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
4932 }
4933
4934 static unsigned
4935 Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4936 {
4937   unsigned tie_t = 0;
4938   tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
4939   return tie_t;
4940 }
4941
4942 static void
4943 Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4944 {
4945   uint32 tie_t;
4946   tie_t = (val << 20) >> 20;
4947   insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
4948 }
4949
4950 static unsigned
4951 Field_ftsf283ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4952 {
4953   unsigned tie_t = 0;
4954   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
4955   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4956   tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
4957   return tie_t;
4958 }
4959
4960 static void
4961 Field_ftsf283ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4962 {
4963   uint32 tie_t;
4964   tie_t = (val << 26) >> 26;
4965   insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
4966   tie_t = (val << 25) >> 31;
4967   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4968   tie_t = (val << 17) >> 24;
4969   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
4970 }
4971
4972 static unsigned
4973 Field_ftsf352ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4974 {
4975   unsigned tie_t = 0;
4976   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
4977   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
4978   return tie_t;
4979 }
4980
4981 static void
4982 Field_ftsf352ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4983 {
4984   uint32 tie_t;
4985   tie_t = (val << 31) >> 31;
4986   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
4987   tie_t = (val << 27) >> 28;
4988   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
4989 }
4990
4991 static unsigned
4992 Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4993 {
4994   unsigned tie_t = 0;
4995   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
4996   tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
4997   return tie_t;
4998 }
4999
5000 static void
5001 Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5002 {
5003   uint32 tie_t;
5004   tie_t = (val << 24) >> 24;
5005   insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
5006   tie_t = (val << 16) >> 24;
5007   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5008 }
5009
5010 static unsigned
5011 Field_ftsf288ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5012 {
5013   unsigned tie_t = 0;
5014   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5015   tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29);
5016   return tie_t;
5017 }
5018
5019 static void
5020 Field_ftsf288ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5021 {
5022   uint32 tie_t;
5023   tie_t = (val << 29) >> 29;
5024   insn[0] = (insn[0] & ~0x38) | (tie_t << 3);
5025   tie_t = (val << 21) >> 24;
5026   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5027 }
5028
5029 static unsigned
5030 Field_ftsf359ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5031 {
5032   unsigned tie_t = 0;
5033   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
5034   tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
5035   return tie_t;
5036 }
5037
5038 static void
5039 Field_ftsf359ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5040 {
5041   uint32 tie_t;
5042   tie_t = (val << 29) >> 29;
5043   insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
5044   tie_t = (val << 27) >> 30;
5045   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
5046 }
5047
5048 static unsigned
5049 Field_ftsf286ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5050 {
5051   unsigned tie_t = 0;
5052   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5053   tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28);
5054   return tie_t;
5055 }
5056
5057 static void
5058 Field_ftsf286ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5059 {
5060   uint32 tie_t;
5061   tie_t = (val << 28) >> 28;
5062   insn[0] = (insn[0] & ~0x3c) | (tie_t << 2);
5063   tie_t = (val << 20) >> 24;
5064   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5065 }
5066
5067 static unsigned
5068 Field_ftsf356ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5069 {
5070   unsigned tie_t = 0;
5071   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
5072   tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
5073   return tie_t;
5074 }
5075
5076 static void
5077 Field_ftsf356ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5078 {
5079   uint32 tie_t;
5080   tie_t = (val << 30) >> 30;
5081   insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
5082   tie_t = (val << 28) >> 30;
5083   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
5084 }
5085
5086 static unsigned
5087 Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5088 {
5089   unsigned tie_t = 0;
5090   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5091   tie_t = (tie_t << 5) | ((insn[0] << 26) >> 27);
5092   return tie_t;
5093 }
5094
5095 static void
5096 Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5097 {
5098   uint32 tie_t;
5099   tie_t = (val << 27) >> 27;
5100   insn[0] = (insn[0] & ~0x3e) | (tie_t << 1);
5101   tie_t = (val << 19) >> 24;
5102   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5103 }
5104
5105 static unsigned
5106 Field_ftsf354ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5107 {
5108   unsigned tie_t = 0;
5109   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
5110   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
5111   return tie_t;
5112 }
5113
5114 static void
5115 Field_ftsf354ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5116 {
5117   uint32 tie_t;
5118   tie_t = (val << 31) >> 31;
5119   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
5120   tie_t = (val << 29) >> 30;
5121   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
5122 }
5123
5124 static unsigned
5125 Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5126 {
5127   unsigned tie_t = 0;
5128   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5129   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5130   tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
5131   return tie_t;
5132 }
5133
5134 static void
5135 Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5136 {
5137   uint32 tie_t;
5138   tie_t = (val << 31) >> 31;
5139   insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
5140   tie_t = (val << 30) >> 31;
5141   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5142   tie_t = (val << 22) >> 24;
5143   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5144 }
5145
5146 static unsigned
5147 Field_ftsf358ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5148 {
5149   unsigned tie_t = 0;
5150   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
5151   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
5152   return tie_t;
5153 }
5154
5155 static void
5156 Field_ftsf358ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5157 {
5158   uint32 tie_t;
5159   tie_t = (val << 31) >> 31;
5160   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
5161   tie_t = (val << 27) >> 28;
5162   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
5163 }
5164
5165 static unsigned
5166 Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5167 {
5168   unsigned tie_t = 0;
5169   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5170   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
5171   return tie_t;
5172 }
5173
5174 static void
5175 Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5176 {
5177   uint32 tie_t;
5178   tie_t = (val << 28) >> 28;
5179   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
5180   tie_t = (val << 20) >> 24;
5181   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5182 }
5183
5184 static unsigned
5185 Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5186 {
5187   unsigned tie_t = 0;
5188   tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25);
5189   return tie_t;
5190 }
5191
5192 static void
5193 Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5194 {
5195   uint32 tie_t;
5196   tie_t = (val << 25) >> 25;
5197   insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13);
5198 }
5199
5200 static unsigned
5201 Field_ftsf301ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5202 {
5203   unsigned tie_t = 0;
5204   tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19);
5205   return tie_t;
5206 }
5207
5208 static void
5209 Field_ftsf301ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5210 {
5211   uint32 tie_t;
5212   tie_t = (val << 19) >> 19;
5213   insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7);
5214 }
5215
5216 static unsigned
5217 Field_ftsf353_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5218 {
5219   unsigned tie_t = 0;
5220   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
5221   return tie_t;
5222 }
5223
5224 static void
5225 Field_ftsf353_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5226 {
5227   uint32 tie_t;
5228   tie_t = (val << 31) >> 31;
5229   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
5230 }
5231
5232 static unsigned
5233 Field_ftsf309ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5234 {
5235   unsigned tie_t = 0;
5236   tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23);
5237   return tie_t;
5238 }
5239
5240 static void
5241 Field_ftsf309ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5242 {
5243   uint32 tie_t;
5244   tie_t = (val << 23) >> 23;
5245   insn[0] = (insn[0] & ~0xff800) | (tie_t << 11);
5246 }
5247
5248 static unsigned
5249 Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5250 {
5251   unsigned tie_t = 0;
5252   tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27);
5253   return tie_t;
5254 }
5255
5256 static void
5257 Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5258 {
5259   uint32 tie_t;
5260   tie_t = (val << 27) >> 27;
5261   insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6);
5262 }
5263
5264 static unsigned
5265 Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5266 {
5267   unsigned tie_t = 0;
5268   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5269   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
5270   return tie_t;
5271 }
5272
5273 static void
5274 Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5275 {
5276   uint32 tie_t;
5277   tie_t = (val << 29) >> 29;
5278   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
5279   tie_t = (val << 21) >> 24;
5280   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5281 }
5282
5283 static unsigned
5284 Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5285 {
5286   unsigned tie_t = 0;
5287   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
5288   return tie_t;
5289 }
5290
5291 static void
5292 Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5293 {
5294   uint32 tie_t;
5295   tie_t = (val << 28) >> 28;
5296   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
5297 }
5298
5299 static unsigned
5300 Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5301 {
5302   unsigned tie_t = 0;
5303   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5304   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
5305   return tie_t;
5306 }
5307
5308 static void
5309 Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5310 {
5311   uint32 tie_t;
5312   tie_t = (val << 29) >> 29;
5313   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
5314   tie_t = (val << 21) >> 24;
5315   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5316 }
5317
5318 static unsigned
5319 Field_ftsf319_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5320 {
5321   unsigned tie_t = 0;
5322   tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
5323   return tie_t;
5324 }
5325
5326 static void
5327 Field_ftsf319_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5328 {
5329   uint32 tie_t;
5330   tie_t = (val << 29) >> 29;
5331   insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
5332 }
5333
5334 static unsigned
5335 Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5336 {
5337   unsigned tie_t = 0;
5338   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
5339   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
5340   return tie_t;
5341 }
5342
5343 static void
5344 Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5345 {
5346   uint32 tie_t;
5347   tie_t = (val << 31) >> 31;
5348   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
5349   tie_t = (val << 27) >> 28;
5350   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
5351 }
5352
5353 static unsigned
5354 Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5355 {
5356   unsigned tie_t = 0;
5357   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5358   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5359   return tie_t;
5360 }
5361
5362 static void
5363 Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5364 {
5365   uint32 tie_t;
5366   tie_t = (val << 31) >> 31;
5367   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5368   tie_t = (val << 23) >> 24;
5369   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5370 }
5371
5372 static unsigned
5373 Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5374 {
5375   unsigned tie_t = 0;
5376   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5377   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5378   return tie_t;
5379 }
5380
5381 static void
5382 Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5383 {
5384   uint32 tie_t;
5385   tie_t = (val << 31) >> 31;
5386   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5387   tie_t = (val << 23) >> 24;
5388   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5389 }
5390
5391 static unsigned
5392 Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5393 {
5394   unsigned tie_t = 0;
5395   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5396   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5397   return tie_t;
5398 }
5399
5400 static void
5401 Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5402 {
5403   uint32 tie_t;
5404   tie_t = (val << 31) >> 31;
5405   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5406   tie_t = (val << 23) >> 24;
5407   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5408 }
5409
5410 static unsigned
5411 Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5412 {
5413   unsigned tie_t = 0;
5414   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5415   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5416   return tie_t;
5417 }
5418
5419 static void
5420 Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5421 {
5422   uint32 tie_t;
5423   tie_t = (val << 31) >> 31;
5424   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5425   tie_t = (val << 23) >> 24;
5426   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5427 }
5428
5429 static unsigned
5430 Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5431 {
5432   unsigned tie_t = 0;
5433   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5434   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5435   return tie_t;
5436 }
5437
5438 static void
5439 Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5440 {
5441   uint32 tie_t;
5442   tie_t = (val << 31) >> 31;
5443   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5444   tie_t = (val << 23) >> 24;
5445   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5446 }
5447
5448 static unsigned
5449 Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5450 {
5451   unsigned tie_t = 0;
5452   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5453   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5454   return tie_t;
5455 }
5456
5457 static void
5458 Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5459 {
5460   uint32 tie_t;
5461   tie_t = (val << 31) >> 31;
5462   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5463   tie_t = (val << 23) >> 24;
5464   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5465 }
5466
5467 static unsigned
5468 Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5469 {
5470   unsigned tie_t = 0;
5471   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5472   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5473   return tie_t;
5474 }
5475
5476 static void
5477 Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5478 {
5479   uint32 tie_t;
5480   tie_t = (val << 31) >> 31;
5481   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5482   tie_t = (val << 23) >> 24;
5483   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5484 }
5485
5486 static unsigned
5487 Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5488 {
5489   unsigned tie_t = 0;
5490   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5491   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5492   return tie_t;
5493 }
5494
5495 static void
5496 Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5497 {
5498   uint32 tie_t;
5499   tie_t = (val << 31) >> 31;
5500   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5501   tie_t = (val << 23) >> 24;
5502   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5503 }
5504
5505 static unsigned
5506 Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5507 {
5508   unsigned tie_t = 0;
5509   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5510   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5511   return tie_t;
5512 }
5513
5514 static void
5515 Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5516 {
5517   uint32 tie_t;
5518   tie_t = (val << 31) >> 31;
5519   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5520   tie_t = (val << 23) >> 24;
5521   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5522 }
5523
5524 static unsigned
5525 Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5526 {
5527   unsigned tie_t = 0;
5528   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5529   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5530   return tie_t;
5531 }
5532
5533 static void
5534 Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5535 {
5536   uint32 tie_t;
5537   tie_t = (val << 31) >> 31;
5538   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5539   tie_t = (val << 23) >> 24;
5540   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5541 }
5542
5543 static unsigned
5544 Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5545 {
5546   unsigned tie_t = 0;
5547   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5548   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5549   return tie_t;
5550 }
5551
5552 static void
5553 Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5554 {
5555   uint32 tie_t;
5556   tie_t = (val << 31) >> 31;
5557   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5558   tie_t = (val << 23) >> 24;
5559   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5560 }
5561
5562 static unsigned
5563 Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5564 {
5565   unsigned tie_t = 0;
5566   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5567   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5568   return tie_t;
5569 }
5570
5571 static void
5572 Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5573 {
5574   uint32 tie_t;
5575   tie_t = (val << 31) >> 31;
5576   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5577   tie_t = (val << 23) >> 24;
5578   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5579 }
5580
5581 static unsigned
5582 Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5583 {
5584   unsigned tie_t = 0;
5585   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5586   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5587   return tie_t;
5588 }
5589
5590 static void
5591 Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5592 {
5593   uint32 tie_t;
5594   tie_t = (val << 31) >> 31;
5595   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5596   tie_t = (val << 23) >> 24;
5597   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5598 }
5599
5600 static unsigned
5601 Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5602 {
5603   unsigned tie_t = 0;
5604   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5605   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5606   return tie_t;
5607 }
5608
5609 static void
5610 Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5611 {
5612   uint32 tie_t;
5613   tie_t = (val << 31) >> 31;
5614   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5615   tie_t = (val << 23) >> 24;
5616   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5617 }
5618
5619 static unsigned
5620 Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5621 {
5622   unsigned tie_t = 0;
5623   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5624   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5625   return tie_t;
5626 }
5627
5628 static void
5629 Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5630 {
5631   uint32 tie_t;
5632   tie_t = (val << 31) >> 31;
5633   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5634   tie_t = (val << 23) >> 24;
5635   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5636 }
5637
5638 static unsigned
5639 Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5640 {
5641   unsigned tie_t = 0;
5642   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5643   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5644   return tie_t;
5645 }
5646
5647 static void
5648 Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5649 {
5650   uint32 tie_t;
5651   tie_t = (val << 31) >> 31;
5652   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5653   tie_t = (val << 23) >> 24;
5654   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5655 }
5656
5657 static unsigned
5658 Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5659 {
5660   unsigned tie_t = 0;
5661   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5662   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5663   return tie_t;
5664 }
5665
5666 static void
5667 Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5668 {
5669   uint32 tie_t;
5670   tie_t = (val << 31) >> 31;
5671   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5672   tie_t = (val << 23) >> 24;
5673   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5674 }
5675
5676 static unsigned
5677 Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5678 {
5679   unsigned tie_t = 0;
5680   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5681   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5682   return tie_t;
5683 }
5684
5685 static void
5686 Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5687 {
5688   uint32 tie_t;
5689   tie_t = (val << 31) >> 31;
5690   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5691   tie_t = (val << 23) >> 24;
5692   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5693 }
5694
5695 static unsigned
5696 Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5697 {
5698   unsigned tie_t = 0;
5699   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5700   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5701   return tie_t;
5702 }
5703
5704 static void
5705 Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5706 {
5707   uint32 tie_t;
5708   tie_t = (val << 31) >> 31;
5709   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5710   tie_t = (val << 23) >> 24;
5711   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5712 }
5713
5714 static unsigned
5715 Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5716 {
5717   unsigned tie_t = 0;
5718   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5719   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5720   return tie_t;
5721 }
5722
5723 static void
5724 Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5725 {
5726   uint32 tie_t;
5727   tie_t = (val << 31) >> 31;
5728   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5729   tie_t = (val << 23) >> 24;
5730   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5731 }
5732
5733 static unsigned
5734 Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5735 {
5736   unsigned tie_t = 0;
5737   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5738   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5739   return tie_t;
5740 }
5741
5742 static void
5743 Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5744 {
5745   uint32 tie_t;
5746   tie_t = (val << 31) >> 31;
5747   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5748   tie_t = (val << 23) >> 24;
5749   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5750 }
5751
5752 static unsigned
5753 Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5754 {
5755   unsigned tie_t = 0;
5756   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5757   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5758   return tie_t;
5759 }
5760
5761 static void
5762 Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5763 {
5764   uint32 tie_t;
5765   tie_t = (val << 31) >> 31;
5766   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5767   tie_t = (val << 23) >> 24;
5768   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5769 }
5770
5771 static unsigned
5772 Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5773 {
5774   unsigned tie_t = 0;
5775   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5776   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5777   return tie_t;
5778 }
5779
5780 static void
5781 Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5782 {
5783   uint32 tie_t;
5784   tie_t = (val << 31) >> 31;
5785   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5786   tie_t = (val << 23) >> 24;
5787   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5788 }
5789
5790 static unsigned
5791 Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5792 {
5793   unsigned tie_t = 0;
5794   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5795   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5796   return tie_t;
5797 }
5798
5799 static void
5800 Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5801 {
5802   uint32 tie_t;
5803   tie_t = (val << 31) >> 31;
5804   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5805   tie_t = (val << 23) >> 24;
5806   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5807 }
5808
5809 static unsigned
5810 Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5811 {
5812   unsigned tie_t = 0;
5813   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5814   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5815   return tie_t;
5816 }
5817
5818 static void
5819 Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5820 {
5821   uint32 tie_t;
5822   tie_t = (val << 31) >> 31;
5823   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5824   tie_t = (val << 23) >> 24;
5825   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5826 }
5827
5828 static unsigned
5829 Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5830 {
5831   unsigned tie_t = 0;
5832   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5833   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5834   return tie_t;
5835 }
5836
5837 static void
5838 Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5839 {
5840   uint32 tie_t;
5841   tie_t = (val << 31) >> 31;
5842   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5843   tie_t = (val << 23) >> 24;
5844   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5845 }
5846
5847 static unsigned
5848 Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5849 {
5850   unsigned tie_t = 0;
5851   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5852   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5853   return tie_t;
5854 }
5855
5856 static void
5857 Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5858 {
5859   uint32 tie_t;
5860   tie_t = (val << 31) >> 31;
5861   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5862   tie_t = (val << 23) >> 24;
5863   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5864 }
5865
5866 static unsigned
5867 Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5868 {
5869   unsigned tie_t = 0;
5870   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5871   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5872   return tie_t;
5873 }
5874
5875 static void
5876 Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5877 {
5878   uint32 tie_t;
5879   tie_t = (val << 31) >> 31;
5880   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5881   tie_t = (val << 23) >> 24;
5882   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5883 }
5884
5885 static unsigned
5886 Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5887 {
5888   unsigned tie_t = 0;
5889   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5890   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5891   return tie_t;
5892 }
5893
5894 static void
5895 Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5896 {
5897   uint32 tie_t;
5898   tie_t = (val << 31) >> 31;
5899   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5900   tie_t = (val << 23) >> 24;
5901   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5902 }
5903
5904 static unsigned
5905 Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5906 {
5907   unsigned tie_t = 0;
5908   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5909   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5910   return tie_t;
5911 }
5912
5913 static void
5914 Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5915 {
5916   uint32 tie_t;
5917   tie_t = (val << 31) >> 31;
5918   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5919   tie_t = (val << 23) >> 24;
5920   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5921 }
5922
5923 static unsigned
5924 Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5925 {
5926   unsigned tie_t = 0;
5927   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5928   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5929   return tie_t;
5930 }
5931
5932 static void
5933 Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5934 {
5935   uint32 tie_t;
5936   tie_t = (val << 31) >> 31;
5937   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5938   tie_t = (val << 23) >> 24;
5939   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5940 }
5941
5942 static unsigned
5943 Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5944 {
5945   unsigned tie_t = 0;
5946   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5947   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5948   return tie_t;
5949 }
5950
5951 static void
5952 Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5953 {
5954   uint32 tie_t;
5955   tie_t = (val << 31) >> 31;
5956   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5957   tie_t = (val << 23) >> 24;
5958   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5959 }
5960
5961 static unsigned
5962 Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5963 {
5964   unsigned tie_t = 0;
5965   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5966   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5967   return tie_t;
5968 }
5969
5970 static void
5971 Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5972 {
5973   uint32 tie_t;
5974   tie_t = (val << 31) >> 31;
5975   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5976   tie_t = (val << 23) >> 24;
5977   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5978 }
5979
5980 static unsigned
5981 Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5982 {
5983   unsigned tie_t = 0;
5984   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5985   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5986   return tie_t;
5987 }
5988
5989 static void
5990 Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5991 {
5992   uint32 tie_t;
5993   tie_t = (val << 31) >> 31;
5994   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5995   tie_t = (val << 23) >> 24;
5996   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5997 }
5998
5999 static unsigned
6000 Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6001 {
6002   unsigned tie_t = 0;
6003   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6004   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6005   return tie_t;
6006 }
6007
6008 static void
6009 Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6010 {
6011   uint32 tie_t;
6012   tie_t = (val << 31) >> 31;
6013   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6014   tie_t = (val << 23) >> 24;
6015   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6016 }
6017
6018 static unsigned
6019 Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6020 {
6021   unsigned tie_t = 0;
6022   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6023   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6024   return tie_t;
6025 }
6026
6027 static void
6028 Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6029 {
6030   uint32 tie_t;
6031   tie_t = (val << 31) >> 31;
6032   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6033   tie_t = (val << 23) >> 24;
6034   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6035 }
6036
6037 static unsigned
6038 Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6039 {
6040   unsigned tie_t = 0;
6041   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6042   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6043   return tie_t;
6044 }
6045
6046 static void
6047 Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6048 {
6049   uint32 tie_t;
6050   tie_t = (val << 31) >> 31;
6051   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6052   tie_t = (val << 23) >> 24;
6053   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6054 }
6055
6056 static unsigned
6057 Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6058 {
6059   unsigned tie_t = 0;
6060   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6061   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6062   return tie_t;
6063 }
6064
6065 static void
6066 Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6067 {
6068   uint32 tie_t;
6069   tie_t = (val << 31) >> 31;
6070   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6071   tie_t = (val << 23) >> 24;
6072   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6073 }
6074
6075 static unsigned
6076 Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6077 {
6078   unsigned tie_t = 0;
6079   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6080   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6081   return tie_t;
6082 }
6083
6084 static void
6085 Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6086 {
6087   uint32 tie_t;
6088   tie_t = (val << 31) >> 31;
6089   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6090   tie_t = (val << 23) >> 24;
6091   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6092 }
6093
6094 static unsigned
6095 Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6096 {
6097   unsigned tie_t = 0;
6098   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6099   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6100   return tie_t;
6101 }
6102
6103 static void
6104 Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6105 {
6106   uint32 tie_t;
6107   tie_t = (val << 31) >> 31;
6108   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6109   tie_t = (val << 23) >> 24;
6110   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6111 }
6112
6113 static unsigned
6114 Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6115 {
6116   unsigned tie_t = 0;
6117   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6118   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6119   return tie_t;
6120 }
6121
6122 static void
6123 Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6124 {
6125   uint32 tie_t;
6126   tie_t = (val << 31) >> 31;
6127   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6128   tie_t = (val << 23) >> 24;
6129   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6130 }
6131
6132 static unsigned
6133 Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6134 {
6135   unsigned tie_t = 0;
6136   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6137   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6138   return tie_t;
6139 }
6140
6141 static void
6142 Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6143 {
6144   uint32 tie_t;
6145   tie_t = (val << 31) >> 31;
6146   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6147   tie_t = (val << 23) >> 24;
6148   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6149 }
6150
6151 static unsigned
6152 Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6153 {
6154   unsigned tie_t = 0;
6155   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6156   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6157   return tie_t;
6158 }
6159
6160 static void
6161 Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6162 {
6163   uint32 tie_t;
6164   tie_t = (val << 31) >> 31;
6165   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6166   tie_t = (val << 23) >> 24;
6167   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6168 }
6169
6170 static unsigned
6171 Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6172 {
6173   unsigned tie_t = 0;
6174   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6175   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6176   return tie_t;
6177 }
6178
6179 static void
6180 Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6181 {
6182   uint32 tie_t;
6183   tie_t = (val << 31) >> 31;
6184   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6185   tie_t = (val << 23) >> 24;
6186   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6187 }
6188
6189 static unsigned
6190 Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6191 {
6192   unsigned tie_t = 0;
6193   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6194   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6195   return tie_t;
6196 }
6197
6198 static void
6199 Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6200 {
6201   uint32 tie_t;
6202   tie_t = (val << 31) >> 31;
6203   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6204   tie_t = (val << 23) >> 24;
6205   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6206 }
6207
6208 static unsigned
6209 Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6210 {
6211   unsigned tie_t = 0;
6212   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6213   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6214   return tie_t;
6215 }
6216
6217 static void
6218 Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6219 {
6220   uint32 tie_t;
6221   tie_t = (val << 31) >> 31;
6222   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6223   tie_t = (val << 23) >> 24;
6224   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6225 }
6226
6227 static unsigned
6228 Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6229 {
6230   unsigned tie_t = 0;
6231   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6232   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6233   return tie_t;
6234 }
6235
6236 static void
6237 Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6238 {
6239   uint32 tie_t;
6240   tie_t = (val << 31) >> 31;
6241   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6242   tie_t = (val << 23) >> 24;
6243   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6244 }
6245
6246 static unsigned
6247 Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6248 {
6249   unsigned tie_t = 0;
6250   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6251   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6252   return tie_t;
6253 }
6254
6255 static void
6256 Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6257 {
6258   uint32 tie_t;
6259   tie_t = (val << 31) >> 31;
6260   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6261   tie_t = (val << 23) >> 24;
6262   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6263 }
6264
6265 static unsigned
6266 Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6267 {
6268   unsigned tie_t = 0;
6269   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6270   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6271   return tie_t;
6272 }
6273
6274 static void
6275 Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6276 {
6277   uint32 tie_t;
6278   tie_t = (val << 30) >> 30;
6279   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6280   tie_t = (val << 22) >> 24;
6281   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6282 }
6283
6284 static unsigned
6285 Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6286 {
6287   unsigned tie_t = 0;
6288   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6289   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6290   return tie_t;
6291 }
6292
6293 static void
6294 Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6295 {
6296   uint32 tie_t;
6297   tie_t = (val << 30) >> 30;
6298   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6299   tie_t = (val << 22) >> 24;
6300   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6301 }
6302
6303 static unsigned
6304 Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6305 {
6306   unsigned tie_t = 0;
6307   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6308   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6309   return tie_t;
6310 }
6311
6312 static void
6313 Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6314 {
6315   uint32 tie_t;
6316   tie_t = (val << 30) >> 30;
6317   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6318   tie_t = (val << 22) >> 24;
6319   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6320 }
6321
6322 static unsigned
6323 Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6324 {
6325   unsigned tie_t = 0;
6326   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6327   tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
6328   return tie_t;
6329 }
6330
6331 static void
6332 Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6333 {
6334   uint32 tie_t;
6335   tie_t = (val << 31) >> 31;
6336   insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
6337   tie_t = (val << 23) >> 24;
6338   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6339 }
6340
6341 static unsigned
6342 Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6343 {
6344   unsigned tie_t = 0;
6345   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
6346   return tie_t;
6347 }
6348
6349 static void
6350 Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6351 {
6352   uint32 tie_t;
6353   tie_t = (val << 31) >> 31;
6354   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
6355 }
6356
6357 static unsigned
6358 Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6359 {
6360   unsigned tie_t = 0;
6361   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6362   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6363   return tie_t;
6364 }
6365
6366 static void
6367 Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6368 {
6369   uint32 tie_t;
6370   tie_t = (val << 30) >> 30;
6371   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6372   tie_t = (val << 22) >> 24;
6373   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6374 }
6375
6376 static unsigned
6377 Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6378 {
6379   unsigned tie_t = 0;
6380   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6381   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6382   return tie_t;
6383 }
6384
6385 static void
6386 Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6387 {
6388   uint32 tie_t;
6389   tie_t = (val << 30) >> 30;
6390   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6391   tie_t = (val << 22) >> 24;
6392   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6393 }
6394
6395 static unsigned
6396 Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6397 {
6398   unsigned tie_t = 0;
6399   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6400   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6401   return tie_t;
6402 }
6403
6404 static void
6405 Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6406 {
6407   uint32 tie_t;
6408   tie_t = (val << 30) >> 30;
6409   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6410   tie_t = (val << 22) >> 24;
6411   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6412 }
6413
6414 static unsigned
6415 Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6416 {
6417   unsigned tie_t = 0;
6418   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6419   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6420   return tie_t;
6421 }
6422
6423 static void
6424 Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6425 {
6426   uint32 tie_t;
6427   tie_t = (val << 30) >> 30;
6428   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6429   tie_t = (val << 22) >> 24;
6430   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6431 }
6432
6433 static unsigned
6434 Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6435 {
6436   unsigned tie_t = 0;
6437   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6438   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6439   return tie_t;
6440 }
6441
6442 static void
6443 Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6444 {
6445   uint32 tie_t;
6446   tie_t = (val << 30) >> 30;
6447   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6448   tie_t = (val << 22) >> 24;
6449   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6450 }
6451
6452 static unsigned
6453 Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6454 {
6455   unsigned tie_t = 0;
6456   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6457   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6458   return tie_t;
6459 }
6460
6461 static void
6462 Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6463 {
6464   uint32 tie_t;
6465   tie_t = (val << 30) >> 30;
6466   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6467   tie_t = (val << 22) >> 24;
6468   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6469 }
6470
6471 static unsigned
6472 Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6473 {
6474   unsigned tie_t = 0;
6475   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6476   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6477   return tie_t;
6478 }
6479
6480 static void
6481 Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6482 {
6483   uint32 tie_t;
6484   tie_t = (val << 30) >> 30;
6485   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6486   tie_t = (val << 22) >> 24;
6487   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6488 }
6489
6490 static unsigned
6491 Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6492 {
6493   unsigned tie_t = 0;
6494   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6495   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6496   return tie_t;
6497 }
6498
6499 static void
6500 Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6501 {
6502   uint32 tie_t;
6503   tie_t = (val << 30) >> 30;
6504   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6505   tie_t = (val << 22) >> 24;
6506   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6507 }
6508
6509 static unsigned
6510 Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6511 {
6512   unsigned tie_t = 0;
6513   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6514   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6515   return tie_t;
6516 }
6517
6518 static void
6519 Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6520 {
6521   uint32 tie_t;
6522   tie_t = (val << 30) >> 30;
6523   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6524   tie_t = (val << 22) >> 24;
6525   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6526 }
6527
6528 static unsigned
6529 Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6530 {
6531   unsigned tie_t = 0;
6532   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6533   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6534   return tie_t;
6535 }
6536
6537 static void
6538 Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6539 {
6540   uint32 tie_t;
6541   tie_t = (val << 30) >> 30;
6542   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6543   tie_t = (val << 22) >> 24;
6544   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6545 }
6546
6547 static unsigned
6548 Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6549 {
6550   unsigned tie_t = 0;
6551   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6552   return tie_t;
6553 }
6554
6555 static void
6556 Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6557 {
6558   uint32 tie_t;
6559   tie_t = (val << 30) >> 30;
6560   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6561 }
6562
6563 static unsigned
6564 Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6565 {
6566   unsigned tie_t = 0;
6567   tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27);
6568   return tie_t;
6569 }
6570
6571 static void
6572 Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6573 {
6574   uint32 tie_t;
6575   tie_t = (val << 27) >> 27;
6576   insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15);
6577 }
6578
6579 static unsigned
6580 Field_ftsf362ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6581 {
6582   unsigned tie_t = 0;
6583   tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
6584   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6585   return tie_t;
6586 }
6587
6588 static void
6589 Field_ftsf362ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6590 {
6591   uint32 tie_t;
6592   tie_t = (val << 30) >> 30;
6593   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6594   tie_t = (val << 27) >> 29;
6595   insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
6596 }
6597
6598 static unsigned
6599 Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6600 {
6601   unsigned tie_t = 0;
6602   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6603   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6604   return tie_t;
6605 }
6606
6607 static void
6608 Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6609 {
6610   uint32 tie_t;
6611   tie_t = (val << 31) >> 31;
6612   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6613   tie_t = (val << 23) >> 24;
6614   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6615 }
6616
6617 static unsigned
6618 Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6619 {
6620   unsigned tie_t = 0;
6621   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6622   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6623   return tie_t;
6624 }
6625
6626 static void
6627 Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6628 {
6629   uint32 tie_t;
6630   tie_t = (val << 31) >> 31;
6631   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6632   tie_t = (val << 23) >> 24;
6633   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6634 }
6635
6636 static unsigned
6637 Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6638 {
6639   unsigned tie_t = 0;
6640   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6641   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6642   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6643   return tie_t;
6644 }
6645
6646 static void
6647 Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6648 {
6649   uint32 tie_t;
6650   tie_t = (val << 28) >> 28;
6651   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6652   tie_t = (val << 27) >> 31;
6653   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6654   tie_t = (val << 19) >> 24;
6655   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6656 }
6657
6658 static unsigned
6659 Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6660 {
6661   unsigned tie_t = 0;
6662   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6663   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6664   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6665   return tie_t;
6666 }
6667
6668 static void
6669 Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6670 {
6671   uint32 tie_t;
6672   tie_t = (val << 28) >> 28;
6673   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6674   tie_t = (val << 27) >> 31;
6675   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6676   tie_t = (val << 19) >> 24;
6677   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6678 }
6679
6680 static unsigned
6681 Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6682 {
6683   unsigned tie_t = 0;
6684   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6685   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6686   return tie_t;
6687 }
6688
6689 static void
6690 Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6691 {
6692   uint32 tie_t;
6693   tie_t = (val << 31) >> 31;
6694   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6695   tie_t = (val << 23) >> 24;
6696   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6697 }
6698
6699 static unsigned
6700 Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6701 {
6702   unsigned tie_t = 0;
6703   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6704   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6705   return tie_t;
6706 }
6707
6708 static void
6709 Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6710 {
6711   uint32 tie_t;
6712   tie_t = (val << 31) >> 31;
6713   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6714   tie_t = (val << 23) >> 24;
6715   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6716 }
6717
6718 static unsigned
6719 Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6720 {
6721   unsigned tie_t = 0;
6722   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6723   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6724   return tie_t;
6725 }
6726
6727 static void
6728 Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6729 {
6730   uint32 tie_t;
6731   tie_t = (val << 31) >> 31;
6732   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6733   tie_t = (val << 23) >> 24;
6734   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6735 }
6736
6737 static unsigned
6738 Field_ftsf216ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6739 {
6740   unsigned tie_t = 0;
6741   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6742   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6743   return tie_t;
6744 }
6745
6746 static void
6747 Field_ftsf216ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6748 {
6749   uint32 tie_t;
6750   tie_t = (val << 31) >> 31;
6751   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6752   tie_t = (val << 23) >> 24;
6753   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6754 }
6755
6756 static unsigned
6757 Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6758 {
6759   unsigned tie_t = 0;
6760   tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
6761   tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
6762   return tie_t;
6763 }
6764
6765 static void
6766 Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6767 {
6768   uint32 tie_t;
6769   tie_t = (val << 29) >> 29;
6770   insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
6771   tie_t = (val << 17) >> 20;
6772   insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
6773 }
6774
6775 static unsigned
6776 Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6777 {
6778   unsigned tie_t = 0;
6779   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
6780   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6781   return tie_t;
6782 }
6783
6784 static void
6785 Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6786 {
6787   uint32 tie_t;
6788   tie_t = (val << 28) >> 28;
6789   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6790   tie_t = (val << 27) >> 31;
6791   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
6792 }
6793
6794 static unsigned
6795 Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6796 {
6797   unsigned tie_t = 0;
6798   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6799   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6800   return tie_t;
6801 }
6802
6803 static void
6804 Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6805 {
6806   uint32 tie_t;
6807   tie_t = (val << 28) >> 28;
6808   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6809   tie_t = (val << 20) >> 24;
6810   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6811 }
6812
6813 static unsigned
6814 Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6815 {
6816   unsigned tie_t = 0;
6817   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6818   tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
6819   return tie_t;
6820 }
6821
6822 static void
6823 Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6824 {
6825   uint32 tie_t;
6826   tie_t = (val << 26) >> 26;
6827   insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
6828   tie_t = (val << 18) >> 24;
6829   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6830 }
6831
6832 static unsigned
6833 Field_ftsf318ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6834 {
6835   unsigned tie_t = 0;
6836   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6837   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6838   tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
6839   return tie_t;
6840 }
6841
6842 static void
6843 Field_ftsf318ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6844 {
6845   uint32 tie_t;
6846   tie_t = (val << 29) >> 29;
6847   insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
6848   tie_t = (val << 28) >> 31;
6849   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6850   tie_t = (val << 20) >> 24;
6851   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6852 }
6853
6854 static unsigned
6855 Field_ftsf365ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6856 {
6857   unsigned tie_t = 0;
6858   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
6859   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
6860   return tie_t;
6861 }
6862
6863 static void
6864 Field_ftsf365ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6865 {
6866   uint32 tie_t;
6867   tie_t = (val << 31) >> 31;
6868   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
6869   tie_t = (val << 30) >> 31;
6870   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
6871 }
6872
6873 static unsigned
6874 Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6875 {
6876   unsigned tie_t = 0;
6877   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6878   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6879   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6880   return tie_t;
6881 }
6882
6883 static void
6884 Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6885 {
6886   uint32 tie_t;
6887   tie_t = (val << 28) >> 28;
6888   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6889   tie_t = (val << 27) >> 31;
6890   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6891   tie_t = (val << 19) >> 24;
6892   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6893 }
6894
6895 static unsigned
6896 Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6897 {
6898   unsigned tie_t = 0;
6899   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6900   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6901   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6902   return tie_t;
6903 }
6904
6905 static void
6906 Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6907 {
6908   uint32 tie_t;
6909   tie_t = (val << 28) >> 28;
6910   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6911   tie_t = (val << 27) >> 31;
6912   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6913   tie_t = (val << 19) >> 24;
6914   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6915 }
6916
6917 static unsigned
6918 Field_ftsf315ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6919 {
6920   unsigned tie_t = 0;
6921   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6922   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6923   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6924   return tie_t;
6925 }
6926
6927 static void
6928 Field_ftsf315ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6929 {
6930   uint32 tie_t;
6931   tie_t = (val << 28) >> 28;
6932   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6933   tie_t = (val << 27) >> 31;
6934   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6935   tie_t = (val << 19) >> 24;
6936   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6937 }
6938
6939 static unsigned
6940 Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6941 {
6942   unsigned tie_t = 0;
6943   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6944   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6945   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
6946   return tie_t;
6947 }
6948
6949 static void
6950 Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6951 {
6952   uint32 tie_t;
6953   tie_t = (val << 31) >> 31;
6954   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
6955   tie_t = (val << 30) >> 31;
6956   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6957   tie_t = (val << 22) >> 24;
6958   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6959 }
6960
6961 static unsigned
6962 Field_ftsf299ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6963 {
6964   unsigned tie_t = 0;
6965   tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22);
6966   return tie_t;
6967 }
6968
6969 static void
6970 Field_ftsf299ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6971 {
6972   uint32 tie_t;
6973   tie_t = (val << 22) >> 22;
6974   insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10);
6975 }
6976
6977 static unsigned
6978 Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6979 {
6980   unsigned tie_t = 0;
6981   tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21);
6982   return tie_t;
6983 }
6984
6985 static void
6986 Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6987 {
6988   uint32 tie_t;
6989   tie_t = (val << 21) >> 21;
6990   insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9);
6991 }
6992
6993 static unsigned
6994 Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6995 {
6996   unsigned tie_t = 0;
6997   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
6998   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6999   return tie_t;
7000 }
7001
7002 static void
7003 Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7004 {
7005   uint32 tie_t;
7006   tie_t = (val << 28) >> 28;
7007   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
7008   tie_t = (val << 27) >> 31;
7009   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
7010 }
7011
7012 static unsigned
7013 Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7014 {
7015   unsigned tie_t = 0;
7016   tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
7017   tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31);
7018   return tie_t;
7019 }
7020
7021 static void
7022 Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7023 {
7024   uint32 tie_t;
7025   tie_t = (val << 31) >> 31;
7026   insn[0] = (insn[0] & ~0x4) | (tie_t << 2);
7027   tie_t = (val << 19) >> 20;
7028   insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
7029 }
7030
7031 static unsigned
7032 Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7033 {
7034   unsigned tie_t = 0;
7035   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
7036   tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
7037   return tie_t;
7038 }
7039
7040 static void
7041 Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7042 {
7043   uint32 tie_t;
7044   tie_t = (val << 30) >> 30;
7045   insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
7046   tie_t = (val << 29) >> 31;
7047   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
7048 }
7049
7050 static unsigned
7051 Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7052 {
7053   unsigned tie_t = 0;
7054   tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
7055   tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30);
7056   return tie_t;
7057 }
7058
7059 static void
7060 Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7061 {
7062   uint32 tie_t;
7063   tie_t = (val << 30) >> 30;
7064   insn[0] = (insn[0] & ~0x6) | (tie_t << 1);
7065   tie_t = (val << 18) >> 20;
7066   insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
7067 }
7068
7069 static unsigned
7070 Field_ftsf369ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7071 {
7072   unsigned tie_t = 0;
7073   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
7074   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
7075   return tie_t;
7076 }
7077
7078 static void
7079 Field_ftsf369ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7080 {
7081   uint32 tie_t;
7082   tie_t = (val << 31) >> 31;
7083   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
7084   tie_t = (val << 30) >> 31;
7085   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
7086 }
7087
7088 static unsigned
7089 Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7090 {
7091   unsigned tie_t = 0;
7092   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
7093   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
7094   return tie_t;
7095 }
7096
7097 static void
7098 Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7099 {
7100   uint32 tie_t;
7101   tie_t = (val << 28) >> 28;
7102   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
7103   tie_t = (val << 20) >> 24;
7104   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
7105 }
7106
7107 static unsigned
7108 Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7109 {
7110   unsigned tie_t = 0;
7111   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
7112   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
7113   return tie_t;
7114 }
7115
7116 static void
7117 Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7118 {
7119   uint32 tie_t;
7120   tie_t = (val << 31) >> 31;
7121   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
7122   tie_t = (val << 23) >> 24;
7123   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
7124 }
7125
7126 static unsigned
7127 Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7128 {
7129   unsigned tie_t = 0;
7130   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
7131   tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
7132   return tie_t;
7133 }
7134
7135 static void
7136 Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7137 {
7138   uint32 tie_t;
7139   tie_t = (val << 30) >> 30;
7140   insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
7141   tie_t = (val << 22) >> 24;
7142   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
7143 }
7144
7145 static unsigned
7146 Field_ftsf357_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7147 {
7148   unsigned tie_t = 0;
7149   tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
7150   return tie_t;
7151 }
7152
7153 static void
7154 Field_ftsf357_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7155 {
7156   uint32 tie_t;
7157   tie_t = (val << 30) >> 30;
7158   insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
7159 }
7160
7161 static unsigned
7162 Field_ftsf303ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7163 {
7164   unsigned tie_t = 0;
7165   tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
7166   tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
7167   return tie_t;
7168 }
7169
7170 static void
7171 Field_ftsf303ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7172 {
7173   uint32 tie_t;
7174   tie_t = (val << 29) >> 29;
7175   insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
7176   tie_t = (val << 17) >> 20;
7177   insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
7178 }
7179
7180 static unsigned
7181 Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7182 {
7183   unsigned tie_t = 0;
7184   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
7185   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
7186   return tie_t;
7187 }
7188
7189 static void
7190 Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7191 {
7192   uint32 tie_t;
7193   tie_t = (val << 28) >> 28;
7194   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
7195   tie_t = (val << 20) >> 24;
7196   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
7197 }
7198
7199 static unsigned
7200 Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7201 {
7202   unsigned tie_t = 0;
7203   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
7204   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
7205   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
7206   return tie_t;
7207 }
7208
7209 static void
7210 Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7211 {
7212   uint32 tie_t;
7213   tie_t = (val << 28) >> 28;
7214   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
7215   tie_t = (val << 27) >> 31;
7216   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
7217   tie_t = (val << 19) >> 24;
7218   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
7219 }
7220
7221 static unsigned
7222 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
7223 {
7224   unsigned tie_t = 0;
7225   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
7226   return tie_t;
7227 }
7228
7229 static void
7230 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7231 {
7232   uint32 tie_t;
7233   tie_t = (val << 28) >> 28;
7234   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
7235 }
7236
7237 static unsigned
7238 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
7239 {
7240   unsigned tie_t = 0;
7241   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
7242   return tie_t;
7243 }
7244
7245 static void
7246 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7247 {
7248   uint32 tie_t;
7249   tie_t = (val << 31) >> 31;
7250   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
7251 }
7252
7253 static unsigned
7254 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
7255 {
7256   unsigned tie_t = 0;
7257   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
7258   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
7259   return tie_t;
7260 }
7261
7262 static void
7263 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7264 {
7265   uint32 tie_t;
7266   tie_t = (val << 28) >> 28;
7267   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
7268   tie_t = (val << 27) >> 31;
7269   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
7270 }
7271
7272 static unsigned
7273 Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7274 {
7275   unsigned tie_t = 0;
7276   tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
7277   return tie_t;
7278 }
7279
7280 static void
7281 Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7282 {
7283   uint32 tie_t;
7284   tie_t = (val << 27) >> 27;
7285   insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
7286 }
7287
7288 static unsigned
7289 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
7290 {
7291   unsigned tie_t = 0;
7292   tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
7293   return tie_t;
7294 }
7295
7296 static void
7297 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7298 {
7299   uint32 tie_t;
7300   tie_t = (val << 20) >> 20;
7301   insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
7302 }
7303
7304 static unsigned
7305 Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7306 {
7307   unsigned tie_t = 0;
7308   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7309   tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
7310   return tie_t;
7311 }
7312
7313 static void
7314 Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7315 {
7316   uint32 tie_t;
7317   tie_t = (val << 24) >> 24;
7318   insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
7319   tie_t = (val << 20) >> 28;
7320   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7321 }
7322
7323 static unsigned
7324 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
7325 {
7326   unsigned tie_t = 0;
7327   tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
7328   return tie_t;
7329 }
7330
7331 static void
7332 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7333 {
7334   uint32 tie_t;
7335   tie_t = (val << 24) >> 24;
7336   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
7337 }
7338
7339 static unsigned
7340 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
7341 {
7342   unsigned tie_t = 0;
7343   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7344   return tie_t;
7345 }
7346
7347 static void
7348 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7349 {
7350   uint32 tie_t;
7351   tie_t = (val << 28) >> 28;
7352   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7353 }
7354
7355 static unsigned
7356 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
7357 {
7358   unsigned tie_t = 0;
7359   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7360   tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
7361   return tie_t;
7362 }
7363
7364 static void
7365 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7366 {
7367   uint32 tie_t;
7368   tie_t = (val << 24) >> 24;
7369   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
7370   tie_t = (val << 20) >> 28;
7371   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7372 }
7373
7374 static unsigned
7375 Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7376 {
7377   unsigned tie_t = 0;
7378   tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20);
7379   return tie_t;
7380 }
7381
7382 static void
7383 Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7384 {
7385   uint32 tie_t;
7386   tie_t = (val << 20) >> 20;
7387   insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4);
7388 }
7389
7390 static unsigned
7391 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
7392 {
7393   unsigned tie_t = 0;
7394   tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
7395   return tie_t;
7396 }
7397
7398 static void
7399 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7400 {
7401   uint32 tie_t;
7402   tie_t = (val << 16) >> 16;
7403   insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
7404 }
7405
7406 static unsigned
7407 Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7408 {
7409   unsigned tie_t = 0;
7410   tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16);
7411   return tie_t;
7412 }
7413
7414 static void
7415 Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7416 {
7417   uint32 tie_t;
7418   tie_t = (val << 16) >> 16;
7419   insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4);
7420 }
7421
7422 static unsigned
7423 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
7424 {
7425   unsigned tie_t = 0;
7426   tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
7427   return tie_t;
7428 }
7429
7430 static void
7431 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7432 {
7433   uint32 tie_t;
7434   tie_t = (val << 14) >> 14;
7435   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
7436 }
7437
7438 static unsigned
7439 Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7440 {
7441   unsigned tie_t = 0;
7442   tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
7443   return tie_t;
7444 }
7445
7446 static void
7447 Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7448 {
7449   uint32 tie_t;
7450   tie_t = (val << 14) >> 14;
7451   insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
7452 }
7453
7454 static unsigned
7455 Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7456 {
7457   unsigned tie_t = 0;
7458   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7459   return tie_t;
7460 }
7461
7462 static void
7463 Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7464 {
7465   uint32 tie_t;
7466   tie_t = (val << 28) >> 28;
7467   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7468 }
7469
7470 static unsigned
7471 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
7472 {
7473   unsigned tie_t = 0;
7474   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7475   return tie_t;
7476 }
7477
7478 static void
7479 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7480 {
7481   uint32 tie_t;
7482   tie_t = (val << 28) >> 28;
7483   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7484 }
7485
7486 static unsigned
7487 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
7488 {
7489   unsigned tie_t = 0;
7490   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
7491   return tie_t;
7492 }
7493
7494 static void
7495 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7496 {
7497   uint32 tie_t;
7498   tie_t = (val << 31) >> 31;
7499   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
7500 }
7501
7502 static unsigned
7503 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
7504 {
7505   unsigned tie_t = 0;
7506   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
7507   return tie_t;
7508 }
7509
7510 static void
7511 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7512 {
7513   uint32 tie_t;
7514   tie_t = (val << 31) >> 31;
7515   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
7516 }
7517
7518 static unsigned
7519 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
7520 {
7521   unsigned tie_t = 0;
7522   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
7523   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7524   return tie_t;
7525 }
7526
7527 static void
7528 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7529 {
7530   uint32 tie_t;
7531   tie_t = (val << 28) >> 28;
7532   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7533   tie_t = (val << 27) >> 31;
7534   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
7535 }
7536
7537 static unsigned
7538 Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7539 {
7540   unsigned tie_t = 0;
7541   tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27);
7542   return tie_t;
7543 }
7544
7545 static void
7546 Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7547 {
7548   uint32 tie_t;
7549   tie_t = (val << 27) >> 27;
7550   insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12);
7551 }
7552
7553 static unsigned
7554 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
7555 {
7556   unsigned tie_t = 0;
7557   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
7558   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
7559   return tie_t;
7560 }
7561
7562 static void
7563 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7564 {
7565   uint32 tie_t;
7566   tie_t = (val << 28) >> 28;
7567   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
7568   tie_t = (val << 27) >> 31;
7569   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
7570 }
7571
7572 static unsigned
7573 Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7574 {
7575   unsigned tie_t = 0;
7576   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
7577   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
7578   return tie_t;
7579 }
7580
7581 static void
7582 Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7583 {
7584   uint32 tie_t;
7585   tie_t = (val << 28) >> 28;
7586   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
7587   tie_t = (val << 27) >> 31;
7588   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
7589 }
7590
7591 static unsigned
7592 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
7593 {
7594   unsigned tie_t = 0;
7595   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
7596   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7597   return tie_t;
7598 }
7599
7600 static void
7601 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7602 {
7603   uint32 tie_t;
7604   tie_t = (val << 28) >> 28;
7605   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7606   tie_t = (val << 27) >> 31;
7607   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
7608 }
7609
7610 static unsigned
7611 Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7612 {
7613   unsigned tie_t = 0;
7614   tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
7615   return tie_t;
7616 }
7617
7618 static void
7619 Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7620 {
7621   uint32 tie_t;
7622   tie_t = (val << 27) >> 27;
7623   insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
7624 }
7625
7626 static unsigned
7627 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
7628 {
7629   unsigned tie_t = 0;
7630   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
7631   return tie_t;
7632 }
7633
7634 static void
7635 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7636 {
7637   uint32 tie_t;
7638   tie_t = (val << 31) >> 31;
7639   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
7640 }
7641
7642 static unsigned
7643 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
7644 {
7645   unsigned tie_t = 0;
7646   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
7647   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7648   return tie_t;
7649 }
7650
7651 static void
7652 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7653 {
7654   uint32 tie_t;
7655   tie_t = (val << 28) >> 28;
7656   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7657   tie_t = (val << 27) >> 31;
7658   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
7659 }
7660
7661 static unsigned
7662 Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7663 {
7664   unsigned tie_t = 0;
7665   tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
7666   return tie_t;
7667 }
7668
7669 static void
7670 Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7671 {
7672   uint32 tie_t;
7673   tie_t = (val << 27) >> 27;
7674   insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
7675 }
7676
7677 static unsigned
7678 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
7679 {
7680   unsigned tie_t = 0;
7681   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7682   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7683   return tie_t;
7684 }
7685
7686 static void
7687 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7688 {
7689   uint32 tie_t;
7690   tie_t = (val << 28) >> 28;
7691   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7692   tie_t = (val << 24) >> 28;
7693   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7694 }
7695
7696 static unsigned
7697 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
7698 {
7699   unsigned tie_t = 0;
7700   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7701   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7702   return tie_t;
7703 }
7704
7705 static void
7706 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7707 {
7708   uint32 tie_t;
7709   tie_t = (val << 28) >> 28;
7710   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7711   tie_t = (val << 24) >> 28;
7712   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7713 }
7714
7715 static unsigned
7716 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
7717 {
7718   unsigned tie_t = 0;
7719   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7720   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
7721   return tie_t;
7722 }
7723
7724 static void
7725 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7726 {
7727   uint32 tie_t;
7728   tie_t = (val << 28) >> 28;
7729   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
7730   tie_t = (val << 24) >> 28;
7731   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7732 }
7733
7734 static unsigned
7735 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
7736 {
7737   unsigned tie_t = 0;
7738   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7739   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
7740   return tie_t;
7741 }
7742
7743 static void
7744 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7745 {
7746   uint32 tie_t;
7747   tie_t = (val << 28) >> 28;
7748   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
7749   tie_t = (val << 24) >> 28;
7750   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7751 }
7752
7753 static unsigned
7754 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
7755 {
7756   unsigned tie_t = 0;
7757   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7758   return tie_t;
7759 }
7760
7761 static void
7762 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7763 {
7764   uint32 tie_t;
7765   tie_t = (val << 28) >> 28;
7766   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7767 }
7768
7769 static unsigned
7770 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
7771 {
7772   unsigned tie_t = 0;
7773   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7774   return tie_t;
7775 }
7776
7777 static void
7778 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7779 {
7780   uint32 tie_t;
7781   tie_t = (val << 28) >> 28;
7782   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7783 }
7784
7785 static unsigned
7786 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
7787 {
7788   unsigned tie_t = 0;
7789   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7790   return tie_t;
7791 }
7792
7793 static void
7794 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7795 {
7796   uint32 tie_t;
7797   tie_t = (val << 28) >> 28;
7798   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7799 }
7800
7801 static unsigned
7802 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
7803 {
7804   unsigned tie_t = 0;
7805   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
7806   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
7807   return tie_t;
7808 }
7809
7810 static void
7811 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7812 {
7813   uint32 tie_t;
7814   tie_t = (val << 30) >> 30;
7815   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
7816   tie_t = (val << 28) >> 30;
7817   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
7818 }
7819
7820 static unsigned
7821 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
7822 {
7823   unsigned tie_t = 0;
7824   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
7825   return tie_t;
7826 }
7827
7828 static void
7829 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7830 {
7831   uint32 tie_t;
7832   tie_t = (val << 31) >> 31;
7833   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
7834 }
7835
7836 static unsigned
7837 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
7838 {
7839   unsigned tie_t = 0;
7840   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7841   return tie_t;
7842 }
7843
7844 static void
7845 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7846 {
7847   uint32 tie_t;
7848   tie_t = (val << 28) >> 28;
7849   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7850 }
7851
7852 static unsigned
7853 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
7854 {
7855   unsigned tie_t = 0;
7856   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7857   return tie_t;
7858 }
7859
7860 static void
7861 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7862 {
7863   uint32 tie_t;
7864   tie_t = (val << 28) >> 28;
7865   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7866 }
7867
7868 static unsigned
7869 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
7870 {
7871   unsigned tie_t = 0;
7872   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
7873   return tie_t;
7874 }
7875
7876 static void
7877 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7878 {
7879   uint32 tie_t;
7880   tie_t = (val << 30) >> 30;
7881   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
7882 }
7883
7884 static unsigned
7885 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
7886 {
7887   unsigned tie_t = 0;
7888   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
7889   return tie_t;
7890 }
7891
7892 static void
7893 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7894 {
7895   uint32 tie_t;
7896   tie_t = (val << 30) >> 30;
7897   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
7898 }
7899
7900 static unsigned
7901 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
7902 {
7903   unsigned tie_t = 0;
7904   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7905   return tie_t;
7906 }
7907
7908 static void
7909 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7910 {
7911   uint32 tie_t;
7912   tie_t = (val << 28) >> 28;
7913   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7914 }
7915
7916 static unsigned
7917 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
7918 {
7919   unsigned tie_t = 0;
7920   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7921   return tie_t;
7922 }
7923
7924 static void
7925 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7926 {
7927   uint32 tie_t;
7928   tie_t = (val << 28) >> 28;
7929   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7930 }
7931
7932 static unsigned
7933 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
7934 {
7935   unsigned tie_t = 0;
7936   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
7937   return tie_t;
7938 }
7939
7940 static void
7941 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7942 {
7943   uint32 tie_t;
7944   tie_t = (val << 29) >> 29;
7945   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
7946 }
7947
7948 static unsigned
7949 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
7950 {
7951   unsigned tie_t = 0;
7952   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
7953   return tie_t;
7954 }
7955
7956 static void
7957 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7958 {
7959   uint32 tie_t;
7960   tie_t = (val << 29) >> 29;
7961   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
7962 }
7963
7964 static unsigned
7965 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
7966 {
7967   unsigned tie_t = 0;
7968   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
7969   return tie_t;
7970 }
7971
7972 static void
7973 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7974 {
7975   uint32 tie_t;
7976   tie_t = (val << 31) >> 31;
7977   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
7978 }
7979
7980 static unsigned
7981 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
7982 {
7983   unsigned tie_t = 0;
7984   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
7985   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7986   return tie_t;
7987 }
7988
7989 static void
7990 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7991 {
7992   uint32 tie_t;
7993   tie_t = (val << 28) >> 28;
7994   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7995   tie_t = (val << 26) >> 30;
7996   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
7997 }
7998
7999 static unsigned
8000 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
8001 {
8002   unsigned tie_t = 0;
8003   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
8004   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
8005   return tie_t;
8006 }
8007
8008 static void
8009 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8010 {
8011   uint32 tie_t;
8012   tie_t = (val << 28) >> 28;
8013   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
8014   tie_t = (val << 26) >> 30;
8015   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
8016 }
8017
8018 static unsigned
8019 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
8020 {
8021   unsigned tie_t = 0;
8022   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
8023   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
8024   return tie_t;
8025 }
8026
8027 static void
8028 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8029 {
8030   uint32 tie_t;
8031   tie_t = (val << 28) >> 28;
8032   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
8033   tie_t = (val << 25) >> 29;
8034   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
8035 }
8036
8037 static unsigned
8038 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
8039 {
8040   unsigned tie_t = 0;
8041   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
8042   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
8043   return tie_t;
8044 }
8045
8046 static void
8047 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8048 {
8049   uint32 tie_t;
8050   tie_t = (val << 28) >> 28;
8051   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
8052   tie_t = (val << 25) >> 29;
8053   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
8054 }
8055
8056 static unsigned
8057 Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
8058 {
8059   unsigned tie_t = 0;
8060   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
8061   return tie_t;
8062 }
8063
8064 static void
8065 Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8066 {
8067   uint32 tie_t;
8068   tie_t = (val << 29) >> 29;
8069   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
8070 }
8071
8072 static unsigned
8073 Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
8074 {
8075   unsigned tie_t = 0;
8076   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
8077   return tie_t;
8078 }
8079
8080 static void
8081 Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8082 {
8083   uint32 tie_t;
8084   tie_t = (val << 29) >> 29;
8085   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
8086 }
8087
8088 static unsigned
8089 Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
8090 {
8091   unsigned tie_t = 0;
8092   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
8093   return tie_t;
8094 }
8095
8096 static void
8097 Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8098 {
8099   uint32 tie_t;
8100   tie_t = (val << 29) >> 29;
8101   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
8102 }
8103
8104 static unsigned
8105 Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn)
8106 {
8107   unsigned tie_t = 0;
8108   tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
8109   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
8110   return tie_t;
8111 }
8112
8113 static void
8114 Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
8115 {
8116   uint32 tie_t;
8117   tie_t = (val << 31) >> 31;
8118   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
8119   tie_t = (val << 29) >> 30;
8120   insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
8121 }
8122
8123 static unsigned
8124 Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
8125 {
8126   unsigned tie_t = 0;
8127   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
8128   return tie_t;
8129 }
8130
8131 static void
8132 Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8133 {
8134   uint32 tie_t;
8135   tie_t = (val << 29) >> 29;
8136   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
8137 }
8138
8139 static unsigned
8140 Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
8141 {
8142   unsigned tie_t = 0;
8143   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
8144   return tie_t;
8145 }
8146
8147 static void
8148 Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8149 {
8150   uint32 tie_t;
8151   tie_t = (val << 29) >> 29;
8152   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
8153 }
8154
8155 static unsigned
8156 Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
8157 {
8158   unsigned tie_t = 0;
8159   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
8160   return tie_t;
8161 }
8162
8163 static void
8164 Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8165 {
8166   uint32 tie_t;
8167   tie_t = (val << 29) >> 29;
8168   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
8169 }
8170
8171 static unsigned
8172 Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
8173 {
8174   unsigned tie_t = 0;
8175   tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
8176   return tie_t;
8177 }
8178
8179 static void
8180 Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8181 {
8182   uint32 tie_t;
8183   tie_t = (val << 29) >> 29;
8184   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
8185 }
8186
8187 static unsigned
8188 Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
8189 {
8190   unsigned tie_t = 0;
8191   tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
8192   return tie_t;
8193 }
8194
8195 static void
8196 Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8197 {
8198   uint32 tie_t;
8199   tie_t = (val << 29) >> 29;
8200   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
8201 }
8202
8203 static unsigned
8204 Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
8205 {
8206   unsigned tie_t = 0;
8207   tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
8208   return tie_t;
8209 }
8210
8211 static void
8212 Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8213 {
8214   uint32 tie_t;
8215   tie_t = (val << 29) >> 29;
8216   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
8217 }
8218
8219 static unsigned
8220 Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
8221 {
8222   unsigned tie_t = 0;
8223   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
8224   return tie_t;
8225 }
8226
8227 static void
8228 Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8229 {
8230   uint32 tie_t;
8231   tie_t = (val << 30) >> 30;
8232   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
8233 }
8234
8235 static unsigned
8236 Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
8237 {
8238   unsigned tie_t = 0;
8239   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
8240   return tie_t;
8241 }
8242
8243 static void
8244 Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8245 {
8246   uint32 tie_t;
8247   tie_t = (val << 30) >> 30;
8248   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
8249 }
8250
8251 static unsigned
8252 Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
8253 {
8254   unsigned tie_t = 0;
8255   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
8256   return tie_t;
8257 }
8258
8259 static void
8260 Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8261 {
8262   uint32 tie_t;
8263   tie_t = (val << 30) >> 30;
8264   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
8265 }
8266
8267 static unsigned
8268 Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
8269 {
8270   unsigned tie_t = 0;
8271   tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
8272   return tie_t;
8273 }
8274
8275 static void
8276 Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8277 {
8278   uint32 tie_t;
8279   tie_t = (val << 30) >> 30;
8280   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
8281 }
8282
8283 static unsigned
8284 Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
8285 {
8286   unsigned tie_t = 0;
8287   tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
8288   return tie_t;
8289 }
8290
8291 static void
8292 Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8293 {
8294   uint32 tie_t;
8295   tie_t = (val << 30) >> 30;
8296   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
8297 }
8298
8299 static unsigned
8300 Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
8301 {
8302   unsigned tie_t = 0;
8303   tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
8304   return tie_t;
8305 }
8306
8307 static void
8308 Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8309 {
8310   uint32 tie_t;
8311   tie_t = (val << 30) >> 30;
8312   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
8313 }
8314
8315 static unsigned
8316 Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
8317 {
8318   unsigned tie_t = 0;
8319   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
8320   return tie_t;
8321 }
8322
8323 static void
8324 Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
8325 {
8326   uint32 tie_t;
8327   tie_t = (val << 30) >> 30;
8328   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
8329 }
8330
8331 static unsigned
8332 Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
8333 {
8334   unsigned tie_t = 0;
8335   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
8336   return tie_t;
8337 }
8338
8339 static void
8340 Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8341 {
8342   uint32 tie_t;
8343   tie_t = (val << 30) >> 30;
8344   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
8345 }
8346
8347 static unsigned
8348 Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
8349 {
8350   unsigned tie_t = 0;
8351   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
8352   return tie_t;
8353 }
8354
8355 static void
8356 Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8357 {
8358   uint32 tie_t;
8359   tie_t = (val << 30) >> 30;
8360   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
8361 }
8362
8363 static unsigned
8364 Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
8365 {
8366   unsigned tie_t = 0;
8367   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
8368   return tie_t;
8369 }
8370
8371 static void
8372 Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8373 {
8374   uint32 tie_t;
8375   tie_t = (val << 30) >> 30;
8376   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
8377 }
8378
8379 static unsigned
8380 Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
8381 {
8382   unsigned tie_t = 0;
8383   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
8384   return tie_t;
8385 }
8386
8387 static void
8388 Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8389 {
8390   uint32 tie_t;
8391   tie_t = (val << 31) >> 31;
8392   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
8393 }
8394
8395 static unsigned
8396 Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
8397 {
8398   unsigned tie_t = 0;
8399   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
8400   return tie_t;
8401 }
8402
8403 static void
8404 Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8405 {
8406   uint32 tie_t;
8407   tie_t = (val << 31) >> 31;
8408   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
8409 }
8410
8411 static unsigned
8412 Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
8413 {
8414   unsigned tie_t = 0;
8415   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
8416   return tie_t;
8417 }
8418
8419 static void
8420 Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8421 {
8422   uint32 tie_t;
8423   tie_t = (val << 31) >> 31;
8424   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
8425 }
8426
8427 static unsigned
8428 Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
8429 {
8430   unsigned tie_t = 0;
8431   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
8432   return tie_t;
8433 }
8434
8435 static void
8436 Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8437 {
8438   uint32 tie_t;
8439   tie_t = (val << 31) >> 31;
8440   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
8441 }
8442
8443 static unsigned
8444 Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
8445 {
8446   unsigned tie_t = 0;
8447   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
8448   return tie_t;
8449 }
8450
8451 static void
8452 Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8453 {
8454   uint32 tie_t;
8455   tie_t = (val << 31) >> 31;
8456   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
8457 }
8458
8459 static unsigned
8460 Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
8461 {
8462   unsigned tie_t = 0;
8463   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
8464   return tie_t;
8465 }
8466
8467 static void
8468 Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8469 {
8470   uint32 tie_t;
8471   tie_t = (val << 31) >> 31;
8472   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
8473 }
8474
8475 static unsigned
8476 Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
8477 {
8478   unsigned tie_t = 0;
8479   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
8480   return tie_t;
8481 }
8482
8483 static void
8484 Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8485 {
8486   uint32 tie_t;
8487   tie_t = (val << 31) >> 31;
8488   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
8489 }
8490
8491 static unsigned
8492 Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
8493 {
8494   unsigned tie_t = 0;
8495   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
8496   return tie_t;
8497 }
8498
8499 static void
8500 Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8501 {
8502   uint32 tie_t;
8503   tie_t = (val << 31) >> 31;
8504   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
8505 }
8506
8507 static unsigned
8508 Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
8509 {
8510   unsigned tie_t = 0;
8511   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
8512   return tie_t;
8513 }
8514
8515 static void
8516 Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8517 {
8518   uint32 tie_t;
8519   tie_t = (val << 31) >> 31;
8520   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
8521 }
8522
8523 static unsigned
8524 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
8525 {
8526   unsigned tie_t = 0;
8527   tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
8528   return tie_t;
8529 }
8530
8531 static void
8532 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8533 {
8534   uint32 tie_t;
8535   tie_t = (val << 17) >> 17;
8536   insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
8537 }
8538
8539 static unsigned
8540 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
8541 {
8542   unsigned tie_t = 0;
8543   tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
8544   return tie_t;
8545 }
8546
8547 static void
8548 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8549 {
8550   uint32 tie_t;
8551   tie_t = (val << 14) >> 14;
8552   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
8553 }
8554
8555 static unsigned
8556 Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn)
8557 {
8558   unsigned tie_t = 0;
8559   tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26);
8560   return tie_t;
8561 }
8562
8563 static void
8564 Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8565 {
8566   uint32 tie_t;
8567   tie_t = (val << 26) >> 26;
8568   insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4);
8569 }
8570
8571 static unsigned
8572 Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
8573 {
8574   unsigned tie_t = 0;
8575   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
8576   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
8577   return tie_t;
8578 }
8579
8580 static void
8581 Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
8582 {
8583   uint32 tie_t;
8584   tie_t = (val << 28) >> 28;
8585   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
8586   tie_t = (val << 26) >> 30;
8587   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
8588 }
8589
8590 static unsigned
8591 Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn)
8592 {
8593   unsigned tie_t = 0;
8594   tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
8595   return tie_t;
8596 }
8597
8598 static void
8599 Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8600 {
8601   uint32 tie_t;
8602   tie_t = (val << 29) >> 29;
8603   insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
8604 }
8605
8606 static unsigned
8607 Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn)
8608 {
8609   unsigned tie_t = 0;
8610   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
8611   return tie_t;
8612 }
8613
8614 static void
8615 Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
8616 {
8617   uint32 tie_t;
8618   tie_t = (val << 30) >> 30;
8619   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
8620 }
8621
8622 static unsigned
8623 Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn)
8624 {
8625   unsigned tie_t = 0;
8626   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
8627   return tie_t;
8628 }
8629
8630 static void
8631 Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8632 {
8633   uint32 tie_t;
8634   tie_t = (val << 29) >> 29;
8635   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
8636 }
8637
8638 static unsigned
8639 Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn)
8640 {
8641   unsigned tie_t = 0;
8642   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
8643   return tie_t;
8644 }
8645
8646 static void
8647 Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8648 {
8649   uint32 tie_t;
8650   tie_t = (val << 28) >> 28;
8651   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
8652 }
8653
8654 static unsigned
8655 Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn)
8656 {
8657   unsigned tie_t = 0;
8658   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
8659   return tie_t;
8660 }
8661
8662 static void
8663 Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8664 {
8665   uint32 tie_t;
8666   tie_t = (val << 28) >> 28;
8667   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
8668 }
8669
8670 static unsigned
8671 Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn)
8672 {
8673   unsigned tie_t = 0;
8674   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
8675   return tie_t;
8676 }
8677
8678 static void
8679 Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8680 {
8681   uint32 tie_t;
8682   tie_t = (val << 29) >> 29;
8683   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
8684 }
8685
8686 static unsigned
8687 Field_ftsf13_Slot_inst_get (const xtensa_insnbuf insn)
8688 {
8689   unsigned tie_t = 0;
8690   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
8691   return tie_t;
8692 }
8693
8694 static void
8695 Field_ftsf13_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8696 {
8697   uint32 tie_t;
8698   tie_t = (val << 30) >> 30;
8699   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
8700 }
8701
8702 static unsigned
8703 Field_ftsf14_Slot_ae_slot1_get (const xtensa_insnbuf insn)
8704 {
8705   unsigned tie_t = 0;
8706   tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
8707   tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
8708   return tie_t;
8709 }
8710
8711 static void
8712 Field_ftsf14_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
8713 {
8714   uint32 tie_t;
8715   tie_t = (val << 31) >> 31;
8716   insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
8717   tie_t = (val << 27) >> 28;
8718   insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
8719 }
8720
8721 static void
8722 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
8723                     uint32 val ATTRIBUTE_UNUSED)
8724 {
8725   /* Do nothing.  */
8726 }
8727
8728 static unsigned
8729 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8730 {
8731   return 0;
8732 }
8733
8734 static unsigned
8735 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8736 {
8737   return 4;
8738 }
8739
8740 static unsigned
8741 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8742 {
8743   return 8;
8744 }
8745
8746 static unsigned
8747 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8748 {
8749   return 12;
8750 }
8751
8752 static unsigned
8753 Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8754 {
8755   return 0;
8756 }
8757
8758 static unsigned
8759 Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8760 {
8761   return 0;
8762 }
8763
8764 static unsigned
8765 Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8766 {
8767   return 0;
8768 }
8769
8770 static unsigned
8771 Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8772 {
8773   return 0;
8774 }
8775
8776 enum xtensa_field_id {
8777   FIELD_t,
8778   FIELD_bbi4,
8779   FIELD_bbi,
8780   FIELD_imm12,
8781   FIELD_imm8,
8782   FIELD_s,
8783   FIELD_imm12b,
8784   FIELD_imm16,
8785   FIELD_m,
8786   FIELD_n,
8787   FIELD_offset,
8788   FIELD_op0,
8789   FIELD_op1,
8790   FIELD_op2,
8791   FIELD_r,
8792   FIELD_sa4,
8793   FIELD_sae4,
8794   FIELD_sae,
8795   FIELD_sal,
8796   FIELD_sargt,
8797   FIELD_sas4,
8798   FIELD_sas,
8799   FIELD_sr,
8800   FIELD_st,
8801   FIELD_thi3,
8802   FIELD_imm4,
8803   FIELD_mn,
8804   FIELD_i,
8805   FIELD_imm6lo,
8806   FIELD_imm6hi,
8807   FIELD_imm7lo,
8808   FIELD_imm7hi,
8809   FIELD_z,
8810   FIELD_imm6,
8811   FIELD_imm7,
8812   FIELD_t2,
8813   FIELD_s2,
8814   FIELD_r2,
8815   FIELD_t4,
8816   FIELD_s4,
8817   FIELD_r4,
8818   FIELD_t8,
8819   FIELD_s8,
8820   FIELD_r8,
8821   FIELD_xt_wbr15_imm,
8822   FIELD_xt_wbr18_imm,
8823   FIELD_ae_r3,
8824   FIELD_ae_s_non_samt,
8825   FIELD_ae_s3,
8826   FIELD_ae_r32,
8827   FIELD_ae_samt_s_t,
8828   FIELD_ae_r20,
8829   FIELD_ae_r10,
8830   FIELD_ae_s20,
8831   FIELD_ae_fld_ohba,
8832   FIELD_ae_fld_ohba2,
8833   FIELD_op0_s3,
8834   FIELD_ftsf12,
8835   FIELD_ftsf13,
8836   FIELD_ftsf14,
8837   FIELD_ftsf21ae_slot1,
8838   FIELD_ftsf22ae_slot1,
8839   FIELD_ftsf23ae_slot1,
8840   FIELD_ftsf24ae_slot1,
8841   FIELD_ftsf25ae_slot1,
8842   FIELD_ftsf26ae_slot1,
8843   FIELD_ftsf27ae_slot1,
8844   FIELD_ftsf28ae_slot1,
8845   FIELD_ftsf29ae_slot1,
8846   FIELD_ftsf30ae_slot1,
8847   FIELD_ftsf31ae_slot1,
8848   FIELD_ftsf32ae_slot1,
8849   FIELD_ftsf33ae_slot1,
8850   FIELD_ftsf34ae_slot1,
8851   FIELD_ftsf35ae_slot1,
8852   FIELD_ftsf36ae_slot1,
8853   FIELD_ftsf37ae_slot1,
8854   FIELD_ftsf38ae_slot1,
8855   FIELD_ftsf39ae_slot1,
8856   FIELD_ftsf40ae_slot1,
8857   FIELD_ftsf41ae_slot1,
8858   FIELD_ftsf42ae_slot1,
8859   FIELD_ftsf43ae_slot1,
8860   FIELD_ftsf44ae_slot1,
8861   FIELD_ftsf45ae_slot1,
8862   FIELD_ftsf46ae_slot1,
8863   FIELD_ftsf47ae_slot1,
8864   FIELD_ftsf48ae_slot1,
8865   FIELD_ftsf49ae_slot1,
8866   FIELD_ftsf50ae_slot1,
8867   FIELD_ftsf51ae_slot1,
8868   FIELD_ftsf52ae_slot1,
8869   FIELD_ftsf53ae_slot1,
8870   FIELD_ftsf54ae_slot1,
8871   FIELD_ftsf55ae_slot1,
8872   FIELD_ftsf56ae_slot1,
8873   FIELD_ftsf57ae_slot1,
8874   FIELD_ftsf58ae_slot1,
8875   FIELD_ftsf59ae_slot1,
8876   FIELD_ftsf60ae_slot1,
8877   FIELD_ftsf61ae_slot1,
8878   FIELD_ftsf63ae_slot1,
8879   FIELD_ftsf64ae_slot1,
8880   FIELD_ftsf66ae_slot1,
8881   FIELD_ftsf67ae_slot1,
8882   FIELD_ftsf69ae_slot1,
8883   FIELD_ftsf71ae_slot1,
8884   FIELD_ftsf72ae_slot1,
8885   FIELD_ftsf73ae_slot1,
8886   FIELD_ftsf75ae_slot1,
8887   FIELD_ftsf76ae_slot1,
8888   FIELD_ftsf77ae_slot1,
8889   FIELD_ftsf78ae_slot1,
8890   FIELD_ftsf79ae_slot1,
8891   FIELD_ftsf80ae_slot1,
8892   FIELD_ftsf81ae_slot1,
8893   FIELD_ftsf82ae_slot1,
8894   FIELD_ftsf84ae_slot1,
8895   FIELD_ftsf86ae_slot1,
8896   FIELD_ftsf87ae_slot1,
8897   FIELD_ftsf88ae_slot1,
8898   FIELD_ftsf89ae_slot1,
8899   FIELD_ftsf90ae_slot1,
8900   FIELD_ftsf91ae_slot1,
8901   FIELD_ftsf92ae_slot1,
8902   FIELD_ftsf94ae_slot1,
8903   FIELD_ftsf96ae_slot1,
8904   FIELD_ftsf97ae_slot1,
8905   FIELD_ftsf98ae_slot1,
8906   FIELD_ftsf99ae_slot1,
8907   FIELD_ftsf100ae_slot1,
8908   FIELD_ftsf101ae_slot1,
8909   FIELD_ftsf103ae_slot1,
8910   FIELD_ftsf104ae_slot1,
8911   FIELD_ftsf105ae_slot1,
8912   FIELD_ftsf106ae_slot1,
8913   FIELD_ftsf107ae_slot1,
8914   FIELD_ftsf108ae_slot1,
8915   FIELD_ftsf109ae_slot1,
8916   FIELD_ftsf110ae_slot1,
8917   FIELD_ftsf111ae_slot1,
8918   FIELD_ftsf112ae_slot1,
8919   FIELD_ftsf113ae_slot1,
8920   FIELD_ftsf114ae_slot1,
8921   FIELD_ftsf115ae_slot1,
8922   FIELD_ftsf116ae_slot1,
8923   FIELD_ftsf118ae_slot1,
8924   FIELD_ftsf119ae_slot1,
8925   FIELD_ftsf120ae_slot1,
8926   FIELD_ftsf122ae_slot1,
8927   FIELD_ftsf124ae_slot1,
8928   FIELD_ftsf125ae_slot1,
8929   FIELD_ftsf126ae_slot1,
8930   FIELD_ftsf127ae_slot1,
8931   FIELD_ftsf128ae_slot1,
8932   FIELD_ftsf129ae_slot1,
8933   FIELD_ftsf130ae_slot1,
8934   FIELD_ftsf131ae_slot1,
8935   FIELD_ftsf132ae_slot1,
8936   FIELD_ftsf133ae_slot1,
8937   FIELD_ftsf134ae_slot1,
8938   FIELD_ftsf135ae_slot1,
8939   FIELD_ftsf136ae_slot1,
8940   FIELD_ftsf137ae_slot1,
8941   FIELD_ftsf138ae_slot1,
8942   FIELD_ftsf139ae_slot1,
8943   FIELD_ftsf140ae_slot1,
8944   FIELD_ftsf141ae_slot1,
8945   FIELD_ftsf142ae_slot1,
8946   FIELD_ftsf143ae_slot1,
8947   FIELD_ftsf144ae_slot1,
8948   FIELD_ftsf145ae_slot1,
8949   FIELD_ftsf146ae_slot1,
8950   FIELD_ftsf147ae_slot1,
8951   FIELD_ftsf148ae_slot1,
8952   FIELD_ftsf149ae_slot1,
8953   FIELD_ftsf150ae_slot1,
8954   FIELD_ftsf151ae_slot1,
8955   FIELD_ftsf152ae_slot1,
8956   FIELD_ftsf153ae_slot1,
8957   FIELD_ftsf154ae_slot1,
8958   FIELD_ftsf155ae_slot1,
8959   FIELD_ftsf156ae_slot1,
8960   FIELD_ftsf157ae_slot1,
8961   FIELD_ftsf158ae_slot1,
8962   FIELD_ftsf159ae_slot1,
8963   FIELD_ftsf160ae_slot1,
8964   FIELD_ftsf161ae_slot1,
8965   FIELD_ftsf162ae_slot1,
8966   FIELD_ftsf163ae_slot1,
8967   FIELD_ftsf164ae_slot1,
8968   FIELD_ftsf165ae_slot1,
8969   FIELD_ftsf166ae_slot1,
8970   FIELD_ftsf167ae_slot1,
8971   FIELD_ftsf168ae_slot1,
8972   FIELD_ftsf169ae_slot1,
8973   FIELD_ftsf170ae_slot1,
8974   FIELD_ftsf171ae_slot1,
8975   FIELD_ftsf172ae_slot1,
8976   FIELD_ftsf173ae_slot1,
8977   FIELD_ftsf174ae_slot1,
8978   FIELD_ftsf175ae_slot1,
8979   FIELD_ftsf176ae_slot1,
8980   FIELD_ftsf177ae_slot1,
8981   FIELD_ftsf178ae_slot1,
8982   FIELD_ftsf179ae_slot1,
8983   FIELD_ftsf180ae_slot1,
8984   FIELD_ftsf181ae_slot1,
8985   FIELD_ftsf182ae_slot1,
8986   FIELD_ftsf183ae_slot1,
8987   FIELD_ftsf184ae_slot1,
8988   FIELD_ftsf185ae_slot1,
8989   FIELD_ftsf186ae_slot1,
8990   FIELD_ftsf187ae_slot1,
8991   FIELD_ftsf188ae_slot1,
8992   FIELD_ftsf189ae_slot1,
8993   FIELD_ftsf190ae_slot1,
8994   FIELD_ftsf191ae_slot1,
8995   FIELD_ftsf192ae_slot1,
8996   FIELD_ftsf193ae_slot1,
8997   FIELD_ftsf194ae_slot1,
8998   FIELD_ftsf195ae_slot1,
8999   FIELD_ftsf196ae_slot1,
9000   FIELD_ftsf197ae_slot1,
9001   FIELD_ftsf198ae_slot1,
9002   FIELD_ftsf199ae_slot1,
9003   FIELD_ftsf200ae_slot1,
9004   FIELD_ftsf201ae_slot1,
9005   FIELD_ftsf202ae_slot1,
9006   FIELD_ftsf203ae_slot1,
9007   FIELD_ftsf204ae_slot1,
9008   FIELD_ftsf205ae_slot1,
9009   FIELD_ftsf206ae_slot1,
9010   FIELD_ftsf207ae_slot1,
9011   FIELD_ftsf208,
9012   FIELD_ftsf209ae_slot1,
9013   FIELD_ftsf210ae_slot1,
9014   FIELD_ftsf211ae_slot1,
9015   FIELD_ftsf330ae_slot1,
9016   FIELD_ftsf332ae_slot1,
9017   FIELD_ftsf334ae_slot1,
9018   FIELD_ftsf336ae_slot1,
9019   FIELD_ftsf337ae_slot1,
9020   FIELD_ftsf338,
9021   FIELD_ftsf339ae_slot1,
9022   FIELD_ftsf340,
9023   FIELD_ftsf341ae_slot1,
9024   FIELD_ftsf342ae_slot1,
9025   FIELD_ftsf343ae_slot1,
9026   FIELD_ftsf344ae_slot1,
9027   FIELD_ftsf346ae_slot1,
9028   FIELD_ftsf347,
9029   FIELD_ftsf348ae_slot1,
9030   FIELD_ftsf349ae_slot1,
9031   FIELD_ftsf350ae_slot1,
9032   FIELD_op0_s4,
9033   FIELD_ftsf212ae_slot0,
9034   FIELD_ftsf213ae_slot0,
9035   FIELD_ftsf214ae_slot0,
9036   FIELD_ftsf215ae_slot0,
9037   FIELD_ftsf216ae_slot0,
9038   FIELD_ftsf217,
9039   FIELD_ftsf218ae_slot0,
9040   FIELD_ftsf219ae_slot0,
9041   FIELD_ftsf220ae_slot0,
9042   FIELD_ftsf221ae_slot0,
9043   FIELD_ftsf222ae_slot0,
9044   FIELD_ftsf223ae_slot0,
9045   FIELD_ftsf224ae_slot0,
9046   FIELD_ftsf225ae_slot0,
9047   FIELD_ftsf226ae_slot0,
9048   FIELD_ftsf227ae_slot0,
9049   FIELD_ftsf228ae_slot0,
9050   FIELD_ftsf229ae_slot0,
9051   FIELD_ftsf230ae_slot0,
9052   FIELD_ftsf231ae_slot0,
9053   FIELD_ftsf232ae_slot0,
9054   FIELD_ftsf233ae_slot0,
9055   FIELD_ftsf234ae_slot0,
9056   FIELD_ftsf235ae_slot0,
9057   FIELD_ftsf236ae_slot0,
9058   FIELD_ftsf237ae_slot0,
9059   FIELD_ftsf238ae_slot0,
9060   FIELD_ftsf239ae_slot0,
9061   FIELD_ftsf240ae_slot0,
9062   FIELD_ftsf241ae_slot0,
9063   FIELD_ftsf242ae_slot0,
9064   FIELD_ftsf243ae_slot0,
9065   FIELD_ftsf244ae_slot0,
9066   FIELD_ftsf245ae_slot0,
9067   FIELD_ftsf246ae_slot0,
9068   FIELD_ftsf247ae_slot0,
9069   FIELD_ftsf248ae_slot0,
9070   FIELD_ftsf249ae_slot0,
9071   FIELD_ftsf250ae_slot0,
9072   FIELD_ftsf251ae_slot0,
9073   FIELD_ftsf252ae_slot0,
9074   FIELD_ftsf253ae_slot0,
9075   FIELD_ftsf254ae_slot0,
9076   FIELD_ftsf255ae_slot0,
9077   FIELD_ftsf256ae_slot0,
9078   FIELD_ftsf257ae_slot0,
9079   FIELD_ftsf258ae_slot0,
9080   FIELD_ftsf259ae_slot0,
9081   FIELD_ftsf260ae_slot0,
9082   FIELD_ftsf261ae_slot0,
9083   FIELD_ftsf262ae_slot0,
9084   FIELD_ftsf263ae_slot0,
9085   FIELD_ftsf264ae_slot0,
9086   FIELD_ftsf265ae_slot0,
9087   FIELD_ftsf266ae_slot0,
9088   FIELD_ftsf267ae_slot0,
9089   FIELD_ftsf268ae_slot0,
9090   FIELD_ftsf269ae_slot0,
9091   FIELD_ftsf270ae_slot0,
9092   FIELD_ftsf271ae_slot0,
9093   FIELD_ftsf272ae_slot0,
9094   FIELD_ftsf273ae_slot0,
9095   FIELD_ftsf274ae_slot0,
9096   FIELD_ftsf275ae_slot0,
9097   FIELD_ftsf276ae_slot0,
9098   FIELD_ftsf277ae_slot0,
9099   FIELD_ftsf278ae_slot0,
9100   FIELD_ftsf279ae_slot0,
9101   FIELD_ftsf281ae_slot0,
9102   FIELD_ftsf282ae_slot0,
9103   FIELD_ftsf283ae_slot0,
9104   FIELD_ftsf284ae_slot0,
9105   FIELD_ftsf286ae_slot0,
9106   FIELD_ftsf288ae_slot0,
9107   FIELD_ftsf290ae_slot0,
9108   FIELD_ftsf292ae_slot0,
9109   FIELD_ftsf293,
9110   FIELD_ftsf294ae_slot0,
9111   FIELD_ftsf295ae_slot0,
9112   FIELD_ftsf296ae_slot0,
9113   FIELD_ftsf297ae_slot0,
9114   FIELD_ftsf298ae_slot0,
9115   FIELD_ftsf299ae_slot0,
9116   FIELD_ftsf300ae_slot0,
9117   FIELD_ftsf301ae_slot0,
9118   FIELD_ftsf302ae_slot0,
9119   FIELD_ftsf303ae_slot0,
9120   FIELD_ftsf304ae_slot0,
9121   FIELD_ftsf306ae_slot0,
9122   FIELD_ftsf308ae_slot0,
9123   FIELD_ftsf309ae_slot0,
9124   FIELD_ftsf310ae_slot0,
9125   FIELD_ftsf311ae_slot0,
9126   FIELD_ftsf312ae_slot0,
9127   FIELD_ftsf313ae_slot0,
9128   FIELD_ftsf314ae_slot0,
9129   FIELD_ftsf315ae_slot0,
9130   FIELD_ftsf316ae_slot0,
9131   FIELD_ftsf317ae_slot0,
9132   FIELD_ftsf318ae_slot0,
9133   FIELD_ftsf319,
9134   FIELD_ftsf320ae_slot0,
9135   FIELD_ftsf321,
9136   FIELD_ftsf322ae_slot0,
9137   FIELD_ftsf323ae_slot0,
9138   FIELD_ftsf324ae_slot0,
9139   FIELD_ftsf325ae_slot0,
9140   FIELD_ftsf326ae_slot0,
9141   FIELD_ftsf328ae_slot0,
9142   FIELD_ftsf329ae_slot0,
9143   FIELD_ftsf352ae_slot0,
9144   FIELD_ftsf353,
9145   FIELD_ftsf354ae_slot0,
9146   FIELD_ftsf356ae_slot0,
9147   FIELD_ftsf357,
9148   FIELD_ftsf358ae_slot0,
9149   FIELD_ftsf359ae_slot0,
9150   FIELD_ftsf360ae_slot0,
9151   FIELD_ftsf361ae_slot0,
9152   FIELD_ftsf362ae_slot0,
9153   FIELD_ftsf364ae_slot0,
9154   FIELD_ftsf365ae_slot0,
9155   FIELD_ftsf366ae_slot0,
9156   FIELD_ftsf368ae_slot0,
9157   FIELD_ftsf369ae_slot0,
9158   FIELD__ar0,
9159   FIELD__ar4,
9160   FIELD__ar8,
9161   FIELD__ar12,
9162   FIELD__bt16,
9163   FIELD__bs16,
9164   FIELD__br16,
9165   FIELD__brall
9166 };
9167
9168 \f
9169 /* Functional units.  */
9170
9171 static xtensa_funcUnit_internal funcUnits[] = {
9172   { "ae_add32", 1 },
9173   { "ae_shift32x4", 1 },
9174   { "ae_shift32x5", 1 },
9175   { "ae_subshift", 1 }
9176 };
9177
9178 enum xtensa_funcUnit_id {
9179   FUNCUNIT_ae_add32,
9180   FUNCUNIT_ae_shift32x4,
9181   FUNCUNIT_ae_shift32x5,
9182   FUNCUNIT_ae_subshift
9183 };
9184
9185 \f
9186 /* Register files.  */
9187
9188 enum xtensa_regfile_id {
9189   REGFILE_AR,
9190   REGFILE_BR,
9191   REGFILE_AE_PR,
9192   REGFILE_AE_QR,
9193   REGFILE_BR2,
9194   REGFILE_BR4,
9195   REGFILE_BR8,
9196   REGFILE_BR16
9197 };
9198
9199 static xtensa_regfile_internal regfiles[] = {
9200   { "AR", "a", REGFILE_AR, 32, 32 },
9201   { "BR", "b", REGFILE_BR, 1, 16 },
9202   { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 },
9203   { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 },
9204   { "BR2", "b", REGFILE_BR, 2, 8 },
9205   { "BR4", "b", REGFILE_BR, 4, 4 },
9206   { "BR8", "b", REGFILE_BR, 8, 2 },
9207   { "BR16", "b", REGFILE_BR, 16, 1 }
9208 };
9209
9210 \f
9211 /* Interfaces.  */
9212
9213 static xtensa_interface_internal interfaces[] = {
9214   { "RMPINT_Out", 12, 0, 0, 'o' },
9215   { "RMPINT_In", 32, 0, 1, 'i' }
9216 };
9217
9218 enum xtensa_interface_id {
9219   INTERFACE_RMPINT_Out,
9220   INTERFACE_RMPINT_In
9221 };
9222
9223
9224 /* Constant tables.  */
9225
9226 /* constant table ai4c */
9227 static const unsigned CONST_TBL_ai4c_0[] = {
9228   0xffffffff,
9229   0x1,
9230   0x2,
9231   0x3,
9232   0x4,
9233   0x5,
9234   0x6,
9235   0x7,
9236   0x8,
9237   0x9,
9238   0xa,
9239   0xb,
9240   0xc,
9241   0xd,
9242   0xe,
9243   0xf,
9244   0
9245 };
9246
9247 /* constant table b4c */
9248 static const unsigned CONST_TBL_b4c_0[] = {
9249   0xffffffff,
9250   0x1,
9251   0x2,
9252   0x3,
9253   0x4,
9254   0x5,
9255   0x6,
9256   0x7,
9257   0x8,
9258   0xa,
9259   0xc,
9260   0x10,
9261   0x20,
9262   0x40,
9263   0x80,
9264   0x100,
9265   0
9266 };
9267
9268 /* constant table b4cu */
9269 static const unsigned CONST_TBL_b4cu_0[] = {
9270   0x8000,
9271   0x10000,
9272   0x2,
9273   0x3,
9274   0x4,
9275   0x5,
9276   0x6,
9277   0x7,
9278   0x8,
9279   0xa,
9280   0xc,
9281   0x10,
9282   0x20,
9283   0x40,
9284   0x80,
9285   0x100,
9286   0
9287 };
9288
9289 \f
9290 /* Instruction operands.  */
9291
9292 static int
9293 OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
9294 {
9295   unsigned soffsetx4_out_0;
9296   unsigned soffsetx4_in_0;
9297   soffsetx4_in_0 = *valp & 0x3ffff;
9298   soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
9299   *valp = soffsetx4_out_0;
9300   return 0;
9301 }
9302
9303 static int
9304 OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
9305 {
9306   unsigned soffsetx4_in_0;
9307   unsigned soffsetx4_out_0;
9308   soffsetx4_out_0 = *valp;
9309   soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
9310   *valp = soffsetx4_in_0;
9311   return 0;
9312 }
9313
9314 static int
9315 OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
9316 {
9317   unsigned uimm12x8_out_0;
9318   unsigned uimm12x8_in_0;
9319   uimm12x8_in_0 = *valp & 0xfff;
9320   uimm12x8_out_0 = uimm12x8_in_0 << 3;
9321   *valp = uimm12x8_out_0;
9322   return 0;
9323 }
9324
9325 static int
9326 OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
9327 {
9328   unsigned uimm12x8_in_0;
9329   unsigned uimm12x8_out_0;
9330   uimm12x8_out_0 = *valp;
9331   uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
9332   *valp = uimm12x8_in_0;
9333   return 0;
9334 }
9335
9336 static int
9337 OperandSem_opnd_sem_simm4_decode (uint32 *valp)
9338 {
9339   unsigned simm4_out_0;
9340   unsigned simm4_in_0;
9341   simm4_in_0 = *valp & 0xf;
9342   simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
9343   *valp = simm4_out_0;
9344   return 0;
9345 }
9346
9347 static int
9348 OperandSem_opnd_sem_simm4_encode (uint32 *valp)
9349 {
9350   unsigned simm4_in_0;
9351   unsigned simm4_out_0;
9352   simm4_out_0 = *valp;
9353   simm4_in_0 = (simm4_out_0 & 0xf);
9354   *valp = simm4_in_0;
9355   return 0;
9356 }
9357
9358 static int
9359 OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
9360 {
9361   return 0;
9362 }
9363
9364 static int
9365 OperandSem_opnd_sem_AR_encode (uint32 *valp)
9366 {
9367   int error;
9368   error = (*valp >= 32);
9369   return error;
9370 }
9371
9372 static int
9373 OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
9374 {
9375   return 0;
9376 }
9377
9378 static int
9379 OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
9380 {
9381   int error;
9382   error = (*valp >= 32);
9383   return error;
9384 }
9385
9386 static int
9387 OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
9388 {
9389   return 0;
9390 }
9391
9392 static int
9393 OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
9394 {
9395   int error;
9396   error = (*valp >= 32);
9397   return error;
9398 }
9399
9400 static int
9401 OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
9402 {
9403   return 0;
9404 }
9405
9406 static int
9407 OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
9408 {
9409   int error;
9410   error = (*valp >= 32);
9411   return error;
9412 }
9413
9414 static int
9415 OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
9416 {
9417   return 0;
9418 }
9419
9420 static int
9421 OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
9422 {
9423   int error;
9424   error = (*valp >= 32);
9425   return error;
9426 }
9427
9428 static int
9429 OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
9430 {
9431   return 0;
9432 }
9433
9434 static int
9435 OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
9436 {
9437   int error;
9438   error = (*valp >= 32);
9439   return error;
9440 }
9441
9442 static int
9443 OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
9444 {
9445   unsigned immrx4_out_0;
9446   unsigned immrx4_in_0;
9447   immrx4_in_0 = *valp & 0xf;
9448   immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
9449   *valp = immrx4_out_0;
9450   return 0;
9451 }
9452
9453 static int
9454 OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
9455 {
9456   unsigned immrx4_in_0;
9457   unsigned immrx4_out_0;
9458   immrx4_out_0 = *valp;
9459   immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
9460   *valp = immrx4_in_0;
9461   return 0;
9462 }
9463
9464 static int
9465 OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
9466 {
9467   unsigned lsi4x4_out_0;
9468   unsigned lsi4x4_in_0;
9469   lsi4x4_in_0 = *valp & 0xf;
9470   lsi4x4_out_0 = lsi4x4_in_0 << 2;
9471   *valp = lsi4x4_out_0;
9472   return 0;
9473 }
9474
9475 static int
9476 OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
9477 {
9478   unsigned lsi4x4_in_0;
9479   unsigned lsi4x4_out_0;
9480   lsi4x4_out_0 = *valp;
9481   lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
9482   *valp = lsi4x4_in_0;
9483   return 0;
9484 }
9485
9486 static int
9487 OperandSem_opnd_sem_simm7_decode (uint32 *valp)
9488 {
9489   unsigned simm7_out_0;
9490   unsigned simm7_in_0;
9491   simm7_in_0 = *valp & 0x7f;
9492   simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
9493   *valp = simm7_out_0;
9494   return 0;
9495 }
9496
9497 static int
9498 OperandSem_opnd_sem_simm7_encode (uint32 *valp)
9499 {
9500   unsigned simm7_in_0;
9501   unsigned simm7_out_0;
9502   simm7_out_0 = *valp;
9503   simm7_in_0 = (simm7_out_0 & 0x7f);
9504   *valp = simm7_in_0;
9505   return 0;
9506 }
9507
9508 static int
9509 OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
9510 {
9511   unsigned uimm6_out_0;
9512   unsigned uimm6_in_0;
9513   uimm6_in_0 = *valp & 0x3f;
9514   uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
9515   *valp = uimm6_out_0;
9516   return 0;
9517 }
9518
9519 static int
9520 OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
9521 {
9522   unsigned uimm6_in_0;
9523   unsigned uimm6_out_0;
9524   uimm6_out_0 = *valp;
9525   uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
9526   *valp = uimm6_in_0;
9527   return 0;
9528 }
9529
9530 static int
9531 OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
9532 {
9533   unsigned ai4const_out_0;
9534   unsigned ai4const_in_0;
9535   ai4const_in_0 = *valp & 0xf;
9536   ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
9537   *valp = ai4const_out_0;
9538   return 0;
9539 }
9540
9541 static int
9542 OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
9543 {
9544   unsigned ai4const_in_0;
9545   unsigned ai4const_out_0;
9546   ai4const_out_0 = *valp;
9547   switch (ai4const_out_0)
9548     {
9549     case 0xffffffff: ai4const_in_0 = 0; break;
9550     case 0x1: ai4const_in_0 = 0x1; break;
9551     case 0x2: ai4const_in_0 = 0x2; break;
9552     case 0x3: ai4const_in_0 = 0x3; break;
9553     case 0x4: ai4const_in_0 = 0x4; break;
9554     case 0x5: ai4const_in_0 = 0x5; break;
9555     case 0x6: ai4const_in_0 = 0x6; break;
9556     case 0x7: ai4const_in_0 = 0x7; break;
9557     case 0x8: ai4const_in_0 = 0x8; break;
9558     case 0x9: ai4const_in_0 = 0x9; break;
9559     case 0xa: ai4const_in_0 = 0xa; break;
9560     case 0xb: ai4const_in_0 = 0xb; break;
9561     case 0xc: ai4const_in_0 = 0xc; break;
9562     case 0xd: ai4const_in_0 = 0xd; break;
9563     case 0xe: ai4const_in_0 = 0xe; break;
9564     default: ai4const_in_0 = 0xf; break;
9565     }
9566   *valp = ai4const_in_0;
9567   return 0;
9568 }
9569
9570 static int
9571 OperandSem_opnd_sem_b4const_decode (uint32 *valp)
9572 {
9573   unsigned b4const_out_0;
9574   unsigned b4const_in_0;
9575   b4const_in_0 = *valp & 0xf;
9576   b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
9577   *valp = b4const_out_0;
9578   return 0;
9579 }
9580
9581 static int
9582 OperandSem_opnd_sem_b4const_encode (uint32 *valp)
9583 {
9584   unsigned b4const_in_0;
9585   unsigned b4const_out_0;
9586   b4const_out_0 = *valp;
9587   switch (b4const_out_0)
9588     {
9589     case 0xffffffff: b4const_in_0 = 0; break;
9590     case 0x1: b4const_in_0 = 0x1; break;
9591     case 0x2: b4const_in_0 = 0x2; break;
9592     case 0x3: b4const_in_0 = 0x3; break;
9593     case 0x4: b4const_in_0 = 0x4; break;
9594     case 0x5: b4const_in_0 = 0x5; break;
9595     case 0x6: b4const_in_0 = 0x6; break;
9596     case 0x7: b4const_in_0 = 0x7; break;
9597     case 0x8: b4const_in_0 = 0x8; break;
9598     case 0xa: b4const_in_0 = 0x9; break;
9599     case 0xc: b4const_in_0 = 0xa; break;
9600     case 0x10: b4const_in_0 = 0xb; break;
9601     case 0x20: b4const_in_0 = 0xc; break;
9602     case 0x40: b4const_in_0 = 0xd; break;
9603     case 0x80: b4const_in_0 = 0xe; break;
9604     default: b4const_in_0 = 0xf; break;
9605     }
9606   *valp = b4const_in_0;
9607   return 0;
9608 }
9609
9610 static int
9611 OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
9612 {
9613   unsigned b4constu_out_0;
9614   unsigned b4constu_in_0;
9615   b4constu_in_0 = *valp & 0xf;
9616   b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
9617   *valp = b4constu_out_0;
9618   return 0;
9619 }
9620
9621 static int
9622 OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
9623 {
9624   unsigned b4constu_in_0;
9625   unsigned b4constu_out_0;
9626   b4constu_out_0 = *valp;
9627   switch (b4constu_out_0)
9628     {
9629     case 0x8000: b4constu_in_0 = 0; break;
9630     case 0x10000: b4constu_in_0 = 0x1; break;
9631     case 0x2: b4constu_in_0 = 0x2; break;
9632     case 0x3: b4constu_in_0 = 0x3; break;
9633     case 0x4: b4constu_in_0 = 0x4; break;
9634     case 0x5: b4constu_in_0 = 0x5; break;
9635     case 0x6: b4constu_in_0 = 0x6; break;
9636     case 0x7: b4constu_in_0 = 0x7; break;
9637     case 0x8: b4constu_in_0 = 0x8; break;
9638     case 0xa: b4constu_in_0 = 0x9; break;
9639     case 0xc: b4constu_in_0 = 0xa; break;
9640     case 0x10: b4constu_in_0 = 0xb; break;
9641     case 0x20: b4constu_in_0 = 0xc; break;
9642     case 0x40: b4constu_in_0 = 0xd; break;
9643     case 0x80: b4constu_in_0 = 0xe; break;
9644     default: b4constu_in_0 = 0xf; break;
9645     }
9646   *valp = b4constu_in_0;
9647   return 0;
9648 }
9649
9650 static int
9651 OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
9652 {
9653   unsigned uimm8_out_0;
9654   unsigned uimm8_in_0;
9655   uimm8_in_0 = *valp & 0xff;
9656   uimm8_out_0 = uimm8_in_0;
9657   *valp = uimm8_out_0;
9658   return 0;
9659 }
9660
9661 static int
9662 OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
9663 {
9664   unsigned uimm8_in_0;
9665   unsigned uimm8_out_0;
9666   uimm8_out_0 = *valp;
9667   uimm8_in_0 = (uimm8_out_0 & 0xff);
9668   *valp = uimm8_in_0;
9669   return 0;
9670 }
9671
9672 static int
9673 OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
9674 {
9675   unsigned uimm8x2_out_0;
9676   unsigned uimm8x2_in_0;
9677   uimm8x2_in_0 = *valp & 0xff;
9678   uimm8x2_out_0 = uimm8x2_in_0 << 1;
9679   *valp = uimm8x2_out_0;
9680   return 0;
9681 }
9682
9683 static int
9684 OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
9685 {
9686   unsigned uimm8x2_in_0;
9687   unsigned uimm8x2_out_0;
9688   uimm8x2_out_0 = *valp;
9689   uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
9690   *valp = uimm8x2_in_0;
9691   return 0;
9692 }
9693
9694 static int
9695 OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
9696 {
9697   unsigned uimm8x4_out_0;
9698   unsigned uimm8x4_in_0;
9699   uimm8x4_in_0 = *valp & 0xff;
9700   uimm8x4_out_0 = uimm8x4_in_0 << 2;
9701   *valp = uimm8x4_out_0;
9702   return 0;
9703 }
9704
9705 static int
9706 OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
9707 {
9708   unsigned uimm8x4_in_0;
9709   unsigned uimm8x4_out_0;
9710   uimm8x4_out_0 = *valp;
9711   uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
9712   *valp = uimm8x4_in_0;
9713   return 0;
9714 }
9715
9716 static int
9717 OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
9718 {
9719   unsigned uimm4x16_out_0;
9720   unsigned uimm4x16_in_0;
9721   uimm4x16_in_0 = *valp & 0xf;
9722   uimm4x16_out_0 = uimm4x16_in_0 << 4;
9723   *valp = uimm4x16_out_0;
9724   return 0;
9725 }
9726
9727 static int
9728 OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
9729 {
9730   unsigned uimm4x16_in_0;
9731   unsigned uimm4x16_out_0;
9732   uimm4x16_out_0 = *valp;
9733   uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
9734   *valp = uimm4x16_in_0;
9735   return 0;
9736 }
9737
9738 static int
9739 OperandSem_opnd_sem_simm8_decode (uint32 *valp)
9740 {
9741   unsigned simm8_out_0;
9742   unsigned simm8_in_0;
9743   simm8_in_0 = *valp & 0xff;
9744   simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
9745   *valp = simm8_out_0;
9746   return 0;
9747 }
9748
9749 static int
9750 OperandSem_opnd_sem_simm8_encode (uint32 *valp)
9751 {
9752   unsigned simm8_in_0;
9753   unsigned simm8_out_0;
9754   simm8_out_0 = *valp;
9755   simm8_in_0 = (simm8_out_0 & 0xff);
9756   *valp = simm8_in_0;
9757   return 0;
9758 }
9759
9760 static int
9761 OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
9762 {
9763   unsigned simm8x256_out_0;
9764   unsigned simm8x256_in_0;
9765   simm8x256_in_0 = *valp & 0xff;
9766   simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
9767   *valp = simm8x256_out_0;
9768   return 0;
9769 }
9770
9771 static int
9772 OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
9773 {
9774   unsigned simm8x256_in_0;
9775   unsigned simm8x256_out_0;
9776   simm8x256_out_0 = *valp;
9777   simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
9778   *valp = simm8x256_in_0;
9779   return 0;
9780 }
9781
9782 static int
9783 OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
9784 {
9785   unsigned simm12b_out_0;
9786   unsigned simm12b_in_0;
9787   simm12b_in_0 = *valp & 0xfff;
9788   simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
9789   *valp = simm12b_out_0;
9790   return 0;
9791 }
9792
9793 static int
9794 OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
9795 {
9796   unsigned simm12b_in_0;
9797   unsigned simm12b_out_0;
9798   simm12b_out_0 = *valp;
9799   simm12b_in_0 = (simm12b_out_0 & 0xfff);
9800   *valp = simm12b_in_0;
9801   return 0;
9802 }
9803
9804 static int
9805 OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
9806 {
9807   unsigned msalp32_out_0;
9808   unsigned msalp32_in_0;
9809   msalp32_in_0 = *valp & 0x1f;
9810   msalp32_out_0 = 0x20 - msalp32_in_0;
9811   *valp = msalp32_out_0;
9812   return 0;
9813 }
9814
9815 static int
9816 OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
9817 {
9818   unsigned msalp32_in_0;
9819   unsigned msalp32_out_0;
9820   msalp32_out_0 = *valp;
9821   msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
9822   *valp = msalp32_in_0;
9823   return 0;
9824 }
9825
9826 static int
9827 OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
9828 {
9829   unsigned op2p1_out_0;
9830   unsigned op2p1_in_0;
9831   op2p1_in_0 = *valp & 0xf;
9832   op2p1_out_0 = op2p1_in_0 + 0x1;
9833   *valp = op2p1_out_0;
9834   return 0;
9835 }
9836
9837 static int
9838 OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
9839 {
9840   unsigned op2p1_in_0;
9841   unsigned op2p1_out_0;
9842   op2p1_out_0 = *valp;
9843   op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
9844   *valp = op2p1_in_0;
9845   return 0;
9846 }
9847
9848 static int
9849 OperandSem_opnd_sem_label8_decode (uint32 *valp)
9850 {
9851   unsigned label8_out_0;
9852   unsigned label8_in_0;
9853   label8_in_0 = *valp & 0xff;
9854   label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
9855   *valp = label8_out_0;
9856   return 0;
9857 }
9858
9859 static int
9860 OperandSem_opnd_sem_label8_encode (uint32 *valp)
9861 {
9862   unsigned label8_in_0;
9863   unsigned label8_out_0;
9864   label8_out_0 = *valp;
9865   label8_in_0 = (label8_out_0 - 0x4) & 0xff;
9866   *valp = label8_in_0;
9867   return 0;
9868 }
9869
9870 static int
9871 OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
9872 {
9873   unsigned ulabel8_out_0;
9874   unsigned ulabel8_in_0;
9875   ulabel8_in_0 = *valp & 0xff;
9876   ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
9877   *valp = ulabel8_out_0;
9878   return 0;
9879 }
9880
9881 static int
9882 OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
9883 {
9884   unsigned ulabel8_in_0;
9885   unsigned ulabel8_out_0;
9886   ulabel8_out_0 = *valp;
9887   ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
9888   *valp = ulabel8_in_0;
9889   return 0;
9890 }
9891
9892 static int
9893 OperandSem_opnd_sem_label12_decode (uint32 *valp)
9894 {
9895   unsigned label12_out_0;
9896   unsigned label12_in_0;
9897   label12_in_0 = *valp & 0xfff;
9898   label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
9899   *valp = label12_out_0;
9900   return 0;
9901 }
9902
9903 static int
9904 OperandSem_opnd_sem_label12_encode (uint32 *valp)
9905 {
9906   unsigned label12_in_0;
9907   unsigned label12_out_0;
9908   label12_out_0 = *valp;
9909   label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
9910   *valp = label12_in_0;
9911   return 0;
9912 }
9913
9914 static int
9915 OperandSem_opnd_sem_soffset_decode (uint32 *valp)
9916 {
9917   unsigned soffset_out_0;
9918   unsigned soffset_in_0;
9919   soffset_in_0 = *valp & 0x3ffff;
9920   soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
9921   *valp = soffset_out_0;
9922   return 0;
9923 }
9924
9925 static int
9926 OperandSem_opnd_sem_soffset_encode (uint32 *valp)
9927 {
9928   unsigned soffset_in_0;
9929   unsigned soffset_out_0;
9930   soffset_out_0 = *valp;
9931   soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
9932   *valp = soffset_in_0;
9933   return 0;
9934 }
9935
9936 static int
9937 OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
9938 {
9939   unsigned uimm16x4_out_0;
9940   unsigned uimm16x4_in_0;
9941   uimm16x4_in_0 = *valp & 0xffff;
9942   uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
9943   *valp = uimm16x4_out_0;
9944   return 0;
9945 }
9946
9947 static int
9948 OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
9949 {
9950   unsigned uimm16x4_in_0;
9951   unsigned uimm16x4_out_0;
9952   uimm16x4_out_0 = *valp;
9953   uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
9954   *valp = uimm16x4_in_0;
9955   return 0;
9956 }
9957
9958 static int
9959 OperandSem_opnd_sem_bbi_decode (uint32 *valp)
9960 {
9961   unsigned bbi_out_0;
9962   unsigned bbi_in_0;
9963   bbi_in_0 = *valp & 0x1f;
9964   bbi_out_0 = (0 << 5) | bbi_in_0;
9965   *valp = bbi_out_0;
9966   return 0;
9967 }
9968
9969 static int
9970 OperandSem_opnd_sem_bbi_encode (uint32 *valp)
9971 {
9972   unsigned bbi_in_0;
9973   unsigned bbi_out_0;
9974   bbi_out_0 = *valp;
9975   bbi_in_0 = (bbi_out_0 & 0x1f);
9976   *valp = bbi_in_0;
9977   return 0;
9978 }
9979
9980 static int
9981 OperandSem_opnd_sem_s_decode (uint32 *valp)
9982 {
9983   unsigned s_out_0;
9984   unsigned s_in_0;
9985   s_in_0 = *valp & 0xf;
9986   s_out_0 = (0 << 4) | s_in_0;
9987   *valp = s_out_0;
9988   return 0;
9989 }
9990
9991 static int
9992 OperandSem_opnd_sem_s_encode (uint32 *valp)
9993 {
9994   unsigned s_in_0;
9995   unsigned s_out_0;
9996   s_out_0 = *valp;
9997   s_in_0 = (s_out_0 & 0xf);
9998   *valp = s_in_0;
9999   return 0;
10000 }
10001
10002 static int
10003 OperandSem_opnd_sem_immt_decode (uint32 *valp)
10004 {
10005   unsigned immt_out_0;
10006   unsigned immt_in_0;
10007   immt_in_0 = *valp & 0xf;
10008   immt_out_0 = immt_in_0;
10009   *valp = immt_out_0;
10010   return 0;
10011 }
10012
10013 static int
10014 OperandSem_opnd_sem_immt_encode (uint32 *valp)
10015 {
10016   unsigned immt_in_0;
10017   unsigned immt_out_0;
10018   immt_out_0 = *valp;
10019   immt_in_0 = immt_out_0 & 0xf;
10020   *valp = immt_in_0;
10021   return 0;
10022 }
10023
10024 static int
10025 OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED)
10026 {
10027   return 0;
10028 }
10029
10030 static int
10031 OperandSem_opnd_sem_BR_encode (uint32 *valp)
10032 {
10033   int error;
10034   error = (*valp >= 16);
10035   return error;
10036 }
10037
10038 static int
10039 OperandSem_opnd_sem_BR2_decode (uint32 *valp)
10040 {
10041   *valp = *valp << 1;
10042   return 0;
10043 }
10044
10045 static int
10046 OperandSem_opnd_sem_BR2_encode (uint32 *valp)
10047 {
10048   int error;
10049   error = (*valp >= 16) || ((*valp & 1) != 0);
10050   *valp = *valp >> 1;
10051   return error;
10052 }
10053
10054 static int
10055 OperandSem_opnd_sem_BR4_decode (uint32 *valp)
10056 {
10057   *valp = *valp << 2;
10058   return 0;
10059 }
10060
10061 static int
10062 OperandSem_opnd_sem_BR4_encode (uint32 *valp)
10063 {
10064   int error;
10065   error = (*valp >= 16) || ((*valp & 3) != 0);
10066   *valp = *valp >> 2;
10067   return error;
10068 }
10069
10070 static int
10071 OperandSem_opnd_sem_BR8_decode (uint32 *valp)
10072 {
10073   *valp = *valp << 3;
10074   return 0;
10075 }
10076
10077 static int
10078 OperandSem_opnd_sem_BR8_encode (uint32 *valp)
10079 {
10080   int error;
10081   error = (*valp >= 16) || ((*valp & 7) != 0);
10082   *valp = *valp >> 3;
10083   return error;
10084 }
10085
10086 static int
10087 OperandSem_opnd_sem_BR16_decode (uint32 *valp)
10088 {
10089   *valp = *valp << 4;
10090   return 0;
10091 }
10092
10093 static int
10094 OperandSem_opnd_sem_BR16_encode (uint32 *valp)
10095 {
10096   int error;
10097   error = (*valp >= 16) || ((*valp & 15) != 0);
10098   *valp = *valp >> 4;
10099   return error;
10100 }
10101
10102 static int
10103 OperandSem_opnd_sem_tp7_decode (uint32 *valp)
10104 {
10105   unsigned tp7_out_0;
10106   unsigned tp7_in_0;
10107   tp7_in_0 = *valp & 0xf;
10108   tp7_out_0 = tp7_in_0 + 0x7;
10109   *valp = tp7_out_0;
10110   return 0;
10111 }
10112
10113 static int
10114 OperandSem_opnd_sem_tp7_encode (uint32 *valp)
10115 {
10116   unsigned tp7_in_0;
10117   unsigned tp7_out_0;
10118   tp7_out_0 = *valp;
10119   tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
10120   *valp = tp7_in_0;
10121   return 0;
10122 }
10123
10124 static int
10125 OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
10126 {
10127   unsigned xt_wbr15_label_out_0;
10128   unsigned xt_wbr15_label_in_0;
10129   xt_wbr15_label_in_0 = *valp & 0x7fff;
10130   xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
10131   *valp = xt_wbr15_label_out_0;
10132   return 0;
10133 }
10134
10135 static int
10136 OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
10137 {
10138   unsigned xt_wbr15_label_in_0;
10139   unsigned xt_wbr15_label_out_0;
10140   xt_wbr15_label_out_0 = *valp;
10141   xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
10142   *valp = xt_wbr15_label_in_0;
10143   return 0;
10144 }
10145
10146 static int
10147 OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp)
10148 {
10149   unsigned ae_samt32_out_0;
10150   unsigned ae_samt32_in_0;
10151   ae_samt32_in_0 = *valp & 0x1f;
10152   ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0;
10153   *valp = ae_samt32_out_0;
10154   return 0;
10155 }
10156
10157 static int
10158 OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp)
10159 {
10160   unsigned ae_samt32_in_0;
10161   unsigned ae_samt32_out_0;
10162   ae_samt32_out_0 = *valp;
10163   ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f);
10164   *valp = ae_samt32_in_0;
10165   return 0;
10166 }
10167
10168 static int
10169 OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED)
10170 {
10171   return 0;
10172 }
10173
10174 static int
10175 OperandSem_opnd_sem_AE_PR_encode (uint32 *valp)
10176 {
10177   int error;
10178   error = (*valp >= 8);
10179   return error;
10180 }
10181
10182 static int
10183 OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED)
10184 {
10185   return 0;
10186 }
10187
10188 static int
10189 OperandSem_opnd_sem_AE_QR_encode (uint32 *valp)
10190 {
10191   int error;
10192   error = (*valp >= 4);
10193   return error;
10194 }
10195
10196 static int
10197 OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp)
10198 {
10199   unsigned ae_lsimm16_out_0;
10200   unsigned ae_lsimm16_in_0;
10201   ae_lsimm16_in_0 = *valp & 0xf;
10202   ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1;
10203   *valp = ae_lsimm16_out_0;
10204   return 0;
10205 }
10206
10207 static int
10208 OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp)
10209 {
10210   unsigned ae_lsimm16_in_0;
10211   unsigned ae_lsimm16_out_0;
10212   ae_lsimm16_out_0 = *valp;
10213   ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf);
10214   *valp = ae_lsimm16_in_0;
10215   return 0;
10216 }
10217
10218 static int
10219 OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp)
10220 {
10221   unsigned ae_lsimm32_out_0;
10222   unsigned ae_lsimm32_in_0;
10223   ae_lsimm32_in_0 = *valp & 0xf;
10224   ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2;
10225   *valp = ae_lsimm32_out_0;
10226   return 0;
10227 }
10228
10229 static int
10230 OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp)
10231 {
10232   unsigned ae_lsimm32_in_0;
10233   unsigned ae_lsimm32_out_0;
10234   ae_lsimm32_out_0 = *valp;
10235   ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf);
10236   *valp = ae_lsimm32_in_0;
10237   return 0;
10238 }
10239
10240 static int
10241 OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp)
10242 {
10243   unsigned ae_lsimm64_out_0;
10244   unsigned ae_lsimm64_in_0;
10245   ae_lsimm64_in_0 = *valp & 0xf;
10246   ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3;
10247   *valp = ae_lsimm64_out_0;
10248   return 0;
10249 }
10250
10251 static int
10252 OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp)
10253 {
10254   unsigned ae_lsimm64_in_0;
10255   unsigned ae_lsimm64_out_0;
10256   ae_lsimm64_out_0 = *valp;
10257   ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf);
10258   *valp = ae_lsimm64_in_0;
10259   return 0;
10260 }
10261
10262 static int
10263 OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp)
10264 {
10265   unsigned ae_samt64_out_0;
10266   unsigned ae_samt64_in_0;
10267   ae_samt64_in_0 = *valp & 0x3f;
10268   ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0;
10269   *valp = ae_samt64_out_0;
10270   return 0;
10271 }
10272
10273 static int
10274 OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp)
10275 {
10276   unsigned ae_samt64_in_0;
10277   unsigned ae_samt64_out_0;
10278   ae_samt64_out_0 = *valp;
10279   ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f);
10280   *valp = ae_samt64_in_0;
10281   return 0;
10282 }
10283
10284 static int
10285 OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp)
10286 {
10287   unsigned ae_ohba_out_0;
10288   unsigned ae_ohba_in_0;
10289   ae_ohba_in_0 = *valp & 0xf;
10290   ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf));
10291   *valp = ae_ohba_out_0;
10292   return 0;
10293 }
10294
10295 static int
10296 OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp)
10297 {
10298   unsigned ae_ohba_in_0;
10299   unsigned ae_ohba_out_0;
10300   ae_ohba_out_0 = *valp;
10301   ae_ohba_in_0 = (ae_ohba_out_0 & 0xf);
10302   *valp = ae_ohba_in_0;
10303   return 0;
10304 }
10305
10306 static int
10307 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
10308 {
10309   *valp -= (pc & ~0x3);
10310   return 0;
10311 }
10312
10313 static int
10314 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
10315 {
10316   *valp += (pc & ~0x3);
10317   return 0;
10318 }
10319
10320 static int
10321 Operand_uimm6_ator (uint32 *valp, uint32 pc)
10322 {
10323   *valp -= pc;
10324   return 0;
10325 }
10326
10327 static int
10328 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
10329 {
10330   *valp += pc;
10331   return 0;
10332 }
10333
10334 static int
10335 Operand_label8_ator (uint32 *valp, uint32 pc)
10336 {
10337   *valp -= pc;
10338   return 0;
10339 }
10340
10341 static int
10342 Operand_label8_rtoa (uint32 *valp, uint32 pc)
10343 {
10344   *valp += pc;
10345   return 0;
10346 }
10347
10348 static int
10349 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
10350 {
10351   *valp -= pc;
10352   return 0;
10353 }
10354
10355 static int
10356 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
10357 {
10358   *valp += pc;
10359   return 0;
10360 }
10361
10362 static int
10363 Operand_label12_ator (uint32 *valp, uint32 pc)
10364 {
10365   *valp -= pc;
10366   return 0;
10367 }
10368
10369 static int
10370 Operand_label12_rtoa (uint32 *valp, uint32 pc)
10371 {
10372   *valp += pc;
10373   return 0;
10374 }
10375
10376 static int
10377 Operand_soffset_ator (uint32 *valp, uint32 pc)
10378 {
10379   *valp -= pc;
10380   return 0;
10381 }
10382
10383 static int
10384 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
10385 {
10386   *valp += pc;
10387   return 0;
10388 }
10389
10390 static int
10391 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
10392 {
10393   *valp -= ((pc + 3) & ~0x3);
10394   return 0;
10395 }
10396
10397 static int
10398 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
10399 {
10400   *valp += ((pc + 3) & ~0x3);
10401   return 0;
10402 }
10403
10404 static int
10405 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
10406 {
10407   *valp -= pc;
10408   return 0;
10409 }
10410
10411 static int
10412 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
10413 {
10414   *valp += pc;
10415   return 0;
10416 }
10417
10418 static int
10419 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
10420 {
10421   *valp -= pc;
10422   return 0;
10423 }
10424
10425 static int
10426 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
10427 {
10428   *valp += pc;
10429   return 0;
10430 }
10431
10432 static xtensa_operand_internal operands[] = {
10433   { "soffsetx4", FIELD_offset, -1, 0,
10434     XTENSA_OPERAND_IS_PCRELATIVE,
10435     OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
10436     Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
10437   { "uimm12x8", FIELD_imm12, -1, 0,
10438     0,
10439     OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
10440     0, 0 },
10441   { "simm4", FIELD_mn, -1, 0,
10442     0,
10443     OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
10444     0, 0 },
10445   { "arr", FIELD_r, REGFILE_AR, 1,
10446     XTENSA_OPERAND_IS_REGISTER,
10447     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
10448     0, 0 },
10449   { "ars", FIELD_s, REGFILE_AR, 1,
10450     XTENSA_OPERAND_IS_REGISTER,
10451     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
10452     0, 0 },
10453   { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
10454     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10455     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
10456     0, 0 },
10457   { "art", FIELD_t, REGFILE_AR, 1,
10458     XTENSA_OPERAND_IS_REGISTER,
10459     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
10460     0, 0 },
10461   { "ar0", FIELD__ar0, REGFILE_AR, 1,
10462     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10463     OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
10464     0, 0 },
10465   { "ar4", FIELD__ar4, REGFILE_AR, 1,
10466     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10467     OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
10468     0, 0 },
10469   { "ar8", FIELD__ar8, REGFILE_AR, 1,
10470     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10471     OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
10472     0, 0 },
10473   { "ar12", FIELD__ar12, REGFILE_AR, 1,
10474     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10475     OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
10476     0, 0 },
10477   { "ars_entry", FIELD_s, REGFILE_AR, 1,
10478     XTENSA_OPERAND_IS_REGISTER,
10479     OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
10480     0, 0 },
10481   { "immrx4", FIELD_r, -1, 0,
10482     0,
10483     OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
10484     0, 0 },
10485   { "lsi4x4", FIELD_r, -1, 0,
10486     0,
10487     OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
10488     0, 0 },
10489   { "simm7", FIELD_imm7, -1, 0,
10490     0,
10491     OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
10492     0, 0 },
10493   { "uimm6", FIELD_imm6, -1, 0,
10494     XTENSA_OPERAND_IS_PCRELATIVE,
10495     OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
10496     Operand_uimm6_ator, Operand_uimm6_rtoa },
10497   { "ai4const", FIELD_t, -1, 0,
10498     0,
10499     OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
10500     0, 0 },
10501   { "b4const", FIELD_r, -1, 0,
10502     0,
10503     OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
10504     0, 0 },
10505   { "b4constu", FIELD_r, -1, 0,
10506     0,
10507     OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
10508     0, 0 },
10509   { "uimm8", FIELD_imm8, -1, 0,
10510     0,
10511     OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
10512     0, 0 },
10513   { "uimm8x2", FIELD_imm8, -1, 0,
10514     0,
10515     OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
10516     0, 0 },
10517   { "uimm8x4", FIELD_imm8, -1, 0,
10518     0,
10519     OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
10520     0, 0 },
10521   { "uimm4x16", FIELD_op2, -1, 0,
10522     0,
10523     OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
10524     0, 0 },
10525   { "uimmrx4", FIELD_r, -1, 0,
10526     0,
10527     OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
10528     0, 0 },
10529   { "simm8", FIELD_imm8, -1, 0,
10530     0,
10531     OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
10532     0, 0 },
10533   { "simm8x256", FIELD_imm8, -1, 0,
10534     0,
10535     OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
10536     0, 0 },
10537   { "simm12b", FIELD_imm12b, -1, 0,
10538     0,
10539     OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
10540     0, 0 },
10541   { "msalp32", FIELD_sal, -1, 0,
10542     0,
10543     OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
10544     0, 0 },
10545   { "op2p1", FIELD_op2, -1, 0,
10546     0,
10547     OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
10548     0, 0 },
10549   { "label8", FIELD_imm8, -1, 0,
10550     XTENSA_OPERAND_IS_PCRELATIVE,
10551     OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
10552     Operand_label8_ator, Operand_label8_rtoa },
10553   { "ulabel8", FIELD_imm8, -1, 0,
10554     XTENSA_OPERAND_IS_PCRELATIVE,
10555     OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
10556     Operand_ulabel8_ator, Operand_ulabel8_rtoa },
10557   { "label12", FIELD_imm12, -1, 0,
10558     XTENSA_OPERAND_IS_PCRELATIVE,
10559     OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
10560     Operand_label12_ator, Operand_label12_rtoa },
10561   { "soffset", FIELD_offset, -1, 0,
10562     XTENSA_OPERAND_IS_PCRELATIVE,
10563     OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
10564     Operand_soffset_ator, Operand_soffset_rtoa },
10565   { "uimm16x4", FIELD_imm16, -1, 0,
10566     XTENSA_OPERAND_IS_PCRELATIVE,
10567     OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
10568     Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
10569   { "bbi", FIELD_bbi, -1, 0,
10570     0,
10571     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
10572     0, 0 },
10573   { "sae", FIELD_sae, -1, 0,
10574     0,
10575     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
10576     0, 0 },
10577   { "sas", FIELD_sas, -1, 0,
10578     0,
10579     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
10580     0, 0 },
10581   { "sargt", FIELD_sargt, -1, 0,
10582     0,
10583     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
10584     0, 0 },
10585   { "s", FIELD_s, -1, 0,
10586     0,
10587     OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
10588     0, 0 },
10589   { "immt", FIELD_t, -1, 0,
10590     0,
10591     OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
10592     0, 0 },
10593   { "imms", FIELD_s, -1, 0,
10594     0,
10595     OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
10596     0, 0 },
10597   { "bt", FIELD_t, REGFILE_BR, 1,
10598     XTENSA_OPERAND_IS_REGISTER,
10599     OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
10600     0, 0 },
10601   { "bs", FIELD_s, REGFILE_BR, 1,
10602     XTENSA_OPERAND_IS_REGISTER,
10603     OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
10604     0, 0 },
10605   { "br", FIELD_r, REGFILE_BR, 1,
10606     XTENSA_OPERAND_IS_REGISTER,
10607     OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
10608     0, 0 },
10609   { "bt2", FIELD_t2, REGFILE_BR, 2,
10610     XTENSA_OPERAND_IS_REGISTER,
10611     OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
10612     0, 0 },
10613   { "bs2", FIELD_s2, REGFILE_BR, 2,
10614     XTENSA_OPERAND_IS_REGISTER,
10615     OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
10616     0, 0 },
10617   { "br2", FIELD_r2, REGFILE_BR, 2,
10618     XTENSA_OPERAND_IS_REGISTER,
10619     OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
10620     0, 0 },
10621   { "bt4", FIELD_t4, REGFILE_BR, 4,
10622     XTENSA_OPERAND_IS_REGISTER,
10623     OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
10624     0, 0 },
10625   { "bs4", FIELD_s4, REGFILE_BR, 4,
10626     XTENSA_OPERAND_IS_REGISTER,
10627     OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
10628     0, 0 },
10629   { "br4", FIELD_r4, REGFILE_BR, 4,
10630     XTENSA_OPERAND_IS_REGISTER,
10631     OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
10632     0, 0 },
10633   { "bt8", FIELD_t8, REGFILE_BR, 8,
10634     XTENSA_OPERAND_IS_REGISTER,
10635     OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
10636     0, 0 },
10637   { "bs8", FIELD_s8, REGFILE_BR, 8,
10638     XTENSA_OPERAND_IS_REGISTER,
10639     OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
10640     0, 0 },
10641   { "br8", FIELD_r8, REGFILE_BR, 8,
10642     XTENSA_OPERAND_IS_REGISTER,
10643     OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
10644     0, 0 },
10645   { "bt16", FIELD__bt16, REGFILE_BR, 16,
10646     XTENSA_OPERAND_IS_REGISTER,
10647     OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
10648     0, 0 },
10649   { "bs16", FIELD__bs16, REGFILE_BR, 16,
10650     XTENSA_OPERAND_IS_REGISTER,
10651     OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
10652     0, 0 },
10653   { "br16", FIELD__br16, REGFILE_BR, 16,
10654     XTENSA_OPERAND_IS_REGISTER,
10655     OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
10656     0, 0 },
10657   { "brall", FIELD__brall, REGFILE_BR, 16,
10658     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10659     OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
10660     0, 0 },
10661   { "tp7", FIELD_t, -1, 0,
10662     0,
10663     OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
10664     0, 0 },
10665   { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
10666     XTENSA_OPERAND_IS_PCRELATIVE,
10667     OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
10668     Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
10669   { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
10670     XTENSA_OPERAND_IS_PCRELATIVE,
10671     OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
10672     Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
10673   { "ae_samt32", FIELD_ftsf14, -1, 0,
10674     0,
10675     OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode,
10676     0, 0 },
10677   { "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1,
10678     XTENSA_OPERAND_IS_REGISTER,
10679     OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10680     0, 0 },
10681   { "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1,
10682     XTENSA_OPERAND_IS_REGISTER,
10683     OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10684     0, 0 },
10685   { "mac_qr0", FIELD_ftsf13, REGFILE_AE_QR, 1,
10686     XTENSA_OPERAND_IS_REGISTER,
10687     OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10688     0, 0 },
10689   { "ae_lsimm16", FIELD_t, -1, 0,
10690     0,
10691     OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode,
10692     0, 0 },
10693   { "ae_lsimm32", FIELD_t, -1, 0,
10694     0,
10695     OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode,
10696     0, 0 },
10697   { "ae_lsimm64", FIELD_t, -1, 0,
10698     0,
10699     OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode,
10700     0, 0 },
10701   { "ae_samt64", FIELD_ae_samt_s_t, -1, 0,
10702     0,
10703     OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode,
10704     0, 0 },
10705   { "ae_ohba", FIELD_ae_fld_ohba, -1, 0,
10706     0,
10707     OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
10708     0, 0 },
10709   { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0,
10710     0,
10711     OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
10712     0, 0 },
10713   { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
10714     XTENSA_OPERAND_IS_REGISTER,
10715     OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10716     0, 0 },
10717   { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
10718     XTENSA_OPERAND_IS_REGISTER,
10719     OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10720     0, 0 },
10721   { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
10722     XTENSA_OPERAND_IS_REGISTER,
10723     OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10724     0, 0 },
10725   { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
10726     XTENSA_OPERAND_IS_REGISTER,
10727     OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10728     0, 0 },
10729   { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
10730     XTENSA_OPERAND_IS_REGISTER,
10731     OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10732     0, 0 },
10733   { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
10734     XTENSA_OPERAND_IS_REGISTER,
10735     OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10736     0, 0 },
10737   { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
10738     XTENSA_OPERAND_IS_REGISTER,
10739     OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10740     0, 0 },
10741   { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
10742     XTENSA_OPERAND_IS_REGISTER,
10743     OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10744     0, 0 },
10745   { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
10746   { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
10747   { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
10748   { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
10749   { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
10750   { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
10751   { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
10752   { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
10753   { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
10754   { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
10755   { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
10756   { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
10757   { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
10758   { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
10759   { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
10760   { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
10761   { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
10762   { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
10763   { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
10764   { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
10765   { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
10766   { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
10767   { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
10768   { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
10769   { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
10770   { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
10771   { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
10772   { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
10773   { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
10774   { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
10775   { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 },
10776   { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 },
10777   { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 },
10778   { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 },
10779   { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 },
10780   { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 },
10781   { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 },
10782   { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 },
10783   { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 },
10784   { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
10785   { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
10786   { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 },
10787   { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 },
10788   { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 },
10789   { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 },
10790   { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 },
10791   { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 },
10792   { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 },
10793   { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 },
10794   { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 },
10795   { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 },
10796   { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 },
10797   { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 },
10798   { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 },
10799   { "ftsf14", FIELD_ftsf14, -1, 0, 0, 0, 0, 0, 0 },
10800   { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10801   { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10802   { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10803   { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10804   { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10805   { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10806   { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10807   { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10808   { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10809   { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10810   { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10811   { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10812   { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10813   { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10814   { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10815   { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10816   { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10817   { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10818   { "ftsf39ae_slot1", FIELD_ftsf39ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10819   { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10820   { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10821   { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10822   { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10823   { "ftsf44ae_slot1", FIELD_ftsf44ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10824   { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10825   { "ftsf46ae_slot1", FIELD_ftsf46ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10826   { "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10827   { "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10828   { "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10829   { "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10830   { "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10831   { "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10832   { "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10833   { "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10834   { "ftsf55ae_slot1", FIELD_ftsf55ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10835   { "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10836   { "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10837   { "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10838   { "ftsf59ae_slot1", FIELD_ftsf59ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10839   { "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10840   { "ftsf61ae_slot1", FIELD_ftsf61ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10841   { "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10842   { "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10843   { "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10844   { "ftsf67ae_slot1", FIELD_ftsf67ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10845   { "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10846   { "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10847   { "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10848   { "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10849   { "ftsf75ae_slot1", FIELD_ftsf75ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10850   { "ftsf76ae_slot1", FIELD_ftsf76ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10851   { "ftsf77ae_slot1", FIELD_ftsf77ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10852   { "ftsf78ae_slot1", FIELD_ftsf78ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10853   { "ftsf79ae_slot1", FIELD_ftsf79ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10854   { "ftsf80ae_slot1", FIELD_ftsf80ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10855   { "ftsf81ae_slot1", FIELD_ftsf81ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10856   { "ftsf82ae_slot1", FIELD_ftsf82ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10857   { "ftsf84ae_slot1", FIELD_ftsf84ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10858   { "ftsf86ae_slot1", FIELD_ftsf86ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10859   { "ftsf87ae_slot1", FIELD_ftsf87ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10860   { "ftsf88ae_slot1", FIELD_ftsf88ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10861   { "ftsf89ae_slot1", FIELD_ftsf89ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10862   { "ftsf90ae_slot1", FIELD_ftsf90ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10863   { "ftsf91ae_slot1", FIELD_ftsf91ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10864   { "ftsf92ae_slot1", FIELD_ftsf92ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10865   { "ftsf94ae_slot1", FIELD_ftsf94ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10866   { "ftsf96ae_slot1", FIELD_ftsf96ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10867   { "ftsf97ae_slot1", FIELD_ftsf97ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10868   { "ftsf98ae_slot1", FIELD_ftsf98ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10869   { "ftsf99ae_slot1", FIELD_ftsf99ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10870   { "ftsf100ae_slot1", FIELD_ftsf100ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10871   { "ftsf101ae_slot1", FIELD_ftsf101ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10872   { "ftsf103ae_slot1", FIELD_ftsf103ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10873   { "ftsf104ae_slot1", FIELD_ftsf104ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10874   { "ftsf105ae_slot1", FIELD_ftsf105ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10875   { "ftsf106ae_slot1", FIELD_ftsf106ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10876   { "ftsf107ae_slot1", FIELD_ftsf107ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10877   { "ftsf108ae_slot1", FIELD_ftsf108ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10878   { "ftsf109ae_slot1", FIELD_ftsf109ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10879   { "ftsf110ae_slot1", FIELD_ftsf110ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10880   { "ftsf111ae_slot1", FIELD_ftsf111ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10881   { "ftsf112ae_slot1", FIELD_ftsf112ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10882   { "ftsf113ae_slot1", FIELD_ftsf113ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10883   { "ftsf114ae_slot1", FIELD_ftsf114ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10884   { "ftsf115ae_slot1", FIELD_ftsf115ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10885   { "ftsf116ae_slot1", FIELD_ftsf116ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10886   { "ftsf118ae_slot1", FIELD_ftsf118ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10887   { "ftsf119ae_slot1", FIELD_ftsf119ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10888   { "ftsf120ae_slot1", FIELD_ftsf120ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10889   { "ftsf122ae_slot1", FIELD_ftsf122ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10890   { "ftsf124ae_slot1", FIELD_ftsf124ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10891   { "ftsf125ae_slot1", FIELD_ftsf125ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10892   { "ftsf126ae_slot1", FIELD_ftsf126ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10893   { "ftsf127ae_slot1", FIELD_ftsf127ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10894   { "ftsf128ae_slot1", FIELD_ftsf128ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10895   { "ftsf129ae_slot1", FIELD_ftsf129ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10896   { "ftsf130ae_slot1", FIELD_ftsf130ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10897   { "ftsf131ae_slot1", FIELD_ftsf131ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10898   { "ftsf132ae_slot1", FIELD_ftsf132ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10899   { "ftsf133ae_slot1", FIELD_ftsf133ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10900   { "ftsf134ae_slot1", FIELD_ftsf134ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10901   { "ftsf135ae_slot1", FIELD_ftsf135ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10902   { "ftsf136ae_slot1", FIELD_ftsf136ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10903   { "ftsf137ae_slot1", FIELD_ftsf137ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10904   { "ftsf138ae_slot1", FIELD_ftsf138ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10905   { "ftsf139ae_slot1", FIELD_ftsf139ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10906   { "ftsf140ae_slot1", FIELD_ftsf140ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10907   { "ftsf141ae_slot1", FIELD_ftsf141ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10908   { "ftsf142ae_slot1", FIELD_ftsf142ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10909   { "ftsf143ae_slot1", FIELD_ftsf143ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10910   { "ftsf144ae_slot1", FIELD_ftsf144ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10911   { "ftsf145ae_slot1", FIELD_ftsf145ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10912   { "ftsf146ae_slot1", FIELD_ftsf146ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10913   { "ftsf147ae_slot1", FIELD_ftsf147ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10914   { "ftsf148ae_slot1", FIELD_ftsf148ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10915   { "ftsf149ae_slot1", FIELD_ftsf149ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10916   { "ftsf150ae_slot1", FIELD_ftsf150ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10917   { "ftsf151ae_slot1", FIELD_ftsf151ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10918   { "ftsf152ae_slot1", FIELD_ftsf152ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10919   { "ftsf153ae_slot1", FIELD_ftsf153ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10920   { "ftsf154ae_slot1", FIELD_ftsf154ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10921   { "ftsf155ae_slot1", FIELD_ftsf155ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10922   { "ftsf156ae_slot1", FIELD_ftsf156ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10923   { "ftsf157ae_slot1", FIELD_ftsf157ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10924   { "ftsf158ae_slot1", FIELD_ftsf158ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10925   { "ftsf159ae_slot1", FIELD_ftsf159ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10926   { "ftsf160ae_slot1", FIELD_ftsf160ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10927   { "ftsf161ae_slot1", FIELD_ftsf161ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10928   { "ftsf162ae_slot1", FIELD_ftsf162ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10929   { "ftsf163ae_slot1", FIELD_ftsf163ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10930   { "ftsf164ae_slot1", FIELD_ftsf164ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10931   { "ftsf165ae_slot1", FIELD_ftsf165ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10932   { "ftsf166ae_slot1", FIELD_ftsf166ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10933   { "ftsf167ae_slot1", FIELD_ftsf167ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10934   { "ftsf168ae_slot1", FIELD_ftsf168ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10935   { "ftsf169ae_slot1", FIELD_ftsf169ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10936   { "ftsf170ae_slot1", FIELD_ftsf170ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10937   { "ftsf171ae_slot1", FIELD_ftsf171ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10938   { "ftsf172ae_slot1", FIELD_ftsf172ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10939   { "ftsf173ae_slot1", FIELD_ftsf173ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10940   { "ftsf174ae_slot1", FIELD_ftsf174ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10941   { "ftsf175ae_slot1", FIELD_ftsf175ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10942   { "ftsf176ae_slot1", FIELD_ftsf176ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10943   { "ftsf177ae_slot1", FIELD_ftsf177ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10944   { "ftsf178ae_slot1", FIELD_ftsf178ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10945   { "ftsf179ae_slot1", FIELD_ftsf179ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10946   { "ftsf180ae_slot1", FIELD_ftsf180ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10947   { "ftsf181ae_slot1", FIELD_ftsf181ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10948   { "ftsf182ae_slot1", FIELD_ftsf182ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10949   { "ftsf183ae_slot1", FIELD_ftsf183ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10950   { "ftsf184ae_slot1", FIELD_ftsf184ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10951   { "ftsf185ae_slot1", FIELD_ftsf185ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10952   { "ftsf186ae_slot1", FIELD_ftsf186ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10953   { "ftsf187ae_slot1", FIELD_ftsf187ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10954   { "ftsf188ae_slot1", FIELD_ftsf188ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10955   { "ftsf189ae_slot1", FIELD_ftsf189ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10956   { "ftsf190ae_slot1", FIELD_ftsf190ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10957   { "ftsf191ae_slot1", FIELD_ftsf191ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10958   { "ftsf192ae_slot1", FIELD_ftsf192ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10959   { "ftsf193ae_slot1", FIELD_ftsf193ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10960   { "ftsf194ae_slot1", FIELD_ftsf194ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10961   { "ftsf195ae_slot1", FIELD_ftsf195ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10962   { "ftsf196ae_slot1", FIELD_ftsf196ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10963   { "ftsf197ae_slot1", FIELD_ftsf197ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10964   { "ftsf198ae_slot1", FIELD_ftsf198ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10965   { "ftsf199ae_slot1", FIELD_ftsf199ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10966   { "ftsf200ae_slot1", FIELD_ftsf200ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10967   { "ftsf201ae_slot1", FIELD_ftsf201ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10968   { "ftsf202ae_slot1", FIELD_ftsf202ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10969   { "ftsf203ae_slot1", FIELD_ftsf203ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10970   { "ftsf204ae_slot1", FIELD_ftsf204ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10971   { "ftsf205ae_slot1", FIELD_ftsf205ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10972   { "ftsf206ae_slot1", FIELD_ftsf206ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10973   { "ftsf207ae_slot1", FIELD_ftsf207ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10974   { "ftsf208", FIELD_ftsf208, -1, 0, 0, 0, 0, 0, 0 },
10975   { "ftsf209ae_slot1", FIELD_ftsf209ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10976   { "ftsf210ae_slot1", FIELD_ftsf210ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10977   { "ftsf211ae_slot1", FIELD_ftsf211ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10978   { "ftsf330ae_slot1", FIELD_ftsf330ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10979   { "ftsf332ae_slot1", FIELD_ftsf332ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10980   { "ftsf334ae_slot1", FIELD_ftsf334ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10981   { "ftsf336ae_slot1", FIELD_ftsf336ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10982   { "ftsf337ae_slot1", FIELD_ftsf337ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10983   { "ftsf338", FIELD_ftsf338, -1, 0, 0, 0, 0, 0, 0 },
10984   { "ftsf339ae_slot1", FIELD_ftsf339ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10985   { "ftsf340", FIELD_ftsf340, -1, 0, 0, 0, 0, 0, 0 },
10986   { "ftsf341ae_slot1", FIELD_ftsf341ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10987   { "ftsf342ae_slot1", FIELD_ftsf342ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10988   { "ftsf343ae_slot1", FIELD_ftsf343ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10989   { "ftsf344ae_slot1", FIELD_ftsf344ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10990   { "ftsf346ae_slot1", FIELD_ftsf346ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10991   { "ftsf347", FIELD_ftsf347, -1, 0, 0, 0, 0, 0, 0 },
10992   { "ftsf348ae_slot1", FIELD_ftsf348ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10993   { "ftsf349ae_slot1", FIELD_ftsf349ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10994   { "ftsf350ae_slot1", FIELD_ftsf350ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10995   { "op0_s4", FIELD_op0_s4, -1, 0, 0, 0, 0, 0, 0 },
10996   { "ftsf212ae_slot0", FIELD_ftsf212ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
10997   { "ftsf213ae_slot0", FIELD_ftsf213ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
10998   { "ftsf214ae_slot0", FIELD_ftsf214ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
10999   { "ftsf215ae_slot0", FIELD_ftsf215ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11000   { "ftsf216ae_slot0", FIELD_ftsf216ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11001   { "ftsf217", FIELD_ftsf217, -1, 0, 0, 0, 0, 0, 0 },
11002   { "ftsf218ae_slot0", FIELD_ftsf218ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11003   { "ftsf219ae_slot0", FIELD_ftsf219ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11004   { "ftsf220ae_slot0", FIELD_ftsf220ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11005   { "ftsf221ae_slot0", FIELD_ftsf221ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11006   { "ftsf222ae_slot0", FIELD_ftsf222ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11007   { "ftsf223ae_slot0", FIELD_ftsf223ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11008   { "ftsf224ae_slot0", FIELD_ftsf224ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11009   { "ftsf225ae_slot0", FIELD_ftsf225ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11010   { "ftsf226ae_slot0", FIELD_ftsf226ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11011   { "ftsf227ae_slot0", FIELD_ftsf227ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11012   { "ftsf228ae_slot0", FIELD_ftsf228ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11013   { "ftsf229ae_slot0", FIELD_ftsf229ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11014   { "ftsf230ae_slot0", FIELD_ftsf230ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11015   { "ftsf231ae_slot0", FIELD_ftsf231ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11016   { "ftsf232ae_slot0", FIELD_ftsf232ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11017   { "ftsf233ae_slot0", FIELD_ftsf233ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11018   { "ftsf234ae_slot0", FIELD_ftsf234ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11019   { "ftsf235ae_slot0", FIELD_ftsf235ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11020   { "ftsf236ae_slot0", FIELD_ftsf236ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11021   { "ftsf237ae_slot0", FIELD_ftsf237ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11022   { "ftsf238ae_slot0", FIELD_ftsf238ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11023   { "ftsf239ae_slot0", FIELD_ftsf239ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11024   { "ftsf240ae_slot0", FIELD_ftsf240ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11025   { "ftsf241ae_slot0", FIELD_ftsf241ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11026   { "ftsf242ae_slot0", FIELD_ftsf242ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11027   { "ftsf243ae_slot0", FIELD_ftsf243ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11028   { "ftsf244ae_slot0", FIELD_ftsf244ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11029   { "ftsf245ae_slot0", FIELD_ftsf245ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11030   { "ftsf246ae_slot0", FIELD_ftsf246ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11031   { "ftsf247ae_slot0", FIELD_ftsf247ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11032   { "ftsf248ae_slot0", FIELD_ftsf248ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11033   { "ftsf249ae_slot0", FIELD_ftsf249ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11034   { "ftsf250ae_slot0", FIELD_ftsf250ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11035   { "ftsf251ae_slot0", FIELD_ftsf251ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11036   { "ftsf252ae_slot0", FIELD_ftsf252ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11037   { "ftsf253ae_slot0", FIELD_ftsf253ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11038   { "ftsf254ae_slot0", FIELD_ftsf254ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11039   { "ftsf255ae_slot0", FIELD_ftsf255ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11040   { "ftsf256ae_slot0", FIELD_ftsf256ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11041   { "ftsf257ae_slot0", FIELD_ftsf257ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11042   { "ftsf258ae_slot0", FIELD_ftsf258ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11043   { "ftsf259ae_slot0", FIELD_ftsf259ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11044   { "ftsf260ae_slot0", FIELD_ftsf260ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11045   { "ftsf261ae_slot0", FIELD_ftsf261ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11046   { "ftsf262ae_slot0", FIELD_ftsf262ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11047   { "ftsf263ae_slot0", FIELD_ftsf263ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11048   { "ftsf264ae_slot0", FIELD_ftsf264ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11049   { "ftsf265ae_slot0", FIELD_ftsf265ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11050   { "ftsf266ae_slot0", FIELD_ftsf266ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11051   { "ftsf267ae_slot0", FIELD_ftsf267ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11052   { "ftsf268ae_slot0", FIELD_ftsf268ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11053   { "ftsf269ae_slot0", FIELD_ftsf269ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11054   { "ftsf270ae_slot0", FIELD_ftsf270ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11055   { "ftsf271ae_slot0", FIELD_ftsf271ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11056   { "ftsf272ae_slot0", FIELD_ftsf272ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11057   { "ftsf273ae_slot0", FIELD_ftsf273ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11058   { "ftsf274ae_slot0", FIELD_ftsf274ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11059   { "ftsf275ae_slot0", FIELD_ftsf275ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11060   { "ftsf276ae_slot0", FIELD_ftsf276ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11061   { "ftsf277ae_slot0", FIELD_ftsf277ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11062   { "ftsf278ae_slot0", FIELD_ftsf278ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11063   { "ftsf279ae_slot0", FIELD_ftsf279ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11064   { "ftsf281ae_slot0", FIELD_ftsf281ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11065   { "ftsf282ae_slot0", FIELD_ftsf282ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11066   { "ftsf283ae_slot0", FIELD_ftsf283ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11067   { "ftsf284ae_slot0", FIELD_ftsf284ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11068   { "ftsf286ae_slot0", FIELD_ftsf286ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11069   { "ftsf288ae_slot0", FIELD_ftsf288ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11070   { "ftsf290ae_slot0", FIELD_ftsf290ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11071   { "ftsf292ae_slot0", FIELD_ftsf292ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11072   { "ftsf293", FIELD_ftsf293, -1, 0, 0, 0, 0, 0, 0 },
11073   { "ftsf294ae_slot0", FIELD_ftsf294ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11074   { "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11075   { "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11076   { "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11077   { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11078   { "ftsf299ae_slot0", FIELD_ftsf299ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11079   { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11080   { "ftsf301ae_slot0", FIELD_ftsf301ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11081   { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11082   { "ftsf303ae_slot0", FIELD_ftsf303ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11083   { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11084   { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11085   { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11086   { "ftsf309ae_slot0", FIELD_ftsf309ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11087   { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11088   { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11089   { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11090   { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11091   { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11092   { "ftsf315ae_slot0", FIELD_ftsf315ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11093   { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11094   { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11095   { "ftsf318ae_slot0", FIELD_ftsf318ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11096   { "ftsf319", FIELD_ftsf319, -1, 0, 0, 0, 0, 0, 0 },
11097   { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11098   { "ftsf321", FIELD_ftsf321, -1, 0, 0, 0, 0, 0, 0 },
11099   { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11100   { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11101   { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11102   { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11103   { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11104   { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11105   { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11106   { "ftsf352ae_slot0", FIELD_ftsf352ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11107   { "ftsf353", FIELD_ftsf353, -1, 0, 0, 0, 0, 0, 0 },
11108   { "ftsf354ae_slot0", FIELD_ftsf354ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11109   { "ftsf356ae_slot0", FIELD_ftsf356ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11110   { "ftsf357", FIELD_ftsf357, -1, 0, 0, 0, 0, 0, 0 },
11111   { "ftsf358ae_slot0", FIELD_ftsf358ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11112   { "ftsf359ae_slot0", FIELD_ftsf359ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11113   { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11114   { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11115   { "ftsf362ae_slot0", FIELD_ftsf362ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11116   { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11117   { "ftsf365ae_slot0", FIELD_ftsf365ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11118   { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11119   { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11120   { "ftsf369ae_slot0", FIELD_ftsf369ae_slot0, -1, 0, 0, 0, 0, 0, 0 }
11121 };
11122
11123 enum xtensa_operand_id {
11124   OPERAND_soffsetx4,
11125   OPERAND_uimm12x8,
11126   OPERAND_simm4,
11127   OPERAND_arr,
11128   OPERAND_ars,
11129   OPERAND__ars_invisible,
11130   OPERAND_art,
11131   OPERAND_ar0,
11132   OPERAND_ar4,
11133   OPERAND_ar8,
11134   OPERAND_ar12,
11135   OPERAND_ars_entry,
11136   OPERAND_immrx4,
11137   OPERAND_lsi4x4,
11138   OPERAND_simm7,
11139   OPERAND_uimm6,
11140   OPERAND_ai4const,
11141   OPERAND_b4const,
11142   OPERAND_b4constu,
11143   OPERAND_uimm8,
11144   OPERAND_uimm8x2,
11145   OPERAND_uimm8x4,
11146   OPERAND_uimm4x16,
11147   OPERAND_uimmrx4,
11148   OPERAND_simm8,
11149   OPERAND_simm8x256,
11150   OPERAND_simm12b,
11151   OPERAND_msalp32,
11152   OPERAND_op2p1,
11153   OPERAND_label8,
11154   OPERAND_ulabel8,
11155   OPERAND_label12,
11156   OPERAND_soffset,
11157   OPERAND_uimm16x4,
11158   OPERAND_bbi,
11159   OPERAND_sae,
11160   OPERAND_sas,
11161   OPERAND_sargt,
11162   OPERAND_s,
11163   OPERAND_immt,
11164   OPERAND_imms,
11165   OPERAND_bt,
11166   OPERAND_bs,
11167   OPERAND_br,
11168   OPERAND_bt2,
11169   OPERAND_bs2,
11170   OPERAND_br2,
11171   OPERAND_bt4,
11172   OPERAND_bs4,
11173   OPERAND_br4,
11174   OPERAND_bt8,
11175   OPERAND_bs8,
11176   OPERAND_br8,
11177   OPERAND_bt16,
11178   OPERAND_bs16,
11179   OPERAND_br16,
11180   OPERAND_brall,
11181   OPERAND_tp7,
11182   OPERAND_xt_wbr15_label,
11183   OPERAND_xt_wbr18_label,
11184   OPERAND_ae_samt32,
11185   OPERAND_pr0,
11186   OPERAND_qr0,
11187   OPERAND_mac_qr0,
11188   OPERAND_ae_lsimm16,
11189   OPERAND_ae_lsimm32,
11190   OPERAND_ae_lsimm64,
11191   OPERAND_ae_samt64,
11192   OPERAND_ae_ohba,
11193   OPERAND_ae_ohba2,
11194   OPERAND_pr,
11195   OPERAND_cvt_pr,
11196   OPERAND_qr0_rw,
11197   OPERAND_mac_qr0_rw,
11198   OPERAND_qr1_w,
11199   OPERAND_mac_qr1_w,
11200   OPERAND_ps,
11201   OPERAND_alupppb_ps,
11202   OPERAND_t,
11203   OPERAND_bbi4,
11204   OPERAND_imm12,
11205   OPERAND_imm8,
11206   OPERAND_imm12b,
11207   OPERAND_imm16,
11208   OPERAND_m,
11209   OPERAND_n,
11210   OPERAND_offset,
11211   OPERAND_op0,
11212   OPERAND_op1,
11213   OPERAND_op2,
11214   OPERAND_r,
11215   OPERAND_sa4,
11216   OPERAND_sae4,
11217   OPERAND_sal,
11218   OPERAND_sas4,
11219   OPERAND_sr,
11220   OPERAND_st,
11221   OPERAND_thi3,
11222   OPERAND_imm4,
11223   OPERAND_mn,
11224   OPERAND_i,
11225   OPERAND_imm6lo,
11226   OPERAND_imm6hi,
11227   OPERAND_imm7lo,
11228   OPERAND_imm7hi,
11229   OPERAND_z,
11230   OPERAND_imm6,
11231   OPERAND_imm7,
11232   OPERAND_t2,
11233   OPERAND_s2,
11234   OPERAND_r2,
11235   OPERAND_t4,
11236   OPERAND_s4,
11237   OPERAND_r4,
11238   OPERAND_t8,
11239   OPERAND_s8,
11240   OPERAND_r8,
11241   OPERAND_xt_wbr15_imm,
11242   OPERAND_xt_wbr18_imm,
11243   OPERAND_ae_r3,
11244   OPERAND_ae_s_non_samt,
11245   OPERAND_ae_s3,
11246   OPERAND_ae_r32,
11247   OPERAND_ae_samt_s_t,
11248   OPERAND_ae_r20,
11249   OPERAND_ae_r10,
11250   OPERAND_ae_s20,
11251   OPERAND_ae_fld_ohba,
11252   OPERAND_ae_fld_ohba2,
11253   OPERAND_op0_s3,
11254   OPERAND_ftsf12,
11255   OPERAND_ftsf13,
11256   OPERAND_ftsf14,
11257   OPERAND_ftsf21ae_slot1,
11258   OPERAND_ftsf22ae_slot1,
11259   OPERAND_ftsf23ae_slot1,
11260   OPERAND_ftsf24ae_slot1,
11261   OPERAND_ftsf25ae_slot1,
11262   OPERAND_ftsf26ae_slot1,
11263   OPERAND_ftsf27ae_slot1,
11264   OPERAND_ftsf28ae_slot1,
11265   OPERAND_ftsf29ae_slot1,
11266   OPERAND_ftsf30ae_slot1,
11267   OPERAND_ftsf31ae_slot1,
11268   OPERAND_ftsf32ae_slot1,
11269   OPERAND_ftsf33ae_slot1,
11270   OPERAND_ftsf34ae_slot1,
11271   OPERAND_ftsf35ae_slot1,
11272   OPERAND_ftsf36ae_slot1,
11273   OPERAND_ftsf37ae_slot1,
11274   OPERAND_ftsf38ae_slot1,
11275   OPERAND_ftsf39ae_slot1,
11276   OPERAND_ftsf40ae_slot1,
11277   OPERAND_ftsf41ae_slot1,
11278   OPERAND_ftsf42ae_slot1,
11279   OPERAND_ftsf43ae_slot1,
11280   OPERAND_ftsf44ae_slot1,
11281   OPERAND_ftsf45ae_slot1,
11282   OPERAND_ftsf46ae_slot1,
11283   OPERAND_ftsf47ae_slot1,
11284   OPERAND_ftsf48ae_slot1,
11285   OPERAND_ftsf49ae_slot1,
11286   OPERAND_ftsf50ae_slot1,
11287   OPERAND_ftsf51ae_slot1,
11288   OPERAND_ftsf52ae_slot1,
11289   OPERAND_ftsf53ae_slot1,
11290   OPERAND_ftsf54ae_slot1,
11291   OPERAND_ftsf55ae_slot1,
11292   OPERAND_ftsf56ae_slot1,
11293   OPERAND_ftsf57ae_slot1,
11294   OPERAND_ftsf58ae_slot1,
11295   OPERAND_ftsf59ae_slot1,
11296   OPERAND_ftsf60ae_slot1,
11297   OPERAND_ftsf61ae_slot1,
11298   OPERAND_ftsf63ae_slot1,
11299   OPERAND_ftsf64ae_slot1,
11300   OPERAND_ftsf66ae_slot1,
11301   OPERAND_ftsf67ae_slot1,
11302   OPERAND_ftsf69ae_slot1,
11303   OPERAND_ftsf71ae_slot1,
11304   OPERAND_ftsf72ae_slot1,
11305   OPERAND_ftsf73ae_slot1,
11306   OPERAND_ftsf75ae_slot1,
11307   OPERAND_ftsf76ae_slot1,
11308   OPERAND_ftsf77ae_slot1,
11309   OPERAND_ftsf78ae_slot1,
11310   OPERAND_ftsf79ae_slot1,
11311   OPERAND_ftsf80ae_slot1,
11312   OPERAND_ftsf81ae_slot1,
11313   OPERAND_ftsf82ae_slot1,
11314   OPERAND_ftsf84ae_slot1,
11315   OPERAND_ftsf86ae_slot1,
11316   OPERAND_ftsf87ae_slot1,
11317   OPERAND_ftsf88ae_slot1,
11318   OPERAND_ftsf89ae_slot1,
11319   OPERAND_ftsf90ae_slot1,
11320   OPERAND_ftsf91ae_slot1,
11321   OPERAND_ftsf92ae_slot1,
11322   OPERAND_ftsf94ae_slot1,
11323   OPERAND_ftsf96ae_slot1,
11324   OPERAND_ftsf97ae_slot1,
11325   OPERAND_ftsf98ae_slot1,
11326   OPERAND_ftsf99ae_slot1,
11327   OPERAND_ftsf100ae_slot1,
11328   OPERAND_ftsf101ae_slot1,
11329   OPERAND_ftsf103ae_slot1,
11330   OPERAND_ftsf104ae_slot1,
11331   OPERAND_ftsf105ae_slot1,
11332   OPERAND_ftsf106ae_slot1,
11333   OPERAND_ftsf107ae_slot1,
11334   OPERAND_ftsf108ae_slot1,
11335   OPERAND_ftsf109ae_slot1,
11336   OPERAND_ftsf110ae_slot1,
11337   OPERAND_ftsf111ae_slot1,
11338   OPERAND_ftsf112ae_slot1,
11339   OPERAND_ftsf113ae_slot1,
11340   OPERAND_ftsf114ae_slot1,
11341   OPERAND_ftsf115ae_slot1,
11342   OPERAND_ftsf116ae_slot1,
11343   OPERAND_ftsf118ae_slot1,
11344   OPERAND_ftsf119ae_slot1,
11345   OPERAND_ftsf120ae_slot1,
11346   OPERAND_ftsf122ae_slot1,
11347   OPERAND_ftsf124ae_slot1,
11348   OPERAND_ftsf125ae_slot1,
11349   OPERAND_ftsf126ae_slot1,
11350   OPERAND_ftsf127ae_slot1,
11351   OPERAND_ftsf128ae_slot1,
11352   OPERAND_ftsf129ae_slot1,
11353   OPERAND_ftsf130ae_slot1,
11354   OPERAND_ftsf131ae_slot1,
11355   OPERAND_ftsf132ae_slot1,
11356   OPERAND_ftsf133ae_slot1,
11357   OPERAND_ftsf134ae_slot1,
11358   OPERAND_ftsf135ae_slot1,
11359   OPERAND_ftsf136ae_slot1,
11360   OPERAND_ftsf137ae_slot1,
11361   OPERAND_ftsf138ae_slot1,
11362   OPERAND_ftsf139ae_slot1,
11363   OPERAND_ftsf140ae_slot1,
11364   OPERAND_ftsf141ae_slot1,
11365   OPERAND_ftsf142ae_slot1,
11366   OPERAND_ftsf143ae_slot1,
11367   OPERAND_ftsf144ae_slot1,
11368   OPERAND_ftsf145ae_slot1,
11369   OPERAND_ftsf146ae_slot1,
11370   OPERAND_ftsf147ae_slot1,
11371   OPERAND_ftsf148ae_slot1,
11372   OPERAND_ftsf149ae_slot1,
11373   OPERAND_ftsf150ae_slot1,
11374   OPERAND_ftsf151ae_slot1,
11375   OPERAND_ftsf152ae_slot1,
11376   OPERAND_ftsf153ae_slot1,
11377   OPERAND_ftsf154ae_slot1,
11378   OPERAND_ftsf155ae_slot1,
11379   OPERAND_ftsf156ae_slot1,
11380   OPERAND_ftsf157ae_slot1,
11381   OPERAND_ftsf158ae_slot1,
11382   OPERAND_ftsf159ae_slot1,
11383   OPERAND_ftsf160ae_slot1,
11384   OPERAND_ftsf161ae_slot1,
11385   OPERAND_ftsf162ae_slot1,
11386   OPERAND_ftsf163ae_slot1,
11387   OPERAND_ftsf164ae_slot1,
11388   OPERAND_ftsf165ae_slot1,
11389   OPERAND_ftsf166ae_slot1,
11390   OPERAND_ftsf167ae_slot1,
11391   OPERAND_ftsf168ae_slot1,
11392   OPERAND_ftsf169ae_slot1,
11393   OPERAND_ftsf170ae_slot1,
11394   OPERAND_ftsf171ae_slot1,
11395   OPERAND_ftsf172ae_slot1,
11396   OPERAND_ftsf173ae_slot1,
11397   OPERAND_ftsf174ae_slot1,
11398   OPERAND_ftsf175ae_slot1,
11399   OPERAND_ftsf176ae_slot1,
11400   OPERAND_ftsf177ae_slot1,
11401   OPERAND_ftsf178ae_slot1,
11402   OPERAND_ftsf179ae_slot1,
11403   OPERAND_ftsf180ae_slot1,
11404   OPERAND_ftsf181ae_slot1,
11405   OPERAND_ftsf182ae_slot1,
11406   OPERAND_ftsf183ae_slot1,
11407   OPERAND_ftsf184ae_slot1,
11408   OPERAND_ftsf185ae_slot1,
11409   OPERAND_ftsf186ae_slot1,
11410   OPERAND_ftsf187ae_slot1,
11411   OPERAND_ftsf188ae_slot1,
11412   OPERAND_ftsf189ae_slot1,
11413   OPERAND_ftsf190ae_slot1,
11414   OPERAND_ftsf191ae_slot1,
11415   OPERAND_ftsf192ae_slot1,
11416   OPERAND_ftsf193ae_slot1,
11417   OPERAND_ftsf194ae_slot1,
11418   OPERAND_ftsf195ae_slot1,
11419   OPERAND_ftsf196ae_slot1,
11420   OPERAND_ftsf197ae_slot1,
11421   OPERAND_ftsf198ae_slot1,
11422   OPERAND_ftsf199ae_slot1,
11423   OPERAND_ftsf200ae_slot1,
11424   OPERAND_ftsf201ae_slot1,
11425   OPERAND_ftsf202ae_slot1,
11426   OPERAND_ftsf203ae_slot1,
11427   OPERAND_ftsf204ae_slot1,
11428   OPERAND_ftsf205ae_slot1,
11429   OPERAND_ftsf206ae_slot1,
11430   OPERAND_ftsf207ae_slot1,
11431   OPERAND_ftsf208,
11432   OPERAND_ftsf209ae_slot1,
11433   OPERAND_ftsf210ae_slot1,
11434   OPERAND_ftsf211ae_slot1,
11435   OPERAND_ftsf330ae_slot1,
11436   OPERAND_ftsf332ae_slot1,
11437   OPERAND_ftsf334ae_slot1,
11438   OPERAND_ftsf336ae_slot1,
11439   OPERAND_ftsf337ae_slot1,
11440   OPERAND_ftsf338,
11441   OPERAND_ftsf339ae_slot1,
11442   OPERAND_ftsf340,
11443   OPERAND_ftsf341ae_slot1,
11444   OPERAND_ftsf342ae_slot1,
11445   OPERAND_ftsf343ae_slot1,
11446   OPERAND_ftsf344ae_slot1,
11447   OPERAND_ftsf346ae_slot1,
11448   OPERAND_ftsf347,
11449   OPERAND_ftsf348ae_slot1,
11450   OPERAND_ftsf349ae_slot1,
11451   OPERAND_ftsf350ae_slot1,
11452   OPERAND_op0_s4,
11453   OPERAND_ftsf212ae_slot0,
11454   OPERAND_ftsf213ae_slot0,
11455   OPERAND_ftsf214ae_slot0,
11456   OPERAND_ftsf215ae_slot0,
11457   OPERAND_ftsf216ae_slot0,
11458   OPERAND_ftsf217,
11459   OPERAND_ftsf218ae_slot0,
11460   OPERAND_ftsf219ae_slot0,
11461   OPERAND_ftsf220ae_slot0,
11462   OPERAND_ftsf221ae_slot0,
11463   OPERAND_ftsf222ae_slot0,
11464   OPERAND_ftsf223ae_slot0,
11465   OPERAND_ftsf224ae_slot0,
11466   OPERAND_ftsf225ae_slot0,
11467   OPERAND_ftsf226ae_slot0,
11468   OPERAND_ftsf227ae_slot0,
11469   OPERAND_ftsf228ae_slot0,
11470   OPERAND_ftsf229ae_slot0,
11471   OPERAND_ftsf230ae_slot0,
11472   OPERAND_ftsf231ae_slot0,
11473   OPERAND_ftsf232ae_slot0,
11474   OPERAND_ftsf233ae_slot0,
11475   OPERAND_ftsf234ae_slot0,
11476   OPERAND_ftsf235ae_slot0,
11477   OPERAND_ftsf236ae_slot0,
11478   OPERAND_ftsf237ae_slot0,
11479   OPERAND_ftsf238ae_slot0,
11480   OPERAND_ftsf239ae_slot0,
11481   OPERAND_ftsf240ae_slot0,
11482   OPERAND_ftsf241ae_slot0,
11483   OPERAND_ftsf242ae_slot0,
11484   OPERAND_ftsf243ae_slot0,
11485   OPERAND_ftsf244ae_slot0,
11486   OPERAND_ftsf245ae_slot0,
11487   OPERAND_ftsf246ae_slot0,
11488   OPERAND_ftsf247ae_slot0,
11489   OPERAND_ftsf248ae_slot0,
11490   OPERAND_ftsf249ae_slot0,
11491   OPERAND_ftsf250ae_slot0,
11492   OPERAND_ftsf251ae_slot0,
11493   OPERAND_ftsf252ae_slot0,
11494   OPERAND_ftsf253ae_slot0,
11495   OPERAND_ftsf254ae_slot0,
11496   OPERAND_ftsf255ae_slot0,
11497   OPERAND_ftsf256ae_slot0,
11498   OPERAND_ftsf257ae_slot0,
11499   OPERAND_ftsf258ae_slot0,
11500   OPERAND_ftsf259ae_slot0,
11501   OPERAND_ftsf260ae_slot0,
11502   OPERAND_ftsf261ae_slot0,
11503   OPERAND_ftsf262ae_slot0,
11504   OPERAND_ftsf263ae_slot0,
11505   OPERAND_ftsf264ae_slot0,
11506   OPERAND_ftsf265ae_slot0,
11507   OPERAND_ftsf266ae_slot0,
11508   OPERAND_ftsf267ae_slot0,
11509   OPERAND_ftsf268ae_slot0,
11510   OPERAND_ftsf269ae_slot0,
11511   OPERAND_ftsf270ae_slot0,
11512   OPERAND_ftsf271ae_slot0,
11513   OPERAND_ftsf272ae_slot0,
11514   OPERAND_ftsf273ae_slot0,
11515   OPERAND_ftsf274ae_slot0,
11516   OPERAND_ftsf275ae_slot0,
11517   OPERAND_ftsf276ae_slot0,
11518   OPERAND_ftsf277ae_slot0,
11519   OPERAND_ftsf278ae_slot0,
11520   OPERAND_ftsf279ae_slot0,
11521   OPERAND_ftsf281ae_slot0,
11522   OPERAND_ftsf282ae_slot0,
11523   OPERAND_ftsf283ae_slot0,
11524   OPERAND_ftsf284ae_slot0,
11525   OPERAND_ftsf286ae_slot0,
11526   OPERAND_ftsf288ae_slot0,
11527   OPERAND_ftsf290ae_slot0,
11528   OPERAND_ftsf292ae_slot0,
11529   OPERAND_ftsf293,
11530   OPERAND_ftsf294ae_slot0,
11531   OPERAND_ftsf295ae_slot0,
11532   OPERAND_ftsf296ae_slot0,
11533   OPERAND_ftsf297ae_slot0,
11534   OPERAND_ftsf298ae_slot0,
11535   OPERAND_ftsf299ae_slot0,
11536   OPERAND_ftsf300ae_slot0,
11537   OPERAND_ftsf301ae_slot0,
11538   OPERAND_ftsf302ae_slot0,
11539   OPERAND_ftsf303ae_slot0,
11540   OPERAND_ftsf304ae_slot0,
11541   OPERAND_ftsf306ae_slot0,
11542   OPERAND_ftsf308ae_slot0,
11543   OPERAND_ftsf309ae_slot0,
11544   OPERAND_ftsf310ae_slot0,
11545   OPERAND_ftsf311ae_slot0,
11546   OPERAND_ftsf312ae_slot0,
11547   OPERAND_ftsf313ae_slot0,
11548   OPERAND_ftsf314ae_slot0,
11549   OPERAND_ftsf315ae_slot0,
11550   OPERAND_ftsf316ae_slot0,
11551   OPERAND_ftsf317ae_slot0,
11552   OPERAND_ftsf318ae_slot0,
11553   OPERAND_ftsf319,
11554   OPERAND_ftsf320ae_slot0,
11555   OPERAND_ftsf321,
11556   OPERAND_ftsf322ae_slot0,
11557   OPERAND_ftsf323ae_slot0,
11558   OPERAND_ftsf324ae_slot0,
11559   OPERAND_ftsf325ae_slot0,
11560   OPERAND_ftsf326ae_slot0,
11561   OPERAND_ftsf328ae_slot0,
11562   OPERAND_ftsf329ae_slot0,
11563   OPERAND_ftsf352ae_slot0,
11564   OPERAND_ftsf353,
11565   OPERAND_ftsf354ae_slot0,
11566   OPERAND_ftsf356ae_slot0,
11567   OPERAND_ftsf357,
11568   OPERAND_ftsf358ae_slot0,
11569   OPERAND_ftsf359ae_slot0,
11570   OPERAND_ftsf360ae_slot0,
11571   OPERAND_ftsf361ae_slot0,
11572   OPERAND_ftsf362ae_slot0,
11573   OPERAND_ftsf364ae_slot0,
11574   OPERAND_ftsf365ae_slot0,
11575   OPERAND_ftsf366ae_slot0,
11576   OPERAND_ftsf368ae_slot0,
11577   OPERAND_ftsf369ae_slot0
11578 };
11579
11580 \f
11581 /* Iclass table.  */
11582
11583 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
11584   { { STATE_PSRING }, 'i' },
11585   { { STATE_PSEXCM }, 'm' },
11586   { { STATE_EPC1 }, 'i' }
11587 };
11588
11589 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
11590   { { STATE_PSEXCM }, 'i' },
11591   { { STATE_PSRING }, 'i' },
11592   { { STATE_DEPC }, 'i' }
11593 };
11594
11595 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
11596   { { OPERAND_soffsetx4 }, 'i' },
11597   { { OPERAND_ar12 }, 'o' }
11598 };
11599
11600 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
11601   { { STATE_PSCALLINC }, 'o' }
11602 };
11603
11604 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
11605   { { OPERAND_soffsetx4 }, 'i' },
11606   { { OPERAND_ar8 }, 'o' }
11607 };
11608
11609 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
11610   { { STATE_PSCALLINC }, 'o' }
11611 };
11612
11613 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
11614   { { OPERAND_soffsetx4 }, 'i' },
11615   { { OPERAND_ar4 }, 'o' }
11616 };
11617
11618 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
11619   { { STATE_PSCALLINC }, 'o' }
11620 };
11621
11622 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
11623   { { OPERAND_ars }, 'i' },
11624   { { OPERAND_ar12 }, 'o' }
11625 };
11626
11627 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
11628   { { STATE_PSCALLINC }, 'o' }
11629 };
11630
11631 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
11632   { { OPERAND_ars }, 'i' },
11633   { { OPERAND_ar8 }, 'o' }
11634 };
11635
11636 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
11637   { { STATE_PSCALLINC }, 'o' }
11638 };
11639
11640 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
11641   { { OPERAND_ars }, 'i' },
11642   { { OPERAND_ar4 }, 'o' }
11643 };
11644
11645 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
11646   { { STATE_PSCALLINC }, 'o' }
11647 };
11648
11649 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
11650   { { OPERAND_ars_entry }, 's' },
11651   { { OPERAND_ars }, 'i' },
11652   { { OPERAND_uimm12x8 }, 'i' }
11653 };
11654
11655 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
11656   { { STATE_PSCALLINC }, 'i' },
11657   { { STATE_PSEXCM }, 'i' },
11658   { { STATE_PSWOE }, 'i' },
11659   { { STATE_WindowBase }, 'm' },
11660   { { STATE_WindowStart }, 'm' }
11661 };
11662
11663 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
11664   { { OPERAND_art }, 'o' },
11665   { { OPERAND_ars }, 'i' }
11666 };
11667
11668 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
11669   { { STATE_WindowBase }, 'i' },
11670   { { STATE_WindowStart }, 'i' }
11671 };
11672
11673 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
11674   { { OPERAND_simm4 }, 'i' }
11675 };
11676
11677 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
11678   { { STATE_PSEXCM }, 'i' },
11679   { { STATE_PSRING }, 'i' },
11680   { { STATE_WindowBase }, 'm' }
11681 };
11682
11683 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
11684   { { OPERAND__ars_invisible }, 'i' }
11685 };
11686
11687 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
11688   { { STATE_WindowBase }, 'm' },
11689   { { STATE_WindowStart }, 'm' },
11690   { { STATE_PSEXCM }, 'i' },
11691   { { STATE_PSWOE }, 'i' }
11692 };
11693
11694 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
11695   { { STATE_EPC1 }, 'i' },
11696   { { STATE_PSEXCM }, 'm' },
11697   { { STATE_PSRING }, 'i' },
11698   { { STATE_WindowBase }, 'm' },
11699   { { STATE_WindowStart }, 'm' },
11700   { { STATE_PSOWB }, 'i' }
11701 };
11702
11703 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
11704   { { OPERAND_art }, 'o' },
11705   { { OPERAND_ars }, 'i' },
11706   { { OPERAND_immrx4 }, 'i' }
11707 };
11708
11709 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
11710   { { STATE_PSEXCM }, 'i' },
11711   { { STATE_PSRING }, 'i' }
11712 };
11713
11714 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
11715   { { OPERAND_art }, 'i' },
11716   { { OPERAND_ars }, 'i' },
11717   { { OPERAND_immrx4 }, 'i' }
11718 };
11719
11720 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
11721   { { STATE_PSEXCM }, 'i' },
11722   { { STATE_PSRING }, 'i' }
11723 };
11724
11725 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
11726   { { OPERAND_art }, 'o' }
11727 };
11728
11729 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
11730   { { STATE_PSEXCM }, 'i' },
11731   { { STATE_PSRING }, 'i' },
11732   { { STATE_WindowBase }, 'i' }
11733 };
11734
11735 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
11736   { { OPERAND_art }, 'i' }
11737 };
11738
11739 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
11740   { { STATE_PSEXCM }, 'i' },
11741   { { STATE_PSRING }, 'i' },
11742   { { STATE_WindowBase }, 'o' }
11743 };
11744
11745 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
11746   { { OPERAND_art }, 'm' }
11747 };
11748
11749 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
11750   { { STATE_PSEXCM }, 'i' },
11751   { { STATE_PSRING }, 'i' },
11752   { { STATE_WindowBase }, 'm' }
11753 };
11754
11755 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
11756   { { OPERAND_art }, 'o' }
11757 };
11758
11759 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
11760   { { STATE_PSEXCM }, 'i' },
11761   { { STATE_PSRING }, 'i' },
11762   { { STATE_WindowStart }, 'i' }
11763 };
11764
11765 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
11766   { { OPERAND_art }, 'i' }
11767 };
11768
11769 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
11770   { { STATE_PSEXCM }, 'i' },
11771   { { STATE_PSRING }, 'i' },
11772   { { STATE_WindowStart }, 'o' }
11773 };
11774
11775 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
11776   { { OPERAND_art }, 'm' }
11777 };
11778
11779 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
11780   { { STATE_PSEXCM }, 'i' },
11781   { { STATE_PSRING }, 'i' },
11782   { { STATE_WindowStart }, 'm' }
11783 };
11784
11785 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
11786   { { OPERAND_arr }, 'o' },
11787   { { OPERAND_ars }, 'i' },
11788   { { OPERAND_art }, 'i' }
11789 };
11790
11791 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
11792   { { OPERAND_arr }, 'o' },
11793   { { OPERAND_ars }, 'i' },
11794   { { OPERAND_ai4const }, 'i' }
11795 };
11796
11797 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
11798   { { OPERAND_ars }, 'i' },
11799   { { OPERAND_uimm6 }, 'i' }
11800 };
11801
11802 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
11803   { { OPERAND_art }, 'o' },
11804   { { OPERAND_ars }, 'i' },
11805   { { OPERAND_lsi4x4 }, 'i' }
11806 };
11807
11808 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
11809   { { OPERAND_art }, 'o' },
11810   { { OPERAND_ars }, 'i' }
11811 };
11812
11813 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
11814   { { OPERAND_ars }, 'o' },
11815   { { OPERAND_simm7 }, 'i' }
11816 };
11817
11818 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
11819   { { OPERAND__ars_invisible }, 'i' }
11820 };
11821
11822 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
11823   { { OPERAND_art }, 'i' },
11824   { { OPERAND_ars }, 'i' },
11825   { { OPERAND_lsi4x4 }, 'i' }
11826 };
11827
11828 static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
11829   { { OPERAND_arr }, 'o' }
11830 };
11831
11832 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
11833   { { STATE_THREADPTR }, 'i' }
11834 };
11835
11836 static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
11837   { { OPERAND_art }, 'i' }
11838 };
11839
11840 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
11841   { { STATE_THREADPTR }, 'o' }
11842 };
11843
11844 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
11845   { { OPERAND_art }, 'o' },
11846   { { OPERAND_ars }, 'i' },
11847   { { OPERAND_simm8 }, 'i' }
11848 };
11849
11850 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
11851   { { OPERAND_art }, 'o' },
11852   { { OPERAND_ars }, 'i' },
11853   { { OPERAND_simm8x256 }, 'i' }
11854 };
11855
11856 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
11857   { { OPERAND_arr }, 'o' },
11858   { { OPERAND_ars }, 'i' },
11859   { { OPERAND_art }, 'i' }
11860 };
11861
11862 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
11863   { { OPERAND_arr }, 'o' },
11864   { { OPERAND_ars }, 'i' },
11865   { { OPERAND_art }, 'i' }
11866 };
11867
11868 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
11869   { { OPERAND_ars }, 'i' },
11870   { { OPERAND_b4const }, 'i' },
11871   { { OPERAND_label8 }, 'i' }
11872 };
11873
11874 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
11875   { { OPERAND_ars }, 'i' },
11876   { { OPERAND_bbi }, 'i' },
11877   { { OPERAND_label8 }, 'i' }
11878 };
11879
11880 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
11881   { { OPERAND_ars }, 'i' },
11882   { { OPERAND_b4constu }, 'i' },
11883   { { OPERAND_label8 }, 'i' }
11884 };
11885
11886 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
11887   { { OPERAND_ars }, 'i' },
11888   { { OPERAND_art }, 'i' },
11889   { { OPERAND_label8 }, 'i' }
11890 };
11891
11892 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
11893   { { OPERAND_ars }, 'i' },
11894   { { OPERAND_label12 }, 'i' }
11895 };
11896
11897 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
11898   { { OPERAND_soffsetx4 }, 'i' },
11899   { { OPERAND_ar0 }, 'o' }
11900 };
11901
11902 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
11903   { { OPERAND_ars }, 'i' },
11904   { { OPERAND_ar0 }, 'o' }
11905 };
11906
11907 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
11908   { { OPERAND_arr }, 'o' },
11909   { { OPERAND_art }, 'i' },
11910   { { OPERAND_sae }, 'i' },
11911   { { OPERAND_op2p1 }, 'i' }
11912 };
11913
11914 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
11915   { { OPERAND_soffset }, 'i' }
11916 };
11917
11918 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
11919   { { OPERAND_ars }, 'i' }
11920 };
11921
11922 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
11923   { { OPERAND_art }, 'o' },
11924   { { OPERAND_ars }, 'i' },
11925   { { OPERAND_uimm8x2 }, 'i' }
11926 };
11927
11928 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
11929   { { OPERAND_art }, 'o' },
11930   { { OPERAND_ars }, 'i' },
11931   { { OPERAND_uimm8x2 }, 'i' }
11932 };
11933
11934 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
11935   { { OPERAND_art }, 'o' },
11936   { { OPERAND_ars }, 'i' },
11937   { { OPERAND_uimm8x4 }, 'i' }
11938 };
11939
11940 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
11941   { { OPERAND_art }, 'o' },
11942   { { OPERAND_uimm16x4 }, 'i' }
11943 };
11944
11945 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
11946   { { STATE_LITBADDR }, 'i' },
11947   { { STATE_LITBEN }, 'i' }
11948 };
11949
11950 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
11951   { { OPERAND_art }, 'o' },
11952   { { OPERAND_ars }, 'i' },
11953   { { OPERAND_uimm8 }, 'i' }
11954 };
11955
11956 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
11957   { { OPERAND_ars }, 'i' },
11958   { { OPERAND_ulabel8 }, 'i' }
11959 };
11960
11961 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
11962   { { STATE_LBEG }, 'o' },
11963   { { STATE_LEND }, 'o' },
11964   { { STATE_LCOUNT }, 'o' }
11965 };
11966
11967 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
11968   { { OPERAND_ars }, 'i' },
11969   { { OPERAND_ulabel8 }, 'i' }
11970 };
11971
11972 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
11973   { { STATE_LBEG }, 'o' },
11974   { { STATE_LEND }, 'o' },
11975   { { STATE_LCOUNT }, 'o' }
11976 };
11977
11978 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
11979   { { OPERAND_art }, 'o' },
11980   { { OPERAND_simm12b }, 'i' }
11981 };
11982
11983 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
11984   { { OPERAND_arr }, 'm' },
11985   { { OPERAND_ars }, 'i' },
11986   { { OPERAND_art }, 'i' }
11987 };
11988
11989 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
11990   { { OPERAND_arr }, 'o' },
11991   { { OPERAND_art }, 'i' }
11992 };
11993
11994 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
11995   { { OPERAND__ars_invisible }, 'i' }
11996 };
11997
11998 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
11999   { { OPERAND_art }, 'i' },
12000   { { OPERAND_ars }, 'i' },
12001   { { OPERAND_uimm8x2 }, 'i' }
12002 };
12003
12004 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
12005   { { OPERAND_art }, 'i' },
12006   { { OPERAND_ars }, 'i' },
12007   { { OPERAND_uimm8x4 }, 'i' }
12008 };
12009
12010 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
12011   { { OPERAND_art }, 'i' },
12012   { { OPERAND_ars }, 'i' },
12013   { { OPERAND_uimm8 }, 'i' }
12014 };
12015
12016 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
12017   { { OPERAND_ars }, 'i' }
12018 };
12019
12020 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
12021   { { STATE_SAR }, 'o' }
12022 };
12023
12024 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
12025   { { OPERAND_sas }, 'i' }
12026 };
12027
12028 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
12029   { { STATE_SAR }, 'o' }
12030 };
12031
12032 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
12033   { { OPERAND_arr }, 'o' },
12034   { { OPERAND_ars }, 'i' }
12035 };
12036
12037 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
12038   { { STATE_SAR }, 'i' }
12039 };
12040
12041 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
12042   { { OPERAND_arr }, 'o' },
12043   { { OPERAND_ars }, 'i' },
12044   { { OPERAND_art }, 'i' }
12045 };
12046
12047 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
12048   { { STATE_SAR }, 'i' }
12049 };
12050
12051 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
12052   { { OPERAND_arr }, 'o' },
12053   { { OPERAND_art }, 'i' }
12054 };
12055
12056 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
12057   { { STATE_SAR }, 'i' }
12058 };
12059
12060 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
12061   { { OPERAND_arr }, 'o' },
12062   { { OPERAND_ars }, 'i' },
12063   { { OPERAND_msalp32 }, 'i' }
12064 };
12065
12066 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
12067   { { OPERAND_arr }, 'o' },
12068   { { OPERAND_art }, 'i' },
12069   { { OPERAND_sargt }, 'i' }
12070 };
12071
12072 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
12073   { { OPERAND_arr }, 'o' },
12074   { { OPERAND_art }, 'i' },
12075   { { OPERAND_s }, 'i' }
12076 };
12077
12078 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
12079   { { STATE_XTSYNC }, 'i' }
12080 };
12081
12082 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
12083   { { OPERAND_art }, 'o' },
12084   { { OPERAND_s }, 'i' }
12085 };
12086
12087 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
12088   { { STATE_PSWOE }, 'i' },
12089   { { STATE_PSCALLINC }, 'i' },
12090   { { STATE_PSOWB }, 'i' },
12091   { { STATE_PSRING }, 'i' },
12092   { { STATE_PSUM }, 'i' },
12093   { { STATE_PSEXCM }, 'i' },
12094   { { STATE_PSINTLEVEL }, 'm' }
12095 };
12096
12097 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
12098   { { OPERAND_art }, 'o' }
12099 };
12100
12101 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
12102   { { STATE_LEND }, 'i' }
12103 };
12104
12105 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
12106   { { OPERAND_art }, 'i' }
12107 };
12108
12109 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
12110   { { STATE_LEND }, 'o' }
12111 };
12112
12113 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
12114   { { OPERAND_art }, 'm' }
12115 };
12116
12117 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
12118   { { STATE_LEND }, 'm' }
12119 };
12120
12121 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
12122   { { OPERAND_art }, 'o' }
12123 };
12124
12125 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
12126   { { STATE_LCOUNT }, 'i' }
12127 };
12128
12129 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
12130   { { OPERAND_art }, 'i' }
12131 };
12132
12133 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
12134   { { STATE_XTSYNC }, 'o' },
12135   { { STATE_LCOUNT }, 'o' }
12136 };
12137
12138 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
12139   { { OPERAND_art }, 'm' }
12140 };
12141
12142 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
12143   { { STATE_XTSYNC }, 'o' },
12144   { { STATE_LCOUNT }, 'm' }
12145 };
12146
12147 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
12148   { { OPERAND_art }, 'o' }
12149 };
12150
12151 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
12152   { { STATE_LBEG }, 'i' }
12153 };
12154
12155 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
12156   { { OPERAND_art }, 'i' }
12157 };
12158
12159 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
12160   { { STATE_LBEG }, 'o' }
12161 };
12162
12163 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
12164   { { OPERAND_art }, 'm' }
12165 };
12166
12167 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
12168   { { STATE_LBEG }, 'm' }
12169 };
12170
12171 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
12172   { { OPERAND_art }, 'o' }
12173 };
12174
12175 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
12176   { { STATE_SAR }, 'i' }
12177 };
12178
12179 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
12180   { { OPERAND_art }, 'i' }
12181 };
12182
12183 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
12184   { { STATE_SAR }, 'o' },
12185   { { STATE_XTSYNC }, 'o' }
12186 };
12187
12188 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
12189   { { OPERAND_art }, 'm' }
12190 };
12191
12192 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
12193   { { STATE_SAR }, 'm' }
12194 };
12195
12196 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
12197   { { OPERAND_art }, 'o' }
12198 };
12199
12200 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
12201   { { STATE_LITBADDR }, 'i' },
12202   { { STATE_LITBEN }, 'i' }
12203 };
12204
12205 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
12206   { { OPERAND_art }, 'i' }
12207 };
12208
12209 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
12210   { { STATE_LITBADDR }, 'o' },
12211   { { STATE_LITBEN }, 'o' }
12212 };
12213
12214 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
12215   { { OPERAND_art }, 'm' }
12216 };
12217
12218 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
12219   { { STATE_LITBADDR }, 'm' },
12220   { { STATE_LITBEN }, 'm' }
12221 };
12222
12223 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
12224   { { OPERAND_art }, 'o' }
12225 };
12226
12227 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = {
12228   { { STATE_PSEXCM }, 'i' },
12229   { { STATE_PSRING }, 'i' }
12230 };
12231
12232 static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
12233   { { OPERAND_art }, 'i' }
12234 };
12235
12236 static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = {
12237   { { STATE_PSEXCM }, 'i' },
12238   { { STATE_PSRING }, 'i' }
12239 };
12240
12241 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
12242   { { OPERAND_art }, 'o' }
12243 };
12244
12245 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = {
12246   { { STATE_PSEXCM }, 'i' },
12247   { { STATE_PSRING }, 'i' }
12248 };
12249
12250 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
12251   { { OPERAND_art }, 'o' }
12252 };
12253
12254 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
12255   { { STATE_PSWOE }, 'i' },
12256   { { STATE_PSCALLINC }, 'i' },
12257   { { STATE_PSOWB }, 'i' },
12258   { { STATE_PSRING }, 'i' },
12259   { { STATE_PSUM }, 'i' },
12260   { { STATE_PSEXCM }, 'i' },
12261   { { STATE_PSINTLEVEL }, 'i' }
12262 };
12263
12264 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
12265   { { OPERAND_art }, 'i' }
12266 };
12267
12268 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
12269   { { STATE_PSWOE }, 'o' },
12270   { { STATE_PSCALLINC }, 'o' },
12271   { { STATE_PSOWB }, 'o' },
12272   { { STATE_PSRING }, 'm' },
12273   { { STATE_PSUM }, 'o' },
12274   { { STATE_PSEXCM }, 'm' },
12275   { { STATE_PSINTLEVEL }, 'o' }
12276 };
12277
12278 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
12279   { { OPERAND_art }, 'm' }
12280 };
12281
12282 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
12283   { { STATE_PSWOE }, 'm' },
12284   { { STATE_PSCALLINC }, 'm' },
12285   { { STATE_PSOWB }, 'm' },
12286   { { STATE_PSRING }, 'm' },
12287   { { STATE_PSUM }, 'm' },
12288   { { STATE_PSEXCM }, 'm' },
12289   { { STATE_PSINTLEVEL }, 'm' }
12290 };
12291
12292 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
12293   { { OPERAND_art }, 'o' }
12294 };
12295
12296 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
12297   { { STATE_PSEXCM }, 'i' },
12298   { { STATE_PSRING }, 'i' },
12299   { { STATE_EPC1 }, 'i' }
12300 };
12301
12302 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
12303   { { OPERAND_art }, 'i' }
12304 };
12305
12306 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
12307   { { STATE_PSEXCM }, 'i' },
12308   { { STATE_PSRING }, 'i' },
12309   { { STATE_EPC1 }, 'o' }
12310 };
12311
12312 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
12313   { { OPERAND_art }, 'm' }
12314 };
12315
12316 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
12317   { { STATE_PSEXCM }, 'i' },
12318   { { STATE_PSRING }, 'i' },
12319   { { STATE_EPC1 }, 'm' }
12320 };
12321
12322 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
12323   { { OPERAND_art }, 'o' }
12324 };
12325
12326 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
12327   { { STATE_PSEXCM }, 'i' },
12328   { { STATE_PSRING }, 'i' },
12329   { { STATE_EXCSAVE1 }, 'i' }
12330 };
12331
12332 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
12333   { { OPERAND_art }, 'i' }
12334 };
12335
12336 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
12337   { { STATE_PSEXCM }, 'i' },
12338   { { STATE_PSRING }, 'i' },
12339   { { STATE_EXCSAVE1 }, 'o' }
12340 };
12341
12342 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
12343   { { OPERAND_art }, 'm' }
12344 };
12345
12346 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
12347   { { STATE_PSEXCM }, 'i' },
12348   { { STATE_PSRING }, 'i' },
12349   { { STATE_EXCSAVE1 }, 'm' }
12350 };
12351
12352 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
12353   { { OPERAND_art }, 'o' }
12354 };
12355
12356 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
12357   { { STATE_PSEXCM }, 'i' },
12358   { { STATE_PSRING }, 'i' },
12359   { { STATE_EPC2 }, 'i' }
12360 };
12361
12362 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
12363   { { OPERAND_art }, 'i' }
12364 };
12365
12366 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
12367   { { STATE_PSEXCM }, 'i' },
12368   { { STATE_PSRING }, 'i' },
12369   { { STATE_EPC2 }, 'o' }
12370 };
12371
12372 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
12373   { { OPERAND_art }, 'm' }
12374 };
12375
12376 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
12377   { { STATE_PSEXCM }, 'i' },
12378   { { STATE_PSRING }, 'i' },
12379   { { STATE_EPC2 }, 'm' }
12380 };
12381
12382 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
12383   { { OPERAND_art }, 'o' }
12384 };
12385
12386 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
12387   { { STATE_PSEXCM }, 'i' },
12388   { { STATE_PSRING }, 'i' },
12389   { { STATE_EXCSAVE2 }, 'i' }
12390 };
12391
12392 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
12393   { { OPERAND_art }, 'i' }
12394 };
12395
12396 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
12397   { { STATE_PSEXCM }, 'i' },
12398   { { STATE_PSRING }, 'i' },
12399   { { STATE_EXCSAVE2 }, 'o' }
12400 };
12401
12402 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
12403   { { OPERAND_art }, 'm' }
12404 };
12405
12406 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
12407   { { STATE_PSEXCM }, 'i' },
12408   { { STATE_PSRING }, 'i' },
12409   { { STATE_EXCSAVE2 }, 'm' }
12410 };
12411
12412 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
12413   { { OPERAND_art }, 'o' }
12414 };
12415
12416 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
12417   { { STATE_PSEXCM }, 'i' },
12418   { { STATE_PSRING }, 'i' },
12419   { { STATE_EPS2 }, 'i' }
12420 };
12421
12422 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
12423   { { OPERAND_art }, 'i' }
12424 };
12425
12426 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
12427   { { STATE_PSEXCM }, 'i' },
12428   { { STATE_PSRING }, 'i' },
12429   { { STATE_EPS2 }, 'o' }
12430 };
12431
12432 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
12433   { { OPERAND_art }, 'm' }
12434 };
12435
12436 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
12437   { { STATE_PSEXCM }, 'i' },
12438   { { STATE_PSRING }, 'i' },
12439   { { STATE_EPS2 }, 'm' }
12440 };
12441
12442 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
12443   { { OPERAND_art }, 'o' }
12444 };
12445
12446 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
12447   { { STATE_PSEXCM }, 'i' },
12448   { { STATE_PSRING }, 'i' },
12449   { { STATE_EXCVADDR }, 'i' }
12450 };
12451
12452 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
12453   { { OPERAND_art }, 'i' }
12454 };
12455
12456 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
12457   { { STATE_PSEXCM }, 'i' },
12458   { { STATE_PSRING }, 'i' },
12459   { { STATE_EXCVADDR }, 'o' }
12460 };
12461
12462 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
12463   { { OPERAND_art }, 'm' }
12464 };
12465
12466 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
12467   { { STATE_PSEXCM }, 'i' },
12468   { { STATE_PSRING }, 'i' },
12469   { { STATE_EXCVADDR }, 'm' }
12470 };
12471
12472 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
12473   { { OPERAND_art }, 'o' }
12474 };
12475
12476 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
12477   { { STATE_PSEXCM }, 'i' },
12478   { { STATE_PSRING }, 'i' },
12479   { { STATE_DEPC }, 'i' }
12480 };
12481
12482 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
12483   { { OPERAND_art }, 'i' }
12484 };
12485
12486 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
12487   { { STATE_PSEXCM }, 'i' },
12488   { { STATE_PSRING }, 'i' },
12489   { { STATE_DEPC }, 'o' }
12490 };
12491
12492 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
12493   { { OPERAND_art }, 'm' }
12494 };
12495
12496 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
12497   { { STATE_PSEXCM }, 'i' },
12498   { { STATE_PSRING }, 'i' },
12499   { { STATE_DEPC }, 'm' }
12500 };
12501
12502 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
12503   { { OPERAND_art }, 'o' }
12504 };
12505
12506 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
12507   { { STATE_PSEXCM }, 'i' },
12508   { { STATE_PSRING }, 'i' },
12509   { { STATE_EXCCAUSE }, 'i' },
12510   { { STATE_XTSYNC }, 'i' }
12511 };
12512
12513 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
12514   { { OPERAND_art }, 'i' }
12515 };
12516
12517 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
12518   { { STATE_PSEXCM }, 'i' },
12519   { { STATE_PSRING }, 'i' },
12520   { { STATE_EXCCAUSE }, 'o' }
12521 };
12522
12523 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
12524   { { OPERAND_art }, 'm' }
12525 };
12526
12527 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
12528   { { STATE_PSEXCM }, 'i' },
12529   { { STATE_PSRING }, 'i' },
12530   { { STATE_EXCCAUSE }, 'm' }
12531 };
12532
12533 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
12534   { { OPERAND_art }, 'o' }
12535 };
12536
12537 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
12538   { { STATE_PSEXCM }, 'i' },
12539   { { STATE_PSRING }, 'i' },
12540   { { STATE_MISC0 }, 'i' }
12541 };
12542
12543 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
12544   { { OPERAND_art }, 'i' }
12545 };
12546
12547 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
12548   { { STATE_PSEXCM }, 'i' },
12549   { { STATE_PSRING }, 'i' },
12550   { { STATE_MISC0 }, 'o' }
12551 };
12552
12553 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
12554   { { OPERAND_art }, 'm' }
12555 };
12556
12557 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
12558   { { STATE_PSEXCM }, 'i' },
12559   { { STATE_PSRING }, 'i' },
12560   { { STATE_MISC0 }, 'm' }
12561 };
12562
12563 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
12564   { { OPERAND_art }, 'o' }
12565 };
12566
12567 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
12568   { { STATE_PSEXCM }, 'i' },
12569   { { STATE_PSRING }, 'i' },
12570   { { STATE_MISC1 }, 'i' }
12571 };
12572
12573 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
12574   { { OPERAND_art }, 'i' }
12575 };
12576
12577 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
12578   { { STATE_PSEXCM }, 'i' },
12579   { { STATE_PSRING }, 'i' },
12580   { { STATE_MISC1 }, 'o' }
12581 };
12582
12583 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
12584   { { OPERAND_art }, 'm' }
12585 };
12586
12587 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
12588   { { STATE_PSEXCM }, 'i' },
12589   { { STATE_PSRING }, 'i' },
12590   { { STATE_MISC1 }, 'm' }
12591 };
12592
12593 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
12594   { { OPERAND_art }, 'o' }
12595 };
12596
12597 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
12598   { { STATE_PSEXCM }, 'i' },
12599   { { STATE_PSRING }, 'i' }
12600 };
12601
12602 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
12603   { { OPERAND_art }, 'o' }
12604 };
12605
12606 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
12607   { { STATE_PSEXCM }, 'i' },
12608   { { STATE_PSRING }, 'i' },
12609   { { STATE_VECBASE }, 'i' }
12610 };
12611
12612 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
12613   { { OPERAND_art }, 'i' }
12614 };
12615
12616 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
12617   { { STATE_PSEXCM }, 'i' },
12618   { { STATE_PSRING }, 'i' },
12619   { { STATE_VECBASE }, 'o' }
12620 };
12621
12622 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
12623   { { OPERAND_art }, 'm' }
12624 };
12625
12626 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
12627   { { STATE_PSEXCM }, 'i' },
12628   { { STATE_PSRING }, 'i' },
12629   { { STATE_VECBASE }, 'm' }
12630 };
12631
12632 static xtensa_arg_internal Iclass_xt_mul16_args[] = {
12633   { { OPERAND_arr }, 'o' },
12634   { { OPERAND_ars }, 'i' },
12635   { { OPERAND_art }, 'i' }
12636 };
12637
12638 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
12639   { { OPERAND_arr }, 'o' },
12640   { { OPERAND_ars }, 'i' },
12641   { { OPERAND_art }, 'i' }
12642 };
12643
12644 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
12645   { { OPERAND_s }, 'i' }
12646 };
12647
12648 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
12649   { { STATE_PSWOE }, 'o' },
12650   { { STATE_PSCALLINC }, 'o' },
12651   { { STATE_PSOWB }, 'o' },
12652   { { STATE_PSRING }, 'm' },
12653   { { STATE_PSUM }, 'o' },
12654   { { STATE_PSEXCM }, 'm' },
12655   { { STATE_PSINTLEVEL }, 'o' },
12656   { { STATE_EPC1 }, 'i' },
12657   { { STATE_EPC2 }, 'i' },
12658   { { STATE_EPS2 }, 'i' },
12659   { { STATE_InOCDMode }, 'm' }
12660 };
12661
12662 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
12663   { { OPERAND_s }, 'i' }
12664 };
12665
12666 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
12667   { { STATE_PSEXCM }, 'i' },
12668   { { STATE_PSRING }, 'i' },
12669   { { STATE_PSINTLEVEL }, 'o' }
12670 };
12671
12672 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
12673   { { OPERAND_art }, 'o' }
12674 };
12675
12676 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
12677   { { STATE_PSEXCM }, 'i' },
12678   { { STATE_PSRING }, 'i' },
12679   { { STATE_INTERRUPT }, 'i' }
12680 };
12681
12682 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
12683   { { OPERAND_art }, 'i' }
12684 };
12685
12686 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
12687   { { STATE_PSEXCM }, 'i' },
12688   { { STATE_PSRING }, 'i' },
12689   { { STATE_XTSYNC }, 'o' },
12690   { { STATE_INTERRUPT }, 'm' }
12691 };
12692
12693 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
12694   { { OPERAND_art }, 'i' }
12695 };
12696
12697 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
12698   { { STATE_PSEXCM }, 'i' },
12699   { { STATE_PSRING }, 'i' },
12700   { { STATE_XTSYNC }, 'o' },
12701   { { STATE_INTERRUPT }, 'm' }
12702 };
12703
12704 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
12705   { { OPERAND_art }, 'o' }
12706 };
12707
12708 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
12709   { { STATE_PSEXCM }, 'i' },
12710   { { STATE_PSRING }, 'i' },
12711   { { STATE_INTENABLE }, 'i' }
12712 };
12713
12714 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
12715   { { OPERAND_art }, 'i' }
12716 };
12717
12718 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
12719   { { STATE_PSEXCM }, 'i' },
12720   { { STATE_PSRING }, 'i' },
12721   { { STATE_INTENABLE }, 'o' }
12722 };
12723
12724 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
12725   { { OPERAND_art }, 'm' }
12726 };
12727
12728 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
12729   { { STATE_PSEXCM }, 'i' },
12730   { { STATE_PSRING }, 'i' },
12731   { { STATE_INTENABLE }, 'm' }
12732 };
12733
12734 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
12735   { { OPERAND_imms }, 'i' },
12736   { { OPERAND_immt }, 'i' }
12737 };
12738
12739 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
12740   { { STATE_PSEXCM }, 'i' },
12741   { { STATE_PSINTLEVEL }, 'i' }
12742 };
12743
12744 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
12745   { { OPERAND_imms }, 'i' }
12746 };
12747
12748 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
12749   { { STATE_PSEXCM }, 'i' },
12750   { { STATE_PSINTLEVEL }, 'i' }
12751 };
12752
12753 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
12754   { { OPERAND_art }, 'o' }
12755 };
12756
12757 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
12758   { { STATE_PSEXCM }, 'i' },
12759   { { STATE_PSRING }, 'i' },
12760   { { STATE_DEBUGCAUSE }, 'i' },
12761   { { STATE_DBNUM }, 'i' }
12762 };
12763
12764 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
12765   { { OPERAND_art }, 'i' }
12766 };
12767
12768 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
12769   { { STATE_PSEXCM }, 'i' },
12770   { { STATE_PSRING }, 'i' },
12771   { { STATE_DEBUGCAUSE }, 'o' },
12772   { { STATE_DBNUM }, 'o' }
12773 };
12774
12775 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
12776   { { OPERAND_art }, 'm' }
12777 };
12778
12779 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
12780   { { STATE_PSEXCM }, 'i' },
12781   { { STATE_PSRING }, 'i' },
12782   { { STATE_DEBUGCAUSE }, 'm' },
12783   { { STATE_DBNUM }, 'm' }
12784 };
12785
12786 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
12787   { { OPERAND_art }, 'o' }
12788 };
12789
12790 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
12791   { { STATE_PSEXCM }, 'i' },
12792   { { STATE_PSRING }, 'i' },
12793   { { STATE_ICOUNT }, 'i' }
12794 };
12795
12796 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
12797   { { OPERAND_art }, 'i' }
12798 };
12799
12800 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
12801   { { STATE_PSEXCM }, 'i' },
12802   { { STATE_PSRING }, 'i' },
12803   { { STATE_XTSYNC }, 'o' },
12804   { { STATE_ICOUNT }, 'o' }
12805 };
12806
12807 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
12808   { { OPERAND_art }, 'm' }
12809 };
12810
12811 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
12812   { { STATE_PSEXCM }, 'i' },
12813   { { STATE_PSRING }, 'i' },
12814   { { STATE_XTSYNC }, 'o' },
12815   { { STATE_ICOUNT }, 'm' }
12816 };
12817
12818 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
12819   { { OPERAND_art }, 'o' }
12820 };
12821
12822 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
12823   { { STATE_PSEXCM }, 'i' },
12824   { { STATE_PSRING }, 'i' },
12825   { { STATE_ICOUNTLEVEL }, 'i' }
12826 };
12827
12828 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
12829   { { OPERAND_art }, 'i' }
12830 };
12831
12832 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
12833   { { STATE_PSEXCM }, 'i' },
12834   { { STATE_PSRING }, 'i' },
12835   { { STATE_ICOUNTLEVEL }, 'o' }
12836 };
12837
12838 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
12839   { { OPERAND_art }, 'm' }
12840 };
12841
12842 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
12843   { { STATE_PSEXCM }, 'i' },
12844   { { STATE_PSRING }, 'i' },
12845   { { STATE_ICOUNTLEVEL }, 'm' }
12846 };
12847
12848 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
12849   { { OPERAND_art }, 'o' }
12850 };
12851
12852 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
12853   { { STATE_PSEXCM }, 'i' },
12854   { { STATE_PSRING }, 'i' },
12855   { { STATE_DDR }, 'i' }
12856 };
12857
12858 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
12859   { { OPERAND_art }, 'i' }
12860 };
12861
12862 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
12863   { { STATE_PSEXCM }, 'i' },
12864   { { STATE_PSRING }, 'i' },
12865   { { STATE_XTSYNC }, 'o' },
12866   { { STATE_DDR }, 'o' }
12867 };
12868
12869 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
12870   { { OPERAND_art }, 'm' }
12871 };
12872
12873 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
12874   { { STATE_PSEXCM }, 'i' },
12875   { { STATE_PSRING }, 'i' },
12876   { { STATE_XTSYNC }, 'o' },
12877   { { STATE_DDR }, 'm' }
12878 };
12879
12880 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
12881   { { OPERAND_imms }, 'i' }
12882 };
12883
12884 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
12885   { { STATE_InOCDMode }, 'm' },
12886   { { STATE_EPC2 }, 'i' },
12887   { { STATE_PSWOE }, 'o' },
12888   { { STATE_PSCALLINC }, 'o' },
12889   { { STATE_PSOWB }, 'o' },
12890   { { STATE_PSRING }, 'o' },
12891   { { STATE_PSUM }, 'o' },
12892   { { STATE_PSEXCM }, 'o' },
12893   { { STATE_PSINTLEVEL }, 'o' },
12894   { { STATE_EPS2 }, 'i' }
12895 };
12896
12897 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
12898   { { STATE_InOCDMode }, 'm' }
12899 };
12900
12901 static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
12902   { { OPERAND_br }, 'o' },
12903   { { OPERAND_bs }, 'i' },
12904   { { OPERAND_bt }, 'i' }
12905 };
12906
12907 static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
12908   { { OPERAND_bt }, 'o' },
12909   { { OPERAND_bs4 }, 'i' }
12910 };
12911
12912 static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
12913   { { OPERAND_bt }, 'o' },
12914   { { OPERAND_bs8 }, 'i' }
12915 };
12916
12917 static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
12918   { { OPERAND_bs }, 'i' },
12919   { { OPERAND_label8 }, 'i' }
12920 };
12921
12922 static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
12923   { { OPERAND_arr }, 'm' },
12924   { { OPERAND_ars }, 'i' },
12925   { { OPERAND_bt }, 'i' }
12926 };
12927
12928 static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
12929   { { OPERAND_art }, 'o' },
12930   { { OPERAND_brall }, 'i' }
12931 };
12932
12933 static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
12934   { { OPERAND_art }, 'i' },
12935   { { OPERAND_brall }, 'o' }
12936 };
12937
12938 static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
12939   { { OPERAND_art }, 'm' },
12940   { { OPERAND_brall }, 'm' }
12941 };
12942
12943 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
12944   { { OPERAND_art }, 'o' }
12945 };
12946
12947 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
12948   { { STATE_PSEXCM }, 'i' },
12949   { { STATE_PSRING }, 'i' },
12950   { { STATE_CCOUNT }, 'i' }
12951 };
12952
12953 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
12954   { { OPERAND_art }, 'i' }
12955 };
12956
12957 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
12958   { { STATE_PSEXCM }, 'i' },
12959   { { STATE_PSRING }, 'i' },
12960   { { STATE_XTSYNC }, 'o' },
12961   { { STATE_CCOUNT }, 'o' }
12962 };
12963
12964 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
12965   { { OPERAND_art }, 'm' }
12966 };
12967
12968 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
12969   { { STATE_PSEXCM }, 'i' },
12970   { { STATE_PSRING }, 'i' },
12971   { { STATE_XTSYNC }, 'o' },
12972   { { STATE_CCOUNT }, 'm' }
12973 };
12974
12975 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
12976   { { OPERAND_art }, 'o' }
12977 };
12978
12979 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
12980   { { STATE_PSEXCM }, 'i' },
12981   { { STATE_PSRING }, 'i' },
12982   { { STATE_CCOMPARE0 }, 'i' }
12983 };
12984
12985 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
12986   { { OPERAND_art }, 'i' }
12987 };
12988
12989 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
12990   { { STATE_PSEXCM }, 'i' },
12991   { { STATE_PSRING }, 'i' },
12992   { { STATE_CCOMPARE0 }, 'o' },
12993   { { STATE_INTERRUPT }, 'm' }
12994 };
12995
12996 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
12997   { { OPERAND_art }, 'm' }
12998 };
12999
13000 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
13001   { { STATE_PSEXCM }, 'i' },
13002   { { STATE_PSRING }, 'i' },
13003   { { STATE_CCOMPARE0 }, 'm' },
13004   { { STATE_INTERRUPT }, 'm' }
13005 };
13006
13007 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
13008   { { OPERAND_art }, 'o' }
13009 };
13010
13011 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
13012   { { STATE_PSEXCM }, 'i' },
13013   { { STATE_PSRING }, 'i' },
13014   { { STATE_CCOMPARE1 }, 'i' }
13015 };
13016
13017 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
13018   { { OPERAND_art }, 'i' }
13019 };
13020
13021 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
13022   { { STATE_PSEXCM }, 'i' },
13023   { { STATE_PSRING }, 'i' },
13024   { { STATE_CCOMPARE1 }, 'o' },
13025   { { STATE_INTERRUPT }, 'm' }
13026 };
13027
13028 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
13029   { { OPERAND_art }, 'm' }
13030 };
13031
13032 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
13033   { { STATE_PSEXCM }, 'i' },
13034   { { STATE_PSRING }, 'i' },
13035   { { STATE_CCOMPARE1 }, 'm' },
13036   { { STATE_INTERRUPT }, 'm' }
13037 };
13038
13039 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
13040   { { OPERAND_ars }, 'i' },
13041   { { OPERAND_uimm8x4 }, 'i' }
13042 };
13043
13044 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
13045   { { OPERAND_ars }, 'i' },
13046   { { OPERAND_uimm8x4 }, 'i' }
13047 };
13048
13049 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
13050   { { STATE_PSEXCM }, 'i' },
13051   { { STATE_PSRING }, 'i' }
13052 };
13053
13054 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
13055   { { OPERAND_art }, 'o' },
13056   { { OPERAND_ars }, 'i' }
13057 };
13058
13059 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
13060   { { STATE_PSEXCM }, 'i' },
13061   { { STATE_PSRING }, 'i' }
13062 };
13063
13064 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
13065   { { OPERAND_art }, 'i' },
13066   { { OPERAND_ars }, 'i' }
13067 };
13068
13069 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
13070   { { STATE_PSEXCM }, 'i' },
13071   { { STATE_PSRING }, 'i' }
13072 };
13073
13074 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
13075   { { OPERAND_ars }, 'i' },
13076   { { OPERAND_uimm8x4 }, 'i' }
13077 };
13078
13079 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
13080   { { OPERAND_ars }, 'i' },
13081   { { OPERAND_uimm4x16 }, 'i' }
13082 };
13083
13084 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
13085   { { STATE_PSEXCM }, 'i' },
13086   { { STATE_PSRING }, 'i' }
13087 };
13088
13089 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
13090   { { OPERAND_ars }, 'i' },
13091   { { OPERAND_uimm8x4 }, 'i' }
13092 };
13093
13094 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
13095   { { STATE_PSEXCM }, 'i' },
13096   { { STATE_PSRING }, 'i' }
13097 };
13098
13099 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
13100   { { OPERAND_ars }, 'i' },
13101   { { OPERAND_uimm8x4 }, 'i' }
13102 };
13103
13104 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
13105   { { OPERAND_art }, 'i' },
13106   { { OPERAND_ars }, 'i' }
13107 };
13108
13109 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
13110   { { STATE_PSEXCM }, 'i' },
13111   { { STATE_PSRING }, 'i' }
13112 };
13113
13114 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
13115   { { OPERAND_art }, 'o' },
13116   { { OPERAND_ars }, 'i' }
13117 };
13118
13119 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
13120   { { STATE_PSEXCM }, 'i' },
13121   { { STATE_PSRING }, 'i' }
13122 };
13123
13124 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
13125   { { OPERAND_art }, 'i' }
13126 };
13127
13128 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
13129   { { STATE_PSEXCM }, 'i' },
13130   { { STATE_PSRING }, 'i' },
13131   { { STATE_PTBASE }, 'o' },
13132   { { STATE_XTSYNC }, 'o' }
13133 };
13134
13135 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
13136   { { OPERAND_art }, 'o' }
13137 };
13138
13139 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
13140   { { STATE_PSEXCM }, 'i' },
13141   { { STATE_PSRING }, 'i' },
13142   { { STATE_PTBASE }, 'i' },
13143   { { STATE_EXCVADDR }, 'i' }
13144 };
13145
13146 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
13147   { { OPERAND_art }, 'm' }
13148 };
13149
13150 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
13151   { { STATE_PSEXCM }, 'i' },
13152   { { STATE_PSRING }, 'i' },
13153   { { STATE_PTBASE }, 'm' },
13154   { { STATE_EXCVADDR }, 'i' },
13155   { { STATE_XTSYNC }, 'o' }
13156 };
13157
13158 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
13159   { { OPERAND_art }, 'o' }
13160 };
13161
13162 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
13163   { { STATE_PSEXCM }, 'i' },
13164   { { STATE_PSRING }, 'i' },
13165   { { STATE_ASID3 }, 'i' },
13166   { { STATE_ASID2 }, 'i' },
13167   { { STATE_ASID1 }, 'i' }
13168 };
13169
13170 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
13171   { { OPERAND_art }, 'i' }
13172 };
13173
13174 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
13175   { { STATE_XTSYNC }, 'o' },
13176   { { STATE_PSEXCM }, 'i' },
13177   { { STATE_PSRING }, 'i' },
13178   { { STATE_ASID3 }, 'o' },
13179   { { STATE_ASID2 }, 'o' },
13180   { { STATE_ASID1 }, 'o' }
13181 };
13182
13183 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
13184   { { OPERAND_art }, 'm' }
13185 };
13186
13187 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
13188   { { STATE_XTSYNC }, 'o' },
13189   { { STATE_PSEXCM }, 'i' },
13190   { { STATE_PSRING }, 'i' },
13191   { { STATE_ASID3 }, 'm' },
13192   { { STATE_ASID2 }, 'm' },
13193   { { STATE_ASID1 }, 'm' }
13194 };
13195
13196 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
13197   { { OPERAND_art }, 'o' }
13198 };
13199
13200 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
13201   { { STATE_PSEXCM }, 'i' },
13202   { { STATE_PSRING }, 'i' },
13203   { { STATE_INSTPGSZID4 }, 'i' }
13204 };
13205
13206 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
13207   { { OPERAND_art }, 'i' }
13208 };
13209
13210 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
13211   { { STATE_XTSYNC }, 'o' },
13212   { { STATE_PSEXCM }, 'i' },
13213   { { STATE_PSRING }, 'i' },
13214   { { STATE_INSTPGSZID4 }, 'o' }
13215 };
13216
13217 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
13218   { { OPERAND_art }, 'm' }
13219 };
13220
13221 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
13222   { { STATE_XTSYNC }, 'o' },
13223   { { STATE_PSEXCM }, 'i' },
13224   { { STATE_PSRING }, 'i' },
13225   { { STATE_INSTPGSZID4 }, 'm' }
13226 };
13227
13228 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
13229   { { OPERAND_art }, 'o' }
13230 };
13231
13232 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
13233   { { STATE_PSEXCM }, 'i' },
13234   { { STATE_PSRING }, 'i' },
13235   { { STATE_DATAPGSZID4 }, 'i' }
13236 };
13237
13238 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
13239   { { OPERAND_art }, 'i' }
13240 };
13241
13242 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
13243   { { STATE_XTSYNC }, 'o' },
13244   { { STATE_PSEXCM }, 'i' },
13245   { { STATE_PSRING }, 'i' },
13246   { { STATE_DATAPGSZID4 }, 'o' }
13247 };
13248
13249 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
13250   { { OPERAND_art }, 'm' }
13251 };
13252
13253 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
13254   { { STATE_XTSYNC }, 'o' },
13255   { { STATE_PSEXCM }, 'i' },
13256   { { STATE_PSRING }, 'i' },
13257   { { STATE_DATAPGSZID4 }, 'm' }
13258 };
13259
13260 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
13261   { { OPERAND_ars }, 'i' }
13262 };
13263
13264 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
13265   { { STATE_PSEXCM }, 'i' },
13266   { { STATE_PSRING }, 'i' },
13267   { { STATE_XTSYNC }, 'o' }
13268 };
13269
13270 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
13271   { { OPERAND_art }, 'o' },
13272   { { OPERAND_ars }, 'i' }
13273 };
13274
13275 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
13276   { { STATE_PSEXCM }, 'i' },
13277   { { STATE_PSRING }, 'i' }
13278 };
13279
13280 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
13281   { { OPERAND_art }, 'i' },
13282   { { OPERAND_ars }, 'i' }
13283 };
13284
13285 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
13286   { { STATE_PSEXCM }, 'i' },
13287   { { STATE_PSRING }, 'i' },
13288   { { STATE_XTSYNC }, 'o' }
13289 };
13290
13291 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
13292   { { OPERAND_ars }, 'i' }
13293 };
13294
13295 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
13296   { { STATE_PSEXCM }, 'i' },
13297   { { STATE_PSRING }, 'i' }
13298 };
13299
13300 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
13301   { { OPERAND_art }, 'o' },
13302   { { OPERAND_ars }, 'i' }
13303 };
13304
13305 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
13306   { { STATE_PSEXCM }, 'i' },
13307   { { STATE_PSRING }, 'i' }
13308 };
13309
13310 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
13311   { { OPERAND_art }, 'i' },
13312   { { OPERAND_ars }, 'i' }
13313 };
13314
13315 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
13316   { { STATE_PSEXCM }, 'i' },
13317   { { STATE_PSRING }, 'i' }
13318 };
13319
13320 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
13321   { { STATE_PTBASE }, 'i' },
13322   { { STATE_EXCVADDR }, 'i' }
13323 };
13324
13325 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
13326   { { STATE_EXCVADDR }, 'i' }
13327 };
13328
13329 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
13330   { { STATE_EXCVADDR }, 'i' }
13331 };
13332
13333 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
13334   { { OPERAND_art }, 'o' }
13335 };
13336
13337 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
13338   { { STATE_PSEXCM }, 'i' },
13339   { { STATE_PSRING }, 'i' },
13340   { { STATE_CPENABLE }, 'i' }
13341 };
13342
13343 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
13344   { { OPERAND_art }, 'i' }
13345 };
13346
13347 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
13348   { { STATE_PSEXCM }, 'i' },
13349   { { STATE_PSRING }, 'i' },
13350   { { STATE_CPENABLE }, 'o' }
13351 };
13352
13353 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
13354   { { OPERAND_art }, 'm' }
13355 };
13356
13357 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
13358   { { STATE_PSEXCM }, 'i' },
13359   { { STATE_PSRING }, 'i' },
13360   { { STATE_CPENABLE }, 'm' }
13361 };
13362
13363 static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
13364   { { OPERAND_arr }, 'o' },
13365   { { OPERAND_ars }, 'i' },
13366   { { OPERAND_tp7 }, 'i' }
13367 };
13368
13369 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
13370   { { OPERAND_arr }, 'o' },
13371   { { OPERAND_ars }, 'i' },
13372   { { OPERAND_art }, 'i' }
13373 };
13374
13375 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
13376   { { OPERAND_art }, 'o' },
13377   { { OPERAND_ars }, 'i' }
13378 };
13379
13380 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
13381   { { OPERAND_arr }, 'o' },
13382   { { OPERAND_ars }, 'i' },
13383   { { OPERAND_tp7 }, 'i' }
13384 };
13385
13386 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
13387   { { OPERAND_art }, 'o' },
13388   { { OPERAND_ars }, 'i' },
13389   { { OPERAND_uimm8x4 }, 'i' }
13390 };
13391
13392 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
13393   { { OPERAND_art }, 'i' },
13394   { { OPERAND_ars }, 'i' },
13395   { { OPERAND_uimm8x4 }, 'i' }
13396 };
13397
13398 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
13399   { { OPERAND_art }, 'm' },
13400   { { OPERAND_ars }, 'i' },
13401   { { OPERAND_uimm8x4 }, 'i' }
13402 };
13403
13404 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
13405   { { STATE_SCOMPARE1 }, 'i' },
13406   { { STATE_XTSYNC }, 'i' },
13407   { { STATE_SCOMPARE1 }, 'i' }
13408 };
13409
13410 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
13411   { { OPERAND_art }, 'o' }
13412 };
13413
13414 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
13415   { { STATE_SCOMPARE1 }, 'i' }
13416 };
13417
13418 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
13419   { { OPERAND_art }, 'i' }
13420 };
13421
13422 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
13423   { { STATE_SCOMPARE1 }, 'o' }
13424 };
13425
13426 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
13427   { { OPERAND_art }, 'm' }
13428 };
13429
13430 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
13431   { { STATE_SCOMPARE1 }, 'm' }
13432 };
13433
13434 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
13435   { { OPERAND_art }, 'o' }
13436 };
13437
13438 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
13439   { { STATE_PSEXCM }, 'i' },
13440   { { STATE_PSRING }, 'i' },
13441   { { STATE_ATOMCTL }, 'i' }
13442 };
13443
13444 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
13445   { { OPERAND_art }, 'i' }
13446 };
13447
13448 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
13449   { { STATE_PSEXCM }, 'i' },
13450   { { STATE_PSRING }, 'i' },
13451   { { STATE_ATOMCTL }, 'o' },
13452   { { STATE_XTSYNC }, 'o' }
13453 };
13454
13455 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
13456   { { OPERAND_art }, 'm' }
13457 };
13458
13459 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
13460   { { STATE_PSEXCM }, 'i' },
13461   { { STATE_PSRING }, 'i' },
13462   { { STATE_ATOMCTL }, 'm' },
13463   { { STATE_XTSYNC }, 'o' }
13464 };
13465
13466 static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
13467   { { OPERAND_art }, 'o' },
13468   { { OPERAND_ars }, 'i' }
13469 };
13470
13471 static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
13472   { { STATE_CCON }, 'i' },
13473   { { STATE_PSEXCM }, 'i' },
13474   { { STATE_PSRING }, 'i' },
13475   { { STATE_MPSCORE }, 'i' }
13476 };
13477
13478 static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
13479   INTERFACE_RMPINT_Out,
13480   INTERFACE_RMPINT_In
13481 };
13482
13483 static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
13484   { { OPERAND_art }, 'i' },
13485   { { OPERAND_ars }, 'i' }
13486 };
13487
13488 static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
13489   { { STATE_CCON }, 'm' },
13490   { { STATE_PSEXCM }, 'i' },
13491   { { STATE_PSRING }, 'i' },
13492   { { STATE_WMPINT_DATA }, 'o' },
13493   { { STATE_WMPINT_ADDR }, 'o' },
13494   { { STATE_MPSCORE }, 'm' },
13495   { { STATE_WMPINT_TOGGLEEN }, 'm' }
13496 };
13497
13498 static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = {
13499   { { OPERAND_arr }, 'o' }
13500 };
13501
13502 static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = {
13503   { { STATE_AE_OVERFLOW }, 'i' },
13504   { { STATE_AE_SAR }, 'i' },
13505   { { STATE_CPENABLE }, 'i' }
13506 };
13507
13508 static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = {
13509   { { OPERAND_art }, 'i' }
13510 };
13511
13512 static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = {
13513   { { STATE_AE_OVERFLOW }, 'o' },
13514   { { STATE_AE_SAR }, 'o' },
13515   { { STATE_CPENABLE }, 'i' }
13516 };
13517
13518 static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = {
13519   { { OPERAND_arr }, 'o' }
13520 };
13521
13522 static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = {
13523   { { STATE_AE_BITHEAD }, 'i' },
13524   { { STATE_CPENABLE }, 'i' }
13525 };
13526
13527 static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = {
13528   { { OPERAND_art }, 'i' }
13529 };
13530
13531 static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = {
13532   { { STATE_AE_BITHEAD }, 'o' },
13533   { { STATE_CPENABLE }, 'i' }
13534 };
13535
13536 static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = {
13537   { { OPERAND_arr }, 'o' }
13538 };
13539
13540 static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = {
13541   { { STATE_AE_BITPTR }, 'i' },
13542   { { STATE_AE_BITSUSED }, 'i' },
13543   { { STATE_AE_TABLESIZE }, 'i' },
13544   { { STATE_AE_FIRST_TS }, 'i' },
13545   { { STATE_CPENABLE }, 'i' }
13546 };
13547
13548 static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = {
13549   { { OPERAND_art }, 'i' }
13550 };
13551
13552 static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = {
13553   { { STATE_AE_BITPTR }, 'o' },
13554   { { STATE_AE_BITSUSED }, 'o' },
13555   { { STATE_AE_TABLESIZE }, 'o' },
13556   { { STATE_AE_FIRST_TS }, 'o' },
13557   { { STATE_CPENABLE }, 'i' }
13558 };
13559
13560 static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = {
13561   { { OPERAND_arr }, 'o' }
13562 };
13563
13564 static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = {
13565   { { STATE_AE_NEXTOFFSET }, 'i' },
13566   { { STATE_AE_SEARCHDONE }, 'i' },
13567   { { STATE_CPENABLE }, 'i' }
13568 };
13569
13570 static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = {
13571   { { OPERAND_art }, 'i' }
13572 };
13573
13574 static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = {
13575   { { STATE_AE_NEXTOFFSET }, 'o' },
13576   { { STATE_AE_SEARCHDONE }, 'o' },
13577   { { STATE_CPENABLE }, 'i' }
13578 };
13579
13580 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = {
13581   { { OPERAND_arr }, 'o' }
13582 };
13583
13584 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = {
13585   { { STATE_AE_OVERFLOW }, 'i' },
13586   { { STATE_CPENABLE }, 'i' }
13587 };
13588
13589 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = {
13590   { { OPERAND_art }, 'i' }
13591 };
13592
13593 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = {
13594   { { STATE_AE_OVERFLOW }, 'o' },
13595   { { STATE_CPENABLE }, 'i' }
13596 };
13597
13598 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = {
13599   { { OPERAND_arr }, 'o' }
13600 };
13601
13602 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = {
13603   { { STATE_AE_SAR }, 'i' },
13604   { { STATE_CPENABLE }, 'i' }
13605 };
13606
13607 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = {
13608   { { OPERAND_art }, 'i' }
13609 };
13610
13611 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = {
13612   { { STATE_AE_SAR }, 'o' },
13613   { { STATE_CPENABLE }, 'i' }
13614 };
13615
13616 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = {
13617   { { OPERAND_arr }, 'o' }
13618 };
13619
13620 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = {
13621   { { STATE_AE_BITPTR }, 'i' },
13622   { { STATE_CPENABLE }, 'i' }
13623 };
13624
13625 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = {
13626   { { OPERAND_art }, 'i' }
13627 };
13628
13629 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = {
13630   { { STATE_AE_BITPTR }, 'o' },
13631   { { STATE_CPENABLE }, 'i' }
13632 };
13633
13634 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = {
13635   { { OPERAND_arr }, 'o' }
13636 };
13637
13638 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = {
13639   { { STATE_AE_BITSUSED }, 'i' },
13640   { { STATE_CPENABLE }, 'i' }
13641 };
13642
13643 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = {
13644   { { OPERAND_art }, 'i' }
13645 };
13646
13647 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = {
13648   { { STATE_AE_BITSUSED }, 'o' },
13649   { { STATE_CPENABLE }, 'i' }
13650 };
13651
13652 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = {
13653   { { OPERAND_arr }, 'o' }
13654 };
13655
13656 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = {
13657   { { STATE_AE_TABLESIZE }, 'i' },
13658   { { STATE_CPENABLE }, 'i' }
13659 };
13660
13661 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = {
13662   { { OPERAND_art }, 'i' }
13663 };
13664
13665 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = {
13666   { { STATE_AE_TABLESIZE }, 'o' },
13667   { { STATE_CPENABLE }, 'i' }
13668 };
13669
13670 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = {
13671   { { OPERAND_arr }, 'o' }
13672 };
13673
13674 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = {
13675   { { STATE_AE_FIRST_TS }, 'i' },
13676   { { STATE_CPENABLE }, 'i' }
13677 };
13678
13679 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = {
13680   { { OPERAND_art }, 'i' }
13681 };
13682
13683 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = {
13684   { { STATE_AE_FIRST_TS }, 'o' },
13685   { { STATE_CPENABLE }, 'i' }
13686 };
13687
13688 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = {
13689   { { OPERAND_arr }, 'o' }
13690 };
13691
13692 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = {
13693   { { STATE_AE_NEXTOFFSET }, 'i' },
13694   { { STATE_CPENABLE }, 'i' }
13695 };
13696
13697 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = {
13698   { { OPERAND_art }, 'i' }
13699 };
13700
13701 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = {
13702   { { STATE_AE_NEXTOFFSET }, 'o' },
13703   { { STATE_CPENABLE }, 'i' }
13704 };
13705
13706 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = {
13707   { { OPERAND_arr }, 'o' }
13708 };
13709
13710 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = {
13711   { { STATE_AE_SEARCHDONE }, 'i' },
13712   { { STATE_CPENABLE }, 'i' }
13713 };
13714
13715 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = {
13716   { { OPERAND_art }, 'i' }
13717 };
13718
13719 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = {
13720   { { STATE_AE_SEARCHDONE }, 'o' },
13721   { { STATE_CPENABLE }, 'i' }
13722 };
13723
13724 static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = {
13725   { { OPERAND_pr }, 'o' },
13726   { { OPERAND_ars }, 'i' },
13727   { { OPERAND_ae_lsimm16 }, 'i' }
13728 };
13729
13730 static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = {
13731   { { STATE_CPENABLE }, 'i' }
13732 };
13733
13734 static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = {
13735   { { OPERAND_pr }, 'o' },
13736   { { OPERAND_ars }, 'm' },
13737   { { OPERAND_ae_lsimm16 }, 'i' }
13738 };
13739
13740 static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = {
13741   { { STATE_CPENABLE }, 'i' }
13742 };
13743
13744 static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = {
13745   { { OPERAND_pr }, 'o' },
13746   { { OPERAND_ars }, 'i' },
13747   { { OPERAND_art }, 'i' }
13748 };
13749
13750 static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = {
13751   { { STATE_CPENABLE }, 'i' }
13752 };
13753
13754 static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = {
13755   { { OPERAND_pr }, 'o' },
13756   { { OPERAND_ars }, 'm' },
13757   { { OPERAND_art }, 'i' }
13758 };
13759
13760 static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = {
13761   { { STATE_CPENABLE }, 'i' }
13762 };
13763
13764 static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = {
13765   { { OPERAND_pr }, 'o' },
13766   { { OPERAND_ars }, 'i' },
13767   { { OPERAND_ae_lsimm32 }, 'i' }
13768 };
13769
13770 static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = {
13771   { { STATE_CPENABLE }, 'i' }
13772 };
13773
13774 static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = {
13775   { { OPERAND_pr }, 'o' },
13776   { { OPERAND_ars }, 'm' },
13777   { { OPERAND_ae_lsimm32 }, 'i' }
13778 };
13779
13780 static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = {
13781   { { STATE_CPENABLE }, 'i' }
13782 };
13783
13784 static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = {
13785   { { OPERAND_pr }, 'o' },
13786   { { OPERAND_ars }, 'i' },
13787   { { OPERAND_art }, 'i' }
13788 };
13789
13790 static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = {
13791   { { STATE_CPENABLE }, 'i' }
13792 };
13793
13794 static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = {
13795   { { OPERAND_pr }, 'o' },
13796   { { OPERAND_ars }, 'm' },
13797   { { OPERAND_art }, 'i' }
13798 };
13799
13800 static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = {
13801   { { STATE_CPENABLE }, 'i' }
13802 };
13803
13804 static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = {
13805   { { OPERAND_pr }, 'o' },
13806   { { OPERAND_ars }, 'i' },
13807   { { OPERAND_ae_lsimm32 }, 'i' }
13808 };
13809
13810 static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = {
13811   { { STATE_CPENABLE }, 'i' }
13812 };
13813
13814 static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = {
13815   { { OPERAND_pr }, 'o' },
13816   { { OPERAND_ars }, 'm' },
13817   { { OPERAND_ae_lsimm32 }, 'i' }
13818 };
13819
13820 static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = {
13821   { { STATE_CPENABLE }, 'i' }
13822 };
13823
13824 static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = {
13825   { { OPERAND_pr }, 'o' },
13826   { { OPERAND_ars }, 'i' },
13827   { { OPERAND_art }, 'i' }
13828 };
13829
13830 static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = {
13831   { { STATE_CPENABLE }, 'i' }
13832 };
13833
13834 static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = {
13835   { { OPERAND_pr }, 'o' },
13836   { { OPERAND_ars }, 'm' },
13837   { { OPERAND_art }, 'i' }
13838 };
13839
13840 static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = {
13841   { { STATE_CPENABLE }, 'i' }
13842 };
13843
13844 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = {
13845   { { OPERAND_pr }, 'o' },
13846   { { OPERAND_ars }, 'i' },
13847   { { OPERAND_ae_lsimm32 }, 'i' }
13848 };
13849
13850 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = {
13851   { { STATE_CPENABLE }, 'i' }
13852 };
13853
13854 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = {
13855   { { OPERAND_pr }, 'o' },
13856   { { OPERAND_ars }, 'm' },
13857   { { OPERAND_ae_lsimm32 }, 'i' }
13858 };
13859
13860 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = {
13861   { { STATE_CPENABLE }, 'i' }
13862 };
13863
13864 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = {
13865   { { OPERAND_pr }, 'o' },
13866   { { OPERAND_ars }, 'i' },
13867   { { OPERAND_art }, 'i' }
13868 };
13869
13870 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = {
13871   { { STATE_CPENABLE }, 'i' }
13872 };
13873
13874 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = {
13875   { { OPERAND_pr }, 'o' },
13876   { { OPERAND_ars }, 'm' },
13877   { { OPERAND_art }, 'i' }
13878 };
13879
13880 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = {
13881   { { STATE_CPENABLE }, 'i' }
13882 };
13883
13884 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = {
13885   { { OPERAND_pr }, 'o' },
13886   { { OPERAND_ars }, 'i' },
13887   { { OPERAND_ae_lsimm64 }, 'i' }
13888 };
13889
13890 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = {
13891   { { STATE_CPENABLE }, 'i' }
13892 };
13893
13894 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = {
13895   { { OPERAND_pr }, 'o' },
13896   { { OPERAND_ars }, 'm' },
13897   { { OPERAND_ae_lsimm64 }, 'i' }
13898 };
13899
13900 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = {
13901   { { STATE_CPENABLE }, 'i' }
13902 };
13903
13904 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = {
13905   { { OPERAND_pr }, 'o' },
13906   { { OPERAND_ars }, 'i' },
13907   { { OPERAND_art }, 'i' }
13908 };
13909
13910 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = {
13911   { { STATE_CPENABLE }, 'i' }
13912 };
13913
13914 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = {
13915   { { OPERAND_pr }, 'o' },
13916   { { OPERAND_ars }, 'm' },
13917   { { OPERAND_art }, 'i' }
13918 };
13919
13920 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = {
13921   { { STATE_CPENABLE }, 'i' }
13922 };
13923
13924 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = {
13925   { { OPERAND_pr }, 'o' },
13926   { { OPERAND_ars }, 'i' },
13927   { { OPERAND_ae_lsimm64 }, 'i' }
13928 };
13929
13930 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = {
13931   { { STATE_CPENABLE }, 'i' }
13932 };
13933
13934 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = {
13935   { { OPERAND_pr }, 'o' },
13936   { { OPERAND_ars }, 'm' },
13937   { { OPERAND_ae_lsimm64 }, 'i' }
13938 };
13939
13940 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = {
13941   { { STATE_CPENABLE }, 'i' }
13942 };
13943
13944 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = {
13945   { { OPERAND_pr }, 'o' },
13946   { { OPERAND_ars }, 'i' },
13947   { { OPERAND_art }, 'i' }
13948 };
13949
13950 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = {
13951   { { STATE_CPENABLE }, 'i' }
13952 };
13953
13954 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = {
13955   { { OPERAND_pr }, 'o' },
13956   { { OPERAND_ars }, 'm' },
13957   { { OPERAND_art }, 'i' }
13958 };
13959
13960 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = {
13961   { { STATE_CPENABLE }, 'i' }
13962 };
13963
13964 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = {
13965   { { OPERAND_pr }, 'i' },
13966   { { OPERAND_ars }, 'i' },
13967   { { OPERAND_ae_lsimm32 }, 'i' }
13968 };
13969
13970 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = {
13971   { { STATE_CPENABLE }, 'i' }
13972 };
13973
13974 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = {
13975   { { OPERAND_pr }, 'i' },
13976   { { OPERAND_ars }, 'm' },
13977   { { OPERAND_ae_lsimm32 }, 'i' }
13978 };
13979
13980 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = {
13981   { { STATE_CPENABLE }, 'i' }
13982 };
13983
13984 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = {
13985   { { OPERAND_pr }, 'i' },
13986   { { OPERAND_ars }, 'i' },
13987   { { OPERAND_art }, 'i' }
13988 };
13989
13990 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = {
13991   { { STATE_CPENABLE }, 'i' }
13992 };
13993
13994 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = {
13995   { { OPERAND_pr }, 'i' },
13996   { { OPERAND_ars }, 'm' },
13997   { { OPERAND_art }, 'i' }
13998 };
13999
14000 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = {
14001   { { STATE_CPENABLE }, 'i' }
14002 };
14003
14004 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = {
14005   { { OPERAND_pr }, 'i' },
14006   { { OPERAND_ars }, 'i' },
14007   { { OPERAND_ae_lsimm64 }, 'i' }
14008 };
14009
14010 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = {
14011   { { STATE_CPENABLE }, 'i' }
14012 };
14013
14014 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = {
14015   { { OPERAND_pr }, 'i' },
14016   { { OPERAND_ars }, 'm' },
14017   { { OPERAND_ae_lsimm64 }, 'i' }
14018 };
14019
14020 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = {
14021   { { STATE_CPENABLE }, 'i' }
14022 };
14023
14024 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = {
14025   { { OPERAND_pr }, 'i' },
14026   { { OPERAND_ars }, 'i' },
14027   { { OPERAND_art }, 'i' }
14028 };
14029
14030 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = {
14031   { { STATE_CPENABLE }, 'i' }
14032 };
14033
14034 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = {
14035   { { OPERAND_pr }, 'i' },
14036   { { OPERAND_ars }, 'm' },
14037   { { OPERAND_art }, 'i' }
14038 };
14039
14040 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = {
14041   { { STATE_CPENABLE }, 'i' }
14042 };
14043
14044 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = {
14045   { { OPERAND_pr }, 'i' },
14046   { { OPERAND_ars }, 'i' },
14047   { { OPERAND_ae_lsimm64 }, 'i' }
14048 };
14049
14050 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = {
14051   { { STATE_CPENABLE }, 'i' }
14052 };
14053
14054 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = {
14055   { { OPERAND_pr }, 'i' },
14056   { { OPERAND_ars }, 'm' },
14057   { { OPERAND_ae_lsimm64 }, 'i' }
14058 };
14059
14060 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = {
14061   { { STATE_CPENABLE }, 'i' }
14062 };
14063
14064 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = {
14065   { { OPERAND_pr }, 'i' },
14066   { { OPERAND_ars }, 'i' },
14067   { { OPERAND_art }, 'i' }
14068 };
14069
14070 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = {
14071   { { STATE_CPENABLE }, 'i' }
14072 };
14073
14074 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = {
14075   { { OPERAND_pr }, 'i' },
14076   { { OPERAND_ars }, 'm' },
14077   { { OPERAND_art }, 'i' }
14078 };
14079
14080 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = {
14081   { { STATE_CPENABLE }, 'i' }
14082 };
14083
14084 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = {
14085   { { OPERAND_pr }, 'i' },
14086   { { OPERAND_ars }, 'i' },
14087   { { OPERAND_ae_lsimm16 }, 'i' }
14088 };
14089
14090 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = {
14091   { { STATE_CPENABLE }, 'i' }
14092 };
14093
14094 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = {
14095   { { OPERAND_pr }, 'i' },
14096   { { OPERAND_ars }, 'm' },
14097   { { OPERAND_ae_lsimm16 }, 'i' }
14098 };
14099
14100 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = {
14101   { { STATE_CPENABLE }, 'i' }
14102 };
14103
14104 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = {
14105   { { OPERAND_pr }, 'i' },
14106   { { OPERAND_ars }, 'i' },
14107   { { OPERAND_art }, 'i' }
14108 };
14109
14110 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = {
14111   { { STATE_CPENABLE }, 'i' }
14112 };
14113
14114 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = {
14115   { { OPERAND_pr }, 'i' },
14116   { { OPERAND_ars }, 'm' },
14117   { { OPERAND_art }, 'i' }
14118 };
14119
14120 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = {
14121   { { STATE_CPENABLE }, 'i' }
14122 };
14123
14124 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = {
14125   { { OPERAND_pr }, 'i' },
14126   { { OPERAND_ars }, 'i' },
14127   { { OPERAND_ae_lsimm32 }, 'i' }
14128 };
14129
14130 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = {
14131   { { STATE_CPENABLE }, 'i' }
14132 };
14133
14134 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = {
14135   { { OPERAND_pr }, 'i' },
14136   { { OPERAND_ars }, 'm' },
14137   { { OPERAND_ae_lsimm32 }, 'i' }
14138 };
14139
14140 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = {
14141   { { STATE_CPENABLE }, 'i' }
14142 };
14143
14144 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = {
14145   { { OPERAND_pr }, 'i' },
14146   { { OPERAND_ars }, 'i' },
14147   { { OPERAND_art }, 'i' }
14148 };
14149
14150 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = {
14151   { { STATE_CPENABLE }, 'i' }
14152 };
14153
14154 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = {
14155   { { OPERAND_pr }, 'i' },
14156   { { OPERAND_ars }, 'm' },
14157   { { OPERAND_art }, 'i' }
14158 };
14159
14160 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = {
14161   { { STATE_CPENABLE }, 'i' }
14162 };
14163
14164 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = {
14165   { { OPERAND_pr }, 'i' },
14166   { { OPERAND_ars }, 'i' },
14167   { { OPERAND_ae_lsimm32 }, 'i' }
14168 };
14169
14170 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = {
14171   { { STATE_CPENABLE }, 'i' }
14172 };
14173
14174 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = {
14175   { { OPERAND_pr }, 'i' },
14176   { { OPERAND_ars }, 'm' },
14177   { { OPERAND_ae_lsimm32 }, 'i' }
14178 };
14179
14180 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = {
14181   { { STATE_CPENABLE }, 'i' }
14182 };
14183
14184 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = {
14185   { { OPERAND_pr }, 'i' },
14186   { { OPERAND_ars }, 'i' },
14187   { { OPERAND_art }, 'i' }
14188 };
14189
14190 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = {
14191   { { STATE_CPENABLE }, 'i' }
14192 };
14193
14194 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = {
14195   { { OPERAND_pr }, 'i' },
14196   { { OPERAND_ars }, 'm' },
14197   { { OPERAND_art }, 'i' }
14198 };
14199
14200 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = {
14201   { { STATE_CPENABLE }, 'i' }
14202 };
14203
14204 static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = {
14205   { { OPERAND_qr1_w }, 'o' },
14206   { { OPERAND_ars }, 'i' },
14207   { { OPERAND_ae_lsimm64 }, 'i' }
14208 };
14209
14210 static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = {
14211   { { STATE_CPENABLE }, 'i' }
14212 };
14213
14214 static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = {
14215   { { OPERAND_qr1_w }, 'o' },
14216   { { OPERAND_ars }, 'm' },
14217   { { OPERAND_ae_lsimm64 }, 'i' }
14218 };
14219
14220 static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = {
14221   { { STATE_CPENABLE }, 'i' }
14222 };
14223
14224 static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = {
14225   { { OPERAND_qr1_w }, 'o' },
14226   { { OPERAND_ars }, 'i' },
14227   { { OPERAND_art }, 'i' }
14228 };
14229
14230 static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = {
14231   { { STATE_CPENABLE }, 'i' }
14232 };
14233
14234 static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = {
14235   { { OPERAND_qr1_w }, 'o' },
14236   { { OPERAND_ars }, 'm' },
14237   { { OPERAND_art }, 'i' }
14238 };
14239
14240 static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = {
14241   { { STATE_CPENABLE }, 'i' }
14242 };
14243
14244 static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = {
14245   { { OPERAND_qr1_w }, 'o' },
14246   { { OPERAND_ars }, 'i' },
14247   { { OPERAND_ae_lsimm32 }, 'i' }
14248 };
14249
14250 static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = {
14251   { { STATE_CPENABLE }, 'i' }
14252 };
14253
14254 static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = {
14255   { { OPERAND_qr1_w }, 'o' },
14256   { { OPERAND_ars }, 'm' },
14257   { { OPERAND_ae_lsimm32 }, 'i' }
14258 };
14259
14260 static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = {
14261   { { STATE_CPENABLE }, 'i' }
14262 };
14263
14264 static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = {
14265   { { OPERAND_qr1_w }, 'o' },
14266   { { OPERAND_ars }, 'i' },
14267   { { OPERAND_art }, 'i' }
14268 };
14269
14270 static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = {
14271   { { STATE_CPENABLE }, 'i' }
14272 };
14273
14274 static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = {
14275   { { OPERAND_qr1_w }, 'o' },
14276   { { OPERAND_ars }, 'm' },
14277   { { OPERAND_art }, 'i' }
14278 };
14279
14280 static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = {
14281   { { STATE_CPENABLE }, 'i' }
14282 };
14283
14284 static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = {
14285   { { OPERAND_qr0_rw }, 'i' },
14286   { { OPERAND_ars }, 'i' },
14287   { { OPERAND_ae_lsimm64 }, 'i' }
14288 };
14289
14290 static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = {
14291   { { STATE_CPENABLE }, 'i' }
14292 };
14293
14294 static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = {
14295   { { OPERAND_qr0_rw }, 'i' },
14296   { { OPERAND_ars }, 'm' },
14297   { { OPERAND_ae_lsimm64 }, 'i' }
14298 };
14299
14300 static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = {
14301   { { STATE_CPENABLE }, 'i' }
14302 };
14303
14304 static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = {
14305   { { OPERAND_qr0_rw }, 'i' },
14306   { { OPERAND_ars }, 'i' },
14307   { { OPERAND_art }, 'i' }
14308 };
14309
14310 static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = {
14311   { { STATE_CPENABLE }, 'i' }
14312 };
14313
14314 static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = {
14315   { { OPERAND_qr0_rw }, 'i' },
14316   { { OPERAND_ars }, 'm' },
14317   { { OPERAND_art }, 'i' }
14318 };
14319
14320 static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = {
14321   { { STATE_CPENABLE }, 'i' }
14322 };
14323
14324 static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = {
14325   { { OPERAND_qr0_rw }, 'i' },
14326   { { OPERAND_ars }, 'i' },
14327   { { OPERAND_ae_lsimm32 }, 'i' }
14328 };
14329
14330 static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = {
14331   { { STATE_CPENABLE }, 'i' }
14332 };
14333
14334 static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = {
14335   { { OPERAND_qr0_rw }, 'i' },
14336   { { OPERAND_ars }, 'm' },
14337   { { OPERAND_ae_lsimm32 }, 'i' }
14338 };
14339
14340 static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = {
14341   { { STATE_CPENABLE }, 'i' }
14342 };
14343
14344 static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = {
14345   { { OPERAND_qr0_rw }, 'i' },
14346   { { OPERAND_ars }, 'i' },
14347   { { OPERAND_art }, 'i' }
14348 };
14349
14350 static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = {
14351   { { STATE_CPENABLE }, 'i' }
14352 };
14353
14354 static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = {
14355   { { OPERAND_qr0_rw }, 'i' },
14356   { { OPERAND_ars }, 'm' },
14357   { { OPERAND_art }, 'i' }
14358 };
14359
14360 static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = {
14361   { { STATE_CPENABLE }, 'i' }
14362 };
14363
14364 static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = {
14365   { { OPERAND_ps }, 'o' }
14366 };
14367
14368 static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = {
14369   { { STATE_CPENABLE }, 'i' }
14370 };
14371
14372 static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = {
14373   { { OPERAND_ps }, 'o' },
14374   { { OPERAND_pr }, 'i' }
14375 };
14376
14377 static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = {
14378   { { STATE_CPENABLE }, 'i' }
14379 };
14380
14381 static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = {
14382   { { OPERAND_ps }, 'o' },
14383   { { OPERAND_pr }, 'i' },
14384   { { OPERAND_pr0 }, 'i' }
14385 };
14386
14387 static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = {
14388   { { STATE_CPENABLE }, 'i' }
14389 };
14390
14391 static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = {
14392   { { OPERAND_ps }, 'o' },
14393   { { OPERAND_pr }, 'i' },
14394   { { OPERAND_pr0 }, 'i' }
14395 };
14396
14397 static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = {
14398   { { STATE_CPENABLE }, 'i' }
14399 };
14400
14401 static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = {
14402   { { OPERAND_ps }, 'o' },
14403   { { OPERAND_pr }, 'i' },
14404   { { OPERAND_pr0 }, 'i' }
14405 };
14406
14407 static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = {
14408   { { STATE_CPENABLE }, 'i' }
14409 };
14410
14411 static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = {
14412   { { OPERAND_ps }, 'o' },
14413   { { OPERAND_pr }, 'i' },
14414   { { OPERAND_pr0 }, 'i' }
14415 };
14416
14417 static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = {
14418   { { STATE_CPENABLE }, 'i' }
14419 };
14420
14421 static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = {
14422   { { OPERAND_pr }, 'm' },
14423   { { OPERAND_pr0 }, 'i' },
14424   { { OPERAND_bt2 }, 'i' }
14425 };
14426
14427 static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = {
14428   { { STATE_CPENABLE }, 'i' }
14429 };
14430
14431 static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = {
14432   { { OPERAND_pr }, 'm' },
14433   { { OPERAND_pr0 }, 'i' },
14434   { { OPERAND_bt2 }, 'i' }
14435 };
14436
14437 static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = {
14438   { { STATE_CPENABLE }, 'i' }
14439 };
14440
14441 static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = {
14442   { { OPERAND_pr }, 'm' },
14443   { { OPERAND_pr0 }, 'i' },
14444   { { OPERAND_bt }, 'i' }
14445 };
14446
14447 static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = {
14448   { { STATE_CPENABLE }, 'i' }
14449 };
14450
14451 static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = {
14452   { { OPERAND_pr }, 'm' },
14453   { { OPERAND_pr0 }, 'i' },
14454   { { OPERAND_bt }, 'i' }
14455 };
14456
14457 static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = {
14458   { { STATE_CPENABLE }, 'i' }
14459 };
14460
14461 static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = {
14462   { { OPERAND_pr }, 'o' },
14463   { { OPERAND_ars }, 'i' },
14464   { { OPERAND_art }, 'i' }
14465 };
14466
14467 static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = {
14468   { { STATE_CPENABLE }, 'i' }
14469 };
14470
14471 static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = {
14472   { { OPERAND_pr }, 'o' },
14473   { { OPERAND_ars }, 'i' },
14474   { { OPERAND_art }, 'i' }
14475 };
14476
14477 static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = {
14478   { { STATE_CPENABLE }, 'i' }
14479 };
14480
14481 static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = {
14482   { { OPERAND_ars }, 'o' },
14483   { { OPERAND_pr }, 'i' }
14484 };
14485
14486 static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = {
14487   { { STATE_CPENABLE }, 'i' }
14488 };
14489
14490 static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = {
14491   { { OPERAND_ars }, 'o' },
14492   { { OPERAND_pr }, 'i' }
14493 };
14494
14495 static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = {
14496   { { STATE_CPENABLE }, 'i' }
14497 };
14498
14499 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = {
14500   { { OPERAND_pr }, 'o' },
14501   { { OPERAND_ars }, 'i' },
14502   { { OPERAND_art }, 'i' }
14503 };
14504
14505 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = {
14506   { { STATE_CPENABLE }, 'i' }
14507 };
14508
14509 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = {
14510   { { OPERAND_pr }, 'o' },
14511   { { OPERAND_ars }, 'i' },
14512   { { OPERAND_art }, 'i' }
14513 };
14514
14515 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = {
14516   { { STATE_CPENABLE }, 'i' }
14517 };
14518
14519 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = {
14520   { { OPERAND_pr }, 'o' },
14521   { { OPERAND_ars }, 'i' },
14522   { { OPERAND_art }, 'i' }
14523 };
14524
14525 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = {
14526   { { STATE_CPENABLE }, 'i' }
14527 };
14528
14529 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = {
14530   { { OPERAND_pr }, 'o' },
14531   { { OPERAND_ars }, 'i' },
14532   { { OPERAND_art }, 'i' }
14533 };
14534
14535 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = {
14536   { { STATE_CPENABLE }, 'i' }
14537 };
14538
14539 static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = {
14540   { { OPERAND_ps }, 'o' },
14541   { { OPERAND_qr0_rw }, 'i' },
14542   { { OPERAND_qr0 }, 'i' }
14543 };
14544
14545 static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = {
14546   { { STATE_CPENABLE }, 'i' }
14547 };
14548
14549 static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = {
14550   { { OPERAND_ps }, 'o' },
14551   { { OPERAND_pr }, 'i' }
14552 };
14553
14554 static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = {
14555   { { STATE_CPENABLE }, 'i' }
14556 };
14557
14558 static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = {
14559   { { OPERAND_ps }, 'o' },
14560   { { OPERAND_qr0_rw }, 'i' }
14561 };
14562
14563 static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = {
14564   { { STATE_AE_OVERFLOW }, 'm' },
14565   { { STATE_CPENABLE }, 'i' }
14566 };
14567
14568 static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = {
14569   { { OPERAND_ps }, 'o' },
14570   { { OPERAND_qr0_rw }, 'i' }
14571 };
14572
14573 static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = {
14574   { { STATE_AE_OVERFLOW }, 'm' },
14575   { { STATE_CPENABLE }, 'i' }
14576 };
14577
14578 static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = {
14579   { { OPERAND_ps }, 'o' },
14580   { { OPERAND_qr0_rw }, 'i' }
14581 };
14582
14583 static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = {
14584   { { STATE_AE_OVERFLOW }, 'm' },
14585   { { STATE_CPENABLE }, 'i' }
14586 };
14587
14588 static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = {
14589   { { OPERAND_ps }, 'o' },
14590   { { OPERAND_qr0_rw }, 'i' }
14591 };
14592
14593 static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = {
14594   { { STATE_AE_OVERFLOW }, 'm' },
14595   { { STATE_CPENABLE }, 'i' }
14596 };
14597
14598 static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = {
14599   { { OPERAND_ps }, 'o' },
14600   { { OPERAND_pr }, 'i' }
14601 };
14602
14603 static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = {
14604   { { STATE_AE_OVERFLOW }, 'm' },
14605   { { STATE_CPENABLE }, 'i' }
14606 };
14607
14608 static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = {
14609   { { OPERAND_ps }, 'o' },
14610   { { OPERAND_pr }, 'i' }
14611 };
14612
14613 static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = {
14614   { { STATE_AE_OVERFLOW }, 'm' },
14615   { { STATE_CPENABLE }, 'i' }
14616 };
14617
14618 static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = {
14619   { { OPERAND_qr1_w }, 'o' }
14620 };
14621
14622 static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = {
14623   { { STATE_CPENABLE }, 'i' }
14624 };
14625
14626 static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = {
14627   { { OPERAND_qr1_w }, 'o' },
14628   { { OPERAND_qr0_rw }, 'i' }
14629 };
14630
14631 static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = {
14632   { { STATE_CPENABLE }, 'i' }
14633 };
14634
14635 static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = {
14636   { { OPERAND_qr1_w }, 'm' },
14637   { { OPERAND_qr0_rw }, 'i' },
14638   { { OPERAND_bs }, 'i' }
14639 };
14640
14641 static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = {
14642   { { STATE_CPENABLE }, 'i' }
14643 };
14644
14645 static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = {
14646   { { OPERAND_qr1_w }, 'm' },
14647   { { OPERAND_qr0_rw }, 'i' },
14648   { { OPERAND_bs }, 'i' }
14649 };
14650
14651 static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = {
14652   { { STATE_CPENABLE }, 'i' }
14653 };
14654
14655 static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = {
14656   { { OPERAND_qr1_w }, 'o' },
14657   { { OPERAND_ars }, 'i' }
14658 };
14659
14660 static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = {
14661   { { STATE_CPENABLE }, 'i' }
14662 };
14663
14664 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = {
14665   { { OPERAND_qr1_w }, 'o' },
14666   { { OPERAND_cvt_pr }, 'i' }
14667 };
14668
14669 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = {
14670   { { STATE_CPENABLE }, 'i' }
14671 };
14672
14673 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = {
14674   { { OPERAND_qr1_w }, 'o' },
14675   { { OPERAND_cvt_pr }, 'i' }
14676 };
14677
14678 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = {
14679   { { STATE_CPENABLE }, 'i' }
14680 };
14681
14682 static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = {
14683   { { OPERAND_qr1_w }, 'o' },
14684   { { OPERAND_qr0 }, 'i' }
14685 };
14686
14687 static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = {
14688   { { STATE_AE_OVERFLOW }, 'm' },
14689   { { STATE_CPENABLE }, 'i' }
14690 };
14691
14692 static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = {
14693   { { OPERAND_qr1_w }, 'o' },
14694   { { OPERAND_qr0_rw }, 'i' }
14695 };
14696
14697 static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = {
14698   { { STATE_CPENABLE }, 'i' }
14699 };
14700
14701 static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = {
14702   { { OPERAND_qr1_w }, 'o' },
14703   { { OPERAND_qr0_rw }, 'i' }
14704 };
14705
14706 static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = {
14707   { { STATE_AE_OVERFLOW }, 'm' },
14708   { { STATE_CPENABLE }, 'i' }
14709 };
14710
14711 static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = {
14712   { { OPERAND_qr1_w }, 'o' },
14713   { { OPERAND_qr0_rw }, 'i' }
14714 };
14715
14716 static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = {
14717   { { STATE_AE_OVERFLOW }, 'm' },
14718   { { STATE_CPENABLE }, 'i' }
14719 };
14720
14721 static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = {
14722   { { OPERAND_ars }, 'o' },
14723   { { OPERAND_qr0_rw }, 'i' }
14724 };
14725
14726 static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = {
14727   { { STATE_CPENABLE }, 'i' }
14728 };
14729
14730 static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = {
14731   { { OPERAND_ars }, 'o' },
14732   { { OPERAND_pr }, 'i' }
14733 };
14734
14735 static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = {
14736   { { STATE_CPENABLE }, 'i' }
14737 };
14738
14739 static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = {
14740   { { OPERAND_ars }, 'o' },
14741   { { OPERAND_pr }, 'i' }
14742 };
14743
14744 static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = {
14745   { { STATE_CPENABLE }, 'i' }
14746 };
14747
14748 static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = {
14749   { { OPERAND_ars }, 'o' },
14750   { { OPERAND_pr }, 'i' }
14751 };
14752
14753 static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = {
14754   { { STATE_CPENABLE }, 'i' }
14755 };
14756
14757 static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = {
14758   { { OPERAND_ars }, 'o' },
14759   { { OPERAND_pr }, 'i' }
14760 };
14761
14762 static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = {
14763   { { STATE_CPENABLE }, 'i' }
14764 };
14765
14766 static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = {
14767   { { OPERAND_ps }, 'o' },
14768   { { OPERAND_pr }, 'i' },
14769   { { OPERAND_pr0 }, 'i' }
14770 };
14771
14772 static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = {
14773   { { STATE_CPENABLE }, 'i' }
14774 };
14775
14776 static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = {
14777   { { OPERAND_ps }, 'o' },
14778   { { OPERAND_pr }, 'i' },
14779   { { OPERAND_pr0 }, 'i' }
14780 };
14781
14782 static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = {
14783   { { STATE_CPENABLE }, 'i' }
14784 };
14785
14786 static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = {
14787   { { OPERAND_ps }, 'o' },
14788   { { OPERAND_pr0 }, 'i' }
14789 };
14790
14791 static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = {
14792   { { STATE_CPENABLE }, 'i' }
14793 };
14794
14795 static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = {
14796   { { OPERAND_ps }, 'o' },
14797   { { OPERAND_pr0 }, 'i' }
14798 };
14799
14800 static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = {
14801   { { STATE_CPENABLE }, 'i' }
14802 };
14803
14804 static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = {
14805   { { OPERAND_ps }, 'o' },
14806   { { OPERAND_pr }, 'i' },
14807   { { OPERAND_pr0 }, 'i' }
14808 };
14809
14810 static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = {
14811   { { STATE_CPENABLE }, 'i' }
14812 };
14813
14814 static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = {
14815   { { OPERAND_ps }, 'o' },
14816   { { OPERAND_pr }, 'i' },
14817   { { OPERAND_pr0 }, 'i' }
14818 };
14819
14820 static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = {
14821   { { STATE_CPENABLE }, 'i' }
14822 };
14823
14824 static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = {
14825   { { OPERAND_alupppb_ps }, 'o' },
14826   { { OPERAND_pr }, 'i' },
14827   { { OPERAND_pr0 }, 'i' },
14828   { { OPERAND_bt2 }, 'o' }
14829 };
14830
14831 static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = {
14832   { { STATE_CPENABLE }, 'i' }
14833 };
14834
14835 static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = {
14836   { { OPERAND_alupppb_ps }, 'o' },
14837   { { OPERAND_pr }, 'i' },
14838   { { OPERAND_pr0 }, 'i' },
14839   { { OPERAND_bt2 }, 'o' }
14840 };
14841
14842 static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = {
14843   { { STATE_CPENABLE }, 'i' }
14844 };
14845
14846 static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = {
14847   { { OPERAND_ps }, 'o' },
14848   { { OPERAND_pr }, 'i' },
14849   { { OPERAND_pr0 }, 'i' }
14850 };
14851
14852 static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = {
14853   { { STATE_AE_OVERFLOW }, 'm' },
14854   { { STATE_CPENABLE }, 'i' }
14855 };
14856
14857 static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = {
14858   { { OPERAND_ps }, 'o' },
14859   { { OPERAND_pr }, 'i' },
14860   { { OPERAND_pr0 }, 'i' }
14861 };
14862
14863 static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = {
14864   { { STATE_AE_OVERFLOW }, 'm' },
14865   { { STATE_CPENABLE }, 'i' }
14866 };
14867
14868 static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = {
14869   { { OPERAND_ps }, 'o' },
14870   { { OPERAND_pr0 }, 'i' }
14871 };
14872
14873 static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = {
14874   { { STATE_AE_OVERFLOW }, 'm' },
14875   { { STATE_CPENABLE }, 'i' }
14876 };
14877
14878 static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = {
14879   { { OPERAND_ps }, 'o' },
14880   { { OPERAND_pr0 }, 'i' }
14881 };
14882
14883 static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = {
14884   { { STATE_AE_OVERFLOW }, 'm' },
14885   { { STATE_CPENABLE }, 'i' }
14886 };
14887
14888 static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = {
14889   { { OPERAND_ps }, 'o' },
14890   { { OPERAND_pr }, 'i' },
14891   { { OPERAND_pr0 }, 'i' }
14892 };
14893
14894 static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = {
14895   { { STATE_CPENABLE }, 'i' }
14896 };
14897
14898 static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = {
14899   { { OPERAND_ps }, 'o' },
14900   { { OPERAND_pr }, 'i' },
14901   { { OPERAND_pr0 }, 'i' }
14902 };
14903
14904 static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = {
14905   { { STATE_CPENABLE }, 'i' }
14906 };
14907
14908 static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = {
14909   { { OPERAND_ps }, 'o' },
14910   { { OPERAND_pr }, 'i' },
14911   { { OPERAND_pr0 }, 'i' }
14912 };
14913
14914 static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = {
14915   { { STATE_CPENABLE }, 'i' }
14916 };
14917
14918 static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = {
14919   { { OPERAND_ps }, 'o' },
14920   { { OPERAND_pr }, 'i' },
14921   { { OPERAND_pr0 }, 'i' }
14922 };
14923
14924 static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = {
14925   { { STATE_CPENABLE }, 'i' }
14926 };
14927
14928 static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = {
14929   { { OPERAND_bt2 }, 'o' },
14930   { { OPERAND_pr }, 'i' },
14931   { { OPERAND_pr0 }, 'i' }
14932 };
14933
14934 static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = {
14935   { { STATE_CPENABLE }, 'i' }
14936 };
14937
14938 static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = {
14939   { { OPERAND_bt2 }, 'o' },
14940   { { OPERAND_pr }, 'i' },
14941   { { OPERAND_pr0 }, 'i' }
14942 };
14943
14944 static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = {
14945   { { STATE_CPENABLE }, 'i' }
14946 };
14947
14948 static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = {
14949   { { OPERAND_bt2 }, 'o' },
14950   { { OPERAND_pr }, 'i' },
14951   { { OPERAND_pr0 }, 'i' }
14952 };
14953
14954 static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = {
14955   { { STATE_CPENABLE }, 'i' }
14956 };
14957
14958 static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = {
14959   { { OPERAND_qr1_w }, 'o' },
14960   { { OPERAND_qr0_rw }, 'i' },
14961   { { OPERAND_qr0 }, 'i' }
14962 };
14963
14964 static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = {
14965   { { STATE_CPENABLE }, 'i' }
14966 };
14967
14968 static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = {
14969   { { OPERAND_qr1_w }, 'o' },
14970   { { OPERAND_qr0_rw }, 'i' },
14971   { { OPERAND_qr0 }, 'i' }
14972 };
14973
14974 static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = {
14975   { { STATE_CPENABLE }, 'i' }
14976 };
14977
14978 static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = {
14979   { { OPERAND_qr1_w }, 'o' },
14980   { { OPERAND_qr0 }, 'i' }
14981 };
14982
14983 static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = {
14984   { { STATE_CPENABLE }, 'i' }
14985 };
14986
14987 static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = {
14988   { { OPERAND_qr1_w }, 'o' },
14989   { { OPERAND_qr0 }, 'i' }
14990 };
14991
14992 static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = {
14993   { { STATE_CPENABLE }, 'i' }
14994 };
14995
14996 static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = {
14997   { { OPERAND_qr1_w }, 'o' },
14998   { { OPERAND_qr0 }, 'i' },
14999   { { OPERAND_qr0_rw }, 'i' }
15000 };
15001
15002 static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = {
15003   { { STATE_CPENABLE }, 'i' }
15004 };
15005
15006 static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = {
15007   { { OPERAND_qr1_w }, 'o' },
15008   { { OPERAND_qr0 }, 'i' },
15009   { { OPERAND_qr0_rw }, 'i' }
15010 };
15011
15012 static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = {
15013   { { STATE_CPENABLE }, 'i' }
15014 };
15015
15016 static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = {
15017   { { OPERAND_qr1_w }, 'o' },
15018   { { OPERAND_qr0 }, 'i' },
15019   { { OPERAND_qr0_rw }, 'i' },
15020   { { OPERAND_bt }, 'o' }
15021 };
15022
15023 static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = {
15024   { { STATE_CPENABLE }, 'i' }
15025 };
15026
15027 static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = {
15028   { { OPERAND_qr1_w }, 'o' },
15029   { { OPERAND_qr0 }, 'i' },
15030   { { OPERAND_qr0_rw }, 'i' },
15031   { { OPERAND_bt }, 'o' }
15032 };
15033
15034 static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = {
15035   { { STATE_CPENABLE }, 'i' }
15036 };
15037
15038 static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = {
15039   { { OPERAND_qr1_w }, 'o' },
15040   { { OPERAND_qr0_rw }, 'i' },
15041   { { OPERAND_qr0 }, 'i' }
15042 };
15043
15044 static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = {
15045   { { STATE_AE_OVERFLOW }, 'm' },
15046   { { STATE_CPENABLE }, 'i' }
15047 };
15048
15049 static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = {
15050   { { OPERAND_qr1_w }, 'o' },
15051   { { OPERAND_qr0_rw }, 'i' },
15052   { { OPERAND_qr0 }, 'i' }
15053 };
15054
15055 static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = {
15056   { { STATE_AE_OVERFLOW }, 'm' },
15057   { { STATE_CPENABLE }, 'i' }
15058 };
15059
15060 static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = {
15061   { { OPERAND_qr1_w }, 'o' },
15062   { { OPERAND_qr0 }, 'i' }
15063 };
15064
15065 static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = {
15066   { { STATE_AE_OVERFLOW }, 'm' },
15067   { { STATE_CPENABLE }, 'i' }
15068 };
15069
15070 static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = {
15071   { { OPERAND_qr1_w }, 'o' },
15072   { { OPERAND_qr0 }, 'i' }
15073 };
15074
15075 static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = {
15076   { { STATE_AE_OVERFLOW }, 'm' },
15077   { { STATE_CPENABLE }, 'i' }
15078 };
15079
15080 static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = {
15081   { { OPERAND_qr1_w }, 'o' },
15082   { { OPERAND_qr0 }, 'i' },
15083   { { OPERAND_qr0_rw }, 'i' }
15084 };
15085
15086 static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = {
15087   { { STATE_CPENABLE }, 'i' }
15088 };
15089
15090 static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = {
15091   { { OPERAND_qr1_w }, 'o' },
15092   { { OPERAND_qr0 }, 'i' },
15093   { { OPERAND_qr0_rw }, 'i' }
15094 };
15095
15096 static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = {
15097   { { STATE_CPENABLE }, 'i' }
15098 };
15099
15100 static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = {
15101   { { OPERAND_qr1_w }, 'o' },
15102   { { OPERAND_qr0 }, 'i' },
15103   { { OPERAND_qr0_rw }, 'i' }
15104 };
15105
15106 static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = {
15107   { { STATE_CPENABLE }, 'i' }
15108 };
15109
15110 static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = {
15111   { { OPERAND_qr1_w }, 'o' },
15112   { { OPERAND_qr0 }, 'i' },
15113   { { OPERAND_qr0_rw }, 'i' }
15114 };
15115
15116 static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = {
15117   { { STATE_CPENABLE }, 'i' }
15118 };
15119
15120 static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = {
15121   { { OPERAND_ps }, 'o' },
15122   { { OPERAND_pr }, 'i' },
15123   { { OPERAND_ae_samt32 }, 'i' }
15124 };
15125
15126 static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = {
15127   { { STATE_CPENABLE }, 'i' }
15128 };
15129
15130 static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = {
15131   { { OPERAND_ps }, 'o' },
15132   { { OPERAND_pr }, 'i' },
15133   { { OPERAND_ae_samt32 }, 'i' }
15134 };
15135
15136 static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = {
15137   { { STATE_CPENABLE }, 'i' }
15138 };
15139
15140 static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = {
15141   { { OPERAND_ps }, 'o' },
15142   { { OPERAND_pr }, 'i' },
15143   { { OPERAND_ae_samt32 }, 'i' }
15144 };
15145
15146 static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = {
15147   { { STATE_CPENABLE }, 'i' }
15148 };
15149
15150 static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = {
15151   { { OPERAND_ps }, 'o' },
15152   { { OPERAND_pr }, 'i' }
15153 };
15154
15155 static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = {
15156   { { STATE_AE_SAR }, 'i' },
15157   { { STATE_CPENABLE }, 'i' }
15158 };
15159
15160 static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = {
15161   { { OPERAND_ps }, 'o' },
15162   { { OPERAND_pr }, 'i' }
15163 };
15164
15165 static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = {
15166   { { STATE_AE_SAR }, 'i' },
15167   { { STATE_CPENABLE }, 'i' }
15168 };
15169
15170 static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = {
15171   { { OPERAND_ps }, 'o' },
15172   { { OPERAND_pr }, 'i' }
15173 };
15174
15175 static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = {
15176   { { STATE_AE_SAR }, 'i' },
15177   { { STATE_CPENABLE }, 'i' }
15178 };
15179
15180 static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = {
15181   { { OPERAND_ps }, 'o' },
15182   { { OPERAND_pr }, 'i' },
15183   { { OPERAND_ae_samt32 }, 'i' }
15184 };
15185
15186 static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = {
15187   { { STATE_AE_OVERFLOW }, 'm' },
15188   { { STATE_CPENABLE }, 'i' }
15189 };
15190
15191 static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = {
15192   { { OPERAND_ps }, 'o' },
15193   { { OPERAND_pr }, 'i' }
15194 };
15195
15196 static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = {
15197   { { STATE_AE_OVERFLOW }, 'm' },
15198   { { STATE_AE_SAR }, 'i' },
15199   { { STATE_CPENABLE }, 'i' }
15200 };
15201
15202 static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = {
15203   { { OPERAND_qr1_w }, 'o' },
15204   { { OPERAND_qr0_rw }, 'i' },
15205   { { OPERAND_ae_samt64 }, 'i' }
15206 };
15207
15208 static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = {
15209   { { STATE_CPENABLE }, 'i' }
15210 };
15211
15212 static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = {
15213   { { OPERAND_qr1_w }, 'o' },
15214   { { OPERAND_qr0_rw }, 'i' },
15215   { { OPERAND_ae_samt64 }, 'i' }
15216 };
15217
15218 static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = {
15219   { { STATE_CPENABLE }, 'i' }
15220 };
15221
15222 static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = {
15223   { { OPERAND_qr1_w }, 'o' },
15224   { { OPERAND_qr0_rw }, 'i' },
15225   { { OPERAND_ae_samt64 }, 'i' }
15226 };
15227
15228 static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = {
15229   { { STATE_CPENABLE }, 'i' }
15230 };
15231
15232 static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = {
15233   { { OPERAND_qr1_w }, 'o' },
15234   { { OPERAND_qr0_rw }, 'i' }
15235 };
15236
15237 static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = {
15238   { { STATE_AE_SAR }, 'i' },
15239   { { STATE_CPENABLE }, 'i' }
15240 };
15241
15242 static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = {
15243   { { OPERAND_qr1_w }, 'o' },
15244   { { OPERAND_qr0_rw }, 'i' }
15245 };
15246
15247 static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = {
15248   { { STATE_AE_SAR }, 'i' },
15249   { { STATE_CPENABLE }, 'i' }
15250 };
15251
15252 static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = {
15253   { { OPERAND_qr1_w }, 'o' },
15254   { { OPERAND_qr0_rw }, 'i' }
15255 };
15256
15257 static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = {
15258   { { STATE_AE_SAR }, 'i' },
15259   { { STATE_CPENABLE }, 'i' }
15260 };
15261
15262 static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = {
15263   { { OPERAND_qr1_w }, 'o' },
15264   { { OPERAND_qr0_rw }, 'i' },
15265   { { OPERAND_ars }, 'i' }
15266 };
15267
15268 static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = {
15269   { { STATE_CPENABLE }, 'i' }
15270 };
15271
15272 static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = {
15273   { { OPERAND_qr1_w }, 'o' },
15274   { { OPERAND_qr0_rw }, 'i' },
15275   { { OPERAND_ars }, 'i' }
15276 };
15277
15278 static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = {
15279   { { STATE_CPENABLE }, 'i' }
15280 };
15281
15282 static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = {
15283   { { OPERAND_qr1_w }, 'o' },
15284   { { OPERAND_qr0_rw }, 'i' },
15285   { { OPERAND_ars }, 'i' }
15286 };
15287
15288 static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = {
15289   { { STATE_CPENABLE }, 'i' }
15290 };
15291
15292 static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = {
15293   { { OPERAND_qr1_w }, 'o' },
15294   { { OPERAND_qr0_rw }, 'i' },
15295   { { OPERAND_ae_samt64 }, 'i' }
15296 };
15297
15298 static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = {
15299   { { STATE_AE_OVERFLOW }, 'm' },
15300   { { STATE_CPENABLE }, 'i' }
15301 };
15302
15303 static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = {
15304   { { OPERAND_qr1_w }, 'o' },
15305   { { OPERAND_qr0_rw }, 'i' }
15306 };
15307
15308 static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = {
15309   { { STATE_AE_OVERFLOW }, 'm' },
15310   { { STATE_AE_SAR }, 'i' },
15311   { { STATE_CPENABLE }, 'i' }
15312 };
15313
15314 static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = {
15315   { { OPERAND_qr1_w }, 'o' },
15316   { { OPERAND_qr0_rw }, 'i' },
15317   { { OPERAND_ars }, 'i' }
15318 };
15319
15320 static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = {
15321   { { STATE_AE_OVERFLOW }, 'm' },
15322   { { STATE_CPENABLE }, 'i' }
15323 };
15324
15325 static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = {
15326   { { OPERAND_bt }, 'o' },
15327   { { OPERAND_qr0 }, 'i' },
15328   { { OPERAND_qr0_rw }, 'i' }
15329 };
15330
15331 static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = {
15332   { { STATE_CPENABLE }, 'i' }
15333 };
15334
15335 static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = {
15336   { { OPERAND_bt }, 'o' },
15337   { { OPERAND_qr0 }, 'i' },
15338   { { OPERAND_qr0_rw }, 'i' }
15339 };
15340
15341 static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = {
15342   { { STATE_CPENABLE }, 'i' }
15343 };
15344
15345 static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = {
15346   { { OPERAND_bt }, 'o' },
15347   { { OPERAND_qr0 }, 'i' },
15348   { { OPERAND_qr0_rw }, 'i' }
15349 };
15350
15351 static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = {
15352   { { STATE_CPENABLE }, 'i' }
15353 };
15354
15355 static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = {
15356   { { OPERAND_ars }, 'o' },
15357   { { OPERAND_qr0_rw }, 'i' }
15358 };
15359
15360 static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = {
15361   { { STATE_CPENABLE }, 'i' }
15362 };
15363
15364 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = {
15365   { { OPERAND_mac_qr1_w }, 'o' },
15366   { { OPERAND_pr }, 'i' },
15367   { { OPERAND_pr0 }, 'i' }
15368 };
15369
15370 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = {
15371   { { STATE_AE_OVERFLOW }, 'm' },
15372   { { STATE_CPENABLE }, 'i' }
15373 };
15374
15375 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = {
15376   { { OPERAND_mac_qr1_w }, 'o' },
15377   { { OPERAND_pr }, 'i' },
15378   { { OPERAND_pr0 }, 'i' }
15379 };
15380
15381 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = {
15382   { { STATE_CPENABLE }, 'i' }
15383 };
15384
15385 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = {
15386   { { OPERAND_mac_qr1_w }, 'o' },
15387   { { OPERAND_pr }, 'i' },
15388   { { OPERAND_pr0 }, 'i' }
15389 };
15390
15391 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = {
15392   { { STATE_CPENABLE }, 'i' }
15393 };
15394
15395 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = {
15396   { { OPERAND_mac_qr1_w }, 'o' },
15397   { { OPERAND_pr }, 'i' },
15398   { { OPERAND_pr0 }, 'i' }
15399 };
15400
15401 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = {
15402   { { STATE_AE_OVERFLOW }, 'm' },
15403   { { STATE_CPENABLE }, 'i' }
15404 };
15405
15406 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = {
15407   { { OPERAND_mac_qr1_w }, 'o' },
15408   { { OPERAND_pr }, 'i' },
15409   { { OPERAND_pr0 }, 'i' }
15410 };
15411
15412 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = {
15413   { { STATE_CPENABLE }, 'i' }
15414 };
15415
15416 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = {
15417   { { OPERAND_mac_qr1_w }, 'o' },
15418   { { OPERAND_pr }, 'i' },
15419   { { OPERAND_pr0 }, 'i' }
15420 };
15421
15422 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = {
15423   { { STATE_CPENABLE }, 'i' }
15424 };
15425
15426 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = {
15427   { { OPERAND_mac_qr1_w }, 'o' },
15428   { { OPERAND_pr }, 'i' },
15429   { { OPERAND_pr0 }, 'i' }
15430 };
15431
15432 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = {
15433   { { STATE_AE_OVERFLOW }, 'm' },
15434   { { STATE_CPENABLE }, 'i' }
15435 };
15436
15437 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = {
15438   { { OPERAND_mac_qr1_w }, 'o' },
15439   { { OPERAND_pr }, 'i' },
15440   { { OPERAND_pr0 }, 'i' }
15441 };
15442
15443 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = {
15444   { { STATE_CPENABLE }, 'i' }
15445 };
15446
15447 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = {
15448   { { OPERAND_mac_qr1_w }, 'o' },
15449   { { OPERAND_pr }, 'i' },
15450   { { OPERAND_pr0 }, 'i' }
15451 };
15452
15453 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = {
15454   { { STATE_CPENABLE }, 'i' }
15455 };
15456
15457 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = {
15458   { { OPERAND_mac_qr1_w }, 'o' },
15459   { { OPERAND_pr }, 'i' },
15460   { { OPERAND_pr0 }, 'i' }
15461 };
15462
15463 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = {
15464   { { STATE_AE_OVERFLOW }, 'm' },
15465   { { STATE_CPENABLE }, 'i' }
15466 };
15467
15468 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = {
15469   { { OPERAND_mac_qr1_w }, 'o' },
15470   { { OPERAND_pr }, 'i' },
15471   { { OPERAND_pr0 }, 'i' }
15472 };
15473
15474 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = {
15475   { { STATE_CPENABLE }, 'i' }
15476 };
15477
15478 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = {
15479   { { OPERAND_mac_qr1_w }, 'o' },
15480   { { OPERAND_pr }, 'i' },
15481   { { OPERAND_pr0 }, 'i' }
15482 };
15483
15484 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = {
15485   { { STATE_CPENABLE }, 'i' }
15486 };
15487
15488 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = {
15489   { { OPERAND_mac_qr1_w }, 'm' },
15490   { { OPERAND_pr }, 'i' },
15491   { { OPERAND_pr0 }, 'i' }
15492 };
15493
15494 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = {
15495   { { STATE_AE_OVERFLOW }, 'm' },
15496   { { STATE_CPENABLE }, 'i' }
15497 };
15498
15499 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = {
15500   { { OPERAND_mac_qr1_w }, 'm' },
15501   { { OPERAND_pr }, 'i' },
15502   { { OPERAND_pr0 }, 'i' }
15503 };
15504
15505 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = {
15506   { { STATE_CPENABLE }, 'i' }
15507 };
15508
15509 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = {
15510   { { OPERAND_mac_qr1_w }, 'm' },
15511   { { OPERAND_pr }, 'i' },
15512   { { OPERAND_pr0 }, 'i' }
15513 };
15514
15515 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = {
15516   { { STATE_CPENABLE }, 'i' }
15517 };
15518
15519 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = {
15520   { { OPERAND_mac_qr1_w }, 'm' },
15521   { { OPERAND_pr }, 'i' },
15522   { { OPERAND_pr0 }, 'i' }
15523 };
15524
15525 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = {
15526   { { STATE_AE_OVERFLOW }, 'm' },
15527   { { STATE_CPENABLE }, 'i' }
15528 };
15529
15530 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = {
15531   { { OPERAND_mac_qr1_w }, 'm' },
15532   { { OPERAND_pr }, 'i' },
15533   { { OPERAND_pr0 }, 'i' }
15534 };
15535
15536 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = {
15537   { { STATE_CPENABLE }, 'i' }
15538 };
15539
15540 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = {
15541   { { OPERAND_mac_qr1_w }, 'm' },
15542   { { OPERAND_pr }, 'i' },
15543   { { OPERAND_pr0 }, 'i' }
15544 };
15545
15546 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = {
15547   { { STATE_CPENABLE }, 'i' }
15548 };
15549
15550 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = {
15551   { { OPERAND_mac_qr1_w }, 'm' },
15552   { { OPERAND_pr }, 'i' },
15553   { { OPERAND_pr0 }, 'i' }
15554 };
15555
15556 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = {
15557   { { STATE_AE_OVERFLOW }, 'm' },
15558   { { STATE_CPENABLE }, 'i' }
15559 };
15560
15561 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = {
15562   { { OPERAND_mac_qr1_w }, 'm' },
15563   { { OPERAND_pr }, 'i' },
15564   { { OPERAND_pr0 }, 'i' }
15565 };
15566
15567 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = {
15568   { { STATE_CPENABLE }, 'i' }
15569 };
15570
15571 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = {
15572   { { OPERAND_mac_qr1_w }, 'm' },
15573   { { OPERAND_pr }, 'i' },
15574   { { OPERAND_pr0 }, 'i' }
15575 };
15576
15577 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = {
15578   { { STATE_CPENABLE }, 'i' }
15579 };
15580
15581 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = {
15582   { { OPERAND_mac_qr1_w }, 'm' },
15583   { { OPERAND_pr }, 'i' },
15584   { { OPERAND_pr0 }, 'i' }
15585 };
15586
15587 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = {
15588   { { STATE_AE_OVERFLOW }, 'm' },
15589   { { STATE_CPENABLE }, 'i' }
15590 };
15591
15592 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = {
15593   { { OPERAND_mac_qr1_w }, 'm' },
15594   { { OPERAND_pr }, 'i' },
15595   { { OPERAND_pr0 }, 'i' }
15596 };
15597
15598 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = {
15599   { { STATE_CPENABLE }, 'i' }
15600 };
15601
15602 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = {
15603   { { OPERAND_mac_qr1_w }, 'm' },
15604   { { OPERAND_pr }, 'i' },
15605   { { OPERAND_pr0 }, 'i' }
15606 };
15607
15608 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = {
15609   { { STATE_CPENABLE }, 'i' }
15610 };
15611
15612 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = {
15613   { { OPERAND_mac_qr1_w }, 'm' },
15614   { { OPERAND_pr }, 'i' },
15615   { { OPERAND_pr0 }, 'i' }
15616 };
15617
15618 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = {
15619   { { STATE_AE_OVERFLOW }, 'm' },
15620   { { STATE_CPENABLE }, 'i' }
15621 };
15622
15623 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = {
15624   { { OPERAND_mac_qr1_w }, 'm' },
15625   { { OPERAND_pr }, 'i' },
15626   { { OPERAND_pr0 }, 'i' }
15627 };
15628
15629 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = {
15630   { { STATE_CPENABLE }, 'i' }
15631 };
15632
15633 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = {
15634   { { OPERAND_mac_qr1_w }, 'm' },
15635   { { OPERAND_pr }, 'i' },
15636   { { OPERAND_pr0 }, 'i' }
15637 };
15638
15639 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = {
15640   { { STATE_CPENABLE }, 'i' }
15641 };
15642
15643 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = {
15644   { { OPERAND_mac_qr1_w }, 'm' },
15645   { { OPERAND_pr }, 'i' },
15646   { { OPERAND_pr0 }, 'i' }
15647 };
15648
15649 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = {
15650   { { STATE_AE_OVERFLOW }, 'm' },
15651   { { STATE_CPENABLE }, 'i' }
15652 };
15653
15654 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = {
15655   { { OPERAND_mac_qr1_w }, 'm' },
15656   { { OPERAND_pr }, 'i' },
15657   { { OPERAND_pr0 }, 'i' }
15658 };
15659
15660 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = {
15661   { { STATE_CPENABLE }, 'i' }
15662 };
15663
15664 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = {
15665   { { OPERAND_mac_qr1_w }, 'm' },
15666   { { OPERAND_pr }, 'i' },
15667   { { OPERAND_pr0 }, 'i' }
15668 };
15669
15670 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = {
15671   { { STATE_CPENABLE }, 'i' }
15672 };
15673
15674 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = {
15675   { { OPERAND_mac_qr1_w }, 'm' },
15676   { { OPERAND_pr }, 'i' },
15677   { { OPERAND_pr0 }, 'i' }
15678 };
15679
15680 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = {
15681   { { STATE_AE_OVERFLOW }, 'm' },
15682   { { STATE_CPENABLE }, 'i' }
15683 };
15684
15685 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = {
15686   { { OPERAND_mac_qr1_w }, 'm' },
15687   { { OPERAND_pr }, 'i' },
15688   { { OPERAND_pr0 }, 'i' }
15689 };
15690
15691 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = {
15692   { { STATE_CPENABLE }, 'i' }
15693 };
15694
15695 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = {
15696   { { OPERAND_mac_qr1_w }, 'm' },
15697   { { OPERAND_pr }, 'i' },
15698   { { OPERAND_pr0 }, 'i' }
15699 };
15700
15701 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = {
15702   { { STATE_CPENABLE }, 'i' }
15703 };
15704
15705 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = {
15706   { { OPERAND_mac_qr1_w }, 'm' },
15707   { { OPERAND_pr }, 'i' },
15708   { { OPERAND_pr0 }, 'i' }
15709 };
15710
15711 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = {
15712   { { STATE_AE_OVERFLOW }, 'm' },
15713   { { STATE_CPENABLE }, 'i' }
15714 };
15715
15716 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = {
15717   { { OPERAND_mac_qr1_w }, 'm' },
15718   { { OPERAND_pr }, 'i' },
15719   { { OPERAND_pr0 }, 'i' }
15720 };
15721
15722 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = {
15723   { { STATE_CPENABLE }, 'i' }
15724 };
15725
15726 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = {
15727   { { OPERAND_mac_qr1_w }, 'm' },
15728   { { OPERAND_pr }, 'i' },
15729   { { OPERAND_pr0 }, 'i' }
15730 };
15731
15732 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = {
15733   { { STATE_CPENABLE }, 'i' }
15734 };
15735
15736 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = {
15737   { { OPERAND_mac_qr1_w }, 'm' },
15738   { { OPERAND_pr }, 'i' },
15739   { { OPERAND_pr0 }, 'i' }
15740 };
15741
15742 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = {
15743   { { STATE_AE_OVERFLOW }, 'm' },
15744   { { STATE_CPENABLE }, 'i' }
15745 };
15746
15747 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = {
15748   { { OPERAND_mac_qr1_w }, 'm' },
15749   { { OPERAND_pr }, 'i' },
15750   { { OPERAND_pr0 }, 'i' }
15751 };
15752
15753 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = {
15754   { { STATE_AE_OVERFLOW }, 'm' },
15755   { { STATE_CPENABLE }, 'i' }
15756 };
15757
15758 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = {
15759   { { OPERAND_mac_qr1_w }, 'm' },
15760   { { OPERAND_pr }, 'i' },
15761   { { OPERAND_pr0 }, 'i' }
15762 };
15763
15764 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = {
15765   { { STATE_AE_OVERFLOW }, 'm' },
15766   { { STATE_CPENABLE }, 'i' }
15767 };
15768
15769 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = {
15770   { { OPERAND_mac_qr1_w }, 'm' },
15771   { { OPERAND_pr }, 'i' },
15772   { { OPERAND_pr0 }, 'i' }
15773 };
15774
15775 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = {
15776   { { STATE_AE_OVERFLOW }, 'm' },
15777   { { STATE_CPENABLE }, 'i' }
15778 };
15779
15780 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = {
15781   { { OPERAND_mac_qr1_w }, 'm' },
15782   { { OPERAND_pr }, 'i' },
15783   { { OPERAND_pr0 }, 'i' }
15784 };
15785
15786 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = {
15787   { { STATE_AE_OVERFLOW }, 'm' },
15788   { { STATE_CPENABLE }, 'i' }
15789 };
15790
15791 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = {
15792   { { OPERAND_mac_qr1_w }, 'm' },
15793   { { OPERAND_pr }, 'i' },
15794   { { OPERAND_pr0 }, 'i' }
15795 };
15796
15797 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = {
15798   { { STATE_AE_OVERFLOW }, 'm' },
15799   { { STATE_CPENABLE }, 'i' }
15800 };
15801
15802 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = {
15803   { { OPERAND_mac_qr1_w }, 'm' },
15804   { { OPERAND_pr }, 'i' },
15805   { { OPERAND_pr0 }, 'i' }
15806 };
15807
15808 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = {
15809   { { STATE_AE_OVERFLOW }, 'm' },
15810   { { STATE_CPENABLE }, 'i' }
15811 };
15812
15813 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = {
15814   { { OPERAND_mac_qr1_w }, 'm' },
15815   { { OPERAND_pr }, 'i' },
15816   { { OPERAND_pr0 }, 'i' }
15817 };
15818
15819 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = {
15820   { { STATE_AE_OVERFLOW }, 'm' },
15821   { { STATE_CPENABLE }, 'i' }
15822 };
15823
15824 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = {
15825   { { OPERAND_mac_qr1_w }, 'm' },
15826   { { OPERAND_pr }, 'i' },
15827   { { OPERAND_pr0 }, 'i' }
15828 };
15829
15830 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = {
15831   { { STATE_AE_OVERFLOW }, 'm' },
15832   { { STATE_CPENABLE }, 'i' }
15833 };
15834
15835 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = {
15836   { { OPERAND_mac_qr1_w }, 'm' },
15837   { { OPERAND_pr }, 'i' },
15838   { { OPERAND_pr0 }, 'i' }
15839 };
15840
15841 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = {
15842   { { STATE_AE_OVERFLOW }, 'm' },
15843   { { STATE_CPENABLE }, 'i' }
15844 };
15845
15846 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = {
15847   { { OPERAND_mac_qr1_w }, 'm' },
15848   { { OPERAND_pr }, 'i' },
15849   { { OPERAND_pr0 }, 'i' }
15850 };
15851
15852 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = {
15853   { { STATE_AE_OVERFLOW }, 'm' },
15854   { { STATE_CPENABLE }, 'i' }
15855 };
15856
15857 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = {
15858   { { OPERAND_mac_qr1_w }, 'm' },
15859   { { OPERAND_pr }, 'i' },
15860   { { OPERAND_pr0 }, 'i' }
15861 };
15862
15863 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = {
15864   { { STATE_AE_OVERFLOW }, 'm' },
15865   { { STATE_CPENABLE }, 'i' }
15866 };
15867
15868 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = {
15869   { { OPERAND_mac_qr1_w }, 'm' },
15870   { { OPERAND_pr }, 'i' },
15871   { { OPERAND_pr0 }, 'i' }
15872 };
15873
15874 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = {
15875   { { STATE_AE_OVERFLOW }, 'm' },
15876   { { STATE_CPENABLE }, 'i' }
15877 };
15878
15879 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = {
15880   { { OPERAND_mac_qr1_w }, 'm' },
15881   { { OPERAND_pr }, 'i' },
15882   { { OPERAND_pr0 }, 'i' }
15883 };
15884
15885 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = {
15886   { { STATE_AE_OVERFLOW }, 'm' },
15887   { { STATE_CPENABLE }, 'i' }
15888 };
15889
15890 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = {
15891   { { OPERAND_mac_qr1_w }, 'm' },
15892   { { OPERAND_pr }, 'i' },
15893   { { OPERAND_pr0 }, 'i' }
15894 };
15895
15896 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = {
15897   { { STATE_AE_OVERFLOW }, 'm' },
15898   { { STATE_CPENABLE }, 'i' }
15899 };
15900
15901 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = {
15902   { { OPERAND_mac_qr1_w }, 'm' },
15903   { { OPERAND_pr }, 'i' },
15904   { { OPERAND_pr0 }, 'i' }
15905 };
15906
15907 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = {
15908   { { STATE_AE_OVERFLOW }, 'm' },
15909   { { STATE_CPENABLE }, 'i' }
15910 };
15911
15912 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = {
15913   { { OPERAND_mac_qr1_w }, 'o' },
15914   { { OPERAND_mac_qr0_rw }, 'i' },
15915   { { OPERAND_pr }, 'i' }
15916 };
15917
15918 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = {
15919   { { STATE_CPENABLE }, 'i' }
15920 };
15921
15922 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = {
15923   { { OPERAND_mac_qr1_w }, 'o' },
15924   { { OPERAND_mac_qr0_rw }, 'i' },
15925   { { OPERAND_pr }, 'i' }
15926 };
15927
15928 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = {
15929   { { STATE_CPENABLE }, 'i' }
15930 };
15931
15932 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = {
15933   { { OPERAND_mac_qr1_w }, 'o' },
15934   { { OPERAND_mac_qr0_rw }, 'i' },
15935   { { OPERAND_pr }, 'i' }
15936 };
15937
15938 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = {
15939   { { STATE_CPENABLE }, 'i' }
15940 };
15941
15942 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = {
15943   { { OPERAND_mac_qr1_w }, 'o' },
15944   { { OPERAND_mac_qr0_rw }, 'i' },
15945   { { OPERAND_pr }, 'i' }
15946 };
15947
15948 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = {
15949   { { STATE_CPENABLE }, 'i' }
15950 };
15951
15952 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = {
15953   { { OPERAND_mac_qr1_w }, 'o' },
15954   { { OPERAND_mac_qr0_rw }, 'i' },
15955   { { OPERAND_pr }, 'i' }
15956 };
15957
15958 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = {
15959   { { STATE_CPENABLE }, 'i' }
15960 };
15961
15962 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = {
15963   { { OPERAND_mac_qr1_w }, 'o' },
15964   { { OPERAND_mac_qr0_rw }, 'i' },
15965   { { OPERAND_pr }, 'i' }
15966 };
15967
15968 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = {
15969   { { STATE_CPENABLE }, 'i' }
15970 };
15971
15972 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = {
15973   { { OPERAND_mac_qr1_w }, 'o' },
15974   { { OPERAND_mac_qr0_rw }, 'i' },
15975   { { OPERAND_pr }, 'i' }
15976 };
15977
15978 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = {
15979   { { STATE_CPENABLE }, 'i' }
15980 };
15981
15982 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = {
15983   { { OPERAND_mac_qr1_w }, 'o' },
15984   { { OPERAND_mac_qr0_rw }, 'i' },
15985   { { OPERAND_pr }, 'i' }
15986 };
15987
15988 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = {
15989   { { STATE_CPENABLE }, 'i' }
15990 };
15991
15992 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = {
15993   { { OPERAND_mac_qr1_w }, 'm' },
15994   { { OPERAND_mac_qr0_rw }, 'i' },
15995   { { OPERAND_pr }, 'i' }
15996 };
15997
15998 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = {
15999   { { STATE_CPENABLE }, 'i' }
16000 };
16001
16002 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = {
16003   { { OPERAND_mac_qr1_w }, 'm' },
16004   { { OPERAND_mac_qr0_rw }, 'i' },
16005   { { OPERAND_pr }, 'i' }
16006 };
16007
16008 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = {
16009   { { STATE_CPENABLE }, 'i' }
16010 };
16011
16012 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = {
16013   { { OPERAND_mac_qr1_w }, 'm' },
16014   { { OPERAND_mac_qr0_rw }, 'i' },
16015   { { OPERAND_pr }, 'i' }
16016 };
16017
16018 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = {
16019   { { STATE_CPENABLE }, 'i' }
16020 };
16021
16022 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = {
16023   { { OPERAND_mac_qr1_w }, 'm' },
16024   { { OPERAND_mac_qr0_rw }, 'i' },
16025   { { OPERAND_pr }, 'i' }
16026 };
16027
16028 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = {
16029   { { STATE_CPENABLE }, 'i' }
16030 };
16031
16032 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = {
16033   { { OPERAND_mac_qr1_w }, 'm' },
16034   { { OPERAND_mac_qr0_rw }, 'i' },
16035   { { OPERAND_pr }, 'i' }
16036 };
16037
16038 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = {
16039   { { STATE_CPENABLE }, 'i' }
16040 };
16041
16042 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = {
16043   { { OPERAND_mac_qr1_w }, 'm' },
16044   { { OPERAND_mac_qr0_rw }, 'i' },
16045   { { OPERAND_pr }, 'i' }
16046 };
16047
16048 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = {
16049   { { STATE_CPENABLE }, 'i' }
16050 };
16051
16052 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = {
16053   { { OPERAND_mac_qr1_w }, 'm' },
16054   { { OPERAND_mac_qr0_rw }, 'i' },
16055   { { OPERAND_pr }, 'i' }
16056 };
16057
16058 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = {
16059   { { STATE_CPENABLE }, 'i' }
16060 };
16061
16062 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = {
16063   { { OPERAND_mac_qr1_w }, 'm' },
16064   { { OPERAND_mac_qr0_rw }, 'i' },
16065   { { OPERAND_pr }, 'i' }
16066 };
16067
16068 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = {
16069   { { STATE_CPENABLE }, 'i' }
16070 };
16071
16072 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = {
16073   { { OPERAND_mac_qr1_w }, 'm' },
16074   { { OPERAND_mac_qr0_rw }, 'i' },
16075   { { OPERAND_pr }, 'i' }
16076 };
16077
16078 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = {
16079   { { STATE_CPENABLE }, 'i' }
16080 };
16081
16082 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = {
16083   { { OPERAND_mac_qr1_w }, 'm' },
16084   { { OPERAND_mac_qr0_rw }, 'i' },
16085   { { OPERAND_pr }, 'i' }
16086 };
16087
16088 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = {
16089   { { STATE_CPENABLE }, 'i' }
16090 };
16091
16092 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = {
16093   { { OPERAND_mac_qr1_w }, 'm' },
16094   { { OPERAND_mac_qr0_rw }, 'i' },
16095   { { OPERAND_pr }, 'i' }
16096 };
16097
16098 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = {
16099   { { STATE_CPENABLE }, 'i' }
16100 };
16101
16102 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = {
16103   { { OPERAND_mac_qr1_w }, 'm' },
16104   { { OPERAND_mac_qr0_rw }, 'i' },
16105   { { OPERAND_pr }, 'i' }
16106 };
16107
16108 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = {
16109   { { STATE_CPENABLE }, 'i' }
16110 };
16111
16112 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = {
16113   { { OPERAND_mac_qr1_w }, 'm' },
16114   { { OPERAND_mac_qr0_rw }, 'i' },
16115   { { OPERAND_pr }, 'i' }
16116 };
16117
16118 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = {
16119   { { STATE_CPENABLE }, 'i' }
16120 };
16121
16122 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = {
16123   { { OPERAND_mac_qr1_w }, 'm' },
16124   { { OPERAND_mac_qr0_rw }, 'i' },
16125   { { OPERAND_pr }, 'i' }
16126 };
16127
16128 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = {
16129   { { STATE_CPENABLE }, 'i' }
16130 };
16131
16132 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = {
16133   { { OPERAND_mac_qr1_w }, 'm' },
16134   { { OPERAND_mac_qr0_rw }, 'i' },
16135   { { OPERAND_pr }, 'i' }
16136 };
16137
16138 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = {
16139   { { STATE_CPENABLE }, 'i' }
16140 };
16141
16142 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = {
16143   { { OPERAND_mac_qr1_w }, 'm' },
16144   { { OPERAND_mac_qr0_rw }, 'i' },
16145   { { OPERAND_pr }, 'i' }
16146 };
16147
16148 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = {
16149   { { STATE_CPENABLE }, 'i' }
16150 };
16151
16152 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = {
16153   { { OPERAND_mac_qr1_w }, 'o' },
16154   { { OPERAND_mac_qr0_rw }, 'i' },
16155   { { OPERAND_pr }, 'i' },
16156   { { OPERAND_mac_qr0 }, 'i' },
16157   { { OPERAND_pr0 }, 'i' }
16158 };
16159
16160 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = {
16161   { { STATE_CPENABLE }, 'i' }
16162 };
16163
16164 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = {
16165   { { OPERAND_mac_qr1_w }, 'o' },
16166   { { OPERAND_mac_qr0_rw }, 'i' },
16167   { { OPERAND_pr }, 'i' },
16168   { { OPERAND_mac_qr0 }, 'i' },
16169   { { OPERAND_pr0 }, 'i' }
16170 };
16171
16172 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = {
16173   { { STATE_CPENABLE }, 'i' }
16174 };
16175
16176 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = {
16177   { { OPERAND_mac_qr1_w }, 'o' },
16178   { { OPERAND_mac_qr0_rw }, 'i' },
16179   { { OPERAND_pr }, 'i' },
16180   { { OPERAND_mac_qr0 }, 'i' },
16181   { { OPERAND_pr0 }, 'i' }
16182 };
16183
16184 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = {
16185   { { STATE_CPENABLE }, 'i' }
16186 };
16187
16188 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = {
16189   { { OPERAND_mac_qr1_w }, 'o' },
16190   { { OPERAND_mac_qr0_rw }, 'i' },
16191   { { OPERAND_pr }, 'i' },
16192   { { OPERAND_mac_qr0 }, 'i' },
16193   { { OPERAND_pr0 }, 'i' }
16194 };
16195
16196 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = {
16197   { { STATE_CPENABLE }, 'i' }
16198 };
16199
16200 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = {
16201   { { OPERAND_mac_qr1_w }, 'o' },
16202   { { OPERAND_mac_qr0_rw }, 'i' },
16203   { { OPERAND_pr }, 'i' },
16204   { { OPERAND_mac_qr0 }, 'i' },
16205   { { OPERAND_pr0 }, 'i' }
16206 };
16207
16208 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = {
16209   { { STATE_CPENABLE }, 'i' }
16210 };
16211
16212 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = {
16213   { { OPERAND_mac_qr1_w }, 'o' },
16214   { { OPERAND_mac_qr0_rw }, 'i' },
16215   { { OPERAND_pr }, 'i' },
16216   { { OPERAND_mac_qr0 }, 'i' },
16217   { { OPERAND_pr0 }, 'i' }
16218 };
16219
16220 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = {
16221   { { STATE_CPENABLE }, 'i' }
16222 };
16223
16224 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = {
16225   { { OPERAND_mac_qr1_w }, 'o' },
16226   { { OPERAND_mac_qr0_rw }, 'i' },
16227   { { OPERAND_pr }, 'i' },
16228   { { OPERAND_mac_qr0 }, 'i' },
16229   { { OPERAND_pr0 }, 'i' }
16230 };
16231
16232 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = {
16233   { { STATE_CPENABLE }, 'i' }
16234 };
16235
16236 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = {
16237   { { OPERAND_mac_qr1_w }, 'o' },
16238   { { OPERAND_mac_qr0_rw }, 'i' },
16239   { { OPERAND_pr }, 'i' },
16240   { { OPERAND_mac_qr0 }, 'i' },
16241   { { OPERAND_pr0 }, 'i' }
16242 };
16243
16244 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = {
16245   { { STATE_CPENABLE }, 'i' }
16246 };
16247
16248 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = {
16249   { { OPERAND_mac_qr1_w }, 'o' },
16250   { { OPERAND_mac_qr0_rw }, 'i' },
16251   { { OPERAND_pr }, 'i' },
16252   { { OPERAND_mac_qr0 }, 'i' },
16253   { { OPERAND_pr0 }, 'i' }
16254 };
16255
16256 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = {
16257   { { STATE_CPENABLE }, 'i' }
16258 };
16259
16260 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = {
16261   { { OPERAND_mac_qr1_w }, 'o' },
16262   { { OPERAND_mac_qr0_rw }, 'i' },
16263   { { OPERAND_pr }, 'i' },
16264   { { OPERAND_mac_qr0 }, 'i' },
16265   { { OPERAND_pr0 }, 'i' }
16266 };
16267
16268 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = {
16269   { { STATE_CPENABLE }, 'i' }
16270 };
16271
16272 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = {
16273   { { OPERAND_mac_qr1_w }, 'o' },
16274   { { OPERAND_mac_qr0_rw }, 'i' },
16275   { { OPERAND_pr }, 'i' },
16276   { { OPERAND_mac_qr0 }, 'i' },
16277   { { OPERAND_pr0 }, 'i' }
16278 };
16279
16280 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = {
16281   { { STATE_CPENABLE }, 'i' }
16282 };
16283
16284 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = {
16285   { { OPERAND_mac_qr1_w }, 'o' },
16286   { { OPERAND_mac_qr0_rw }, 'i' },
16287   { { OPERAND_pr }, 'i' },
16288   { { OPERAND_mac_qr0 }, 'i' },
16289   { { OPERAND_pr0 }, 'i' }
16290 };
16291
16292 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = {
16293   { { STATE_CPENABLE }, 'i' }
16294 };
16295
16296 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = {
16297   { { OPERAND_mac_qr1_w }, 'o' },
16298   { { OPERAND_mac_qr0_rw }, 'i' },
16299   { { OPERAND_pr }, 'i' },
16300   { { OPERAND_mac_qr0 }, 'i' },
16301   { { OPERAND_pr0 }, 'i' }
16302 };
16303
16304 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = {
16305   { { STATE_CPENABLE }, 'i' }
16306 };
16307
16308 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = {
16309   { { OPERAND_mac_qr1_w }, 'o' },
16310   { { OPERAND_mac_qr0_rw }, 'i' },
16311   { { OPERAND_pr }, 'i' },
16312   { { OPERAND_mac_qr0 }, 'i' },
16313   { { OPERAND_pr0 }, 'i' }
16314 };
16315
16316 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = {
16317   { { STATE_CPENABLE }, 'i' }
16318 };
16319
16320 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = {
16321   { { OPERAND_mac_qr1_w }, 'o' },
16322   { { OPERAND_mac_qr0_rw }, 'i' },
16323   { { OPERAND_pr }, 'i' },
16324   { { OPERAND_mac_qr0 }, 'i' },
16325   { { OPERAND_pr0 }, 'i' }
16326 };
16327
16328 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = {
16329   { { STATE_CPENABLE }, 'i' }
16330 };
16331
16332 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = {
16333   { { OPERAND_mac_qr1_w }, 'o' },
16334   { { OPERAND_mac_qr0_rw }, 'i' },
16335   { { OPERAND_pr }, 'i' },
16336   { { OPERAND_mac_qr0 }, 'i' },
16337   { { OPERAND_pr0 }, 'i' }
16338 };
16339
16340 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = {
16341   { { STATE_CPENABLE }, 'i' }
16342 };
16343
16344 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = {
16345   { { OPERAND_mac_qr1_w }, 'o' },
16346   { { OPERAND_mac_qr0_rw }, 'i' },
16347   { { OPERAND_pr }, 'i' },
16348   { { OPERAND_mac_qr0 }, 'i' },
16349   { { OPERAND_pr0 }, 'i' }
16350 };
16351
16352 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = {
16353   { { STATE_CPENABLE }, 'i' }
16354 };
16355
16356 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = {
16357   { { OPERAND_mac_qr1_w }, 'o' },
16358   { { OPERAND_mac_qr0_rw }, 'i' },
16359   { { OPERAND_pr }, 'i' },
16360   { { OPERAND_mac_qr0 }, 'i' },
16361   { { OPERAND_pr0 }, 'i' }
16362 };
16363
16364 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = {
16365   { { STATE_CPENABLE }, 'i' }
16366 };
16367
16368 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = {
16369   { { OPERAND_mac_qr1_w }, 'o' },
16370   { { OPERAND_mac_qr0_rw }, 'i' },
16371   { { OPERAND_pr }, 'i' },
16372   { { OPERAND_mac_qr0 }, 'i' },
16373   { { OPERAND_pr0 }, 'i' }
16374 };
16375
16376 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = {
16377   { { STATE_CPENABLE }, 'i' }
16378 };
16379
16380 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = {
16381   { { OPERAND_mac_qr1_w }, 'o' },
16382   { { OPERAND_mac_qr0_rw }, 'i' },
16383   { { OPERAND_pr }, 'i' },
16384   { { OPERAND_mac_qr0 }, 'i' },
16385   { { OPERAND_pr0 }, 'i' }
16386 };
16387
16388 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = {
16389   { { STATE_CPENABLE }, 'i' }
16390 };
16391
16392 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = {
16393   { { OPERAND_mac_qr1_w }, 'o' },
16394   { { OPERAND_mac_qr0_rw }, 'i' },
16395   { { OPERAND_pr }, 'i' },
16396   { { OPERAND_mac_qr0 }, 'i' },
16397   { { OPERAND_pr0 }, 'i' }
16398 };
16399
16400 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = {
16401   { { STATE_CPENABLE }, 'i' }
16402 };
16403
16404 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = {
16405   { { OPERAND_mac_qr1_w }, 'o' },
16406   { { OPERAND_mac_qr0_rw }, 'i' },
16407   { { OPERAND_pr }, 'i' },
16408   { { OPERAND_mac_qr0 }, 'i' },
16409   { { OPERAND_pr0 }, 'i' }
16410 };
16411
16412 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = {
16413   { { STATE_CPENABLE }, 'i' }
16414 };
16415
16416 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = {
16417   { { OPERAND_mac_qr1_w }, 'o' },
16418   { { OPERAND_mac_qr0_rw }, 'i' },
16419   { { OPERAND_pr }, 'i' },
16420   { { OPERAND_mac_qr0 }, 'i' },
16421   { { OPERAND_pr0 }, 'i' }
16422 };
16423
16424 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = {
16425   { { STATE_CPENABLE }, 'i' }
16426 };
16427
16428 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = {
16429   { { OPERAND_mac_qr1_w }, 'o' },
16430   { { OPERAND_mac_qr0_rw }, 'i' },
16431   { { OPERAND_pr }, 'i' },
16432   { { OPERAND_mac_qr0 }, 'i' },
16433   { { OPERAND_pr0 }, 'i' }
16434 };
16435
16436 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = {
16437   { { STATE_CPENABLE }, 'i' }
16438 };
16439
16440 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = {
16441   { { OPERAND_mac_qr1_w }, 'o' },
16442   { { OPERAND_mac_qr0_rw }, 'i' },
16443   { { OPERAND_pr }, 'i' },
16444   { { OPERAND_mac_qr0 }, 'i' },
16445   { { OPERAND_pr0 }, 'i' }
16446 };
16447
16448 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = {
16449   { { STATE_CPENABLE }, 'i' }
16450 };
16451
16452 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = {
16453   { { OPERAND_mac_qr1_w }, 'o' },
16454   { { OPERAND_mac_qr0_rw }, 'i' },
16455   { { OPERAND_pr }, 'i' },
16456   { { OPERAND_mac_qr0 }, 'i' },
16457   { { OPERAND_pr0 }, 'i' }
16458 };
16459
16460 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = {
16461   { { STATE_CPENABLE }, 'i' }
16462 };
16463
16464 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = {
16465   { { OPERAND_mac_qr1_w }, 'o' },
16466   { { OPERAND_mac_qr0_rw }, 'i' },
16467   { { OPERAND_pr }, 'i' },
16468   { { OPERAND_mac_qr0 }, 'i' },
16469   { { OPERAND_pr0 }, 'i' }
16470 };
16471
16472 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = {
16473   { { STATE_CPENABLE }, 'i' }
16474 };
16475
16476 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = {
16477   { { OPERAND_mac_qr1_w }, 'o' },
16478   { { OPERAND_mac_qr0_rw }, 'i' },
16479   { { OPERAND_pr }, 'i' },
16480   { { OPERAND_mac_qr0 }, 'i' },
16481   { { OPERAND_pr0 }, 'i' }
16482 };
16483
16484 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = {
16485   { { STATE_CPENABLE }, 'i' }
16486 };
16487
16488 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = {
16489   { { OPERAND_mac_qr1_w }, 'o' },
16490   { { OPERAND_mac_qr0_rw }, 'i' },
16491   { { OPERAND_pr }, 'i' },
16492   { { OPERAND_mac_qr0 }, 'i' },
16493   { { OPERAND_pr0 }, 'i' }
16494 };
16495
16496 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = {
16497   { { STATE_CPENABLE }, 'i' }
16498 };
16499
16500 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = {
16501   { { OPERAND_mac_qr1_w }, 'o' },
16502   { { OPERAND_mac_qr0_rw }, 'i' },
16503   { { OPERAND_pr }, 'i' },
16504   { { OPERAND_mac_qr0 }, 'i' },
16505   { { OPERAND_pr0 }, 'i' }
16506 };
16507
16508 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = {
16509   { { STATE_CPENABLE }, 'i' }
16510 };
16511
16512 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = {
16513   { { OPERAND_mac_qr1_w }, 'o' },
16514   { { OPERAND_mac_qr0_rw }, 'i' },
16515   { { OPERAND_pr }, 'i' },
16516   { { OPERAND_mac_qr0 }, 'i' },
16517   { { OPERAND_pr0 }, 'i' }
16518 };
16519
16520 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = {
16521   { { STATE_CPENABLE }, 'i' }
16522 };
16523
16524 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = {
16525   { { OPERAND_mac_qr1_w }, 'o' },
16526   { { OPERAND_mac_qr0_rw }, 'i' },
16527   { { OPERAND_pr }, 'i' },
16528   { { OPERAND_mac_qr0 }, 'i' },
16529   { { OPERAND_pr0 }, 'i' }
16530 };
16531
16532 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = {
16533   { { STATE_CPENABLE }, 'i' }
16534 };
16535
16536 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = {
16537   { { OPERAND_mac_qr1_w }, 'o' },
16538   { { OPERAND_mac_qr0_rw }, 'i' },
16539   { { OPERAND_pr }, 'i' },
16540   { { OPERAND_mac_qr0 }, 'i' },
16541   { { OPERAND_pr0 }, 'i' }
16542 };
16543
16544 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = {
16545   { { STATE_CPENABLE }, 'i' }
16546 };
16547
16548 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = {
16549   { { OPERAND_mac_qr1_w }, 'o' },
16550   { { OPERAND_mac_qr0_rw }, 'i' },
16551   { { OPERAND_pr }, 'i' },
16552   { { OPERAND_mac_qr0 }, 'i' },
16553   { { OPERAND_pr0 }, 'i' }
16554 };
16555
16556 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = {
16557   { { STATE_CPENABLE }, 'i' }
16558 };
16559
16560 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = {
16561   { { OPERAND_mac_qr1_w }, 'o' },
16562   { { OPERAND_mac_qr0_rw }, 'i' },
16563   { { OPERAND_pr }, 'i' },
16564   { { OPERAND_mac_qr0 }, 'i' },
16565   { { OPERAND_pr0 }, 'i' }
16566 };
16567
16568 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = {
16569   { { STATE_CPENABLE }, 'i' }
16570 };
16571
16572 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = {
16573   { { OPERAND_mac_qr1_w }, 'o' },
16574   { { OPERAND_mac_qr0_rw }, 'i' },
16575   { { OPERAND_pr }, 'i' },
16576   { { OPERAND_mac_qr0 }, 'i' },
16577   { { OPERAND_pr0 }, 'i' }
16578 };
16579
16580 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = {
16581   { { STATE_CPENABLE }, 'i' }
16582 };
16583
16584 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = {
16585   { { OPERAND_mac_qr1_w }, 'o' },
16586   { { OPERAND_mac_qr0_rw }, 'i' },
16587   { { OPERAND_pr }, 'i' },
16588   { { OPERAND_mac_qr0 }, 'i' },
16589   { { OPERAND_pr0 }, 'i' }
16590 };
16591
16592 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = {
16593   { { STATE_CPENABLE }, 'i' }
16594 };
16595
16596 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = {
16597   { { OPERAND_mac_qr1_w }, 'o' },
16598   { { OPERAND_mac_qr0_rw }, 'i' },
16599   { { OPERAND_pr }, 'i' },
16600   { { OPERAND_mac_qr0 }, 'i' },
16601   { { OPERAND_pr0 }, 'i' }
16602 };
16603
16604 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = {
16605   { { STATE_CPENABLE }, 'i' }
16606 };
16607
16608 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = {
16609   { { OPERAND_mac_qr1_w }, 'o' },
16610   { { OPERAND_mac_qr0_rw }, 'i' },
16611   { { OPERAND_pr }, 'i' },
16612   { { OPERAND_mac_qr0 }, 'i' },
16613   { { OPERAND_pr0 }, 'i' }
16614 };
16615
16616 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = {
16617   { { STATE_CPENABLE }, 'i' }
16618 };
16619
16620 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = {
16621   { { OPERAND_mac_qr1_w }, 'o' },
16622   { { OPERAND_mac_qr0_rw }, 'i' },
16623   { { OPERAND_pr }, 'i' },
16624   { { OPERAND_mac_qr0 }, 'i' },
16625   { { OPERAND_pr0 }, 'i' }
16626 };
16627
16628 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = {
16629   { { STATE_CPENABLE }, 'i' }
16630 };
16631
16632 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = {
16633   { { OPERAND_mac_qr1_w }, 'o' },
16634   { { OPERAND_mac_qr0_rw }, 'i' },
16635   { { OPERAND_pr }, 'i' },
16636   { { OPERAND_mac_qr0 }, 'i' },
16637   { { OPERAND_pr0 }, 'i' }
16638 };
16639
16640 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = {
16641   { { STATE_CPENABLE }, 'i' }
16642 };
16643
16644 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = {
16645   { { OPERAND_mac_qr1_w }, 'o' },
16646   { { OPERAND_mac_qr0_rw }, 'i' },
16647   { { OPERAND_pr }, 'i' },
16648   { { OPERAND_mac_qr0 }, 'i' },
16649   { { OPERAND_pr0 }, 'i' }
16650 };
16651
16652 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = {
16653   { { STATE_CPENABLE }, 'i' }
16654 };
16655
16656 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = {
16657   { { OPERAND_mac_qr1_w }, 'o' },
16658   { { OPERAND_mac_qr0_rw }, 'i' },
16659   { { OPERAND_pr }, 'i' },
16660   { { OPERAND_mac_qr0 }, 'i' },
16661   { { OPERAND_pr0 }, 'i' }
16662 };
16663
16664 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = {
16665   { { STATE_CPENABLE }, 'i' }
16666 };
16667
16668 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = {
16669   { { OPERAND_mac_qr1_w }, 'o' },
16670   { { OPERAND_mac_qr0_rw }, 'i' },
16671   { { OPERAND_pr }, 'i' },
16672   { { OPERAND_mac_qr0 }, 'i' },
16673   { { OPERAND_pr0 }, 'i' }
16674 };
16675
16676 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = {
16677   { { STATE_CPENABLE }, 'i' }
16678 };
16679
16680 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = {
16681   { { OPERAND_mac_qr1_w }, 'o' },
16682   { { OPERAND_mac_qr0_rw }, 'i' },
16683   { { OPERAND_pr }, 'i' },
16684   { { OPERAND_mac_qr0 }, 'i' },
16685   { { OPERAND_pr0 }, 'i' }
16686 };
16687
16688 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = {
16689   { { STATE_CPENABLE }, 'i' }
16690 };
16691
16692 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = {
16693   { { OPERAND_mac_qr1_w }, 'o' },
16694   { { OPERAND_mac_qr0_rw }, 'i' },
16695   { { OPERAND_pr }, 'i' },
16696   { { OPERAND_mac_qr0 }, 'i' },
16697   { { OPERAND_pr0 }, 'i' }
16698 };
16699
16700 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = {
16701   { { STATE_CPENABLE }, 'i' }
16702 };
16703
16704 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = {
16705   { { OPERAND_mac_qr1_w }, 'o' },
16706   { { OPERAND_mac_qr0_rw }, 'i' },
16707   { { OPERAND_pr }, 'i' },
16708   { { OPERAND_mac_qr0 }, 'i' },
16709   { { OPERAND_pr0 }, 'i' }
16710 };
16711
16712 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = {
16713   { { STATE_CPENABLE }, 'i' }
16714 };
16715
16716 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = {
16717   { { OPERAND_mac_qr1_w }, 'o' },
16718   { { OPERAND_mac_qr0_rw }, 'i' },
16719   { { OPERAND_pr }, 'i' },
16720   { { OPERAND_mac_qr0 }, 'i' },
16721   { { OPERAND_pr0 }, 'i' }
16722 };
16723
16724 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = {
16725   { { STATE_CPENABLE }, 'i' }
16726 };
16727
16728 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = {
16729   { { OPERAND_mac_qr1_w }, 'o' },
16730   { { OPERAND_pr }, 'i' },
16731   { { OPERAND_pr0 }, 'i' }
16732 };
16733
16734 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = {
16735   { { STATE_CPENABLE }, 'i' }
16736 };
16737
16738 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = {
16739   { { OPERAND_mac_qr1_w }, 'o' },
16740   { { OPERAND_pr }, 'i' },
16741   { { OPERAND_pr0 }, 'i' }
16742 };
16743
16744 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = {
16745   { { STATE_CPENABLE }, 'i' }
16746 };
16747
16748 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = {
16749   { { OPERAND_mac_qr1_w }, 'o' },
16750   { { OPERAND_pr }, 'i' },
16751   { { OPERAND_pr0 }, 'i' }
16752 };
16753
16754 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = {
16755   { { STATE_CPENABLE }, 'i' }
16756 };
16757
16758 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = {
16759   { { OPERAND_mac_qr1_w }, 'o' },
16760   { { OPERAND_pr }, 'i' },
16761   { { OPERAND_pr0 }, 'i' }
16762 };
16763
16764 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = {
16765   { { STATE_CPENABLE }, 'i' }
16766 };
16767
16768 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = {
16769   { { OPERAND_mac_qr1_w }, 'o' },
16770   { { OPERAND_pr }, 'i' },
16771   { { OPERAND_pr0 }, 'i' }
16772 };
16773
16774 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = {
16775   { { STATE_CPENABLE }, 'i' }
16776 };
16777
16778 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = {
16779   { { OPERAND_mac_qr1_w }, 'o' },
16780   { { OPERAND_pr }, 'i' },
16781   { { OPERAND_pr0 }, 'i' }
16782 };
16783
16784 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = {
16785   { { STATE_CPENABLE }, 'i' }
16786 };
16787
16788 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = {
16789   { { OPERAND_mac_qr1_w }, 'o' },
16790   { { OPERAND_pr }, 'i' },
16791   { { OPERAND_pr0 }, 'i' }
16792 };
16793
16794 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = {
16795   { { STATE_CPENABLE }, 'i' }
16796 };
16797
16798 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = {
16799   { { OPERAND_mac_qr1_w }, 'o' },
16800   { { OPERAND_pr }, 'i' },
16801   { { OPERAND_pr0 }, 'i' }
16802 };
16803
16804 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = {
16805   { { STATE_CPENABLE }, 'i' }
16806 };
16807
16808 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = {
16809   { { OPERAND_mac_qr1_w }, 'o' },
16810   { { OPERAND_pr }, 'i' },
16811   { { OPERAND_pr0 }, 'i' }
16812 };
16813
16814 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = {
16815   { { STATE_CPENABLE }, 'i' }
16816 };
16817
16818 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = {
16819   { { OPERAND_mac_qr1_w }, 'o' },
16820   { { OPERAND_pr }, 'i' },
16821   { { OPERAND_pr0 }, 'i' }
16822 };
16823
16824 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = {
16825   { { STATE_CPENABLE }, 'i' }
16826 };
16827
16828 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = {
16829   { { OPERAND_mac_qr1_w }, 'o' },
16830   { { OPERAND_pr }, 'i' },
16831   { { OPERAND_pr0 }, 'i' }
16832 };
16833
16834 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = {
16835   { { STATE_CPENABLE }, 'i' }
16836 };
16837
16838 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = {
16839   { { OPERAND_mac_qr1_w }, 'o' },
16840   { { OPERAND_pr }, 'i' },
16841   { { OPERAND_pr0 }, 'i' }
16842 };
16843
16844 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = {
16845   { { STATE_CPENABLE }, 'i' }
16846 };
16847
16848 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = {
16849   { { OPERAND_mac_qr1_w }, 'o' },
16850   { { OPERAND_pr }, 'i' },
16851   { { OPERAND_pr0 }, 'i' }
16852 };
16853
16854 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = {
16855   { { STATE_CPENABLE }, 'i' }
16856 };
16857
16858 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = {
16859   { { OPERAND_mac_qr1_w }, 'o' },
16860   { { OPERAND_pr }, 'i' },
16861   { { OPERAND_pr0 }, 'i' }
16862 };
16863
16864 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = {
16865   { { STATE_CPENABLE }, 'i' }
16866 };
16867
16868 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = {
16869   { { OPERAND_mac_qr1_w }, 'o' },
16870   { { OPERAND_pr }, 'i' },
16871   { { OPERAND_pr0 }, 'i' }
16872 };
16873
16874 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = {
16875   { { STATE_CPENABLE }, 'i' }
16876 };
16877
16878 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = {
16879   { { OPERAND_mac_qr1_w }, 'o' },
16880   { { OPERAND_pr }, 'i' },
16881   { { OPERAND_pr0 }, 'i' }
16882 };
16883
16884 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = {
16885   { { STATE_CPENABLE }, 'i' }
16886 };
16887
16888 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = {
16889   { { OPERAND_mac_qr1_w }, 'm' },
16890   { { OPERAND_pr }, 'i' },
16891   { { OPERAND_pr0 }, 'i' }
16892 };
16893
16894 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = {
16895   { { STATE_CPENABLE }, 'i' }
16896 };
16897
16898 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = {
16899   { { OPERAND_mac_qr1_w }, 'm' },
16900   { { OPERAND_pr }, 'i' },
16901   { { OPERAND_pr0 }, 'i' }
16902 };
16903
16904 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = {
16905   { { STATE_CPENABLE }, 'i' }
16906 };
16907
16908 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = {
16909   { { OPERAND_mac_qr1_w }, 'm' },
16910   { { OPERAND_pr }, 'i' },
16911   { { OPERAND_pr0 }, 'i' }
16912 };
16913
16914 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = {
16915   { { STATE_CPENABLE }, 'i' }
16916 };
16917
16918 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = {
16919   { { OPERAND_mac_qr1_w }, 'm' },
16920   { { OPERAND_pr }, 'i' },
16921   { { OPERAND_pr0 }, 'i' }
16922 };
16923
16924 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = {
16925   { { STATE_CPENABLE }, 'i' }
16926 };
16927
16928 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = {
16929   { { OPERAND_mac_qr1_w }, 'm' },
16930   { { OPERAND_pr }, 'i' },
16931   { { OPERAND_pr0 }, 'i' }
16932 };
16933
16934 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = {
16935   { { STATE_CPENABLE }, 'i' }
16936 };
16937
16938 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = {
16939   { { OPERAND_mac_qr1_w }, 'm' },
16940   { { OPERAND_pr }, 'i' },
16941   { { OPERAND_pr0 }, 'i' }
16942 };
16943
16944 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = {
16945   { { STATE_CPENABLE }, 'i' }
16946 };
16947
16948 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = {
16949   { { OPERAND_mac_qr1_w }, 'm' },
16950   { { OPERAND_pr }, 'i' },
16951   { { OPERAND_pr0 }, 'i' }
16952 };
16953
16954 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = {
16955   { { STATE_CPENABLE }, 'i' }
16956 };
16957
16958 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = {
16959   { { OPERAND_mac_qr1_w }, 'm' },
16960   { { OPERAND_pr }, 'i' },
16961   { { OPERAND_pr0 }, 'i' }
16962 };
16963
16964 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = {
16965   { { STATE_CPENABLE }, 'i' }
16966 };
16967
16968 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = {
16969   { { OPERAND_mac_qr1_w }, 'm' },
16970   { { OPERAND_pr }, 'i' },
16971   { { OPERAND_pr0 }, 'i' }
16972 };
16973
16974 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = {
16975   { { STATE_CPENABLE }, 'i' }
16976 };
16977
16978 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = {
16979   { { OPERAND_mac_qr1_w }, 'm' },
16980   { { OPERAND_pr }, 'i' },
16981   { { OPERAND_pr0 }, 'i' }
16982 };
16983
16984 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = {
16985   { { STATE_CPENABLE }, 'i' }
16986 };
16987
16988 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = {
16989   { { OPERAND_mac_qr1_w }, 'm' },
16990   { { OPERAND_pr }, 'i' },
16991   { { OPERAND_pr0 }, 'i' }
16992 };
16993
16994 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = {
16995   { { STATE_CPENABLE }, 'i' }
16996 };
16997
16998 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = {
16999   { { OPERAND_mac_qr1_w }, 'm' },
17000   { { OPERAND_pr }, 'i' },
17001   { { OPERAND_pr0 }, 'i' }
17002 };
17003
17004 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = {
17005   { { STATE_CPENABLE }, 'i' }
17006 };
17007
17008 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = {
17009   { { OPERAND_mac_qr1_w }, 'm' },
17010   { { OPERAND_pr }, 'i' },
17011   { { OPERAND_pr0 }, 'i' }
17012 };
17013
17014 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = {
17015   { { STATE_CPENABLE }, 'i' }
17016 };
17017
17018 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = {
17019   { { OPERAND_mac_qr1_w }, 'm' },
17020   { { OPERAND_pr }, 'i' },
17021   { { OPERAND_pr0 }, 'i' }
17022 };
17023
17024 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = {
17025   { { STATE_CPENABLE }, 'i' }
17026 };
17027
17028 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = {
17029   { { OPERAND_mac_qr1_w }, 'm' },
17030   { { OPERAND_pr }, 'i' },
17031   { { OPERAND_pr0 }, 'i' }
17032 };
17033
17034 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = {
17035   { { STATE_CPENABLE }, 'i' }
17036 };
17037
17038 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = {
17039   { { OPERAND_mac_qr1_w }, 'm' },
17040   { { OPERAND_pr }, 'i' },
17041   { { OPERAND_pr0 }, 'i' }
17042 };
17043
17044 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = {
17045   { { STATE_CPENABLE }, 'i' }
17046 };
17047
17048 static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = {
17049   { { OPERAND_arr }, 'o' },
17050   { { OPERAND_ars }, 'i' }
17051 };
17052
17053 static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = {
17054   { { OPERAND_br }, 'o' },
17055   { { OPERAND_art }, 'o' },
17056   { { OPERAND_ars }, 'i' }
17057 };
17058
17059 static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = {
17060   { { STATE_AE_TABLESIZE }, 'm' },
17061   { { STATE_AE_BITSUSED }, 'o' },
17062   { { STATE_AE_NEXTOFFSET }, 'm' },
17063   { { STATE_AE_SEARCHDONE }, 'o' },
17064   { { STATE_CPENABLE }, 'i' }
17065 };
17066
17067 static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = {
17068   { { OPERAND_br }, 'o' },
17069   { { OPERAND_art }, 'o' },
17070   { { OPERAND_ars }, 'i' }
17071 };
17072
17073 static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = {
17074   { { STATE_AE_TABLESIZE }, 'm' },
17075   { { STATE_AE_BITSUSED }, 'o' },
17076   { { STATE_AE_NEXTOFFSET }, 'm' },
17077   { { STATE_AE_SEARCHDONE }, 'o' },
17078   { { STATE_CPENABLE }, 'i' }
17079 };
17080
17081 static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = {
17082   { { OPERAND_ars }, 'm' }
17083 };
17084
17085 static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = {
17086   { { STATE_AE_NEXTOFFSET }, 'm' },
17087   { { STATE_AE_TABLESIZE }, 'm' },
17088   { { STATE_AE_BITPTR }, 'm' },
17089   { { STATE_AE_BITHEAD }, 'm' },
17090   { { STATE_AE_FIRST_TS }, 'i' },
17091   { { STATE_AE_BITSUSED }, 'i' },
17092   { { STATE_AE_SEARCHDONE }, 'i' },
17093   { { STATE_CPENABLE }, 'i' }
17094 };
17095
17096 static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = {
17097   { { OPERAND_art }, 'i' }
17098 };
17099
17100 static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = {
17101   { { STATE_AE_BITPTR }, 'i' },
17102   { { STATE_AE_BITHEAD }, 'i' },
17103   { { STATE_AE_FIRST_TS }, 'o' },
17104   { { STATE_AE_NEXTOFFSET }, 'o' },
17105   { { STATE_AE_TABLESIZE }, 'o' },
17106   { { STATE_CPENABLE }, 'i' }
17107 };
17108
17109 static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = {
17110   { { OPERAND_arr }, 'o' },
17111   { { OPERAND_art }, 'i' }
17112 };
17113
17114 static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = {
17115   { { STATE_AE_BITPTR }, 'i' },
17116   { { STATE_AE_BITHEAD }, 'i' },
17117   { { STATE_CPENABLE }, 'i' }
17118 };
17119
17120 static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = {
17121   { { OPERAND_arr }, 'o' },
17122   { { OPERAND_ae_ohba2 }, 'i' }
17123 };
17124
17125 static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = {
17126   { { STATE_AE_BITPTR }, 'i' },
17127   { { STATE_AE_BITHEAD }, 'i' },
17128   { { STATE_CPENABLE }, 'i' }
17129 };
17130
17131 static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = {
17132   { { OPERAND_arr }, 'o' },
17133   { { OPERAND_ars }, 'i' },
17134   { { OPERAND_art }, 'i' }
17135 };
17136
17137 static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = {
17138   { { STATE_AE_BITPTR }, 'i' },
17139   { { STATE_AE_BITHEAD }, 'i' },
17140   { { STATE_CPENABLE }, 'i' }
17141 };
17142
17143 static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = {
17144   { { OPERAND_arr }, 'o' },
17145   { { OPERAND_ars }, 'i' },
17146   { { OPERAND_ae_ohba2 }, 'i' }
17147 };
17148
17149 static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = {
17150   { { STATE_AE_BITPTR }, 'i' },
17151   { { STATE_AE_BITHEAD }, 'i' },
17152   { { STATE_CPENABLE }, 'i' }
17153 };
17154
17155 static xtensa_arg_internal Iclass_ae_iclass_db_args[] = {
17156   { { OPERAND_ars }, 'm' },
17157   { { OPERAND_art }, 'i' }
17158 };
17159
17160 static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = {
17161   { { STATE_AE_BITPTR }, 'm' },
17162   { { STATE_AE_BITHEAD }, 'm' },
17163   { { STATE_CPENABLE }, 'i' }
17164 };
17165
17166 static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = {
17167   { { OPERAND_ars }, 'm' },
17168   { { OPERAND_ae_ohba }, 'i' }
17169 };
17170
17171 static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = {
17172   { { STATE_AE_BITPTR }, 'm' },
17173   { { STATE_AE_BITHEAD }, 'm' },
17174   { { STATE_CPENABLE }, 'i' }
17175 };
17176
17177 static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = {
17178   { { OPERAND_br }, 'o' },
17179   { { OPERAND_art }, 'm' },
17180   { { OPERAND_ars }, 'i' }
17181 };
17182
17183 static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = {
17184   { { STATE_AE_BITSUSED }, 'o' },
17185   { { STATE_AE_NEXTOFFSET }, 'o' },
17186   { { STATE_CPENABLE }, 'i' }
17187 };
17188
17189 static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = {
17190   { { OPERAND_br }, 'o' },
17191   { { OPERAND_art }, 'm' },
17192   { { OPERAND_ars }, 'i' }
17193 };
17194
17195 static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = {
17196   { { STATE_AE_BITSUSED }, 'o' },
17197   { { STATE_AE_NEXTOFFSET }, 'o' },
17198   { { STATE_CPENABLE }, 'i' }
17199 };
17200
17201 static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = {
17202   { { OPERAND_ars }, 'm' },
17203   { { OPERAND_art }, 'i' }
17204 };
17205
17206 static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = {
17207   { { STATE_AE_BITSUSED }, 'i' },
17208   { { STATE_AE_BITPTR }, 'm' },
17209   { { STATE_AE_BITHEAD }, 'm' },
17210   { { STATE_CPENABLE }, 'i' }
17211 };
17212
17213 static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = {
17214   { { OPERAND_ars }, 'm' },
17215   { { OPERAND_art }, 'i' },
17216   { { OPERAND_ae_ohba }, 'i' }
17217 };
17218
17219 static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = {
17220   { { STATE_AE_BITPTR }, 'm' },
17221   { { STATE_AE_BITHEAD }, 'm' },
17222   { { STATE_CPENABLE }, 'i' }
17223 };
17224
17225 static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = {
17226   { { OPERAND_ars }, 'm' }
17227 };
17228
17229 static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = {
17230   { { STATE_AE_BITPTR }, 'm' },
17231   { { STATE_AE_BITHEAD }, 'm' },
17232   { { STATE_AE_BITSUSED }, 'i' },
17233   { { STATE_AE_NEXTOFFSET }, 'i' },
17234   { { STATE_CPENABLE }, 'i' }
17235 };
17236
17237 static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = {
17238   { { OPERAND_ars }, 'm' }
17239 };
17240
17241 static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = {
17242   { { STATE_AE_BITPTR }, 'i' },
17243   { { STATE_AE_BITHEAD }, 'm' },
17244   { { STATE_CPENABLE }, 'i' }
17245 };
17246
17247 static xtensa_iclass_internal iclasses[] = {
17248   { 0, 0 /* xt_iclass_excw */,
17249     0, 0, 0, 0 },
17250   { 0, 0 /* xt_iclass_rfe */,
17251     3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
17252   { 0, 0 /* xt_iclass_rfde */,
17253     3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
17254   { 0, 0 /* xt_iclass_syscall */,
17255     0, 0, 0, 0 },
17256   { 2, Iclass_xt_iclass_call12_args,
17257     1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
17258   { 2, Iclass_xt_iclass_call8_args,
17259     1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
17260   { 2, Iclass_xt_iclass_call4_args,
17261     1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
17262   { 2, Iclass_xt_iclass_callx12_args,
17263     1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
17264   { 2, Iclass_xt_iclass_callx8_args,
17265     1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
17266   { 2, Iclass_xt_iclass_callx4_args,
17267     1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
17268   { 3, Iclass_xt_iclass_entry_args,
17269     5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
17270   { 2, Iclass_xt_iclass_movsp_args,
17271     2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
17272   { 1, Iclass_xt_iclass_rotw_args,
17273     3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
17274   { 1, Iclass_xt_iclass_retw_args,
17275     4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
17276   { 0, 0 /* xt_iclass_rfwou */,
17277     6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
17278   { 3, Iclass_xt_iclass_l32e_args,
17279     2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
17280   { 3, Iclass_xt_iclass_s32e_args,
17281     2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
17282   { 1, Iclass_xt_iclass_rsr_windowbase_args,
17283     3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
17284   { 1, Iclass_xt_iclass_wsr_windowbase_args,
17285     3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
17286   { 1, Iclass_xt_iclass_xsr_windowbase_args,
17287     3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
17288   { 1, Iclass_xt_iclass_rsr_windowstart_args,
17289     3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
17290   { 1, Iclass_xt_iclass_wsr_windowstart_args,
17291     3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
17292   { 1, Iclass_xt_iclass_xsr_windowstart_args,
17293     3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
17294   { 3, Iclass_xt_iclass_add_n_args,
17295     0, 0, 0, 0 },
17296   { 3, Iclass_xt_iclass_addi_n_args,
17297     0, 0, 0, 0 },
17298   { 2, Iclass_xt_iclass_bz6_args,
17299     0, 0, 0, 0 },
17300   { 0, 0 /* xt_iclass_ill_n */,
17301     0, 0, 0, 0 },
17302   { 3, Iclass_xt_iclass_loadi4_args,
17303     0, 0, 0, 0 },
17304   { 2, Iclass_xt_iclass_mov_n_args,
17305     0, 0, 0, 0 },
17306   { 2, Iclass_xt_iclass_movi_n_args,
17307     0, 0, 0, 0 },
17308   { 0, 0 /* xt_iclass_nopn */,
17309     0, 0, 0, 0 },
17310   { 1, Iclass_xt_iclass_retn_args,
17311     0, 0, 0, 0 },
17312   { 3, Iclass_xt_iclass_storei4_args,
17313     0, 0, 0, 0 },
17314   { 1, Iclass_rur_threadptr_args,
17315     1, Iclass_rur_threadptr_stateArgs, 0, 0 },
17316   { 1, Iclass_wur_threadptr_args,
17317     1, Iclass_wur_threadptr_stateArgs, 0, 0 },
17318   { 3, Iclass_xt_iclass_addi_args,
17319     0, 0, 0, 0 },
17320   { 3, Iclass_xt_iclass_addmi_args,
17321     0, 0, 0, 0 },
17322   { 3, Iclass_xt_iclass_addsub_args,
17323     0, 0, 0, 0 },
17324   { 3, Iclass_xt_iclass_bit_args,
17325     0, 0, 0, 0 },
17326   { 3, Iclass_xt_iclass_bsi8_args,
17327     0, 0, 0, 0 },
17328   { 3, Iclass_xt_iclass_bsi8b_args,
17329     0, 0, 0, 0 },
17330   { 3, Iclass_xt_iclass_bsi8u_args,
17331     0, 0, 0, 0 },
17332   { 3, Iclass_xt_iclass_bst8_args,
17333     0, 0, 0, 0 },
17334   { 2, Iclass_xt_iclass_bsz12_args,
17335     0, 0, 0, 0 },
17336   { 2, Iclass_xt_iclass_call0_args,
17337     0, 0, 0, 0 },
17338   { 2, Iclass_xt_iclass_callx0_args,
17339     0, 0, 0, 0 },
17340   { 4, Iclass_xt_iclass_exti_args,
17341     0, 0, 0, 0 },
17342   { 0, 0 /* xt_iclass_ill */,
17343     0, 0, 0, 0 },
17344   { 1, Iclass_xt_iclass_jump_args,
17345     0, 0, 0, 0 },
17346   { 1, Iclass_xt_iclass_jumpx_args,
17347     0, 0, 0, 0 },
17348   { 3, Iclass_xt_iclass_l16ui_args,
17349     0, 0, 0, 0 },
17350   { 3, Iclass_xt_iclass_l16si_args,
17351     0, 0, 0, 0 },
17352   { 3, Iclass_xt_iclass_l32i_args,
17353     0, 0, 0, 0 },
17354   { 2, Iclass_xt_iclass_l32r_args,
17355     2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
17356   { 3, Iclass_xt_iclass_l8i_args,
17357     0, 0, 0, 0 },
17358   { 2, Iclass_xt_iclass_loop_args,
17359     3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
17360   { 2, Iclass_xt_iclass_loopz_args,
17361     3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
17362   { 2, Iclass_xt_iclass_movi_args,
17363     0, 0, 0, 0 },
17364   { 3, Iclass_xt_iclass_movz_args,
17365     0, 0, 0, 0 },
17366   { 2, Iclass_xt_iclass_neg_args,
17367     0, 0, 0, 0 },
17368   { 0, 0 /* xt_iclass_nop */,
17369     0, 0, 0, 0 },
17370   { 1, Iclass_xt_iclass_return_args,
17371     0, 0, 0, 0 },
17372   { 0, 0 /* xt_iclass_simcall */,
17373     0, 0, 0, 0 },
17374   { 3, Iclass_xt_iclass_s16i_args,
17375     0, 0, 0, 0 },
17376   { 3, Iclass_xt_iclass_s32i_args,
17377     0, 0, 0, 0 },
17378   { 3, Iclass_xt_iclass_s8i_args,
17379     0, 0, 0, 0 },
17380   { 1, Iclass_xt_iclass_sar_args,
17381     1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
17382   { 1, Iclass_xt_iclass_sari_args,
17383     1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
17384   { 2, Iclass_xt_iclass_shifts_args,
17385     1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
17386   { 3, Iclass_xt_iclass_shiftst_args,
17387     1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
17388   { 2, Iclass_xt_iclass_shiftt_args,
17389     1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
17390   { 3, Iclass_xt_iclass_slli_args,
17391     0, 0, 0, 0 },
17392   { 3, Iclass_xt_iclass_srai_args,
17393     0, 0, 0, 0 },
17394   { 3, Iclass_xt_iclass_srli_args,
17395     0, 0, 0, 0 },
17396   { 0, 0 /* xt_iclass_memw */,
17397     0, 0, 0, 0 },
17398   { 0, 0 /* xt_iclass_extw */,
17399     0, 0, 0, 0 },
17400   { 0, 0 /* xt_iclass_isync */,
17401     0, 0, 0, 0 },
17402   { 0, 0 /* xt_iclass_sync */,
17403     1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
17404   { 2, Iclass_xt_iclass_rsil_args,
17405     7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
17406   { 1, Iclass_xt_iclass_rsr_lend_args,
17407     1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
17408   { 1, Iclass_xt_iclass_wsr_lend_args,
17409     1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
17410   { 1, Iclass_xt_iclass_xsr_lend_args,
17411     1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
17412   { 1, Iclass_xt_iclass_rsr_lcount_args,
17413     1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
17414   { 1, Iclass_xt_iclass_wsr_lcount_args,
17415     2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
17416   { 1, Iclass_xt_iclass_xsr_lcount_args,
17417     2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
17418   { 1, Iclass_xt_iclass_rsr_lbeg_args,
17419     1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
17420   { 1, Iclass_xt_iclass_wsr_lbeg_args,
17421     1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
17422   { 1, Iclass_xt_iclass_xsr_lbeg_args,
17423     1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
17424   { 1, Iclass_xt_iclass_rsr_sar_args,
17425     1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
17426   { 1, Iclass_xt_iclass_wsr_sar_args,
17427     2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
17428   { 1, Iclass_xt_iclass_xsr_sar_args,
17429     1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
17430   { 1, Iclass_xt_iclass_rsr_litbase_args,
17431     2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
17432   { 1, Iclass_xt_iclass_wsr_litbase_args,
17433     2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
17434   { 1, Iclass_xt_iclass_xsr_litbase_args,
17435     2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
17436   { 1, Iclass_xt_iclass_rsr_configid0_args,
17437     2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 },
17438   { 1, Iclass_xt_iclass_wsr_configid0_args,
17439     2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 },
17440   { 1, Iclass_xt_iclass_rsr_configid1_args,
17441     2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 },
17442   { 1, Iclass_xt_iclass_rsr_ps_args,
17443     7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
17444   { 1, Iclass_xt_iclass_wsr_ps_args,
17445     7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
17446   { 1, Iclass_xt_iclass_xsr_ps_args,
17447     7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
17448   { 1, Iclass_xt_iclass_rsr_epc1_args,
17449     3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
17450   { 1, Iclass_xt_iclass_wsr_epc1_args,
17451     3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
17452   { 1, Iclass_xt_iclass_xsr_epc1_args,
17453     3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
17454   { 1, Iclass_xt_iclass_rsr_excsave1_args,
17455     3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
17456   { 1, Iclass_xt_iclass_wsr_excsave1_args,
17457     3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
17458   { 1, Iclass_xt_iclass_xsr_excsave1_args,
17459     3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
17460   { 1, Iclass_xt_iclass_rsr_epc2_args,
17461     3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
17462   { 1, Iclass_xt_iclass_wsr_epc2_args,
17463     3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
17464   { 1, Iclass_xt_iclass_xsr_epc2_args,
17465     3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
17466   { 1, Iclass_xt_iclass_rsr_excsave2_args,
17467     3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
17468   { 1, Iclass_xt_iclass_wsr_excsave2_args,
17469     3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
17470   { 1, Iclass_xt_iclass_xsr_excsave2_args,
17471     3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
17472   { 1, Iclass_xt_iclass_rsr_eps2_args,
17473     3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
17474   { 1, Iclass_xt_iclass_wsr_eps2_args,
17475     3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
17476   { 1, Iclass_xt_iclass_xsr_eps2_args,
17477     3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
17478   { 1, Iclass_xt_iclass_rsr_excvaddr_args,
17479     3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
17480   { 1, Iclass_xt_iclass_wsr_excvaddr_args,
17481     3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
17482   { 1, Iclass_xt_iclass_xsr_excvaddr_args,
17483     3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
17484   { 1, Iclass_xt_iclass_rsr_depc_args,
17485     3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
17486   { 1, Iclass_xt_iclass_wsr_depc_args,
17487     3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
17488   { 1, Iclass_xt_iclass_xsr_depc_args,
17489     3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
17490   { 1, Iclass_xt_iclass_rsr_exccause_args,
17491     4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
17492   { 1, Iclass_xt_iclass_wsr_exccause_args,
17493     3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
17494   { 1, Iclass_xt_iclass_xsr_exccause_args,
17495     3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
17496   { 1, Iclass_xt_iclass_rsr_misc0_args,
17497     3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
17498   { 1, Iclass_xt_iclass_wsr_misc0_args,
17499     3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
17500   { 1, Iclass_xt_iclass_xsr_misc0_args,
17501     3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
17502   { 1, Iclass_xt_iclass_rsr_misc1_args,
17503     3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
17504   { 1, Iclass_xt_iclass_wsr_misc1_args,
17505     3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
17506   { 1, Iclass_xt_iclass_xsr_misc1_args,
17507     3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
17508   { 1, Iclass_xt_iclass_rsr_prid_args,
17509     2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
17510   { 1, Iclass_xt_iclass_rsr_vecbase_args,
17511     3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
17512   { 1, Iclass_xt_iclass_wsr_vecbase_args,
17513     3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
17514   { 1, Iclass_xt_iclass_xsr_vecbase_args,
17515     3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
17516   { 3, Iclass_xt_mul16_args,
17517     0, 0, 0, 0 },
17518   { 3, Iclass_xt_mul32_args,
17519     0, 0, 0, 0 },
17520   { 1, Iclass_xt_iclass_rfi_args,
17521     11, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
17522   { 1, Iclass_xt_iclass_wait_args,
17523     3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
17524   { 1, Iclass_xt_iclass_rsr_interrupt_args,
17525     3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
17526   { 1, Iclass_xt_iclass_wsr_intset_args,
17527     4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
17528   { 1, Iclass_xt_iclass_wsr_intclear_args,
17529     4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
17530   { 1, Iclass_xt_iclass_rsr_intenable_args,
17531     3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
17532   { 1, Iclass_xt_iclass_wsr_intenable_args,
17533     3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
17534   { 1, Iclass_xt_iclass_xsr_intenable_args,
17535     3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
17536   { 2, Iclass_xt_iclass_break_args,
17537     2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
17538   { 1, Iclass_xt_iclass_break_n_args,
17539     2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
17540   { 1, Iclass_xt_iclass_rsr_debugcause_args,
17541     4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
17542   { 1, Iclass_xt_iclass_wsr_debugcause_args,
17543     4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
17544   { 1, Iclass_xt_iclass_xsr_debugcause_args,
17545     4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
17546   { 1, Iclass_xt_iclass_rsr_icount_args,
17547     3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
17548   { 1, Iclass_xt_iclass_wsr_icount_args,
17549     4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
17550   { 1, Iclass_xt_iclass_xsr_icount_args,
17551     4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
17552   { 1, Iclass_xt_iclass_rsr_icountlevel_args,
17553     3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
17554   { 1, Iclass_xt_iclass_wsr_icountlevel_args,
17555     3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
17556   { 1, Iclass_xt_iclass_xsr_icountlevel_args,
17557     3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
17558   { 1, Iclass_xt_iclass_rsr_ddr_args,
17559     3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
17560   { 1, Iclass_xt_iclass_wsr_ddr_args,
17561     4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
17562   { 1, Iclass_xt_iclass_xsr_ddr_args,
17563     4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
17564   { 1, Iclass_xt_iclass_rfdo_args,
17565     10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
17566   { 0, 0 /* xt_iclass_rfdd */,
17567     1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
17568   { 3, Iclass_xt_iclass_bbool1_args,
17569     0, 0, 0, 0 },
17570   { 2, Iclass_xt_iclass_bbool4_args,
17571     0, 0, 0, 0 },
17572   { 2, Iclass_xt_iclass_bbool8_args,
17573     0, 0, 0, 0 },
17574   { 2, Iclass_xt_iclass_bbranch_args,
17575     0, 0, 0, 0 },
17576   { 3, Iclass_xt_iclass_bmove_args,
17577     0, 0, 0, 0 },
17578   { 2, Iclass_xt_iclass_RSR_BR_args,
17579     0, 0, 0, 0 },
17580   { 2, Iclass_xt_iclass_WSR_BR_args,
17581     0, 0, 0, 0 },
17582   { 2, Iclass_xt_iclass_XSR_BR_args,
17583     0, 0, 0, 0 },
17584   { 1, Iclass_xt_iclass_rsr_ccount_args,
17585     3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
17586   { 1, Iclass_xt_iclass_wsr_ccount_args,
17587     4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
17588   { 1, Iclass_xt_iclass_xsr_ccount_args,
17589     4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
17590   { 1, Iclass_xt_iclass_rsr_ccompare0_args,
17591     3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
17592   { 1, Iclass_xt_iclass_wsr_ccompare0_args,
17593     4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
17594   { 1, Iclass_xt_iclass_xsr_ccompare0_args,
17595     4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
17596   { 1, Iclass_xt_iclass_rsr_ccompare1_args,
17597     3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
17598   { 1, Iclass_xt_iclass_wsr_ccompare1_args,
17599     4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
17600   { 1, Iclass_xt_iclass_xsr_ccompare1_args,
17601     4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
17602   { 2, Iclass_xt_iclass_icache_args,
17603     0, 0, 0, 0 },
17604   { 2, Iclass_xt_iclass_icache_inv_args,
17605     2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
17606   { 2, Iclass_xt_iclass_licx_args,
17607     2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
17608   { 2, Iclass_xt_iclass_sicx_args,
17609     2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
17610   { 2, Iclass_xt_iclass_dcache_args,
17611     0, 0, 0, 0 },
17612   { 2, Iclass_xt_iclass_dcache_ind_args,
17613     2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
17614   { 2, Iclass_xt_iclass_dcache_inv_args,
17615     2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
17616   { 2, Iclass_xt_iclass_dpf_args,
17617     0, 0, 0, 0 },
17618   { 2, Iclass_xt_iclass_sdct_args,
17619     2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
17620   { 2, Iclass_xt_iclass_ldct_args,
17621     2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
17622   { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
17623     4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
17624   { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
17625     4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
17626   { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
17627     5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
17628   { 1, Iclass_xt_iclass_rsr_rasid_args,
17629     5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
17630   { 1, Iclass_xt_iclass_wsr_rasid_args,
17631     6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
17632   { 1, Iclass_xt_iclass_xsr_rasid_args,
17633     6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
17634   { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
17635     3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
17636   { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
17637     4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
17638   { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
17639     4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
17640   { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
17641     3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
17642   { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
17643     4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
17644   { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
17645     4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
17646   { 1, Iclass_xt_iclass_idtlb_args,
17647     3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
17648   { 2, Iclass_xt_iclass_rdtlb_args,
17649     2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
17650   { 2, Iclass_xt_iclass_wdtlb_args,
17651     3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
17652   { 1, Iclass_xt_iclass_iitlb_args,
17653     2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
17654   { 2, Iclass_xt_iclass_ritlb_args,
17655     2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
17656   { 2, Iclass_xt_iclass_witlb_args,
17657     2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
17658   { 0, 0 /* xt_iclass_ldpte */,
17659     2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
17660   { 0, 0 /* xt_iclass_hwwitlba */,
17661     1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
17662   { 0, 0 /* xt_iclass_hwwdtlba */,
17663     1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
17664   { 1, Iclass_xt_iclass_rsr_cpenable_args,
17665     3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
17666   { 1, Iclass_xt_iclass_wsr_cpenable_args,
17667     3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
17668   { 1, Iclass_xt_iclass_xsr_cpenable_args,
17669     3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
17670   { 3, Iclass_xt_iclass_clamp_args,
17671     0, 0, 0, 0 },
17672   { 3, Iclass_xt_iclass_minmax_args,
17673     0, 0, 0, 0 },
17674   { 2, Iclass_xt_iclass_nsa_args,
17675     0, 0, 0, 0 },
17676   { 3, Iclass_xt_iclass_sx_args,
17677     0, 0, 0, 0 },
17678   { 3, Iclass_xt_iclass_l32ai_args,
17679     0, 0, 0, 0 },
17680   { 3, Iclass_xt_iclass_s32ri_args,
17681     0, 0, 0, 0 },
17682   { 3, Iclass_xt_iclass_s32c1i_args,
17683     3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
17684   { 1, Iclass_xt_iclass_rsr_scompare1_args,
17685     1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
17686   { 1, Iclass_xt_iclass_wsr_scompare1_args,
17687     1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
17688   { 1, Iclass_xt_iclass_xsr_scompare1_args,
17689     1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
17690   { 1, Iclass_xt_iclass_rsr_atomctl_args,
17691     3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
17692   { 1, Iclass_xt_iclass_wsr_atomctl_args,
17693     4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
17694   { 1, Iclass_xt_iclass_xsr_atomctl_args,
17695     4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
17696   { 2, Iclass_xt_iclass_rer_args,
17697     4, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
17698   { 2, Iclass_xt_iclass_wer_args,
17699     7, Iclass_xt_iclass_wer_stateArgs, 0, 0 },
17700   { 1, Iclass_rur_ae_ovf_sar_args,
17701     3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 },
17702   { 1, Iclass_wur_ae_ovf_sar_args,
17703     3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 },
17704   { 1, Iclass_rur_ae_bithead_args,
17705     2, Iclass_rur_ae_bithead_stateArgs, 0, 0 },
17706   { 1, Iclass_wur_ae_bithead_args,
17707     2, Iclass_wur_ae_bithead_stateArgs, 0, 0 },
17708   { 1, Iclass_rur_ae_ts_fts_bu_bp_args,
17709     5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 },
17710   { 1, Iclass_wur_ae_ts_fts_bu_bp_args,
17711     5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 },
17712   { 1, Iclass_rur_ae_sd_no_args,
17713     3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 },
17714   { 1, Iclass_wur_ae_sd_no_args,
17715     3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 },
17716   { 1, Iclass_ae_iclass_rur_ae_overflow_args,
17717     2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 },
17718   { 1, Iclass_ae_iclass_wur_ae_overflow_args,
17719     2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 },
17720   { 1, Iclass_ae_iclass_rur_ae_sar_args,
17721     2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 },
17722   { 1, Iclass_ae_iclass_wur_ae_sar_args,
17723     2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 },
17724   { 1, Iclass_ae_iclass_rur_ae_bitptr_args,
17725     2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 },
17726   { 1, Iclass_ae_iclass_wur_ae_bitptr_args,
17727     2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 },
17728   { 1, Iclass_ae_iclass_rur_ae_bitsused_args,
17729     2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 },
17730   { 1, Iclass_ae_iclass_wur_ae_bitsused_args,
17731     2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 },
17732   { 1, Iclass_ae_iclass_rur_ae_tablesize_args,
17733     2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 },
17734   { 1, Iclass_ae_iclass_wur_ae_tablesize_args,
17735     2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 },
17736   { 1, Iclass_ae_iclass_rur_ae_first_ts_args,
17737     2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 },
17738   { 1, Iclass_ae_iclass_wur_ae_first_ts_args,
17739     2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 },
17740   { 1, Iclass_ae_iclass_rur_ae_nextoffset_args,
17741     2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 },
17742   { 1, Iclass_ae_iclass_wur_ae_nextoffset_args,
17743     2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 },
17744   { 1, Iclass_ae_iclass_rur_ae_searchdone_args,
17745     2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 },
17746   { 1, Iclass_ae_iclass_wur_ae_searchdone_args,
17747     2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 },
17748   { 3, Iclass_ae_iclass_lp16f_i_args,
17749     1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 },
17750   { 3, Iclass_ae_iclass_lp16f_iu_args,
17751     1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 },
17752   { 3, Iclass_ae_iclass_lp16f_x_args,
17753     1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 },
17754   { 3, Iclass_ae_iclass_lp16f_xu_args,
17755     1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 },
17756   { 3, Iclass_ae_iclass_lp24_i_args,
17757     1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 },
17758   { 3, Iclass_ae_iclass_lp24_iu_args,
17759     1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 },
17760   { 3, Iclass_ae_iclass_lp24_x_args,
17761     1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 },
17762   { 3, Iclass_ae_iclass_lp24_xu_args,
17763     1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 },
17764   { 3, Iclass_ae_iclass_lp24f_i_args,
17765     1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 },
17766   { 3, Iclass_ae_iclass_lp24f_iu_args,
17767     1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 },
17768   { 3, Iclass_ae_iclass_lp24f_x_args,
17769     1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 },
17770   { 3, Iclass_ae_iclass_lp24f_xu_args,
17771     1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 },
17772   { 3, Iclass_ae_iclass_lp16x2f_i_args,
17773     1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 },
17774   { 3, Iclass_ae_iclass_lp16x2f_iu_args,
17775     1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 },
17776   { 3, Iclass_ae_iclass_lp16x2f_x_args,
17777     1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 },
17778   { 3, Iclass_ae_iclass_lp16x2f_xu_args,
17779     1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 },
17780   { 3, Iclass_ae_iclass_lp24x2f_i_args,
17781     1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 },
17782   { 3, Iclass_ae_iclass_lp24x2f_iu_args,
17783     1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 },
17784   { 3, Iclass_ae_iclass_lp24x2f_x_args,
17785     1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 },
17786   { 3, Iclass_ae_iclass_lp24x2f_xu_args,
17787     1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 },
17788   { 3, Iclass_ae_iclass_lp24x2_i_args,
17789     1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 },
17790   { 3, Iclass_ae_iclass_lp24x2_iu_args,
17791     1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 },
17792   { 3, Iclass_ae_iclass_lp24x2_x_args,
17793     1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 },
17794   { 3, Iclass_ae_iclass_lp24x2_xu_args,
17795     1, Iclass_ae_iclass_lp24x2_xu_stateArgs, 0, 0 },
17796   { 3, Iclass_ae_iclass_sp16x2f_i_args,
17797     1, Iclass_ae_iclass_sp16x2f_i_stateArgs, 0, 0 },
17798   { 3, Iclass_ae_iclass_sp16x2f_iu_args,
17799     1, Iclass_ae_iclass_sp16x2f_iu_stateArgs, 0, 0 },
17800   { 3, Iclass_ae_iclass_sp16x2f_x_args,
17801     1, Iclass_ae_iclass_sp16x2f_x_stateArgs, 0, 0 },
17802   { 3, Iclass_ae_iclass_sp16x2f_xu_args,
17803     1, Iclass_ae_iclass_sp16x2f_xu_stateArgs, 0, 0 },
17804   { 3, Iclass_ae_iclass_sp24x2s_i_args,
17805     1, Iclass_ae_iclass_sp24x2s_i_stateArgs, 0, 0 },
17806   { 3, Iclass_ae_iclass_sp24x2s_iu_args,
17807     1, Iclass_ae_iclass_sp24x2s_iu_stateArgs, 0, 0 },
17808   { 3, Iclass_ae_iclass_sp24x2s_x_args,
17809     1, Iclass_ae_iclass_sp24x2s_x_stateArgs, 0, 0 },
17810   { 3, Iclass_ae_iclass_sp24x2s_xu_args,
17811     1, Iclass_ae_iclass_sp24x2s_xu_stateArgs, 0, 0 },
17812   { 3, Iclass_ae_iclass_sp24x2f_i_args,
17813     1, Iclass_ae_iclass_sp24x2f_i_stateArgs, 0, 0 },
17814   { 3, Iclass_ae_iclass_sp24x2f_iu_args,
17815     1, Iclass_ae_iclass_sp24x2f_iu_stateArgs, 0, 0 },
17816   { 3, Iclass_ae_iclass_sp24x2f_x_args,
17817     1, Iclass_ae_iclass_sp24x2f_x_stateArgs, 0, 0 },
17818   { 3, Iclass_ae_iclass_sp24x2f_xu_args,
17819     1, Iclass_ae_iclass_sp24x2f_xu_stateArgs, 0, 0 },
17820   { 3, Iclass_ae_iclass_sp16f_l_i_args,
17821     1, Iclass_ae_iclass_sp16f_l_i_stateArgs, 0, 0 },
17822   { 3, Iclass_ae_iclass_sp16f_l_iu_args,
17823     1, Iclass_ae_iclass_sp16f_l_iu_stateArgs, 0, 0 },
17824   { 3, Iclass_ae_iclass_sp16f_l_x_args,
17825     1, Iclass_ae_iclass_sp16f_l_x_stateArgs, 0, 0 },
17826   { 3, Iclass_ae_iclass_sp16f_l_xu_args,
17827     1, Iclass_ae_iclass_sp16f_l_xu_stateArgs, 0, 0 },
17828   { 3, Iclass_ae_iclass_sp24s_l_i_args,
17829     1, Iclass_ae_iclass_sp24s_l_i_stateArgs, 0, 0 },
17830   { 3, Iclass_ae_iclass_sp24s_l_iu_args,
17831     1, Iclass_ae_iclass_sp24s_l_iu_stateArgs, 0, 0 },
17832   { 3, Iclass_ae_iclass_sp24s_l_x_args,
17833     1, Iclass_ae_iclass_sp24s_l_x_stateArgs, 0, 0 },
17834   { 3, Iclass_ae_iclass_sp24s_l_xu_args,
17835     1, Iclass_ae_iclass_sp24s_l_xu_stateArgs, 0, 0 },
17836   { 3, Iclass_ae_iclass_sp24f_l_i_args,
17837     1, Iclass_ae_iclass_sp24f_l_i_stateArgs, 0, 0 },
17838   { 3, Iclass_ae_iclass_sp24f_l_iu_args,
17839     1, Iclass_ae_iclass_sp24f_l_iu_stateArgs, 0, 0 },
17840   { 3, Iclass_ae_iclass_sp24f_l_x_args,
17841     1, Iclass_ae_iclass_sp24f_l_x_stateArgs, 0, 0 },
17842   { 3, Iclass_ae_iclass_sp24f_l_xu_args,
17843     1, Iclass_ae_iclass_sp24f_l_xu_stateArgs, 0, 0 },
17844   { 3, Iclass_ae_iclass_lq56_i_args,
17845     1, Iclass_ae_iclass_lq56_i_stateArgs, 0, 0 },
17846   { 3, Iclass_ae_iclass_lq56_iu_args,
17847     1, Iclass_ae_iclass_lq56_iu_stateArgs, 0, 0 },
17848   { 3, Iclass_ae_iclass_lq56_x_args,
17849     1, Iclass_ae_iclass_lq56_x_stateArgs, 0, 0 },
17850   { 3, Iclass_ae_iclass_lq56_xu_args,
17851     1, Iclass_ae_iclass_lq56_xu_stateArgs, 0, 0 },
17852   { 3, Iclass_ae_iclass_lq32f_i_args,
17853     1, Iclass_ae_iclass_lq32f_i_stateArgs, 0, 0 },
17854   { 3, Iclass_ae_iclass_lq32f_iu_args,
17855     1, Iclass_ae_iclass_lq32f_iu_stateArgs, 0, 0 },
17856   { 3, Iclass_ae_iclass_lq32f_x_args,
17857     1, Iclass_ae_iclass_lq32f_x_stateArgs, 0, 0 },
17858   { 3, Iclass_ae_iclass_lq32f_xu_args,
17859     1, Iclass_ae_iclass_lq32f_xu_stateArgs, 0, 0 },
17860   { 3, Iclass_ae_iclass_sq56s_i_args,
17861     1, Iclass_ae_iclass_sq56s_i_stateArgs, 0, 0 },
17862   { 3, Iclass_ae_iclass_sq56s_iu_args,
17863     1, Iclass_ae_iclass_sq56s_iu_stateArgs, 0, 0 },
17864   { 3, Iclass_ae_iclass_sq56s_x_args,
17865     1, Iclass_ae_iclass_sq56s_x_stateArgs, 0, 0 },
17866   { 3, Iclass_ae_iclass_sq56s_xu_args,
17867     1, Iclass_ae_iclass_sq56s_xu_stateArgs, 0, 0 },
17868   { 3, Iclass_ae_iclass_sq32f_i_args,
17869     1, Iclass_ae_iclass_sq32f_i_stateArgs, 0, 0 },
17870   { 3, Iclass_ae_iclass_sq32f_iu_args,
17871     1, Iclass_ae_iclass_sq32f_iu_stateArgs, 0, 0 },
17872   { 3, Iclass_ae_iclass_sq32f_x_args,
17873     1, Iclass_ae_iclass_sq32f_x_stateArgs, 0, 0 },
17874   { 3, Iclass_ae_iclass_sq32f_xu_args,
17875     1, Iclass_ae_iclass_sq32f_xu_stateArgs, 0, 0 },
17876   { 1, Iclass_ae_iclass_zerop48_args,
17877     1, Iclass_ae_iclass_zerop48_stateArgs, 0, 0 },
17878   { 2, Iclass_ae_iclass_movp48_args,
17879     1, Iclass_ae_iclass_movp48_stateArgs, 0, 0 },
17880   { 3, Iclass_ae_iclass_selp24_ll_args,
17881     1, Iclass_ae_iclass_selp24_ll_stateArgs, 0, 0 },
17882   { 3, Iclass_ae_iclass_selp24_lh_args,
17883     1, Iclass_ae_iclass_selp24_lh_stateArgs, 0, 0 },
17884   { 3, Iclass_ae_iclass_selp24_hl_args,
17885     1, Iclass_ae_iclass_selp24_hl_stateArgs, 0, 0 },
17886   { 3, Iclass_ae_iclass_selp24_hh_args,
17887     1, Iclass_ae_iclass_selp24_hh_stateArgs, 0, 0 },
17888   { 3, Iclass_ae_iclass_movtp24x2_args,
17889     1, Iclass_ae_iclass_movtp24x2_stateArgs, 0, 0 },
17890   { 3, Iclass_ae_iclass_movfp24x2_args,
17891     1, Iclass_ae_iclass_movfp24x2_stateArgs, 0, 0 },
17892   { 3, Iclass_ae_iclass_movtp48_args,
17893     1, Iclass_ae_iclass_movtp48_stateArgs, 0, 0 },
17894   { 3, Iclass_ae_iclass_movfp48_args,
17895     1, Iclass_ae_iclass_movfp48_stateArgs, 0, 0 },
17896   { 3, Iclass_ae_iclass_movpa24x2_args,
17897     1, Iclass_ae_iclass_movpa24x2_stateArgs, 0, 0 },
17898   { 3, Iclass_ae_iclass_truncp24a32x2_args,
17899     1, Iclass_ae_iclass_truncp24a32x2_stateArgs, 0, 0 },
17900   { 2, Iclass_ae_iclass_cvta32p24_l_args,
17901     1, Iclass_ae_iclass_cvta32p24_l_stateArgs, 0, 0 },
17902   { 2, Iclass_ae_iclass_cvta32p24_h_args,
17903     1, Iclass_ae_iclass_cvta32p24_h_stateArgs, 0, 0 },
17904   { 3, Iclass_ae_iclass_cvtp24a16x2_ll_args,
17905     1, Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs, 0, 0 },
17906   { 3, Iclass_ae_iclass_cvtp24a16x2_lh_args,
17907     1, Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs, 0, 0 },
17908   { 3, Iclass_ae_iclass_cvtp24a16x2_hl_args,
17909     1, Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs, 0, 0 },
17910   { 3, Iclass_ae_iclass_cvtp24a16x2_hh_args,
17911     1, Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs, 0, 0 },
17912   { 3, Iclass_ae_iclass_truncp24q48x2_args,
17913     1, Iclass_ae_iclass_truncp24q48x2_stateArgs, 0, 0 },
17914   { 2, Iclass_ae_iclass_truncp16_args,
17915     1, Iclass_ae_iclass_truncp16_stateArgs, 0, 0 },
17916   { 2, Iclass_ae_iclass_roundsp24q48sym_args,
17917     2, Iclass_ae_iclass_roundsp24q48sym_stateArgs, 0, 0 },
17918   { 2, Iclass_ae_iclass_roundsp24q48asym_args,
17919     2, Iclass_ae_iclass_roundsp24q48asym_stateArgs, 0, 0 },
17920   { 2, Iclass_ae_iclass_roundsp16q48sym_args,
17921     2, Iclass_ae_iclass_roundsp16q48sym_stateArgs, 0, 0 },
17922   { 2, Iclass_ae_iclass_roundsp16q48asym_args,
17923     2, Iclass_ae_iclass_roundsp16q48asym_stateArgs, 0, 0 },
17924   { 2, Iclass_ae_iclass_roundsp16sym_args,
17925     2, Iclass_ae_iclass_roundsp16sym_stateArgs, 0, 0 },
17926   { 2, Iclass_ae_iclass_roundsp16asym_args,
17927     2, Iclass_ae_iclass_roundsp16asym_stateArgs, 0, 0 },
17928   { 1, Iclass_ae_iclass_zeroq56_args,
17929     1, Iclass_ae_iclass_zeroq56_stateArgs, 0, 0 },
17930   { 2, Iclass_ae_iclass_movq56_args,
17931     1, Iclass_ae_iclass_movq56_stateArgs, 0, 0 },
17932   { 3, Iclass_ae_iclass_movtq56_args,
17933     1, Iclass_ae_iclass_movtq56_stateArgs, 0, 0 },
17934   { 3, Iclass_ae_iclass_movfq56_args,
17935     1, Iclass_ae_iclass_movfq56_stateArgs, 0, 0 },
17936   { 2, Iclass_ae_iclass_cvtq48a32s_args,
17937     1, Iclass_ae_iclass_cvtq48a32s_stateArgs, 0, 0 },
17938   { 2, Iclass_ae_iclass_cvtq48p24s_l_args,
17939     1, Iclass_ae_iclass_cvtq48p24s_l_stateArgs, 0, 0 },
17940   { 2, Iclass_ae_iclass_cvtq48p24s_h_args,
17941     1, Iclass_ae_iclass_cvtq48p24s_h_stateArgs, 0, 0 },
17942   { 2, Iclass_ae_iclass_satq48s_args,
17943     2, Iclass_ae_iclass_satq48s_stateArgs, 0, 0 },
17944   { 2, Iclass_ae_iclass_truncq32_args,
17945     1, Iclass_ae_iclass_truncq32_stateArgs, 0, 0 },
17946   { 2, Iclass_ae_iclass_roundsq32sym_args,
17947     2, Iclass_ae_iclass_roundsq32sym_stateArgs, 0, 0 },
17948   { 2, Iclass_ae_iclass_roundsq32asym_args,
17949     2, Iclass_ae_iclass_roundsq32asym_stateArgs, 0, 0 },
17950   { 2, Iclass_ae_iclass_trunca32q48_args,
17951     1, Iclass_ae_iclass_trunca32q48_stateArgs, 0, 0 },
17952   { 2, Iclass_ae_iclass_movap24s_l_args,
17953     1, Iclass_ae_iclass_movap24s_l_stateArgs, 0, 0 },
17954   { 2, Iclass_ae_iclass_movap24s_h_args,
17955     1, Iclass_ae_iclass_movap24s_h_stateArgs, 0, 0 },
17956   { 2, Iclass_ae_iclass_trunca16p24s_l_args,
17957     1, Iclass_ae_iclass_trunca16p24s_l_stateArgs, 0, 0 },
17958   { 2, Iclass_ae_iclass_trunca16p24s_h_args,
17959     1, Iclass_ae_iclass_trunca16p24s_h_stateArgs, 0, 0 },
17960   { 3, Iclass_ae_iclass_addp24_args,
17961     1, Iclass_ae_iclass_addp24_stateArgs, 0, 0 },
17962   { 3, Iclass_ae_iclass_subp24_args,
17963     1, Iclass_ae_iclass_subp24_stateArgs, 0, 0 },
17964   { 2, Iclass_ae_iclass_negp24_args,
17965     1, Iclass_ae_iclass_negp24_stateArgs, 0, 0 },
17966   { 2, Iclass_ae_iclass_absp24_args,
17967     1, Iclass_ae_iclass_absp24_stateArgs, 0, 0 },
17968   { 3, Iclass_ae_iclass_maxp24s_args,
17969     1, Iclass_ae_iclass_maxp24s_stateArgs, 0, 0 },
17970   { 3, Iclass_ae_iclass_minp24s_args,
17971     1, Iclass_ae_iclass_minp24s_stateArgs, 0, 0 },
17972   { 4, Iclass_ae_iclass_maxbp24s_args,
17973     1, Iclass_ae_iclass_maxbp24s_stateArgs, 0, 0 },
17974   { 4, Iclass_ae_iclass_minbp24s_args,
17975     1, Iclass_ae_iclass_minbp24s_stateArgs, 0, 0 },
17976   { 3, Iclass_ae_iclass_addsp24s_args,
17977     2, Iclass_ae_iclass_addsp24s_stateArgs, 0, 0 },
17978   { 3, Iclass_ae_iclass_subsp24s_args,
17979     2, Iclass_ae_iclass_subsp24s_stateArgs, 0, 0 },
17980   { 2, Iclass_ae_iclass_negsp24s_args,
17981     2, Iclass_ae_iclass_negsp24s_stateArgs, 0, 0 },
17982   { 2, Iclass_ae_iclass_abssp24s_args,
17983     2, Iclass_ae_iclass_abssp24s_stateArgs, 0, 0 },
17984   { 3, Iclass_ae_iclass_andp48_args,
17985     1, Iclass_ae_iclass_andp48_stateArgs, 0, 0 },
17986   { 3, Iclass_ae_iclass_nandp48_args,
17987     1, Iclass_ae_iclass_nandp48_stateArgs, 0, 0 },
17988   { 3, Iclass_ae_iclass_orp48_args,
17989     1, Iclass_ae_iclass_orp48_stateArgs, 0, 0 },
17990   { 3, Iclass_ae_iclass_xorp48_args,
17991     1, Iclass_ae_iclass_xorp48_stateArgs, 0, 0 },
17992   { 3, Iclass_ae_iclass_ltp24s_args,
17993     1, Iclass_ae_iclass_ltp24s_stateArgs, 0, 0 },
17994   { 3, Iclass_ae_iclass_lep24s_args,
17995     1, Iclass_ae_iclass_lep24s_stateArgs, 0, 0 },
17996   { 3, Iclass_ae_iclass_eqp24_args,
17997     1, Iclass_ae_iclass_eqp24_stateArgs, 0, 0 },
17998   { 3, Iclass_ae_iclass_addq56_args,
17999     1, Iclass_ae_iclass_addq56_stateArgs, 0, 0 },
18000   { 3, Iclass_ae_iclass_subq56_args,
18001     1, Iclass_ae_iclass_subq56_stateArgs, 0, 0 },
18002   { 2, Iclass_ae_iclass_negq56_args,
18003     1, Iclass_ae_iclass_negq56_stateArgs, 0, 0 },
18004   { 2, Iclass_ae_iclass_absq56_args,
18005     1, Iclass_ae_iclass_absq56_stateArgs, 0, 0 },
18006   { 3, Iclass_ae_iclass_maxq56s_args,
18007     1, Iclass_ae_iclass_maxq56s_stateArgs, 0, 0 },
18008   { 3, Iclass_ae_iclass_minq56s_args,
18009     1, Iclass_ae_iclass_minq56s_stateArgs, 0, 0 },
18010   { 4, Iclass_ae_iclass_maxbq56s_args,
18011     1, Iclass_ae_iclass_maxbq56s_stateArgs, 0, 0 },
18012   { 4, Iclass_ae_iclass_minbq56s_args,
18013     1, Iclass_ae_iclass_minbq56s_stateArgs, 0, 0 },
18014   { 3, Iclass_ae_iclass_addsq56s_args,
18015     2, Iclass_ae_iclass_addsq56s_stateArgs, 0, 0 },
18016   { 3, Iclass_ae_iclass_subsq56s_args,
18017     2, Iclass_ae_iclass_subsq56s_stateArgs, 0, 0 },
18018   { 2, Iclass_ae_iclass_negsq56s_args,
18019     2, Iclass_ae_iclass_negsq56s_stateArgs, 0, 0 },
18020   { 2, Iclass_ae_iclass_abssq56s_args,
18021     2, Iclass_ae_iclass_abssq56s_stateArgs, 0, 0 },
18022   { 3, Iclass_ae_iclass_andq56_args,
18023     1, Iclass_ae_iclass_andq56_stateArgs, 0, 0 },
18024   { 3, Iclass_ae_iclass_nandq56_args,
18025     1, Iclass_ae_iclass_nandq56_stateArgs, 0, 0 },
18026   { 3, Iclass_ae_iclass_orq56_args,
18027     1, Iclass_ae_iclass_orq56_stateArgs, 0, 0 },
18028   { 3, Iclass_ae_iclass_xorq56_args,
18029     1, Iclass_ae_iclass_xorq56_stateArgs, 0, 0 },
18030   { 3, Iclass_ae_iclass_sllip24_args,
18031     1, Iclass_ae_iclass_sllip24_stateArgs, 0, 0 },
18032   { 3, Iclass_ae_iclass_srlip24_args,
18033     1, Iclass_ae_iclass_srlip24_stateArgs, 0, 0 },
18034   { 3, Iclass_ae_iclass_sraip24_args,
18035     1, Iclass_ae_iclass_sraip24_stateArgs, 0, 0 },
18036   { 2, Iclass_ae_iclass_sllsp24_args,
18037     2, Iclass_ae_iclass_sllsp24_stateArgs, 0, 0 },
18038   { 2, Iclass_ae_iclass_srlsp24_args,
18039     2, Iclass_ae_iclass_srlsp24_stateArgs, 0, 0 },
18040   { 2, Iclass_ae_iclass_srasp24_args,
18041     2, Iclass_ae_iclass_srasp24_stateArgs, 0, 0 },
18042   { 3, Iclass_ae_iclass_sllisp24s_args,
18043     2, Iclass_ae_iclass_sllisp24s_stateArgs, 0, 0 },
18044   { 2, Iclass_ae_iclass_sllssp24s_args,
18045     3, Iclass_ae_iclass_sllssp24s_stateArgs, 0, 0 },
18046   { 3, Iclass_ae_iclass_slliq56_args,
18047     1, Iclass_ae_iclass_slliq56_stateArgs, 0, 0 },
18048   { 3, Iclass_ae_iclass_srliq56_args,
18049     1, Iclass_ae_iclass_srliq56_stateArgs, 0, 0 },
18050   { 3, Iclass_ae_iclass_sraiq56_args,
18051     1, Iclass_ae_iclass_sraiq56_stateArgs, 0, 0 },
18052   { 2, Iclass_ae_iclass_sllsq56_args,
18053     2, Iclass_ae_iclass_sllsq56_stateArgs, 0, 0 },
18054   { 2, Iclass_ae_iclass_srlsq56_args,
18055     2, Iclass_ae_iclass_srlsq56_stateArgs, 0, 0 },
18056   { 2, Iclass_ae_iclass_srasq56_args,
18057     2, Iclass_ae_iclass_srasq56_stateArgs, 0, 0 },
18058   { 3, Iclass_ae_iclass_sllaq56_args,
18059     1, Iclass_ae_iclass_sllaq56_stateArgs, 0, 0 },
18060   { 3, Iclass_ae_iclass_srlaq56_args,
18061     1, Iclass_ae_iclass_srlaq56_stateArgs, 0, 0 },
18062   { 3, Iclass_ae_iclass_sraaq56_args,
18063     1, Iclass_ae_iclass_sraaq56_stateArgs, 0, 0 },
18064   { 3, Iclass_ae_iclass_sllisq56s_args,
18065     2, Iclass_ae_iclass_sllisq56s_stateArgs, 0, 0 },
18066   { 2, Iclass_ae_iclass_sllssq56s_args,
18067     3, Iclass_ae_iclass_sllssq56s_stateArgs, 0, 0 },
18068   { 3, Iclass_ae_iclass_sllasq56s_args,
18069     2, Iclass_ae_iclass_sllasq56s_stateArgs, 0, 0 },
18070   { 3, Iclass_ae_iclass_ltq56s_args,
18071     1, Iclass_ae_iclass_ltq56s_stateArgs, 0, 0 },
18072   { 3, Iclass_ae_iclass_leq56s_args,
18073     1, Iclass_ae_iclass_leq56s_stateArgs, 0, 0 },
18074   { 3, Iclass_ae_iclass_eqq56_args,
18075     1, Iclass_ae_iclass_eqq56_stateArgs, 0, 0 },
18076   { 2, Iclass_ae_iclass_nsaq56s_args,
18077     1, Iclass_ae_iclass_nsaq56s_stateArgs, 0, 0 },
18078   { 3, Iclass_ae_iclass_mulfs32p16s_ll_args,
18079     2, Iclass_ae_iclass_mulfs32p16s_ll_stateArgs, 0, 0 },
18080   { 3, Iclass_ae_iclass_mulfp24s_ll_args,
18081     1, Iclass_ae_iclass_mulfp24s_ll_stateArgs, 0, 0 },
18082   { 3, Iclass_ae_iclass_mulp24s_ll_args,
18083     1, Iclass_ae_iclass_mulp24s_ll_stateArgs, 0, 0 },
18084   { 3, Iclass_ae_iclass_mulfs32p16s_lh_args,
18085     2, Iclass_ae_iclass_mulfs32p16s_lh_stateArgs, 0, 0 },
18086   { 3, Iclass_ae_iclass_mulfp24s_lh_args,
18087     1, Iclass_ae_iclass_mulfp24s_lh_stateArgs, 0, 0 },
18088   { 3, Iclass_ae_iclass_mulp24s_lh_args,
18089     1, Iclass_ae_iclass_mulp24s_lh_stateArgs, 0, 0 },
18090   { 3, Iclass_ae_iclass_mulfs32p16s_hl_args,
18091     2, Iclass_ae_iclass_mulfs32p16s_hl_stateArgs, 0, 0 },
18092   { 3, Iclass_ae_iclass_mulfp24s_hl_args,
18093     1, Iclass_ae_iclass_mulfp24s_hl_stateArgs, 0, 0 },
18094   { 3, Iclass_ae_iclass_mulp24s_hl_args,
18095     1, Iclass_ae_iclass_mulp24s_hl_stateArgs, 0, 0 },
18096   { 3, Iclass_ae_iclass_mulfs32p16s_hh_args,
18097     2, Iclass_ae_iclass_mulfs32p16s_hh_stateArgs, 0, 0 },
18098   { 3, Iclass_ae_iclass_mulfp24s_hh_args,
18099     1, Iclass_ae_iclass_mulfp24s_hh_stateArgs, 0, 0 },
18100   { 3, Iclass_ae_iclass_mulp24s_hh_args,
18101     1, Iclass_ae_iclass_mulp24s_hh_stateArgs, 0, 0 },
18102   { 3, Iclass_ae_iclass_mulafs32p16s_ll_args,
18103     2, Iclass_ae_iclass_mulafs32p16s_ll_stateArgs, 0, 0 },
18104   { 3, Iclass_ae_iclass_mulafp24s_ll_args,
18105     1, Iclass_ae_iclass_mulafp24s_ll_stateArgs, 0, 0 },
18106   { 3, Iclass_ae_iclass_mulap24s_ll_args,
18107     1, Iclass_ae_iclass_mulap24s_ll_stateArgs, 0, 0 },
18108   { 3, Iclass_ae_iclass_mulafs32p16s_lh_args,
18109     2, Iclass_ae_iclass_mulafs32p16s_lh_stateArgs, 0, 0 },
18110   { 3, Iclass_ae_iclass_mulafp24s_lh_args,
18111     1, Iclass_ae_iclass_mulafp24s_lh_stateArgs, 0, 0 },
18112   { 3, Iclass_ae_iclass_mulap24s_lh_args,
18113     1, Iclass_ae_iclass_mulap24s_lh_stateArgs, 0, 0 },
18114   { 3, Iclass_ae_iclass_mulafs32p16s_hl_args,
18115     2, Iclass_ae_iclass_mulafs32p16s_hl_stateArgs, 0, 0 },
18116   { 3, Iclass_ae_iclass_mulafp24s_hl_args,
18117     1, Iclass_ae_iclass_mulafp24s_hl_stateArgs, 0, 0 },
18118   { 3, Iclass_ae_iclass_mulap24s_hl_args,
18119     1, Iclass_ae_iclass_mulap24s_hl_stateArgs, 0, 0 },
18120   { 3, Iclass_ae_iclass_mulafs32p16s_hh_args,
18121     2, Iclass_ae_iclass_mulafs32p16s_hh_stateArgs, 0, 0 },
18122   { 3, Iclass_ae_iclass_mulafp24s_hh_args,
18123     1, Iclass_ae_iclass_mulafp24s_hh_stateArgs, 0, 0 },
18124   { 3, Iclass_ae_iclass_mulap24s_hh_args,
18125     1, Iclass_ae_iclass_mulap24s_hh_stateArgs, 0, 0 },
18126   { 3, Iclass_ae_iclass_mulsfs32p16s_ll_args,
18127     2, Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs, 0, 0 },
18128   { 3, Iclass_ae_iclass_mulsfp24s_ll_args,
18129     1, Iclass_ae_iclass_mulsfp24s_ll_stateArgs, 0, 0 },
18130   { 3, Iclass_ae_iclass_mulsp24s_ll_args,
18131     1, Iclass_ae_iclass_mulsp24s_ll_stateArgs, 0, 0 },
18132   { 3, Iclass_ae_iclass_mulsfs32p16s_lh_args,
18133     2, Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs, 0, 0 },
18134   { 3, Iclass_ae_iclass_mulsfp24s_lh_args,
18135     1, Iclass_ae_iclass_mulsfp24s_lh_stateArgs, 0, 0 },
18136   { 3, Iclass_ae_iclass_mulsp24s_lh_args,
18137     1, Iclass_ae_iclass_mulsp24s_lh_stateArgs, 0, 0 },
18138   { 3, Iclass_ae_iclass_mulsfs32p16s_hl_args,
18139     2, Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs, 0, 0 },
18140   { 3, Iclass_ae_iclass_mulsfp24s_hl_args,
18141     1, Iclass_ae_iclass_mulsfp24s_hl_stateArgs, 0, 0 },
18142   { 3, Iclass_ae_iclass_mulsp24s_hl_args,
18143     1, Iclass_ae_iclass_mulsp24s_hl_stateArgs, 0, 0 },
18144   { 3, Iclass_ae_iclass_mulsfs32p16s_hh_args,
18145     2, Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs, 0, 0 },
18146   { 3, Iclass_ae_iclass_mulsfp24s_hh_args,
18147     1, Iclass_ae_iclass_mulsfp24s_hh_stateArgs, 0, 0 },
18148   { 3, Iclass_ae_iclass_mulsp24s_hh_args,
18149     1, Iclass_ae_iclass_mulsp24s_hh_stateArgs, 0, 0 },
18150   { 3, Iclass_ae_iclass_mulafs56p24s_ll_args,
18151     2, Iclass_ae_iclass_mulafs56p24s_ll_stateArgs, 0, 0 },
18152   { 3, Iclass_ae_iclass_mulas56p24s_ll_args,
18153     2, Iclass_ae_iclass_mulas56p24s_ll_stateArgs, 0, 0 },
18154   { 3, Iclass_ae_iclass_mulafs56p24s_lh_args,
18155     2, Iclass_ae_iclass_mulafs56p24s_lh_stateArgs, 0, 0 },
18156   { 3, Iclass_ae_iclass_mulas56p24s_lh_args,
18157     2, Iclass_ae_iclass_mulas56p24s_lh_stateArgs, 0, 0 },
18158   { 3, Iclass_ae_iclass_mulafs56p24s_hl_args,
18159     2, Iclass_ae_iclass_mulafs56p24s_hl_stateArgs, 0, 0 },
18160   { 3, Iclass_ae_iclass_mulas56p24s_hl_args,
18161     2, Iclass_ae_iclass_mulas56p24s_hl_stateArgs, 0, 0 },
18162   { 3, Iclass_ae_iclass_mulafs56p24s_hh_args,
18163     2, Iclass_ae_iclass_mulafs56p24s_hh_stateArgs, 0, 0 },
18164   { 3, Iclass_ae_iclass_mulas56p24s_hh_args,
18165     2, Iclass_ae_iclass_mulas56p24s_hh_stateArgs, 0, 0 },
18166   { 3, Iclass_ae_iclass_mulsfs56p24s_ll_args,
18167     2, Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs, 0, 0 },
18168   { 3, Iclass_ae_iclass_mulss56p24s_ll_args,
18169     2, Iclass_ae_iclass_mulss56p24s_ll_stateArgs, 0, 0 },
18170   { 3, Iclass_ae_iclass_mulsfs56p24s_lh_args,
18171     2, Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs, 0, 0 },
18172   { 3, Iclass_ae_iclass_mulss56p24s_lh_args,
18173     2, Iclass_ae_iclass_mulss56p24s_lh_stateArgs, 0, 0 },
18174   { 3, Iclass_ae_iclass_mulsfs56p24s_hl_args,
18175     2, Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs, 0, 0 },
18176   { 3, Iclass_ae_iclass_mulss56p24s_hl_args,
18177     2, Iclass_ae_iclass_mulss56p24s_hl_stateArgs, 0, 0 },
18178   { 3, Iclass_ae_iclass_mulsfs56p24s_hh_args,
18179     2, Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs, 0, 0 },
18180   { 3, Iclass_ae_iclass_mulss56p24s_hh_args,
18181     2, Iclass_ae_iclass_mulss56p24s_hh_stateArgs, 0, 0 },
18182   { 3, Iclass_ae_iclass_mulfq32sp16s_l_args,
18183     1, Iclass_ae_iclass_mulfq32sp16s_l_stateArgs, 0, 0 },
18184   { 3, Iclass_ae_iclass_mulfq32sp16s_h_args,
18185     1, Iclass_ae_iclass_mulfq32sp16s_h_stateArgs, 0, 0 },
18186   { 3, Iclass_ae_iclass_mulfq32sp16u_l_args,
18187     1, Iclass_ae_iclass_mulfq32sp16u_l_stateArgs, 0, 0 },
18188   { 3, Iclass_ae_iclass_mulfq32sp16u_h_args,
18189     1, Iclass_ae_iclass_mulfq32sp16u_h_stateArgs, 0, 0 },
18190   { 3, Iclass_ae_iclass_mulq32sp16s_l_args,
18191     1, Iclass_ae_iclass_mulq32sp16s_l_stateArgs, 0, 0 },
18192   { 3, Iclass_ae_iclass_mulq32sp16s_h_args,
18193     1, Iclass_ae_iclass_mulq32sp16s_h_stateArgs, 0, 0 },
18194   { 3, Iclass_ae_iclass_mulq32sp16u_l_args,
18195     1, Iclass_ae_iclass_mulq32sp16u_l_stateArgs, 0, 0 },
18196   { 3, Iclass_ae_iclass_mulq32sp16u_h_args,
18197     1, Iclass_ae_iclass_mulq32sp16u_h_stateArgs, 0, 0 },
18198   { 3, Iclass_ae_iclass_mulafq32sp16s_l_args,
18199     1, Iclass_ae_iclass_mulafq32sp16s_l_stateArgs, 0, 0 },
18200   { 3, Iclass_ae_iclass_mulafq32sp16s_h_args,
18201     1, Iclass_ae_iclass_mulafq32sp16s_h_stateArgs, 0, 0 },
18202   { 3, Iclass_ae_iclass_mulafq32sp16u_l_args,
18203     1, Iclass_ae_iclass_mulafq32sp16u_l_stateArgs, 0, 0 },
18204   { 3, Iclass_ae_iclass_mulafq32sp16u_h_args,
18205     1, Iclass_ae_iclass_mulafq32sp16u_h_stateArgs, 0, 0 },
18206   { 3, Iclass_ae_iclass_mulaq32sp16s_l_args,
18207     1, Iclass_ae_iclass_mulaq32sp16s_l_stateArgs, 0, 0 },
18208   { 3, Iclass_ae_iclass_mulaq32sp16s_h_args,
18209     1, Iclass_ae_iclass_mulaq32sp16s_h_stateArgs, 0, 0 },
18210   { 3, Iclass_ae_iclass_mulaq32sp16u_l_args,
18211     1, Iclass_ae_iclass_mulaq32sp16u_l_stateArgs, 0, 0 },
18212   { 3, Iclass_ae_iclass_mulaq32sp16u_h_args,
18213     1, Iclass_ae_iclass_mulaq32sp16u_h_stateArgs, 0, 0 },
18214   { 3, Iclass_ae_iclass_mulsfq32sp16s_l_args,
18215     1, Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs, 0, 0 },
18216   { 3, Iclass_ae_iclass_mulsfq32sp16s_h_args,
18217     1, Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs, 0, 0 },
18218   { 3, Iclass_ae_iclass_mulsfq32sp16u_l_args,
18219     1, Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs, 0, 0 },
18220   { 3, Iclass_ae_iclass_mulsfq32sp16u_h_args,
18221     1, Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs, 0, 0 },
18222   { 3, Iclass_ae_iclass_mulsq32sp16s_l_args,
18223     1, Iclass_ae_iclass_mulsq32sp16s_l_stateArgs, 0, 0 },
18224   { 3, Iclass_ae_iclass_mulsq32sp16s_h_args,
18225     1, Iclass_ae_iclass_mulsq32sp16s_h_stateArgs, 0, 0 },
18226   { 3, Iclass_ae_iclass_mulsq32sp16u_l_args,
18227     1, Iclass_ae_iclass_mulsq32sp16u_l_stateArgs, 0, 0 },
18228   { 3, Iclass_ae_iclass_mulsq32sp16u_h_args,
18229     1, Iclass_ae_iclass_mulsq32sp16u_h_stateArgs, 0, 0 },
18230   { 5, Iclass_ae_iclass_mulzaaq32sp16s_ll_args,
18231     1, Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs, 0, 0 },
18232   { 5, Iclass_ae_iclass_mulzaafq32sp16s_ll_args,
18233     1, Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs, 0, 0 },
18234   { 5, Iclass_ae_iclass_mulzaaq32sp16u_ll_args,
18235     1, Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs, 0, 0 },
18236   { 5, Iclass_ae_iclass_mulzaafq32sp16u_ll_args,
18237     1, Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs, 0, 0 },
18238   { 5, Iclass_ae_iclass_mulzaaq32sp16s_hh_args,
18239     1, Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs, 0, 0 },
18240   { 5, Iclass_ae_iclass_mulzaafq32sp16s_hh_args,
18241     1, Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs, 0, 0 },
18242   { 5, Iclass_ae_iclass_mulzaaq32sp16u_hh_args,
18243     1, Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs, 0, 0 },
18244   { 5, Iclass_ae_iclass_mulzaafq32sp16u_hh_args,
18245     1, Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs, 0, 0 },
18246   { 5, Iclass_ae_iclass_mulzaaq32sp16s_lh_args,
18247     1, Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs, 0, 0 },
18248   { 5, Iclass_ae_iclass_mulzaafq32sp16s_lh_args,
18249     1, Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs, 0, 0 },
18250   { 5, Iclass_ae_iclass_mulzaaq32sp16u_lh_args,
18251     1, Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs, 0, 0 },
18252   { 5, Iclass_ae_iclass_mulzaafq32sp16u_lh_args,
18253     1, Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs, 0, 0 },
18254   { 5, Iclass_ae_iclass_mulzasq32sp16s_ll_args,
18255     1, Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs, 0, 0 },
18256   { 5, Iclass_ae_iclass_mulzasfq32sp16s_ll_args,
18257     1, Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs, 0, 0 },
18258   { 5, Iclass_ae_iclass_mulzasq32sp16u_ll_args,
18259     1, Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs, 0, 0 },
18260   { 5, Iclass_ae_iclass_mulzasfq32sp16u_ll_args,
18261     1, Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs, 0, 0 },
18262   { 5, Iclass_ae_iclass_mulzasq32sp16s_hh_args,
18263     1, Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs, 0, 0 },
18264   { 5, Iclass_ae_iclass_mulzasfq32sp16s_hh_args,
18265     1, Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs, 0, 0 },
18266   { 5, Iclass_ae_iclass_mulzasq32sp16u_hh_args,
18267     1, Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs, 0, 0 },
18268   { 5, Iclass_ae_iclass_mulzasfq32sp16u_hh_args,
18269     1, Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs, 0, 0 },
18270   { 5, Iclass_ae_iclass_mulzasq32sp16s_lh_args,
18271     1, Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs, 0, 0 },
18272   { 5, Iclass_ae_iclass_mulzasfq32sp16s_lh_args,
18273     1, Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs, 0, 0 },
18274   { 5, Iclass_ae_iclass_mulzasq32sp16u_lh_args,
18275     1, Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs, 0, 0 },
18276   { 5, Iclass_ae_iclass_mulzasfq32sp16u_lh_args,
18277     1, Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs, 0, 0 },
18278   { 5, Iclass_ae_iclass_mulzsaq32sp16s_ll_args,
18279     1, Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs, 0, 0 },
18280   { 5, Iclass_ae_iclass_mulzsafq32sp16s_ll_args,
18281     1, Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs, 0, 0 },
18282   { 5, Iclass_ae_iclass_mulzsaq32sp16u_ll_args,
18283     1, Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs, 0, 0 },
18284   { 5, Iclass_ae_iclass_mulzsafq32sp16u_ll_args,
18285     1, Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs, 0, 0 },
18286   { 5, Iclass_ae_iclass_mulzsaq32sp16s_hh_args,
18287     1, Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs, 0, 0 },
18288   { 5, Iclass_ae_iclass_mulzsafq32sp16s_hh_args,
18289     1, Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs, 0, 0 },
18290   { 5, Iclass_ae_iclass_mulzsaq32sp16u_hh_args,
18291     1, Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs, 0, 0 },
18292   { 5, Iclass_ae_iclass_mulzsafq32sp16u_hh_args,
18293     1, Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs, 0, 0 },
18294   { 5, Iclass_ae_iclass_mulzsaq32sp16s_lh_args,
18295     1, Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs, 0, 0 },
18296   { 5, Iclass_ae_iclass_mulzsafq32sp16s_lh_args,
18297     1, Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs, 0, 0 },
18298   { 5, Iclass_ae_iclass_mulzsaq32sp16u_lh_args,
18299     1, Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs, 0, 0 },
18300   { 5, Iclass_ae_iclass_mulzsafq32sp16u_lh_args,
18301     1, Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs, 0, 0 },
18302   { 5, Iclass_ae_iclass_mulzssq32sp16s_ll_args,
18303     1, Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs, 0, 0 },
18304   { 5, Iclass_ae_iclass_mulzssfq32sp16s_ll_args,
18305     1, Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs, 0, 0 },
18306   { 5, Iclass_ae_iclass_mulzssq32sp16u_ll_args,
18307     1, Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs, 0, 0 },
18308   { 5, Iclass_ae_iclass_mulzssfq32sp16u_ll_args,
18309     1, Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs, 0, 0 },
18310   { 5, Iclass_ae_iclass_mulzssq32sp16s_hh_args,
18311     1, Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs, 0, 0 },
18312   { 5, Iclass_ae_iclass_mulzssfq32sp16s_hh_args,
18313     1, Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs, 0, 0 },
18314   { 5, Iclass_ae_iclass_mulzssq32sp16u_hh_args,
18315     1, Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs, 0, 0 },
18316   { 5, Iclass_ae_iclass_mulzssfq32sp16u_hh_args,
18317     1, Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs, 0, 0 },
18318   { 5, Iclass_ae_iclass_mulzssq32sp16s_lh_args,
18319     1, Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs, 0, 0 },
18320   { 5, Iclass_ae_iclass_mulzssfq32sp16s_lh_args,
18321     1, Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs, 0, 0 },
18322   { 5, Iclass_ae_iclass_mulzssq32sp16u_lh_args,
18323     1, Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs, 0, 0 },
18324   { 5, Iclass_ae_iclass_mulzssfq32sp16u_lh_args,
18325     1, Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs, 0, 0 },
18326   { 3, Iclass_ae_iclass_mulzaafp24s_hh_ll_args,
18327     1, Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs, 0, 0 },
18328   { 3, Iclass_ae_iclass_mulzaap24s_hh_ll_args,
18329     1, Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs, 0, 0 },
18330   { 3, Iclass_ae_iclass_mulzaafp24s_hl_lh_args,
18331     1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 },
18332   { 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args,
18333     1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 },
18334   { 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args,
18335     1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 },
18336   { 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args,
18337     1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 },
18338   { 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args,
18339     1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 },
18340   { 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args,
18341     1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 },
18342   { 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args,
18343     1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 },
18344   { 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args,
18345     1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 },
18346   { 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args,
18347     1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 },
18348   { 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args,
18349     1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 },
18350   { 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args,
18351     1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 },
18352   { 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args,
18353     1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 },
18354   { 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args,
18355     1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 },
18356   { 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args,
18357     1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 },
18358   { 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args,
18359     1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 },
18360   { 3, Iclass_ae_iclass_mulaap24s_hh_ll_args,
18361     1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 },
18362   { 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args,
18363     1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 },
18364   { 3, Iclass_ae_iclass_mulaap24s_hl_lh_args,
18365     1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 },
18366   { 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args,
18367     1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 },
18368   { 3, Iclass_ae_iclass_mulasp24s_hh_ll_args,
18369     1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 },
18370   { 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args,
18371     1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 },
18372   { 3, Iclass_ae_iclass_mulasp24s_hl_lh_args,
18373     1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 },
18374   { 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args,
18375     1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 },
18376   { 3, Iclass_ae_iclass_mulsap24s_hh_ll_args,
18377     1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 },
18378   { 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args,
18379     1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 },
18380   { 3, Iclass_ae_iclass_mulsap24s_hl_lh_args,
18381     1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 },
18382   { 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args,
18383     1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 },
18384   { 3, Iclass_ae_iclass_mulssp24s_hh_ll_args,
18385     1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 },
18386   { 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args,
18387     1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 },
18388   { 3, Iclass_ae_iclass_mulssp24s_hl_lh_args,
18389     1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 },
18390   { 2, Iclass_ae_iclass_sha32_args,
18391     0, 0, 0, 0 },
18392   { 3, Iclass_ae_iclass_vldl32t_args,
18393     5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 },
18394   { 3, Iclass_ae_iclass_vldl16t_args,
18395     5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 },
18396   { 1, Iclass_ae_iclass_vldl16c_args,
18397     8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 },
18398   { 1, Iclass_ae_iclass_vldsht_args,
18399     6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 },
18400   { 2, Iclass_ae_iclass_lb_args,
18401     3, Iclass_ae_iclass_lb_stateArgs, 0, 0 },
18402   { 2, Iclass_ae_iclass_lbi_args,
18403     3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 },
18404   { 3, Iclass_ae_iclass_lbk_args,
18405     3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 },
18406   { 3, Iclass_ae_iclass_lbki_args,
18407     3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 },
18408   { 2, Iclass_ae_iclass_db_args,
18409     3, Iclass_ae_iclass_db_stateArgs, 0, 0 },
18410   { 2, Iclass_ae_iclass_dbi_args,
18411     3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 },
18412   { 3, Iclass_ae_iclass_vlel32t_args,
18413     3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 },
18414   { 3, Iclass_ae_iclass_vlel16t_args,
18415     3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 },
18416   { 2, Iclass_ae_iclass_sb_args,
18417     4, Iclass_ae_iclass_sb_stateArgs, 0, 0 },
18418   { 3, Iclass_ae_iclass_sbi_args,
18419     3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 },
18420   { 1, Iclass_ae_iclass_vles16c_args,
18421     5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 },
18422   { 1, Iclass_ae_iclass_sbf_args,
18423     3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 }
18424 };
18425
18426 enum xtensa_iclass_id {
18427   ICLASS_xt_iclass_excw,
18428   ICLASS_xt_iclass_rfe,
18429   ICLASS_xt_iclass_rfde,
18430   ICLASS_xt_iclass_syscall,
18431   ICLASS_xt_iclass_call12,
18432   ICLASS_xt_iclass_call8,
18433   ICLASS_xt_iclass_call4,
18434   ICLASS_xt_iclass_callx12,
18435   ICLASS_xt_iclass_callx8,
18436   ICLASS_xt_iclass_callx4,
18437   ICLASS_xt_iclass_entry,
18438   ICLASS_xt_iclass_movsp,
18439   ICLASS_xt_iclass_rotw,
18440   ICLASS_xt_iclass_retw,
18441   ICLASS_xt_iclass_rfwou,
18442   ICLASS_xt_iclass_l32e,
18443   ICLASS_xt_iclass_s32e,
18444   ICLASS_xt_iclass_rsr_windowbase,
18445   ICLASS_xt_iclass_wsr_windowbase,
18446   ICLASS_xt_iclass_xsr_windowbase,
18447   ICLASS_xt_iclass_rsr_windowstart,
18448   ICLASS_xt_iclass_wsr_windowstart,
18449   ICLASS_xt_iclass_xsr_windowstart,
18450   ICLASS_xt_iclass_add_n,
18451   ICLASS_xt_iclass_addi_n,
18452   ICLASS_xt_iclass_bz6,
18453   ICLASS_xt_iclass_ill_n,
18454   ICLASS_xt_iclass_loadi4,
18455   ICLASS_xt_iclass_mov_n,
18456   ICLASS_xt_iclass_movi_n,
18457   ICLASS_xt_iclass_nopn,
18458   ICLASS_xt_iclass_retn,
18459   ICLASS_xt_iclass_storei4,
18460   ICLASS_rur_threadptr,
18461   ICLASS_wur_threadptr,
18462   ICLASS_xt_iclass_addi,
18463   ICLASS_xt_iclass_addmi,
18464   ICLASS_xt_iclass_addsub,
18465   ICLASS_xt_iclass_bit,
18466   ICLASS_xt_iclass_bsi8,
18467   ICLASS_xt_iclass_bsi8b,
18468   ICLASS_xt_iclass_bsi8u,
18469   ICLASS_xt_iclass_bst8,
18470   ICLASS_xt_iclass_bsz12,
18471   ICLASS_xt_iclass_call0,
18472   ICLASS_xt_iclass_callx0,
18473   ICLASS_xt_iclass_exti,
18474   ICLASS_xt_iclass_ill,
18475   ICLASS_xt_iclass_jump,
18476   ICLASS_xt_iclass_jumpx,
18477   ICLASS_xt_iclass_l16ui,
18478   ICLASS_xt_iclass_l16si,
18479   ICLASS_xt_iclass_l32i,
18480   ICLASS_xt_iclass_l32r,
18481   ICLASS_xt_iclass_l8i,
18482   ICLASS_xt_iclass_loop,
18483   ICLASS_xt_iclass_loopz,
18484   ICLASS_xt_iclass_movi,
18485   ICLASS_xt_iclass_movz,
18486   ICLASS_xt_iclass_neg,
18487   ICLASS_xt_iclass_nop,
18488   ICLASS_xt_iclass_return,
18489   ICLASS_xt_iclass_simcall,
18490   ICLASS_xt_iclass_s16i,
18491   ICLASS_xt_iclass_s32i,
18492   ICLASS_xt_iclass_s8i,
18493   ICLASS_xt_iclass_sar,
18494   ICLASS_xt_iclass_sari,
18495   ICLASS_xt_iclass_shifts,
18496   ICLASS_xt_iclass_shiftst,
18497   ICLASS_xt_iclass_shiftt,
18498   ICLASS_xt_iclass_slli,
18499   ICLASS_xt_iclass_srai,
18500   ICLASS_xt_iclass_srli,
18501   ICLASS_xt_iclass_memw,
18502   ICLASS_xt_iclass_extw,
18503   ICLASS_xt_iclass_isync,
18504   ICLASS_xt_iclass_sync,
18505   ICLASS_xt_iclass_rsil,
18506   ICLASS_xt_iclass_rsr_lend,
18507   ICLASS_xt_iclass_wsr_lend,
18508   ICLASS_xt_iclass_xsr_lend,
18509   ICLASS_xt_iclass_rsr_lcount,
18510   ICLASS_xt_iclass_wsr_lcount,
18511   ICLASS_xt_iclass_xsr_lcount,
18512   ICLASS_xt_iclass_rsr_lbeg,
18513   ICLASS_xt_iclass_wsr_lbeg,
18514   ICLASS_xt_iclass_xsr_lbeg,
18515   ICLASS_xt_iclass_rsr_sar,
18516   ICLASS_xt_iclass_wsr_sar,
18517   ICLASS_xt_iclass_xsr_sar,
18518   ICLASS_xt_iclass_rsr_litbase,
18519   ICLASS_xt_iclass_wsr_litbase,
18520   ICLASS_xt_iclass_xsr_litbase,
18521   ICLASS_xt_iclass_rsr_configid0,
18522   ICLASS_xt_iclass_wsr_configid0,
18523   ICLASS_xt_iclass_rsr_configid1,
18524   ICLASS_xt_iclass_rsr_ps,
18525   ICLASS_xt_iclass_wsr_ps,
18526   ICLASS_xt_iclass_xsr_ps,
18527   ICLASS_xt_iclass_rsr_epc1,
18528   ICLASS_xt_iclass_wsr_epc1,
18529   ICLASS_xt_iclass_xsr_epc1,
18530   ICLASS_xt_iclass_rsr_excsave1,
18531   ICLASS_xt_iclass_wsr_excsave1,
18532   ICLASS_xt_iclass_xsr_excsave1,
18533   ICLASS_xt_iclass_rsr_epc2,
18534   ICLASS_xt_iclass_wsr_epc2,
18535   ICLASS_xt_iclass_xsr_epc2,
18536   ICLASS_xt_iclass_rsr_excsave2,
18537   ICLASS_xt_iclass_wsr_excsave2,
18538   ICLASS_xt_iclass_xsr_excsave2,
18539   ICLASS_xt_iclass_rsr_eps2,
18540   ICLASS_xt_iclass_wsr_eps2,
18541   ICLASS_xt_iclass_xsr_eps2,
18542   ICLASS_xt_iclass_rsr_excvaddr,
18543   ICLASS_xt_iclass_wsr_excvaddr,
18544   ICLASS_xt_iclass_xsr_excvaddr,
18545   ICLASS_xt_iclass_rsr_depc,
18546   ICLASS_xt_iclass_wsr_depc,
18547   ICLASS_xt_iclass_xsr_depc,
18548   ICLASS_xt_iclass_rsr_exccause,
18549   ICLASS_xt_iclass_wsr_exccause,
18550   ICLASS_xt_iclass_xsr_exccause,
18551   ICLASS_xt_iclass_rsr_misc0,
18552   ICLASS_xt_iclass_wsr_misc0,
18553   ICLASS_xt_iclass_xsr_misc0,
18554   ICLASS_xt_iclass_rsr_misc1,
18555   ICLASS_xt_iclass_wsr_misc1,
18556   ICLASS_xt_iclass_xsr_misc1,
18557   ICLASS_xt_iclass_rsr_prid,
18558   ICLASS_xt_iclass_rsr_vecbase,
18559   ICLASS_xt_iclass_wsr_vecbase,
18560   ICLASS_xt_iclass_xsr_vecbase,
18561   ICLASS_xt_mul16,
18562   ICLASS_xt_mul32,
18563   ICLASS_xt_iclass_rfi,
18564   ICLASS_xt_iclass_wait,
18565   ICLASS_xt_iclass_rsr_interrupt,
18566   ICLASS_xt_iclass_wsr_intset,
18567   ICLASS_xt_iclass_wsr_intclear,
18568   ICLASS_xt_iclass_rsr_intenable,
18569   ICLASS_xt_iclass_wsr_intenable,
18570   ICLASS_xt_iclass_xsr_intenable,
18571   ICLASS_xt_iclass_break,
18572   ICLASS_xt_iclass_break_n,
18573   ICLASS_xt_iclass_rsr_debugcause,
18574   ICLASS_xt_iclass_wsr_debugcause,
18575   ICLASS_xt_iclass_xsr_debugcause,
18576   ICLASS_xt_iclass_rsr_icount,
18577   ICLASS_xt_iclass_wsr_icount,
18578   ICLASS_xt_iclass_xsr_icount,
18579   ICLASS_xt_iclass_rsr_icountlevel,
18580   ICLASS_xt_iclass_wsr_icountlevel,
18581   ICLASS_xt_iclass_xsr_icountlevel,
18582   ICLASS_xt_iclass_rsr_ddr,
18583   ICLASS_xt_iclass_wsr_ddr,
18584   ICLASS_xt_iclass_xsr_ddr,
18585   ICLASS_xt_iclass_rfdo,
18586   ICLASS_xt_iclass_rfdd,
18587   ICLASS_xt_iclass_bbool1,
18588   ICLASS_xt_iclass_bbool4,
18589   ICLASS_xt_iclass_bbool8,
18590   ICLASS_xt_iclass_bbranch,
18591   ICLASS_xt_iclass_bmove,
18592   ICLASS_xt_iclass_RSR_BR,
18593   ICLASS_xt_iclass_WSR_BR,
18594   ICLASS_xt_iclass_XSR_BR,
18595   ICLASS_xt_iclass_rsr_ccount,
18596   ICLASS_xt_iclass_wsr_ccount,
18597   ICLASS_xt_iclass_xsr_ccount,
18598   ICLASS_xt_iclass_rsr_ccompare0,
18599   ICLASS_xt_iclass_wsr_ccompare0,
18600   ICLASS_xt_iclass_xsr_ccompare0,
18601   ICLASS_xt_iclass_rsr_ccompare1,
18602   ICLASS_xt_iclass_wsr_ccompare1,
18603   ICLASS_xt_iclass_xsr_ccompare1,
18604   ICLASS_xt_iclass_icache,
18605   ICLASS_xt_iclass_icache_inv,
18606   ICLASS_xt_iclass_licx,
18607   ICLASS_xt_iclass_sicx,
18608   ICLASS_xt_iclass_dcache,
18609   ICLASS_xt_iclass_dcache_ind,
18610   ICLASS_xt_iclass_dcache_inv,
18611   ICLASS_xt_iclass_dpf,
18612   ICLASS_xt_iclass_sdct,
18613   ICLASS_xt_iclass_ldct,
18614   ICLASS_xt_iclass_wsr_ptevaddr,
18615   ICLASS_xt_iclass_rsr_ptevaddr,
18616   ICLASS_xt_iclass_xsr_ptevaddr,
18617   ICLASS_xt_iclass_rsr_rasid,
18618   ICLASS_xt_iclass_wsr_rasid,
18619   ICLASS_xt_iclass_xsr_rasid,
18620   ICLASS_xt_iclass_rsr_itlbcfg,
18621   ICLASS_xt_iclass_wsr_itlbcfg,
18622   ICLASS_xt_iclass_xsr_itlbcfg,
18623   ICLASS_xt_iclass_rsr_dtlbcfg,
18624   ICLASS_xt_iclass_wsr_dtlbcfg,
18625   ICLASS_xt_iclass_xsr_dtlbcfg,
18626   ICLASS_xt_iclass_idtlb,
18627   ICLASS_xt_iclass_rdtlb,
18628   ICLASS_xt_iclass_wdtlb,
18629   ICLASS_xt_iclass_iitlb,
18630   ICLASS_xt_iclass_ritlb,
18631   ICLASS_xt_iclass_witlb,
18632   ICLASS_xt_iclass_ldpte,
18633   ICLASS_xt_iclass_hwwitlba,
18634   ICLASS_xt_iclass_hwwdtlba,
18635   ICLASS_xt_iclass_rsr_cpenable,
18636   ICLASS_xt_iclass_wsr_cpenable,
18637   ICLASS_xt_iclass_xsr_cpenable,
18638   ICLASS_xt_iclass_clamp,
18639   ICLASS_xt_iclass_minmax,
18640   ICLASS_xt_iclass_nsa,
18641   ICLASS_xt_iclass_sx,
18642   ICLASS_xt_iclass_l32ai,
18643   ICLASS_xt_iclass_s32ri,
18644   ICLASS_xt_iclass_s32c1i,
18645   ICLASS_xt_iclass_rsr_scompare1,
18646   ICLASS_xt_iclass_wsr_scompare1,
18647   ICLASS_xt_iclass_xsr_scompare1,
18648   ICLASS_xt_iclass_rsr_atomctl,
18649   ICLASS_xt_iclass_wsr_atomctl,
18650   ICLASS_xt_iclass_xsr_atomctl,
18651   ICLASS_xt_iclass_rer,
18652   ICLASS_xt_iclass_wer,
18653   ICLASS_rur_ae_ovf_sar,
18654   ICLASS_wur_ae_ovf_sar,
18655   ICLASS_rur_ae_bithead,
18656   ICLASS_wur_ae_bithead,
18657   ICLASS_rur_ae_ts_fts_bu_bp,
18658   ICLASS_wur_ae_ts_fts_bu_bp,
18659   ICLASS_rur_ae_sd_no,
18660   ICLASS_wur_ae_sd_no,
18661   ICLASS_ae_iclass_rur_ae_overflow,
18662   ICLASS_ae_iclass_wur_ae_overflow,
18663   ICLASS_ae_iclass_rur_ae_sar,
18664   ICLASS_ae_iclass_wur_ae_sar,
18665   ICLASS_ae_iclass_rur_ae_bitptr,
18666   ICLASS_ae_iclass_wur_ae_bitptr,
18667   ICLASS_ae_iclass_rur_ae_bitsused,
18668   ICLASS_ae_iclass_wur_ae_bitsused,
18669   ICLASS_ae_iclass_rur_ae_tablesize,
18670   ICLASS_ae_iclass_wur_ae_tablesize,
18671   ICLASS_ae_iclass_rur_ae_first_ts,
18672   ICLASS_ae_iclass_wur_ae_first_ts,
18673   ICLASS_ae_iclass_rur_ae_nextoffset,
18674   ICLASS_ae_iclass_wur_ae_nextoffset,
18675   ICLASS_ae_iclass_rur_ae_searchdone,
18676   ICLASS_ae_iclass_wur_ae_searchdone,
18677   ICLASS_ae_iclass_lp16f_i,
18678   ICLASS_ae_iclass_lp16f_iu,
18679   ICLASS_ae_iclass_lp16f_x,
18680   ICLASS_ae_iclass_lp16f_xu,
18681   ICLASS_ae_iclass_lp24_i,
18682   ICLASS_ae_iclass_lp24_iu,
18683   ICLASS_ae_iclass_lp24_x,
18684   ICLASS_ae_iclass_lp24_xu,
18685   ICLASS_ae_iclass_lp24f_i,
18686   ICLASS_ae_iclass_lp24f_iu,
18687   ICLASS_ae_iclass_lp24f_x,
18688   ICLASS_ae_iclass_lp24f_xu,
18689   ICLASS_ae_iclass_lp16x2f_i,
18690   ICLASS_ae_iclass_lp16x2f_iu,
18691   ICLASS_ae_iclass_lp16x2f_x,
18692   ICLASS_ae_iclass_lp16x2f_xu,
18693   ICLASS_ae_iclass_lp24x2f_i,
18694   ICLASS_ae_iclass_lp24x2f_iu,
18695   ICLASS_ae_iclass_lp24x2f_x,
18696   ICLASS_ae_iclass_lp24x2f_xu,
18697   ICLASS_ae_iclass_lp24x2_i,
18698   ICLASS_ae_iclass_lp24x2_iu,
18699   ICLASS_ae_iclass_lp24x2_x,
18700   ICLASS_ae_iclass_lp24x2_xu,
18701   ICLASS_ae_iclass_sp16x2f_i,
18702   ICLASS_ae_iclass_sp16x2f_iu,
18703   ICLASS_ae_iclass_sp16x2f_x,
18704   ICLASS_ae_iclass_sp16x2f_xu,
18705   ICLASS_ae_iclass_sp24x2s_i,
18706   ICLASS_ae_iclass_sp24x2s_iu,
18707   ICLASS_ae_iclass_sp24x2s_x,
18708   ICLASS_ae_iclass_sp24x2s_xu,
18709   ICLASS_ae_iclass_sp24x2f_i,
18710   ICLASS_ae_iclass_sp24x2f_iu,
18711   ICLASS_ae_iclass_sp24x2f_x,
18712   ICLASS_ae_iclass_sp24x2f_xu,
18713   ICLASS_ae_iclass_sp16f_l_i,
18714   ICLASS_ae_iclass_sp16f_l_iu,
18715   ICLASS_ae_iclass_sp16f_l_x,
18716   ICLASS_ae_iclass_sp16f_l_xu,
18717   ICLASS_ae_iclass_sp24s_l_i,
18718   ICLASS_ae_iclass_sp24s_l_iu,
18719   ICLASS_ae_iclass_sp24s_l_x,
18720   ICLASS_ae_iclass_sp24s_l_xu,
18721   ICLASS_ae_iclass_sp24f_l_i,
18722   ICLASS_ae_iclass_sp24f_l_iu,
18723   ICLASS_ae_iclass_sp24f_l_x,
18724   ICLASS_ae_iclass_sp24f_l_xu,
18725   ICLASS_ae_iclass_lq56_i,
18726   ICLASS_ae_iclass_lq56_iu,
18727   ICLASS_ae_iclass_lq56_x,
18728   ICLASS_ae_iclass_lq56_xu,
18729   ICLASS_ae_iclass_lq32f_i,
18730   ICLASS_ae_iclass_lq32f_iu,
18731   ICLASS_ae_iclass_lq32f_x,
18732   ICLASS_ae_iclass_lq32f_xu,
18733   ICLASS_ae_iclass_sq56s_i,
18734   ICLASS_ae_iclass_sq56s_iu,
18735   ICLASS_ae_iclass_sq56s_x,
18736   ICLASS_ae_iclass_sq56s_xu,
18737   ICLASS_ae_iclass_sq32f_i,
18738   ICLASS_ae_iclass_sq32f_iu,
18739   ICLASS_ae_iclass_sq32f_x,
18740   ICLASS_ae_iclass_sq32f_xu,
18741   ICLASS_ae_iclass_zerop48,
18742   ICLASS_ae_iclass_movp48,
18743   ICLASS_ae_iclass_selp24_ll,
18744   ICLASS_ae_iclass_selp24_lh,
18745   ICLASS_ae_iclass_selp24_hl,
18746   ICLASS_ae_iclass_selp24_hh,
18747   ICLASS_ae_iclass_movtp24x2,
18748   ICLASS_ae_iclass_movfp24x2,
18749   ICLASS_ae_iclass_movtp48,
18750   ICLASS_ae_iclass_movfp48,
18751   ICLASS_ae_iclass_movpa24x2,
18752   ICLASS_ae_iclass_truncp24a32x2,
18753   ICLASS_ae_iclass_cvta32p24_l,
18754   ICLASS_ae_iclass_cvta32p24_h,
18755   ICLASS_ae_iclass_cvtp24a16x2_ll,
18756   ICLASS_ae_iclass_cvtp24a16x2_lh,
18757   ICLASS_ae_iclass_cvtp24a16x2_hl,
18758   ICLASS_ae_iclass_cvtp24a16x2_hh,
18759   ICLASS_ae_iclass_truncp24q48x2,
18760   ICLASS_ae_iclass_truncp16,
18761   ICLASS_ae_iclass_roundsp24q48sym,
18762   ICLASS_ae_iclass_roundsp24q48asym,
18763   ICLASS_ae_iclass_roundsp16q48sym,
18764   ICLASS_ae_iclass_roundsp16q48asym,
18765   ICLASS_ae_iclass_roundsp16sym,
18766   ICLASS_ae_iclass_roundsp16asym,
18767   ICLASS_ae_iclass_zeroq56,
18768   ICLASS_ae_iclass_movq56,
18769   ICLASS_ae_iclass_movtq56,
18770   ICLASS_ae_iclass_movfq56,
18771   ICLASS_ae_iclass_cvtq48a32s,
18772   ICLASS_ae_iclass_cvtq48p24s_l,
18773   ICLASS_ae_iclass_cvtq48p24s_h,
18774   ICLASS_ae_iclass_satq48s,
18775   ICLASS_ae_iclass_truncq32,
18776   ICLASS_ae_iclass_roundsq32sym,
18777   ICLASS_ae_iclass_roundsq32asym,
18778   ICLASS_ae_iclass_trunca32q48,
18779   ICLASS_ae_iclass_movap24s_l,
18780   ICLASS_ae_iclass_movap24s_h,
18781   ICLASS_ae_iclass_trunca16p24s_l,
18782   ICLASS_ae_iclass_trunca16p24s_h,
18783   ICLASS_ae_iclass_addp24,
18784   ICLASS_ae_iclass_subp24,
18785   ICLASS_ae_iclass_negp24,
18786   ICLASS_ae_iclass_absp24,
18787   ICLASS_ae_iclass_maxp24s,
18788   ICLASS_ae_iclass_minp24s,
18789   ICLASS_ae_iclass_maxbp24s,
18790   ICLASS_ae_iclass_minbp24s,
18791   ICLASS_ae_iclass_addsp24s,
18792   ICLASS_ae_iclass_subsp24s,
18793   ICLASS_ae_iclass_negsp24s,
18794   ICLASS_ae_iclass_abssp24s,
18795   ICLASS_ae_iclass_andp48,
18796   ICLASS_ae_iclass_nandp48,
18797   ICLASS_ae_iclass_orp48,
18798   ICLASS_ae_iclass_xorp48,
18799   ICLASS_ae_iclass_ltp24s,
18800   ICLASS_ae_iclass_lep24s,
18801   ICLASS_ae_iclass_eqp24,
18802   ICLASS_ae_iclass_addq56,
18803   ICLASS_ae_iclass_subq56,
18804   ICLASS_ae_iclass_negq56,
18805   ICLASS_ae_iclass_absq56,
18806   ICLASS_ae_iclass_maxq56s,
18807   ICLASS_ae_iclass_minq56s,
18808   ICLASS_ae_iclass_maxbq56s,
18809   ICLASS_ae_iclass_minbq56s,
18810   ICLASS_ae_iclass_addsq56s,
18811   ICLASS_ae_iclass_subsq56s,
18812   ICLASS_ae_iclass_negsq56s,
18813   ICLASS_ae_iclass_abssq56s,
18814   ICLASS_ae_iclass_andq56,
18815   ICLASS_ae_iclass_nandq56,
18816   ICLASS_ae_iclass_orq56,
18817   ICLASS_ae_iclass_xorq56,
18818   ICLASS_ae_iclass_sllip24,
18819   ICLASS_ae_iclass_srlip24,
18820   ICLASS_ae_iclass_sraip24,
18821   ICLASS_ae_iclass_sllsp24,
18822   ICLASS_ae_iclass_srlsp24,
18823   ICLASS_ae_iclass_srasp24,
18824   ICLASS_ae_iclass_sllisp24s,
18825   ICLASS_ae_iclass_sllssp24s,
18826   ICLASS_ae_iclass_slliq56,
18827   ICLASS_ae_iclass_srliq56,
18828   ICLASS_ae_iclass_sraiq56,
18829   ICLASS_ae_iclass_sllsq56,
18830   ICLASS_ae_iclass_srlsq56,
18831   ICLASS_ae_iclass_srasq56,
18832   ICLASS_ae_iclass_sllaq56,
18833   ICLASS_ae_iclass_srlaq56,
18834   ICLASS_ae_iclass_sraaq56,
18835   ICLASS_ae_iclass_sllisq56s,
18836   ICLASS_ae_iclass_sllssq56s,
18837   ICLASS_ae_iclass_sllasq56s,
18838   ICLASS_ae_iclass_ltq56s,
18839   ICLASS_ae_iclass_leq56s,
18840   ICLASS_ae_iclass_eqq56,
18841   ICLASS_ae_iclass_nsaq56s,
18842   ICLASS_ae_iclass_mulfs32p16s_ll,
18843   ICLASS_ae_iclass_mulfp24s_ll,
18844   ICLASS_ae_iclass_mulp24s_ll,
18845   ICLASS_ae_iclass_mulfs32p16s_lh,
18846   ICLASS_ae_iclass_mulfp24s_lh,
18847   ICLASS_ae_iclass_mulp24s_lh,
18848   ICLASS_ae_iclass_mulfs32p16s_hl,
18849   ICLASS_ae_iclass_mulfp24s_hl,
18850   ICLASS_ae_iclass_mulp24s_hl,
18851   ICLASS_ae_iclass_mulfs32p16s_hh,
18852   ICLASS_ae_iclass_mulfp24s_hh,
18853   ICLASS_ae_iclass_mulp24s_hh,
18854   ICLASS_ae_iclass_mulafs32p16s_ll,
18855   ICLASS_ae_iclass_mulafp24s_ll,
18856   ICLASS_ae_iclass_mulap24s_ll,
18857   ICLASS_ae_iclass_mulafs32p16s_lh,
18858   ICLASS_ae_iclass_mulafp24s_lh,
18859   ICLASS_ae_iclass_mulap24s_lh,
18860   ICLASS_ae_iclass_mulafs32p16s_hl,
18861   ICLASS_ae_iclass_mulafp24s_hl,
18862   ICLASS_ae_iclass_mulap24s_hl,
18863   ICLASS_ae_iclass_mulafs32p16s_hh,
18864   ICLASS_ae_iclass_mulafp24s_hh,
18865   ICLASS_ae_iclass_mulap24s_hh,
18866   ICLASS_ae_iclass_mulsfs32p16s_ll,
18867   ICLASS_ae_iclass_mulsfp24s_ll,
18868   ICLASS_ae_iclass_mulsp24s_ll,
18869   ICLASS_ae_iclass_mulsfs32p16s_lh,
18870   ICLASS_ae_iclass_mulsfp24s_lh,
18871   ICLASS_ae_iclass_mulsp24s_lh,
18872   ICLASS_ae_iclass_mulsfs32p16s_hl,
18873   ICLASS_ae_iclass_mulsfp24s_hl,
18874   ICLASS_ae_iclass_mulsp24s_hl,
18875   ICLASS_ae_iclass_mulsfs32p16s_hh,
18876   ICLASS_ae_iclass_mulsfp24s_hh,
18877   ICLASS_ae_iclass_mulsp24s_hh,
18878   ICLASS_ae_iclass_mulafs56p24s_ll,
18879   ICLASS_ae_iclass_mulas56p24s_ll,
18880   ICLASS_ae_iclass_mulafs56p24s_lh,
18881   ICLASS_ae_iclass_mulas56p24s_lh,
18882   ICLASS_ae_iclass_mulafs56p24s_hl,
18883   ICLASS_ae_iclass_mulas56p24s_hl,
18884   ICLASS_ae_iclass_mulafs56p24s_hh,
18885   ICLASS_ae_iclass_mulas56p24s_hh,
18886   ICLASS_ae_iclass_mulsfs56p24s_ll,
18887   ICLASS_ae_iclass_mulss56p24s_ll,
18888   ICLASS_ae_iclass_mulsfs56p24s_lh,
18889   ICLASS_ae_iclass_mulss56p24s_lh,
18890   ICLASS_ae_iclass_mulsfs56p24s_hl,
18891   ICLASS_ae_iclass_mulss56p24s_hl,
18892   ICLASS_ae_iclass_mulsfs56p24s_hh,
18893   ICLASS_ae_iclass_mulss56p24s_hh,
18894   ICLASS_ae_iclass_mulfq32sp16s_l,
18895   ICLASS_ae_iclass_mulfq32sp16s_h,
18896   ICLASS_ae_iclass_mulfq32sp16u_l,
18897   ICLASS_ae_iclass_mulfq32sp16u_h,
18898   ICLASS_ae_iclass_mulq32sp16s_l,
18899   ICLASS_ae_iclass_mulq32sp16s_h,
18900   ICLASS_ae_iclass_mulq32sp16u_l,
18901   ICLASS_ae_iclass_mulq32sp16u_h,
18902   ICLASS_ae_iclass_mulafq32sp16s_l,
18903   ICLASS_ae_iclass_mulafq32sp16s_h,
18904   ICLASS_ae_iclass_mulafq32sp16u_l,
18905   ICLASS_ae_iclass_mulafq32sp16u_h,
18906   ICLASS_ae_iclass_mulaq32sp16s_l,
18907   ICLASS_ae_iclass_mulaq32sp16s_h,
18908   ICLASS_ae_iclass_mulaq32sp16u_l,
18909   ICLASS_ae_iclass_mulaq32sp16u_h,
18910   ICLASS_ae_iclass_mulsfq32sp16s_l,
18911   ICLASS_ae_iclass_mulsfq32sp16s_h,
18912   ICLASS_ae_iclass_mulsfq32sp16u_l,
18913   ICLASS_ae_iclass_mulsfq32sp16u_h,
18914   ICLASS_ae_iclass_mulsq32sp16s_l,
18915   ICLASS_ae_iclass_mulsq32sp16s_h,
18916   ICLASS_ae_iclass_mulsq32sp16u_l,
18917   ICLASS_ae_iclass_mulsq32sp16u_h,
18918   ICLASS_ae_iclass_mulzaaq32sp16s_ll,
18919   ICLASS_ae_iclass_mulzaafq32sp16s_ll,
18920   ICLASS_ae_iclass_mulzaaq32sp16u_ll,
18921   ICLASS_ae_iclass_mulzaafq32sp16u_ll,
18922   ICLASS_ae_iclass_mulzaaq32sp16s_hh,
18923   ICLASS_ae_iclass_mulzaafq32sp16s_hh,
18924   ICLASS_ae_iclass_mulzaaq32sp16u_hh,
18925   ICLASS_ae_iclass_mulzaafq32sp16u_hh,
18926   ICLASS_ae_iclass_mulzaaq32sp16s_lh,
18927   ICLASS_ae_iclass_mulzaafq32sp16s_lh,
18928   ICLASS_ae_iclass_mulzaaq32sp16u_lh,
18929   ICLASS_ae_iclass_mulzaafq32sp16u_lh,
18930   ICLASS_ae_iclass_mulzasq32sp16s_ll,
18931   ICLASS_ae_iclass_mulzasfq32sp16s_ll,
18932   ICLASS_ae_iclass_mulzasq32sp16u_ll,
18933   ICLASS_ae_iclass_mulzasfq32sp16u_ll,
18934   ICLASS_ae_iclass_mulzasq32sp16s_hh,
18935   ICLASS_ae_iclass_mulzasfq32sp16s_hh,
18936   ICLASS_ae_iclass_mulzasq32sp16u_hh,
18937   ICLASS_ae_iclass_mulzasfq32sp16u_hh,
18938   ICLASS_ae_iclass_mulzasq32sp16s_lh,
18939   ICLASS_ae_iclass_mulzasfq32sp16s_lh,
18940   ICLASS_ae_iclass_mulzasq32sp16u_lh,
18941   ICLASS_ae_iclass_mulzasfq32sp16u_lh,
18942   ICLASS_ae_iclass_mulzsaq32sp16s_ll,
18943   ICLASS_ae_iclass_mulzsafq32sp16s_ll,
18944   ICLASS_ae_iclass_mulzsaq32sp16u_ll,
18945   ICLASS_ae_iclass_mulzsafq32sp16u_ll,
18946   ICLASS_ae_iclass_mulzsaq32sp16s_hh,
18947   ICLASS_ae_iclass_mulzsafq32sp16s_hh,
18948   ICLASS_ae_iclass_mulzsaq32sp16u_hh,
18949   ICLASS_ae_iclass_mulzsafq32sp16u_hh,
18950   ICLASS_ae_iclass_mulzsaq32sp16s_lh,
18951   ICLASS_ae_iclass_mulzsafq32sp16s_lh,
18952   ICLASS_ae_iclass_mulzsaq32sp16u_lh,
18953   ICLASS_ae_iclass_mulzsafq32sp16u_lh,
18954   ICLASS_ae_iclass_mulzssq32sp16s_ll,
18955   ICLASS_ae_iclass_mulzssfq32sp16s_ll,
18956   ICLASS_ae_iclass_mulzssq32sp16u_ll,
18957   ICLASS_ae_iclass_mulzssfq32sp16u_ll,
18958   ICLASS_ae_iclass_mulzssq32sp16s_hh,
18959   ICLASS_ae_iclass_mulzssfq32sp16s_hh,
18960   ICLASS_ae_iclass_mulzssq32sp16u_hh,
18961   ICLASS_ae_iclass_mulzssfq32sp16u_hh,
18962   ICLASS_ae_iclass_mulzssq32sp16s_lh,
18963   ICLASS_ae_iclass_mulzssfq32sp16s_lh,
18964   ICLASS_ae_iclass_mulzssq32sp16u_lh,
18965   ICLASS_ae_iclass_mulzssfq32sp16u_lh,
18966   ICLASS_ae_iclass_mulzaafp24s_hh_ll,
18967   ICLASS_ae_iclass_mulzaap24s_hh_ll,
18968   ICLASS_ae_iclass_mulzaafp24s_hl_lh,
18969   ICLASS_ae_iclass_mulzaap24s_hl_lh,
18970   ICLASS_ae_iclass_mulzasfp24s_hh_ll,
18971   ICLASS_ae_iclass_mulzasp24s_hh_ll,
18972   ICLASS_ae_iclass_mulzasfp24s_hl_lh,
18973   ICLASS_ae_iclass_mulzasp24s_hl_lh,
18974   ICLASS_ae_iclass_mulzsafp24s_hh_ll,
18975   ICLASS_ae_iclass_mulzsap24s_hh_ll,
18976   ICLASS_ae_iclass_mulzsafp24s_hl_lh,
18977   ICLASS_ae_iclass_mulzsap24s_hl_lh,
18978   ICLASS_ae_iclass_mulzssfp24s_hh_ll,
18979   ICLASS_ae_iclass_mulzssp24s_hh_ll,
18980   ICLASS_ae_iclass_mulzssfp24s_hl_lh,
18981   ICLASS_ae_iclass_mulzssp24s_hl_lh,
18982   ICLASS_ae_iclass_mulaafp24s_hh_ll,
18983   ICLASS_ae_iclass_mulaap24s_hh_ll,
18984   ICLASS_ae_iclass_mulaafp24s_hl_lh,
18985   ICLASS_ae_iclass_mulaap24s_hl_lh,
18986   ICLASS_ae_iclass_mulasfp24s_hh_ll,
18987   ICLASS_ae_iclass_mulasp24s_hh_ll,
18988   ICLASS_ae_iclass_mulasfp24s_hl_lh,
18989   ICLASS_ae_iclass_mulasp24s_hl_lh,
18990   ICLASS_ae_iclass_mulsafp24s_hh_ll,
18991   ICLASS_ae_iclass_mulsap24s_hh_ll,
18992   ICLASS_ae_iclass_mulsafp24s_hl_lh,
18993   ICLASS_ae_iclass_mulsap24s_hl_lh,
18994   ICLASS_ae_iclass_mulssfp24s_hh_ll,
18995   ICLASS_ae_iclass_mulssp24s_hh_ll,
18996   ICLASS_ae_iclass_mulssfp24s_hl_lh,
18997   ICLASS_ae_iclass_mulssp24s_hl_lh,
18998   ICLASS_ae_iclass_sha32,
18999   ICLASS_ae_iclass_vldl32t,
19000   ICLASS_ae_iclass_vldl16t,
19001   ICLASS_ae_iclass_vldl16c,
19002   ICLASS_ae_iclass_vldsht,
19003   ICLASS_ae_iclass_lb,
19004   ICLASS_ae_iclass_lbi,
19005   ICLASS_ae_iclass_lbk,
19006   ICLASS_ae_iclass_lbki,
19007   ICLASS_ae_iclass_db,
19008   ICLASS_ae_iclass_dbi,
19009   ICLASS_ae_iclass_vlel32t,
19010   ICLASS_ae_iclass_vlel16t,
19011   ICLASS_ae_iclass_sb,
19012   ICLASS_ae_iclass_sbi,
19013   ICLASS_ae_iclass_vles16c,
19014   ICLASS_ae_iclass_sbf
19015 };
19016
19017 \f
19018 /*  Opcode encodings.  */
19019
19020 static void
19021 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
19022 {
19023   slotbuf[0] = 0x2080;
19024 }
19025
19026 static void
19027 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
19028 {
19029   slotbuf[0] = 0x3000;
19030 }
19031
19032 static void
19033 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
19034 {
19035   slotbuf[0] = 0x3200;
19036 }
19037
19038 static void
19039 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
19040 {
19041   slotbuf[0] = 0x5000;
19042 }
19043
19044 static void
19045 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
19046 {
19047   slotbuf[0] = 0x35;
19048 }
19049
19050 static void
19051 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
19052 {
19053   slotbuf[0] = 0x25;
19054 }
19055
19056 static void
19057 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
19058 {
19059   slotbuf[0] = 0x15;
19060 }
19061
19062 static void
19063 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
19064 {
19065   slotbuf[0] = 0xf0;
19066 }
19067
19068 static void
19069 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
19070 {
19071   slotbuf[0] = 0xe0;
19072 }
19073
19074 static void
19075 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
19076 {
19077   slotbuf[0] = 0xd0;
19078 }
19079
19080 static void
19081 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
19082 {
19083   slotbuf[0] = 0x36;
19084 }
19085
19086 static void
19087 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
19088 {
19089   slotbuf[0] = 0x1000;
19090 }
19091
19092 static void
19093 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
19094 {
19095   slotbuf[0] = 0x408000;
19096 }
19097
19098 static void
19099 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
19100 {
19101   slotbuf[0] = 0x90;
19102 }
19103
19104 static void
19105 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19106 {
19107   slotbuf[0] = 0xf01d;
19108 }
19109
19110 static void
19111 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
19112 {
19113   slotbuf[0] = 0x3400;
19114 }
19115
19116 static void
19117 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
19118 {
19119   slotbuf[0] = 0x3500;
19120 }
19121
19122 static void
19123 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
19124 {
19125   slotbuf[0] = 0x90000;
19126 }
19127
19128 static void
19129 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
19130 {
19131   slotbuf[0] = 0x490000;
19132 }
19133
19134 static void
19135 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
19136 {
19137   slotbuf[0] = 0x34800;
19138 }
19139
19140 static void
19141 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
19142 {
19143   slotbuf[0] = 0x134800;
19144 }
19145
19146 static void
19147 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
19148 {
19149   slotbuf[0] = 0x614800;
19150 }
19151
19152 static void
19153 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
19154 {
19155   slotbuf[0] = 0x34900;
19156 }
19157
19158 static void
19159 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
19160 {
19161   slotbuf[0] = 0x134900;
19162 }
19163
19164 static void
19165 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
19166 {
19167   slotbuf[0] = 0x614900;
19168 }
19169
19170 static void
19171 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
19172 {
19173   slotbuf[0] = 0xa;
19174 }
19175
19176 static void
19177 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
19178 {
19179   slotbuf[0] = 0xb;
19180 }
19181
19182 static void
19183 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19184 {
19185   slotbuf[0] = 0x8c;
19186 }
19187
19188 static void
19189 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19190 {
19191   slotbuf[0] = 0xcc;
19192 }
19193
19194 static void
19195 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19196 {
19197   slotbuf[0] = 0xf06d;
19198 }
19199
19200 static void
19201 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
19202 {
19203   slotbuf[0] = 0x8;
19204 }
19205
19206 static void
19207 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19208 {
19209   slotbuf[0] = 0xd;
19210 }
19211
19212 static void
19213 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19214 {
19215   slotbuf[0] = 0xc;
19216 }
19217
19218 static void
19219 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19220 {
19221   slotbuf[0] = 0xf03d;
19222 }
19223
19224 static void
19225 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19226 {
19227   slotbuf[0] = 0xf00d;
19228 }
19229
19230 static void
19231 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
19232 {
19233   slotbuf[0] = 0x9;
19234 }
19235
19236 static void
19237 Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
19238 {
19239   slotbuf[0] = 0xe30e70;
19240 }
19241
19242 static void
19243 Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
19244 {
19245   slotbuf[0] = 0xf3e700;
19246 }
19247
19248 static void
19249 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
19250 {
19251   slotbuf[0] = 0xc002;
19252 }
19253
19254 static void
19255 Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19256 {
19257   slotbuf[0] = 0x200040;
19258 }
19259
19260 static void
19261 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
19262 {
19263   slotbuf[0] = 0xd002;
19264 }
19265
19266 static void
19267 Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19268 {
19269   slotbuf[0] = 0x200080;
19270 }
19271
19272 static void
19273 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
19274 {
19275   slotbuf[0] = 0x800000;
19276 }
19277
19278 static void
19279 Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19280 {
19281   slotbuf[0] = 0x1b2000;
19282 }
19283
19284 static void
19285 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
19286 {
19287   slotbuf[0] = 0xc00000;
19288 }
19289
19290 static void
19291 Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19292 {
19293   slotbuf[0] = 0x1ca000;
19294 }
19295
19296 static void
19297 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
19298 {
19299   slotbuf[0] = 0x900000;
19300 }
19301
19302 static void
19303 Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19304 {
19305   slotbuf[0] = 0x1b4000;
19306 }
19307
19308 static void
19309 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
19310 {
19311   slotbuf[0] = 0xa00000;
19312 }
19313
19314 static void
19315 Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19316 {
19317   slotbuf[0] = 0x1b8000;
19318 }
19319
19320 static void
19321 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
19322 {
19323   slotbuf[0] = 0xb00000;
19324 }
19325
19326 static void
19327 Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19328 {
19329   slotbuf[0] = 0x1b3000;
19330 }
19331
19332 static void
19333 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
19334 {
19335   slotbuf[0] = 0xd00000;
19336 }
19337
19338 static void
19339 Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19340 {
19341   slotbuf[0] = 0x1cc000;
19342 }
19343
19344 static void
19345 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
19346 {
19347   slotbuf[0] = 0xe00000;
19348 }
19349
19350 static void
19351 Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19352 {
19353   slotbuf[0] = 0x1cb000;
19354 }
19355
19356 static void
19357 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
19358 {
19359   slotbuf[0] = 0xf00000;
19360 }
19361
19362 static void
19363 Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19364 {
19365   slotbuf[0] = 0x1cd000;
19366 }
19367
19368 static void
19369 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
19370 {
19371   slotbuf[0] = 0x100000;
19372 }
19373
19374 static void
19375 Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19376 {
19377   slotbuf[0] = 0x1b5000;
19378 }
19379
19380 static void
19381 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
19382 {
19383   slotbuf[0] = 0x200000;
19384 }
19385
19386 static void
19387 Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19388 {
19389   slotbuf[0] = 0x1e0000;
19390 }
19391
19392 static void
19393 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
19394 {
19395   slotbuf[0] = 0x300000;
19396 }
19397
19398 static void
19399 Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19400 {
19401   slotbuf[0] = 0x1ce000;
19402 }
19403
19404 static void
19405 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
19406 {
19407   slotbuf[0] = 0x26;
19408 }
19409
19410 static void
19411 Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19412 {
19413   slotbuf[0] = 0x300000;
19414 }
19415
19416 static void
19417 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
19418 {
19419   slotbuf[0] = 0x66;
19420 }
19421
19422 static void
19423 Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19424 {
19425   slotbuf[0] = 0x300003;
19426 }
19427
19428 static void
19429 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
19430 {
19431   slotbuf[0] = 0xe6;
19432 }
19433
19434 static void
19435 Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19436 {
19437   slotbuf[0] = 0x300001;
19438 }
19439
19440 static void
19441 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
19442 {
19443   slotbuf[0] = 0xa6;
19444 }
19445
19446 static void
19447 Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19448 {
19449   slotbuf[0] = 0x300004;
19450 }
19451
19452 static void
19453 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
19454 {
19455   slotbuf[0] = 0x6007;
19456 }
19457
19458 static void
19459 Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19460 {
19461   slotbuf[0] = 0x200000;
19462 }
19463
19464 static void
19465 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
19466 {
19467   slotbuf[0] = 0xe007;
19468 }
19469
19470 static void
19471 Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19472 {
19473   slotbuf[0] = 0x200020;
19474 }
19475
19476 static void
19477 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
19478 {
19479   slotbuf[0] = 0xf6;
19480 }
19481
19482 static void
19483 Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19484 {
19485   slotbuf[0] = 0x300002;
19486 }
19487
19488 static void
19489 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
19490 {
19491   slotbuf[0] = 0xb6;
19492 }
19493
19494 static void
19495 Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19496 {
19497   slotbuf[0] = 0x300008;
19498 }
19499
19500 static void
19501 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
19502 {
19503   slotbuf[0] = 0x1007;
19504 }
19505
19506 static void
19507 Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19508 {
19509   slotbuf[0] = 0x2000a0;
19510 }
19511
19512 static void
19513 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
19514 {
19515   slotbuf[0] = 0x9007;
19516 }
19517
19518 static void
19519 Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19520 {
19521   slotbuf[0] = 0x400000;
19522 }
19523
19524 static void
19525 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
19526 {
19527   slotbuf[0] = 0xa007;
19528 }
19529
19530 static void
19531 Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19532 {
19533   slotbuf[0] = 0x2000c0;
19534 }
19535
19536 static void
19537 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
19538 {
19539   slotbuf[0] = 0x2007;
19540 }
19541
19542 static void
19543 Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19544 {
19545   slotbuf[0] = 0x2000d0;
19546 }
19547
19548 static void
19549 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
19550 {
19551   slotbuf[0] = 0xb007;
19552 }
19553
19554 static void
19555 Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19556 {
19557   slotbuf[0] = 0x2000b0;
19558 }
19559
19560 static void
19561 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
19562 {
19563   slotbuf[0] = 0x3007;
19564 }
19565
19566 static void
19567 Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19568 {
19569   slotbuf[0] = 0x2000e0;
19570 }
19571
19572 static void
19573 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
19574 {
19575   slotbuf[0] = 0x8007;
19576 }
19577
19578 static void
19579 Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19580 {
19581   slotbuf[0] = 0x200060;
19582 }
19583
19584 static void
19585 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
19586 {
19587   slotbuf[0] = 0x7;
19588 }
19589
19590 static void
19591 Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19592 {
19593   slotbuf[0] = 0x400010;
19594 }
19595
19596 static void
19597 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
19598 {
19599   slotbuf[0] = 0x4007;
19600 }
19601
19602 static void
19603 Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19604 {
19605   slotbuf[0] = 0x200050;
19606 }
19607
19608 static void
19609 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
19610 {
19611   slotbuf[0] = 0xc007;
19612 }
19613
19614 static void
19615 Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19616 {
19617   slotbuf[0] = 0x2000f0;
19618 }
19619
19620 static void
19621 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
19622 {
19623   slotbuf[0] = 0x5007;
19624 }
19625
19626 static void
19627 Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19628 {
19629   slotbuf[0] = 0x200070;
19630 }
19631
19632 static void
19633 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
19634 {
19635   slotbuf[0] = 0xd007;
19636 }
19637
19638 static void
19639 Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19640 {
19641   slotbuf[0] = 0x200090;
19642 }
19643
19644 static void
19645 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
19646 {
19647   slotbuf[0] = 0x16;
19648 }
19649
19650 static void
19651 Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19652 {
19653   slotbuf[0] = 0x180000;
19654 }
19655
19656 static void
19657 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
19658 {
19659   slotbuf[0] = 0x56;
19660 }
19661
19662 static void
19663 Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19664 {
19665   slotbuf[0] = 0x190000;
19666 }
19667
19668 static void
19669 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
19670 {
19671   slotbuf[0] = 0xd6;
19672 }
19673
19674 static void
19675 Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19676 {
19677   slotbuf[0] = 0x160000;
19678 }
19679
19680 static void
19681 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
19682 {
19683   slotbuf[0] = 0x96;
19684 }
19685
19686 static void
19687 Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19688 {
19689   slotbuf[0] = 0x170000;
19690 }
19691
19692 static void
19693 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
19694 {
19695   slotbuf[0] = 0x5;
19696 }
19697
19698 static void
19699 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
19700 {
19701   slotbuf[0] = 0xc0;
19702 }
19703
19704 static void
19705 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
19706 {
19707   slotbuf[0] = 0x40000;
19708 }
19709
19710 static void
19711 Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19712 {
19713   slotbuf[0] = 0x140000;
19714 }
19715
19716 static void
19717 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
19718 {
19719   slotbuf[0] = 0;
19720 }
19721
19722 static void
19723 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
19724 {
19725   slotbuf[0] = 0x6;
19726 }
19727
19728 static void
19729 Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19730 {
19731   slotbuf[0] = 0x100000;
19732 }
19733
19734 static void
19735 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
19736 {
19737   slotbuf[0] = 0xa0;
19738 }
19739
19740 static void
19741 Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19742 {
19743   slotbuf[0] = 0x1ee031;
19744 }
19745
19746 static void
19747 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
19748 {
19749   slotbuf[0] = 0x1002;
19750 }
19751
19752 static void
19753 Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19754 {
19755   slotbuf[0] = 0x400040;
19756 }
19757
19758 static void
19759 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
19760 {
19761   slotbuf[0] = 0x9002;
19762 }
19763
19764 static void
19765 Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19766 {
19767   slotbuf[0] = 0x400020;
19768 }
19769
19770 static void
19771 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
19772 {
19773   slotbuf[0] = 0x2002;
19774 }
19775
19776 static void
19777 Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19778 {
19779   slotbuf[0] = 0x400080;
19780 }
19781
19782 static void
19783 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
19784 {
19785   slotbuf[0] = 0x1;
19786 }
19787
19788 static void
19789 Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19790 {
19791   slotbuf[0] = 0x500000;
19792 }
19793
19794 static void
19795 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
19796 {
19797   slotbuf[0] = 0x2;
19798 }
19799
19800 static void
19801 Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19802 {
19803   slotbuf[0] = 0x400030;
19804 }
19805
19806 static void
19807 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
19808 {
19809   slotbuf[0] = 0x8076;
19810 }
19811
19812 static void
19813 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
19814 {
19815   slotbuf[0] = 0x9076;
19816 }
19817
19818 static void
19819 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
19820 {
19821   slotbuf[0] = 0xa076;
19822 }
19823
19824 static void
19825 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
19826 {
19827   slotbuf[0] = 0xa002;
19828 }
19829
19830 static void
19831 Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19832 {
19833   slotbuf[0] = 0x1a0000;
19834 }
19835
19836 static void
19837 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
19838 {
19839   slotbuf[0] = 0x830000;
19840 }
19841
19842 static void
19843 Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19844 {
19845   slotbuf[0] = 0x1be000;
19846 }
19847
19848 static void
19849 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
19850 {
19851   slotbuf[0] = 0x930000;
19852 }
19853
19854 static void
19855 Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19856 {
19857   slotbuf[0] = 0x1c8000;
19858 }
19859
19860 static void
19861 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
19862 {
19863   slotbuf[0] = 0xa30000;
19864 }
19865
19866 static void
19867 Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19868 {
19869   slotbuf[0] = 0x1c4000;
19870 }
19871
19872 static void
19873 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
19874 {
19875   slotbuf[0] = 0xb30000;
19876 }
19877
19878 static void
19879 Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19880 {
19881   slotbuf[0] = 0x1c2000;
19882 }
19883
19884 static void
19885 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
19886 {
19887   slotbuf[0] = 0x600000;
19888 }
19889
19890 static void
19891 Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19892 {
19893   slotbuf[0] = 0x1f1d00;
19894 }
19895
19896 static void
19897 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
19898 {
19899   slotbuf[0] = 0x600100;
19900 }
19901
19902 static void
19903 Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19904 {
19905   slotbuf[0] = 0x1f1c00;
19906 }
19907
19908 static void
19909 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
19910 {
19911   slotbuf[0] = 0x20f0;
19912 }
19913
19914 static void
19915 Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
19916 {
19917   slotbuf[0] = 0x16105;
19918 }
19919
19920 static void
19921 Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19922 {
19923   slotbuf[0] = 0x1ee0b1;
19924 }
19925
19926 static void
19927 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
19928 {
19929   slotbuf[0] = 0x80;
19930 }
19931
19932 static void
19933 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
19934 {
19935   slotbuf[0] = 0x5100;
19936 }
19937
19938 static void
19939 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
19940 {
19941   slotbuf[0] = 0x5002;
19942 }
19943
19944 static void
19945 Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19946 {
19947   slotbuf[0] = 0x400050;
19948 }
19949
19950 static void
19951 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
19952 {
19953   slotbuf[0] = 0x6002;
19954 }
19955
19956 static void
19957 Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19958 {
19959   slotbuf[0] = 0x400060;
19960 }
19961
19962 static void
19963 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
19964 {
19965   slotbuf[0] = 0x4002;
19966 }
19967
19968 static void
19969 Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19970 {
19971   slotbuf[0] = 0x400070;
19972 }
19973
19974 static void
19975 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
19976 {
19977   slotbuf[0] = 0x400000;
19978 }
19979
19980 static void
19981 Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19982 {
19983   slotbuf[0] = 0x1ee071;
19984 }
19985
19986 static void
19987 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
19988 {
19989   slotbuf[0] = 0x401000;
19990 }
19991
19992 static void
19993 Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19994 {
19995   slotbuf[0] = 0x1ee038;
19996 }
19997
19998 static void
19999 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
20000 {
20001   slotbuf[0] = 0x402000;
20002 }
20003
20004 static void
20005 Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20006 {
20007   slotbuf[0] = 0x1ee034;
20008 }
20009
20010 static void
20011 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
20012 {
20013   slotbuf[0] = 0x403000;
20014 }
20015
20016 static void
20017 Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20018 {
20019   slotbuf[0] = 0x1ee032;
20020 }
20021
20022 static void
20023 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
20024 {
20025   slotbuf[0] = 0x404000;
20026 }
20027
20028 static void
20029 Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20030 {
20031   slotbuf[0] = 0x1ef0a0;
20032 }
20033
20034 static void
20035 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
20036 {
20037   slotbuf[0] = 0xa10000;
20038 }
20039
20040 static void
20041 Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20042 {
20043   slotbuf[0] = 0x1f5003;
20044 }
20045
20046 static void
20047 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
20048 {
20049   slotbuf[0] = 0x810000;
20050 }
20051
20052 static void
20053 Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20054 {
20055   slotbuf[0] = 0x1c7000;
20056 }
20057
20058 static void
20059 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
20060 {
20061   slotbuf[0] = 0x910000;
20062 }
20063
20064 static void
20065 Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20066 {
20067   slotbuf[0] = 0x1f1f00;
20068 }
20069
20070 static void
20071 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
20072 {
20073   slotbuf[0] = 0xb10000;
20074 }
20075
20076 static void
20077 Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20078 {
20079   slotbuf[0] = 0x1f1e00;
20080 }
20081
20082 static void
20083 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
20084 {
20085   slotbuf[0] = 0x10000;
20086 }
20087
20088 static void
20089 Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20090 {
20091   slotbuf[0] = 0x1c0000;
20092 }
20093
20094 static void
20095 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
20096 {
20097   slotbuf[0] = 0x210000;
20098 }
20099
20100 static void
20101 Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20102 {
20103   slotbuf[0] = 0x1b0000;
20104 }
20105
20106 static void
20107 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
20108 {
20109   slotbuf[0] = 0x410000;
20110 }
20111
20112 static void
20113 Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20114 {
20115   slotbuf[0] = 0x1c9000;
20116 }
20117
20118 static void
20119 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
20120 {
20121   slotbuf[0] = 0x20c0;
20122 }
20123
20124 static void
20125 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
20126 {
20127   slotbuf[0] = 0x20d0;
20128 }
20129
20130 static void
20131 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
20132 {
20133   slotbuf[0] = 0x2000;
20134 }
20135
20136 static void
20137 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
20138 {
20139   slotbuf[0] = 0x2010;
20140 }
20141
20142 static void
20143 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
20144 {
20145   slotbuf[0] = 0x2020;
20146 }
20147
20148 static void
20149 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
20150 {
20151   slotbuf[0] = 0x2030;
20152 }
20153
20154 static void
20155 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
20156 {
20157   slotbuf[0] = 0x6000;
20158 }
20159
20160 static void
20161 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
20162 {
20163   slotbuf[0] = 0x30100;
20164 }
20165
20166 static void
20167 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
20168 {
20169   slotbuf[0] = 0x130100;
20170 }
20171
20172 static void
20173 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
20174 {
20175   slotbuf[0] = 0x610100;
20176 }
20177
20178 static void
20179 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20180 {
20181   slotbuf[0] = 0x30200;
20182 }
20183
20184 static void
20185 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20186 {
20187   slotbuf[0] = 0x130200;
20188 }
20189
20190 static void
20191 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20192 {
20193   slotbuf[0] = 0x610200;
20194 }
20195
20196 static void
20197 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
20198 {
20199   slotbuf[0] = 0x30000;
20200 }
20201
20202 static void
20203 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
20204 {
20205   slotbuf[0] = 0x130000;
20206 }
20207
20208 static void
20209 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
20210 {
20211   slotbuf[0] = 0x610000;
20212 }
20213
20214 static void
20215 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
20216 {
20217   slotbuf[0] = 0x30300;
20218 }
20219
20220 static void
20221 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
20222 {
20223   slotbuf[0] = 0x130300;
20224 }
20225
20226 static void
20227 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
20228 {
20229   slotbuf[0] = 0x610300;
20230 }
20231
20232 static void
20233 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
20234 {
20235   slotbuf[0] = 0x30500;
20236 }
20237
20238 static void
20239 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
20240 {
20241   slotbuf[0] = 0x130500;
20242 }
20243
20244 static void
20245 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
20246 {
20247   slotbuf[0] = 0x610500;
20248 }
20249
20250 static void
20251 Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20252 {
20253   slotbuf[0] = 0x3b000;
20254 }
20255
20256 static void
20257 Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20258 {
20259   slotbuf[0] = 0x13b000;
20260 }
20261
20262 static void
20263 Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20264 {
20265   slotbuf[0] = 0x3d000;
20266 }
20267
20268 static void
20269 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
20270 {
20271   slotbuf[0] = 0x3e600;
20272 }
20273
20274 static void
20275 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
20276 {
20277   slotbuf[0] = 0x13e600;
20278 }
20279
20280 static void
20281 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
20282 {
20283   slotbuf[0] = 0x61e600;
20284 }
20285
20286 static void
20287 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20288 {
20289   slotbuf[0] = 0x3b100;
20290 }
20291
20292 static void
20293 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20294 {
20295   slotbuf[0] = 0x13b100;
20296 }
20297
20298 static void
20299 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20300 {
20301   slotbuf[0] = 0x61b100;
20302 }
20303
20304 static void
20305 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20306 {
20307   slotbuf[0] = 0x3d100;
20308 }
20309
20310 static void
20311 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20312 {
20313   slotbuf[0] = 0x13d100;
20314 }
20315
20316 static void
20317 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20318 {
20319   slotbuf[0] = 0x61d100;
20320 }
20321
20322 static void
20323 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20324 {
20325   slotbuf[0] = 0x3b200;
20326 }
20327
20328 static void
20329 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20330 {
20331   slotbuf[0] = 0x13b200;
20332 }
20333
20334 static void
20335 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20336 {
20337   slotbuf[0] = 0x61b200;
20338 }
20339
20340 static void
20341 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20342 {
20343   slotbuf[0] = 0x3d200;
20344 }
20345
20346 static void
20347 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20348 {
20349   slotbuf[0] = 0x13d200;
20350 }
20351
20352 static void
20353 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20354 {
20355   slotbuf[0] = 0x61d200;
20356 }
20357
20358 static void
20359 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20360 {
20361   slotbuf[0] = 0x3c200;
20362 }
20363
20364 static void
20365 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20366 {
20367   slotbuf[0] = 0x13c200;
20368 }
20369
20370 static void
20371 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20372 {
20373   slotbuf[0] = 0x61c200;
20374 }
20375
20376 static void
20377 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20378 {
20379   slotbuf[0] = 0x3ee00;
20380 }
20381
20382 static void
20383 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20384 {
20385   slotbuf[0] = 0x13ee00;
20386 }
20387
20388 static void
20389 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20390 {
20391   slotbuf[0] = 0x61ee00;
20392 }
20393
20394 static void
20395 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
20396 {
20397   slotbuf[0] = 0x3c000;
20398 }
20399
20400 static void
20401 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
20402 {
20403   slotbuf[0] = 0x13c000;
20404 }
20405
20406 static void
20407 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
20408 {
20409   slotbuf[0] = 0x61c000;
20410 }
20411
20412 static void
20413 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
20414 {
20415   slotbuf[0] = 0x3e800;
20416 }
20417
20418 static void
20419 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
20420 {
20421   slotbuf[0] = 0x13e800;
20422 }
20423
20424 static void
20425 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
20426 {
20427   slotbuf[0] = 0x61e800;
20428 }
20429
20430 static void
20431 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20432 {
20433   slotbuf[0] = 0x3f400;
20434 }
20435
20436 static void
20437 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20438 {
20439   slotbuf[0] = 0x13f400;
20440 }
20441
20442 static void
20443 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20444 {
20445   slotbuf[0] = 0x61f400;
20446 }
20447
20448 static void
20449 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20450 {
20451   slotbuf[0] = 0x3f500;
20452 }
20453
20454 static void
20455 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20456 {
20457   slotbuf[0] = 0x13f500;
20458 }
20459
20460 static void
20461 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20462 {
20463   slotbuf[0] = 0x61f500;
20464 }
20465
20466 static void
20467 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
20468 {
20469   slotbuf[0] = 0x3eb00;
20470 }
20471
20472 static void
20473 Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
20474 {
20475   slotbuf[0] = 0x3e700;
20476 }
20477
20478 static void
20479 Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
20480 {
20481   slotbuf[0] = 0x13e700;
20482 }
20483
20484 static void
20485 Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
20486 {
20487   slotbuf[0] = 0x61e700;
20488 }
20489
20490 static void
20491 Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
20492 {
20493   slotbuf[0] = 0xc10000;
20494 }
20495
20496 static void
20497 Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
20498 {
20499   slotbuf[0] = 0xd10000;
20500 }
20501
20502 static void
20503 Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
20504 {
20505   slotbuf[0] = 0x820000;
20506 }
20507
20508 static void
20509 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
20510 {
20511   slotbuf[0] = 0x3010;
20512 }
20513
20514 static void
20515 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
20516 {
20517   slotbuf[0] = 0x7000;
20518 }
20519
20520 static void
20521 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
20522 {
20523   slotbuf[0] = 0x3e200;
20524 }
20525
20526 static void
20527 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
20528 {
20529   slotbuf[0] = 0x13e200;
20530 }
20531
20532 static void
20533 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
20534 {
20535   slotbuf[0] = 0x13e300;
20536 }
20537
20538 static void
20539 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
20540 {
20541   slotbuf[0] = 0x3e400;
20542 }
20543
20544 static void
20545 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
20546 {
20547   slotbuf[0] = 0x13e400;
20548 }
20549
20550 static void
20551 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
20552 {
20553   slotbuf[0] = 0x61e400;
20554 }
20555
20556 static void
20557 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
20558 {
20559   slotbuf[0] = 0x4000;
20560 }
20561
20562 static void
20563 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
20564 {
20565   slotbuf[0] = 0xf02d;
20566 }
20567
20568 static void
20569 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
20570 {
20571   slotbuf[0] = 0x3e900;
20572 }
20573
20574 static void
20575 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
20576 {
20577   slotbuf[0] = 0x13e900;
20578 }
20579
20580 static void
20581 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
20582 {
20583   slotbuf[0] = 0x61e900;
20584 }
20585
20586 static void
20587 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20588 {
20589   slotbuf[0] = 0x3ec00;
20590 }
20591
20592 static void
20593 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20594 {
20595   slotbuf[0] = 0x13ec00;
20596 }
20597
20598 static void
20599 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20600 {
20601   slotbuf[0] = 0x61ec00;
20602 }
20603
20604 static void
20605 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
20606 {
20607   slotbuf[0] = 0x3ed00;
20608 }
20609
20610 static void
20611 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
20612 {
20613   slotbuf[0] = 0x13ed00;
20614 }
20615
20616 static void
20617 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
20618 {
20619   slotbuf[0] = 0x61ed00;
20620 }
20621
20622 static void
20623 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20624 {
20625   slotbuf[0] = 0x36800;
20626 }
20627
20628 static void
20629 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20630 {
20631   slotbuf[0] = 0x136800;
20632 }
20633
20634 static void
20635 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20636 {
20637   slotbuf[0] = 0x616800;
20638 }
20639
20640 static void
20641 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
20642 {
20643   slotbuf[0] = 0xf1e000;
20644 }
20645
20646 static void
20647 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
20648 {
20649   slotbuf[0] = 0xf1e010;
20650 }
20651
20652 static void
20653 Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
20654 {
20655   slotbuf[0] = 0x20000;
20656 }
20657
20658 static void
20659 Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20660 {
20661   slotbuf[0] = 0x1b6000;
20662 }
20663
20664 static void
20665 Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
20666 {
20667   slotbuf[0] = 0x120000;
20668 }
20669
20670 static void
20671 Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20672 {
20673   slotbuf[0] = 0x1b7000;
20674 }
20675
20676 static void
20677 Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
20678 {
20679   slotbuf[0] = 0x220000;
20680 }
20681
20682 static void
20683 Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20684 {
20685   slotbuf[0] = 0x1c3000;
20686 }
20687
20688 static void
20689 Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
20690 {
20691   slotbuf[0] = 0x320000;
20692 }
20693
20694 static void
20695 Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20696 {
20697   slotbuf[0] = 0x1c5000;
20698 }
20699
20700 static void
20701 Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
20702 {
20703   slotbuf[0] = 0x420000;
20704 }
20705
20706 static void
20707 Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20708 {
20709   slotbuf[0] = 0x1cf000;
20710 }
20711
20712 static void
20713 Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
20714 {
20715   slotbuf[0] = 0x8000;
20716 }
20717
20718 static void
20719 Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20720 {
20721   slotbuf[0] = 0x1f2480;
20722 }
20723
20724 static void
20725 Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
20726 {
20727   slotbuf[0] = 0x9000;
20728 }
20729
20730 static void
20731 Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20732 {
20733   slotbuf[0] = 0x1f2800;
20734 }
20735
20736 static void
20737 Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
20738 {
20739   slotbuf[0] = 0xa000;
20740 }
20741
20742 static void
20743 Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20744 {
20745   slotbuf[0] = 0x1ef060;
20746 }
20747
20748 static void
20749 Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
20750 {
20751   slotbuf[0] = 0xb000;
20752 }
20753
20754 static void
20755 Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20756 {
20757   slotbuf[0] = 0x1ef020;
20758 }
20759
20760 static void
20761 Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
20762 {
20763   slotbuf[0] = 0x76;
20764 }
20765
20766 static void
20767 Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20768 {
20769   slotbuf[0] = 0x300005;
20770 }
20771
20772 static void
20773 Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
20774 {
20775   slotbuf[0] = 0x1076;
20776 }
20777
20778 static void
20779 Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20780 {
20781   slotbuf[0] = 0x300006;
20782 }
20783
20784 static void
20785 Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
20786 {
20787   slotbuf[0] = 0xc30000;
20788 }
20789
20790 static void
20791 Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20792 {
20793   slotbuf[0] = 0x1bf000;
20794 }
20795
20796 static void
20797 Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
20798 {
20799   slotbuf[0] = 0xd30000;
20800 }
20801
20802 static void
20803 Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20804 {
20805   slotbuf[0] = 0x1d0000;
20806 }
20807
20808 static void
20809 Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
20810 {
20811   slotbuf[0] = 0x30400;
20812 }
20813
20814 static void
20815 Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
20816 {
20817   slotbuf[0] = 0x130400;
20818 }
20819
20820 static void
20821 Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
20822 {
20823   slotbuf[0] = 0x610400;
20824 }
20825
20826 static void
20827 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20828 {
20829   slotbuf[0] = 0x3ea00;
20830 }
20831
20832 static void
20833 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20834 {
20835   slotbuf[0] = 0x13ea00;
20836 }
20837
20838 static void
20839 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20840 {
20841   slotbuf[0] = 0x61ea00;
20842 }
20843
20844 static void
20845 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20846 {
20847   slotbuf[0] = 0x3f000;
20848 }
20849
20850 static void
20851 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20852 {
20853   slotbuf[0] = 0x13f000;
20854 }
20855
20856 static void
20857 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20858 {
20859   slotbuf[0] = 0x61f000;
20860 }
20861
20862 static void
20863 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20864 {
20865   slotbuf[0] = 0x3f100;
20866 }
20867
20868 static void
20869 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20870 {
20871   slotbuf[0] = 0x13f100;
20872 }
20873
20874 static void
20875 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20876 {
20877   slotbuf[0] = 0x61f100;
20878 }
20879
20880 static void
20881 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
20882 {
20883   slotbuf[0] = 0x70c2;
20884 }
20885
20886 static void
20887 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
20888 {
20889   slotbuf[0] = 0x70e2;
20890 }
20891
20892 static void
20893 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
20894 {
20895   slotbuf[0] = 0x70f2;
20896 }
20897
20898 static void
20899 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
20900 {
20901   slotbuf[0] = 0xf10000;
20902 }
20903
20904 static void
20905 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
20906 {
20907   slotbuf[0] = 0xf12000;
20908 }
20909
20910 static void
20911 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
20912 {
20913   slotbuf[0] = 0xf11000;
20914 }
20915
20916 static void
20917 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
20918 {
20919   slotbuf[0] = 0xf13000;
20920 }
20921
20922 static void
20923 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
20924 {
20925   slotbuf[0] = 0x7042;
20926 }
20927
20928 static void
20929 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
20930 {
20931   slotbuf[0] = 0x7052;
20932 }
20933
20934 static void
20935 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
20936 {
20937   slotbuf[0] = 0x47082;
20938 }
20939
20940 static void
20941 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
20942 {
20943   slotbuf[0] = 0x57082;
20944 }
20945
20946 static void
20947 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
20948 {
20949   slotbuf[0] = 0x7062;
20950 }
20951
20952 static void
20953 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
20954 {
20955   slotbuf[0] = 0x7072;
20956 }
20957
20958 static void
20959 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20960 {
20961   slotbuf[0] = 0x7002;
20962 }
20963
20964 static void
20965 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
20966 {
20967   slotbuf[0] = 0x7012;
20968 }
20969
20970 static void
20971 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
20972 {
20973   slotbuf[0] = 0x7022;
20974 }
20975
20976 static void
20977 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
20978 {
20979   slotbuf[0] = 0x7032;
20980 }
20981
20982 static void
20983 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
20984 {
20985   slotbuf[0] = 0xf19000;
20986 }
20987
20988 static void
20989 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
20990 {
20991   slotbuf[0] = 0xf18000;
20992 }
20993
20994 static void
20995 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20996 {
20997   slotbuf[0] = 0x135300;
20998 }
20999
21000 static void
21001 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21002 {
21003   slotbuf[0] = 0x35300;
21004 }
21005
21006 static void
21007 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21008 {
21009   slotbuf[0] = 0x615300;
21010 }
21011
21012 static void
21013 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
21014 {
21015   slotbuf[0] = 0x35a00;
21016 }
21017
21018 static void
21019 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
21020 {
21021   slotbuf[0] = 0x135a00;
21022 }
21023
21024 static void
21025 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
21026 {
21027   slotbuf[0] = 0x615a00;
21028 }
21029
21030 static void
21031 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
21032 {
21033   slotbuf[0] = 0x35b00;
21034 }
21035
21036 static void
21037 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
21038 {
21039   slotbuf[0] = 0x135b00;
21040 }
21041
21042 static void
21043 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
21044 {
21045   slotbuf[0] = 0x615b00;
21046 }
21047
21048 static void
21049 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
21050 {
21051   slotbuf[0] = 0x35c00;
21052 }
21053
21054 static void
21055 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
21056 {
21057   slotbuf[0] = 0x135c00;
21058 }
21059
21060 static void
21061 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
21062 {
21063   slotbuf[0] = 0x615c00;
21064 }
21065
21066 static void
21067 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
21068 {
21069   slotbuf[0] = 0x50c000;
21070 }
21071
21072 static void
21073 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
21074 {
21075   slotbuf[0] = 0x50d000;
21076 }
21077
21078 static void
21079 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
21080 {
21081   slotbuf[0] = 0x50b000;
21082 }
21083
21084 static void
21085 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
21086 {
21087   slotbuf[0] = 0x50f000;
21088 }
21089
21090 static void
21091 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
21092 {
21093   slotbuf[0] = 0x50e000;
21094 }
21095
21096 static void
21097 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
21098 {
21099   slotbuf[0] = 0x504000;
21100 }
21101
21102 static void
21103 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
21104 {
21105   slotbuf[0] = 0x505000;
21106 }
21107
21108 static void
21109 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
21110 {
21111   slotbuf[0] = 0x503000;
21112 }
21113
21114 static void
21115 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
21116 {
21117   slotbuf[0] = 0x507000;
21118 }
21119
21120 static void
21121 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
21122 {
21123   slotbuf[0] = 0x506000;
21124 }
21125
21126 static void
21127 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
21128 {
21129   slotbuf[0] = 0xf1f000;
21130 }
21131
21132 static void
21133 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
21134 {
21135   slotbuf[0] = 0x501000;
21136 }
21137
21138 static void
21139 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
21140 {
21141   slotbuf[0] = 0x509000;
21142 }
21143
21144 static void
21145 Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
21146 {
21147   slotbuf[0] = 0x3e000;
21148 }
21149
21150 static void
21151 Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
21152 {
21153   slotbuf[0] = 0x13e000;
21154 }
21155
21156 static void
21157 Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
21158 {
21159   slotbuf[0] = 0x61e000;
21160 }
21161
21162 static void
21163 Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
21164 {
21165   slotbuf[0] = 0x330000;
21166 }
21167
21168 static void
21169 Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21170 {
21171   slotbuf[0] = 0x1b9000;
21172 }
21173
21174 static void
21175 Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
21176 {
21177   slotbuf[0] = 0x430000;
21178 }
21179
21180 static void
21181 Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21182 {
21183   slotbuf[0] = 0x1bb000;
21184 }
21185
21186 static void
21187 Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
21188 {
21189   slotbuf[0] = 0x530000;
21190 }
21191
21192 static void
21193 Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21194 {
21195   slotbuf[0] = 0x1ba000;
21196 }
21197
21198 static void
21199 Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21200 {
21201   slotbuf[0] = 0x630000;
21202 }
21203
21204 static void
21205 Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21206 {
21207   slotbuf[0] = 0x1bd000;
21208 }
21209
21210 static void
21211 Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21212 {
21213   slotbuf[0] = 0x730000;
21214 }
21215
21216 static void
21217 Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21218 {
21219   slotbuf[0] = 0x1bc000;
21220 }
21221
21222 static void
21223 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
21224 {
21225   slotbuf[0] = 0x40e000;
21226 }
21227
21228 static void
21229 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
21230 {
21231   slotbuf[0] = 0x40f000;
21232 }
21233
21234 static void
21235 Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
21236 {
21237   slotbuf[0] = 0x230000;
21238 }
21239
21240 static void
21241 Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21242 {
21243   slotbuf[0] = 0x1c6000;
21244 }
21245
21246 static void
21247 Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
21248 {
21249   slotbuf[0] = 0xb002;
21250 }
21251
21252 static void
21253 Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
21254 {
21255   slotbuf[0] = 0xf002;
21256 }
21257
21258 static void
21259 Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21260 {
21261   slotbuf[0] = 0xe002;
21262 }
21263
21264 static void
21265 Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
21266 {
21267   slotbuf[0] = 0x30c00;
21268 }
21269
21270 static void
21271 Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
21272 {
21273   slotbuf[0] = 0x130c00;
21274 }
21275
21276 static void
21277 Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
21278 {
21279   slotbuf[0] = 0x610c00;
21280 }
21281
21282 static void
21283 Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
21284 {
21285   slotbuf[0] = 0x36300;
21286 }
21287
21288 static void
21289 Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
21290 {
21291   slotbuf[0] = 0x136300;
21292 }
21293
21294 static void
21295 Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
21296 {
21297   slotbuf[0] = 0x616300;
21298 }
21299
21300 static void
21301 Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
21302 {
21303   slotbuf[0] = 0x406000;
21304 }
21305
21306 static void
21307 Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
21308 {
21309   slotbuf[0] = 0x407000;
21310 }
21311
21312 static void
21313 Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
21314 {
21315   slotbuf[0] = 0xe30f00;
21316 }
21317
21318 static void
21319 Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
21320 {
21321   slotbuf[0] = 0xf3f000;
21322 }
21323
21324 static void
21325 Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
21326 {
21327   slotbuf[0] = 0xe30f10;
21328 }
21329
21330 static void
21331 Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
21332 {
21333   slotbuf[0] = 0xf3f100;
21334 }
21335
21336 static void
21337 Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
21338 {
21339   slotbuf[0] = 0xe30f20;
21340 }
21341
21342 static void
21343 Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
21344 {
21345   slotbuf[0] = 0xf3f200;
21346 }
21347
21348 static void
21349 Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
21350 {
21351   slotbuf[0] = 0xe30f30;
21352 }
21353
21354 static void
21355 Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
21356 {
21357   slotbuf[0] = 0xf3f300;
21358 }
21359
21360 static void
21361 Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
21362 {
21363   slotbuf[0] = 0xc90804;
21364 }
21365
21366 static void
21367 Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
21368 {
21369   slotbuf[0] = 0xca0004;
21370 }
21371
21372 static void
21373 Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
21374 {
21375   slotbuf[0] = 0xc90904;
21376 }
21377
21378 static void
21379 Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
21380 {
21381   slotbuf[0] = 0xca1004;
21382 }
21383
21384 static void
21385 Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21386 {
21387   slotbuf[0] = 0xc90a04;
21388 }
21389
21390 static void
21391 Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21392 {
21393   slotbuf[0] = 0xca2004;
21394 }
21395
21396 static void
21397 Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
21398 {
21399   slotbuf[0] = 0xc90b04;
21400 }
21401
21402 static void
21403 Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
21404 {
21405   slotbuf[0] = 0xca3004;
21406 }
21407
21408 static void
21409 Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
21410 {
21411   slotbuf[0] = 0xc90c04;
21412 }
21413
21414 static void
21415 Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
21416 {
21417   slotbuf[0] = 0xca4004;
21418 }
21419
21420 static void
21421 Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
21422 {
21423   slotbuf[0] = 0xc90d04;
21424 }
21425
21426 static void
21427 Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
21428 {
21429   slotbuf[0] = 0xca5004;
21430 }
21431
21432 static void
21433 Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
21434 {
21435   slotbuf[0] = 0xc90e04;
21436 }
21437
21438 static void
21439 Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
21440 {
21441   slotbuf[0] = 0xca6004;
21442 }
21443
21444 static void
21445 Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
21446 {
21447   slotbuf[0] = 0xc90f04;
21448 }
21449
21450 static void
21451 Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
21452 {
21453   slotbuf[0] = 0xca7004;
21454 }
21455
21456 static void
21457 Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21458 {
21459   slotbuf[0] = 0x1d1080;
21460 }
21461
21462 static void
21463 Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21464 {
21465   slotbuf[0] = 0xa50004;
21466 }
21467
21468 static void
21469 Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21470 {
21471   slotbuf[0] = 0x1d2080;
21472 }
21473
21474 static void
21475 Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21476 {
21477   slotbuf[0] = 0xa90004;
21478 }
21479
21480 static void
21481 Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21482 {
21483   slotbuf[0] = 0x1d3000;
21484 }
21485
21486 static void
21487 Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21488 {
21489   slotbuf[0] = 0xac0004;
21490 }
21491
21492 static void
21493 Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21494 {
21495   slotbuf[0] = 0x1d3080;
21496 }
21497
21498 static void
21499 Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21500 {
21501   slotbuf[0] = 0xaf0004;
21502 }
21503
21504 static void
21505 Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21506 {
21507   slotbuf[0] = 0x1d6080;
21508 }
21509
21510 static void
21511 Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21512 {
21513   slotbuf[0] = 0xa58004;
21514 }
21515
21516 static void
21517 Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21518 {
21519   slotbuf[0] = 0x1d7000;
21520 }
21521
21522 static void
21523 Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21524 {
21525   slotbuf[0] = 0xa98004;
21526 }
21527
21528 static void
21529 Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21530 {
21531   slotbuf[0] = 0x1d7080;
21532 }
21533
21534 static void
21535 Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21536 {
21537   slotbuf[0] = 0xac8004;
21538 }
21539
21540 static void
21541 Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21542 {
21543   slotbuf[0] = 0x1d8080;
21544 }
21545
21546 static void
21547 Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21548 {
21549   slotbuf[0] = 0xaf8004;
21550 }
21551
21552 static void
21553 Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21554 {
21555   slotbuf[0] = 0x1d9000;
21556 }
21557
21558 static void
21559 Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21560 {
21561   slotbuf[0] = 0xa60004;
21562 }
21563
21564 static void
21565 Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21566 {
21567   slotbuf[0] = 0x1da000;
21568 }
21569
21570 static void
21571 Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21572 {
21573   slotbuf[0] = 0xaa0004;
21574 }
21575
21576 static void
21577 Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21578 {
21579   slotbuf[0] = 0x1dc000;
21580 }
21581
21582 static void
21583 Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21584 {
21585   slotbuf[0] = 0xad0004;
21586 }
21587
21588 static void
21589 Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21590 {
21591   slotbuf[0] = 0x1d9080;
21592 }
21593
21594 static void
21595 Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21596 {
21597   slotbuf[0] = 0xb00004;
21598 }
21599
21600 static void
21601 Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21602 {
21603   slotbuf[0] = 0x1d4080;
21604 }
21605
21606 static void
21607 Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21608 {
21609   slotbuf[0] = 0xa68004;
21610 }
21611
21612 static void
21613 Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21614 {
21615   slotbuf[0] = 0x1d5000;
21616 }
21617
21618 static void
21619 Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21620 {
21621   slotbuf[0] = 0xaa8004;
21622 }
21623
21624 static void
21625 Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21626 {
21627   slotbuf[0] = 0x1d6000;
21628 }
21629
21630 static void
21631 Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21632 {
21633   slotbuf[0] = 0xad8004;
21634 }
21635
21636 static void
21637 Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21638 {
21639   slotbuf[0] = 0x1d5080;
21640 }
21641
21642 static void
21643 Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21644 {
21645   slotbuf[0] = 0xb08004;
21646 }
21647
21648 static void
21649 Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21650 {
21651   slotbuf[0] = 0x1dd000;
21652 }
21653
21654 static void
21655 Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21656 {
21657   slotbuf[0] = 0xa70004;
21658 }
21659
21660 static void
21661 Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21662 {
21663   slotbuf[0] = 0x1de000;
21664 }
21665
21666 static void
21667 Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21668 {
21669   slotbuf[0] = 0xab0004;
21670 }
21671
21672 static void
21673 Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21674 {
21675   slotbuf[0] = 0x1dd080;
21676 }
21677
21678 static void
21679 Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21680 {
21681   slotbuf[0] = 0xae0004;
21682 }
21683
21684 static void
21685 Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21686 {
21687   slotbuf[0] = 0x1de080;
21688 }
21689
21690 static void
21691 Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21692 {
21693   slotbuf[0] = 0xb10004;
21694 }
21695
21696 static void
21697 Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21698 {
21699   slotbuf[0] = 0x1da080;
21700 }
21701
21702 static void
21703 Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21704 {
21705   slotbuf[0] = 0xa78004;
21706 }
21707
21708 static void
21709 Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21710 {
21711   slotbuf[0] = 0x1db000;
21712 }
21713
21714 static void
21715 Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21716 {
21717   slotbuf[0] = 0xab8004;
21718 }
21719
21720 static void
21721 Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21722 {
21723   slotbuf[0] = 0x1db080;
21724 }
21725
21726 static void
21727 Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21728 {
21729   slotbuf[0] = 0xae8004;
21730 }
21731
21732 static void
21733 Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21734 {
21735   slotbuf[0] = 0x1dc080;
21736 }
21737
21738 static void
21739 Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21740 {
21741   slotbuf[0] = 0xb18004;
21742 }
21743
21744 static void
21745 Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21746 {
21747   slotbuf[0] = 0x1e8000;
21748 }
21749
21750 static void
21751 Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21752 {
21753   slotbuf[0] = 0xb20004;
21754 }
21755
21756 static void
21757 Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21758 {
21759   slotbuf[0] = 0x1f0000;
21760 }
21761
21762 static void
21763 Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21764 {
21765   slotbuf[0] = 0xb50004;
21766 }
21767
21768 static void
21769 Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21770 {
21771   slotbuf[0] = 0x1e1080;
21772 }
21773
21774 static void
21775 Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21776 {
21777   slotbuf[0] = 0xb80004;
21778 }
21779
21780 static void
21781 Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21782 {
21783   slotbuf[0] = 0x1e2080;
21784 }
21785
21786 static void
21787 Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21788 {
21789   slotbuf[0] = 0xbb0004;
21790 }
21791
21792 static void
21793 Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21794 {
21795   slotbuf[0] = 0x1ec000;
21796 }
21797
21798 static void
21799 Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21800 {
21801   slotbuf[0] = 0xb28004;
21802 }
21803
21804 static void
21805 Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21806 {
21807   slotbuf[0] = 0x1e9080;
21808 }
21809
21810 static void
21811 Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21812 {
21813   slotbuf[0] = 0xb58004;
21814 }
21815
21816 static void
21817 Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21818 {
21819   slotbuf[0] = 0x1ea080;
21820 }
21821
21822 static void
21823 Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21824 {
21825   slotbuf[0] = 0xb88004;
21826 }
21827
21828 static void
21829 Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21830 {
21831   slotbuf[0] = 0x1eb000;
21832 }
21833
21834 static void
21835 Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21836 {
21837   slotbuf[0] = 0xbb8004;
21838 }
21839
21840 static void
21841 Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21842 {
21843   slotbuf[0] = 0x1e7080;
21844 }
21845
21846 static void
21847 Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21848 {
21849   slotbuf[0] = 0xb30004;
21850 }
21851
21852 static void
21853 Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21854 {
21855   slotbuf[0] = 0x1e8080;
21856 }
21857
21858 static void
21859 Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21860 {
21861   slotbuf[0] = 0xb60004;
21862 }
21863
21864 static void
21865 Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21866 {
21867   slotbuf[0] = 0x1e9000;
21868 }
21869
21870 static void
21871 Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21872 {
21873   slotbuf[0] = 0xb90004;
21874 }
21875
21876 static void
21877 Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21878 {
21879   slotbuf[0] = 0x1ea000;
21880 }
21881
21882 static void
21883 Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21884 {
21885   slotbuf[0] = 0xbc0004;
21886 }
21887
21888 static void
21889 Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21890 {
21891   slotbuf[0] = 0x1df080;
21892 }
21893
21894 static void
21895 Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21896 {
21897   slotbuf[0] = 0xb38004;
21898 }
21899
21900 static void
21901 Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21902 {
21903   slotbuf[0] = 0x1e1000;
21904 }
21905
21906 static void
21907 Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21908 {
21909   slotbuf[0] = 0xb68004;
21910 }
21911
21912 static void
21913 Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21914 {
21915   slotbuf[0] = 0x1e2000;
21916 }
21917
21918 static void
21919 Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21920 {
21921   slotbuf[0] = 0xb98004;
21922 }
21923
21924 static void
21925 Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21926 {
21927   slotbuf[0] = 0x1e4000;
21928 }
21929
21930 static void
21931 Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21932 {
21933   slotbuf[0] = 0xbc8004;
21934 }
21935
21936 static void
21937 Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21938 {
21939   slotbuf[0] = 0x1e6000;
21940 }
21941
21942 static void
21943 Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21944 {
21945   slotbuf[0] = 0xb40004;
21946 }
21947
21948 static void
21949 Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21950 {
21951   slotbuf[0] = 0x1e5080;
21952 }
21953
21954 static void
21955 Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21956 {
21957   slotbuf[0] = 0xb70004;
21958 }
21959
21960 static void
21961 Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21962 {
21963   slotbuf[0] = 0x1e6080;
21964 }
21965
21966 static void
21967 Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21968 {
21969   slotbuf[0] = 0xba0004;
21970 }
21971
21972 static void
21973 Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21974 {
21975   slotbuf[0] = 0x1e7000;
21976 }
21977
21978 static void
21979 Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21980 {
21981   slotbuf[0] = 0xbd0004;
21982 }
21983
21984 static void
21985 Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21986 {
21987   slotbuf[0] = 0x1e3000;
21988 }
21989
21990 static void
21991 Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21992 {
21993   slotbuf[0] = 0xb48004;
21994 }
21995
21996 static void
21997 Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21998 {
21999   slotbuf[0] = 0x1e3080;
22000 }
22001
22002 static void
22003 Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22004 {
22005   slotbuf[0] = 0xb78004;
22006 }
22007
22008 static void
22009 Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22010 {
22011   slotbuf[0] = 0x1e4080;
22012 }
22013
22014 static void
22015 Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
22016 {
22017   slotbuf[0] = 0xba8004;
22018 }
22019
22020 static void
22021 Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22022 {
22023   slotbuf[0] = 0x1e5000;
22024 }
22025
22026 static void
22027 Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22028 {
22029   slotbuf[0] = 0xbd8004;
22030 }
22031
22032 static void
22033 Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22034 {
22035   slotbuf[0] = 0x1ed030;
22036 }
22037
22038 static void
22039 Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22040 {
22041   slotbuf[0] = 0xc10004;
22042 }
22043
22044 static void
22045 Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22046 {
22047   slotbuf[0] = 0x1ee010;
22048 }
22049
22050 static void
22051 Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22052 {
22053   slotbuf[0] = 0xc12004;
22054 }
22055
22056 static void
22057 Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22058 {
22059   slotbuf[0] = 0x1ee020;
22060 }
22061
22062 static void
22063 Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
22064 {
22065   slotbuf[0] = 0xc20004;
22066 }
22067
22068 static void
22069 Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22070 {
22071   slotbuf[0] = 0x1ef000;
22072 }
22073
22074 static void
22075 Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22076 {
22077   slotbuf[0] = 0xc22004;
22078 }
22079
22080 static void
22081 Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22082 {
22083   slotbuf[0] = 0x1ed000;
22084 }
22085
22086 static void
22087 Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22088 {
22089   slotbuf[0] = 0xc11004;
22090 }
22091
22092 static void
22093 Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22094 {
22095   slotbuf[0] = 0x1ee000;
22096 }
22097
22098 static void
22099 Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22100 {
22101   slotbuf[0] = 0xc13004;
22102 }
22103
22104 static void
22105 Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22106 {
22107   slotbuf[0] = 0x1ed010;
22108 }
22109
22110 static void
22111 Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
22112 {
22113   slotbuf[0] = 0xc21004;
22114 }
22115
22116 static void
22117 Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22118 {
22119   slotbuf[0] = 0x1ed020;
22120 }
22121
22122 static void
22123 Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22124 {
22125   slotbuf[0] = 0xc23004;
22126 }
22127
22128 static void
22129 Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22130 {
22131   slotbuf[0] = 0x1f0080;
22132 }
22133
22134 static void
22135 Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22136 {
22137   slotbuf[0] = 0xc30004;
22138 }
22139
22140 static void
22141 Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22142 {
22143   slotbuf[0] = 0x1f00c0;
22144 }
22145
22146 static void
22147 Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22148 {
22149   slotbuf[0] = 0xc38004;
22150 }
22151
22152 static void
22153 Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22154 {
22155   slotbuf[0] = 0x1f3000;
22156 }
22157
22158 static void
22159 Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
22160 {
22161   slotbuf[0] = 0xc40004;
22162 }
22163
22164 static void
22165 Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22166 {
22167   slotbuf[0] = 0x1f3040;
22168 }
22169
22170 static void
22171 Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22172 {
22173   slotbuf[0] = 0xc48004;
22174 }
22175
22176 static void
22177 Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22178 {
22179   slotbuf[0] = 0x1ec080;
22180 }
22181
22182 static void
22183 Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22184 {
22185   slotbuf[0] = 0xc34004;
22186 }
22187
22188 static void
22189 Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22190 {
22191   slotbuf[0] = 0x1ec0c0;
22192 }
22193
22194 static void
22195 Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22196 {
22197   slotbuf[0] = 0xc3c004;
22198 }
22199
22200 static void
22201 Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22202 {
22203   slotbuf[0] = 0x1f4000;
22204 }
22205
22206 static void
22207 Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
22208 {
22209   slotbuf[0] = 0xc44004;
22210 }
22211
22212 static void
22213 Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22214 {
22215   slotbuf[0] = 0x1f8000;
22216 }
22217
22218 static void
22219 Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22220 {
22221   slotbuf[0] = 0xc4c004;
22222 }
22223
22224 static void
22225 Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22226 {
22227   slotbuf[0] = 0x16b88;
22228 }
22229
22230 static void
22231 Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22232 {
22233   slotbuf[0] = 0x16808;
22234 }
22235
22236 static void
22237 Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22238 {
22239   slotbuf[0] = 0x1f2400;
22240 }
22241
22242 static void
22243 Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf)
22244 {
22245   slotbuf[0] = 0xc90004;
22246 }
22247
22248 static void
22249 Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22250 {
22251   slotbuf[0] = 0x10780;
22252 }
22253
22254 static void
22255 Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22256 {
22257   slotbuf[0] = 0x10708;
22258 }
22259
22260 static void
22261 Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22262 {
22263   slotbuf[0] = 0x10688;
22264 }
22265
22266 static void
22267 Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22268 {
22269   slotbuf[0] = 0x10700;
22270 }
22271
22272 static void
22273 Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22274 {
22275   slotbuf[0] = 0x1c200;
22276 }
22277
22278 static void
22279 Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22280 {
22281   slotbuf[0] = 0x1c004;
22282 }
22283
22284 static void
22285 Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22286 {
22287   slotbuf[0] = 0x10480;
22288 }
22289
22290 static void
22291 Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22292 {
22293   slotbuf[0] = 0x10400;
22294 }
22295
22296 static void
22297 Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22298 {
22299   slotbuf[0] = 0x1df000;
22300 }
22301
22302 static void
22303 Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22304 {
22305   slotbuf[0] = 0xc00004;
22306 }
22307
22308 static void
22309 Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22310 {
22311   slotbuf[0] = 0x1eb080;
22312 }
22313
22314 static void
22315 Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22316 {
22317   slotbuf[0] = 0xc08004;
22318 }
22319
22320 static void
22321 Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22322 {
22323   slotbuf[0] = 0x1f3081;
22324 }
22325
22326 static void
22327 Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
22328 {
22329   slotbuf[0] = 0xcb0004;
22330 }
22331
22332 static void
22333 Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22334 {
22335   slotbuf[0] = 0x1f3080;
22336 }
22337
22338 static void
22339 Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
22340 {
22341   slotbuf[0] = 0xcb8004;
22342 }
22343
22344 static void
22345 Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22346 {
22347   slotbuf[0] = 0x1d8000;
22348 }
22349
22350 static void
22351 Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
22352 {
22353   slotbuf[0] = 0xbe0004;
22354 }
22355
22356 static void
22357 Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22358 {
22359   slotbuf[0] = 0x1d4000;
22360 }
22361
22362 static void
22363 Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
22364 {
22365   slotbuf[0] = 0xbe8004;
22366 }
22367
22368 static void
22369 Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22370 {
22371   slotbuf[0] = 0x1d2000;
22372 }
22373
22374 static void
22375 Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
22376 {
22377   slotbuf[0] = 0xbf0004;
22378 }
22379
22380 static void
22381 Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22382 {
22383   slotbuf[0] = 0x1d1000;
22384 }
22385
22386 static void
22387 Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
22388 {
22389   slotbuf[0] = 0xbf8004;
22390 }
22391
22392 static void
22393 Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22394 {
22395   slotbuf[0] = 0x51000;
22396 }
22397
22398 static void
22399 Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22400 {
22401   slotbuf[0] = 0x16b08;
22402 }
22403
22404 static void
22405 Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22406 {
22407   slotbuf[0] = 0x16e48;
22408 }
22409
22410 static void
22411 Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22412 {
22413   slotbuf[0] = 0x16e28;
22414 }
22415
22416 static void
22417 Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22418 {
22419   slotbuf[0] = 0x16e18;
22420 }
22421
22422 static void
22423 Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22424 {
22425   slotbuf[0] = 0x16e08;
22426 }
22427
22428 static void
22429 Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22430 {
22431   slotbuf[0] = 0x16908;
22432 }
22433
22434 static void
22435 Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22436 {
22437   slotbuf[0] = 0x16888;
22438 }
22439
22440 static void
22441 Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22442 {
22443   slotbuf[0] = 0x16085;
22444 }
22445
22446 static void
22447 Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22448 {
22449   slotbuf[0] = 0x16007;
22450 }
22451
22452 static void
22453 Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22454 {
22455   slotbuf[0] = 0x1f2500;
22456 }
22457
22458 static void
22459 Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22460 {
22461   slotbuf[0] = 0xc90414;
22462 }
22463
22464 static void
22465 Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22466 {
22467   slotbuf[0] = 0x1f6000;
22468 }
22469
22470 static void
22471 Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22472 {
22473   slotbuf[0] = 0xe50014;
22474 }
22475
22476 static void
22477 Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22478 {
22479   slotbuf[0] = 0x1f5000;
22480 }
22481
22482 static void
22483 Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22484 {
22485   slotbuf[0] = 0xe60014;
22486 }
22487
22488 static void
22489 Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22490 {
22491   slotbuf[0] = 0x1ee030;
22492 }
22493
22494 static void
22495 Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf)
22496 {
22497   slotbuf[0] = 0xe72034;
22498 }
22499
22500 static void
22501 Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22502 {
22503   slotbuf[0] = 0x16006;
22504 }
22505
22506 static void
22507 Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22508 {
22509   slotbuf[0] = 0x16005;
22510 }
22511
22512 static void
22513 Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22514 {
22515   slotbuf[0] = 0x50139;
22516 }
22517
22518 static void
22519 Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22520 {
22521   slotbuf[0] = 0x16047;
22522 }
22523
22524 static void
22525 Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22526 {
22527   slotbuf[0] = 0x16027;
22528 }
22529
22530 static void
22531 Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22532 {
22533   slotbuf[0] = 0x16017;
22534 }
22535
22536 static void
22537 Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22538 {
22539   slotbuf[0] = 0x1f3086;
22540 }
22541
22542 static void
22543 Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf)
22544 {
22545   slotbuf[0] = 0xe70014;
22546 }
22547
22548 static void
22549 Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22550 {
22551   slotbuf[0] = 0x1f3084;
22552 }
22553
22554 static void
22555 Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
22556 {
22557   slotbuf[0] = 0xc70004;
22558 }
22559
22560 static void
22561 Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22562 {
22563   slotbuf[0] = 0x1f3082;
22564 }
22565
22566 static void
22567 Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
22568 {
22569   slotbuf[0] = 0xc78004;
22570 }
22571
22572 static void
22573 Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22574 {
22575   slotbuf[0] = 0x1f3083;
22576 }
22577
22578 static void
22579 Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
22580 {
22581   slotbuf[0] = 0xc80004;
22582 }
22583
22584 static void
22585 Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22586 {
22587   slotbuf[0] = 0x1f3088;
22588 }
22589
22590 static void
22591 Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
22592 {
22593   slotbuf[0] = 0xc88004;
22594 }
22595
22596 static void
22597 Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22598 {
22599   slotbuf[0] = 0x10500;
22600 }
22601
22602 static void
22603 Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22604 {
22605   slotbuf[0] = 0x10788;
22606 }
22607
22608 static void
22609 Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22610 {
22611   slotbuf[0] = 0x1c600;
22612 }
22613
22614 static void
22615 Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22616 {
22617   slotbuf[0] = 0x1c480;
22618 }
22619
22620 static void
22621 Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22622 {
22623   slotbuf[0] = 0x10580;
22624 }
22625
22626 static void
22627 Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22628 {
22629   slotbuf[0] = 0x10588;
22630 }
22631
22632 static void
22633 Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22634 {
22635   slotbuf[0] = 0x10000;
22636 }
22637
22638 static void
22639 Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22640 {
22641   slotbuf[0] = 0x10200;
22642 }
22643
22644 static void
22645 Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22646 {
22647   slotbuf[0] = 0x10600;
22648 }
22649
22650 static void
22651 Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22652 {
22653   slotbuf[0] = 0x1c400;
22654 }
22655
22656 static void
22657 Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22658 {
22659   slotbuf[0] = 0x1c488;
22660 }
22661
22662 static void
22663 Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22664 {
22665   slotbuf[0] = 0x1c500;
22666 }
22667
22668 static void
22669 Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22670 {
22671   slotbuf[0] = 0x10508;
22672 }
22673
22674 static void
22675 Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22676 {
22677   slotbuf[0] = 0x10608;
22678 }
22679
22680 static void
22681 Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22682 {
22683   slotbuf[0] = 0x10680;
22684 }
22685
22686 static void
22687 Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22688 {
22689   slotbuf[0] = 0x1c408;
22690 }
22691
22692 static void
22693 Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22694 {
22695   slotbuf[0] = 0x1c002;
22696 }
22697
22698 static void
22699 Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22700 {
22701   slotbuf[0] = 0x1c001;
22702 }
22703
22704 static void
22705 Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22706 {
22707   slotbuf[0] = 0x1c000;
22708 }
22709
22710 static void
22711 Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22712 {
22713   slotbuf[0] = 0x52000;
22714 }
22715
22716 static void
22717 Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22718 {
22719   slotbuf[0] = 0x50035;
22720 }
22721
22722 static void
22723 Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22724 {
22725   slotbuf[0] = 0x5003c;
22726 }
22727
22728 static void
22729 Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22730 {
22731   slotbuf[0] = 0x50039;
22732 }
22733
22734 static void
22735 Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22736 {
22737   slotbuf[0] = 0x50032;
22738 }
22739
22740 static void
22741 Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22742 {
22743   slotbuf[0] = 0x50034;
22744 }
22745
22746 static void
22747 Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22748 {
22749   slotbuf[0] = 0x50000;
22750 }
22751
22752 static void
22753 Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22754 {
22755   slotbuf[0] = 0x50010;
22756 }
22757
22758 static void
22759 Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22760 {
22761   slotbuf[0] = 0x50030;
22762 }
22763
22764 static void
22765 Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22766 {
22767   slotbuf[0] = 0x50036;
22768 }
22769
22770 static void
22771 Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22772 {
22773   slotbuf[0] = 0x500b9;
22774 }
22775
22776 static void
22777 Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22778 {
22779   slotbuf[0] = 0x5003a;
22780 }
22781
22782 static void
22783 Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22784 {
22785   slotbuf[0] = 0x50031;
22786 }
22787
22788 static void
22789 Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22790 {
22791   slotbuf[0] = 0x50038;
22792 }
22793
22794 static void
22795 Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22796 {
22797   slotbuf[0] = 0x50033;
22798 }
22799
22800 static void
22801 Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22802 {
22803   slotbuf[0] = 0x50037;
22804 }
22805
22806 static void
22807 Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22808 {
22809   slotbuf[0] = 0x14000;
22810 }
22811
22812 static void
22813 Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22814 {
22815   slotbuf[0] = 0x15000;
22816 }
22817
22818 static void
22819 Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22820 {
22821   slotbuf[0] = 0x14800;
22822 }
22823
22824 static void
22825 Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22826 {
22827   slotbuf[0] = 0x16a08;
22828 }
22829
22830 static void
22831 Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22832 {
22833   slotbuf[0] = 0x16a88;
22834 }
22835
22836 static void
22837 Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22838 {
22839   slotbuf[0] = 0x16988;
22840 }
22841
22842 static void
22843 Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22844 {
22845   slotbuf[0] = 0x18000;
22846 }
22847
22848 static void
22849 Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22850 {
22851   slotbuf[0] = 0x16c08;
22852 }
22853
22854 static void
22855 Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22856 {
22857   slotbuf[0] = 0x1f1000;
22858 }
22859
22860 static void
22861 Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22862 {
22863   slotbuf[0] = 0xc50004;
22864 }
22865
22866 static void
22867 Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22868 {
22869   slotbuf[0] = 0x1f1800;
22870 }
22871
22872 static void
22873 Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22874 {
22875   slotbuf[0] = 0xc50404;
22876 }
22877
22878 static void
22879 Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22880 {
22881   slotbuf[0] = 0x1f1400;
22882 }
22883
22884 static void
22885 Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22886 {
22887   slotbuf[0] = 0xc50804;
22888 }
22889
22890 static void
22891 Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22892 {
22893   slotbuf[0] = 0x1f2600;
22894 }
22895
22896 static void
22897 Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22898 {
22899   slotbuf[0] = 0xc90014;
22900 }
22901
22902 static void
22903 Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22904 {
22905   slotbuf[0] = 0x1f2504;
22906 }
22907
22908 static void
22909 Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22910 {
22911   slotbuf[0] = 0xc90114;
22912 }
22913
22914 static void
22915 Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22916 {
22917   slotbuf[0] = 0x1f2502;
22918 }
22919
22920 static void
22921 Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22922 {
22923   slotbuf[0] = 0xc90214;
22924 }
22925
22926 static void
22927 Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22928 {
22929   slotbuf[0] = 0x1f5001;
22930 }
22931
22932 static void
22933 Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22934 {
22935   slotbuf[0] = 0xe10014;
22936 }
22937
22938 static void
22939 Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22940 {
22941   slotbuf[0] = 0x1f5008;
22942 }
22943
22944 static void
22945 Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22946 {
22947   slotbuf[0] = 0xe20014;
22948 }
22949
22950 static void
22951 Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22952 {
22953   slotbuf[0] = 0x1f5004;
22954 }
22955
22956 static void
22957 Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22958 {
22959   slotbuf[0] = 0xe30014;
22960 }
22961
22962 static void
22963 Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22964 {
22965   slotbuf[0] = 0x1f2000;
22966 }
22967
22968 static void
22969 Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
22970 {
22971   slotbuf[0] = 0xc50c04;
22972 }
22973
22974 static void
22975 Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22976 {
22977   slotbuf[0] = 0x1f2501;
22978 }
22979
22980 static void
22981 Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
22982 {
22983   slotbuf[0] = 0xc90314;
22984 }
22985
22986 static void
22987 Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22988 {
22989   slotbuf[0] = 0x1f5002;
22990 }
22991
22992 static void
22993 Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
22994 {
22995   slotbuf[0] = 0xe40014;
22996 }
22997
22998 static void
22999 Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23000 {
23001   slotbuf[0] = 0x50800;
23002 }
23003
23004 static void
23005 Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23006 {
23007   slotbuf[0] = 0x50040;
23008 }
23009
23010 static void
23011 Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23012 {
23013   slotbuf[0] = 0x50020;
23014 }
23015
23016 static void
23017 Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
23018 {
23019   slotbuf[0] = 0x1f3085;
23020 }
23021
23022 static void
23023 Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
23024 {
23025   slotbuf[0] = 0xe74014;
23026 }
23027
23028 static void
23029 Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23030 {
23031   slotbuf[0] = 0x60101;
23032 }
23033
23034 static void
23035 Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23036 {
23037   slotbuf[0] = 0x6008b;
23038 }
23039
23040 static void
23041 Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23042 {
23043   slotbuf[0] = 0x60180;
23044 }
23045
23046 static void
23047 Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23048 {
23049   slotbuf[0] = 0x6008f;
23050 }
23051
23052 static void
23053 Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23054 {
23055   slotbuf[0] = 0x6008c;
23056 }
23057
23058 static void
23059 Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23060 {
23061   slotbuf[0] = 0x60108;
23062 }
23063
23064 static void
23065 Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23066 {
23067   slotbuf[0] = 0x6008e;
23068 }
23069
23070 static void
23071 Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23072 {
23073   slotbuf[0] = 0x6008a;
23074 }
23075
23076 static void
23077 Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23078 {
23079   slotbuf[0] = 0x60104;
23080 }
23081
23082 static void
23083 Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23084 {
23085   slotbuf[0] = 0x6008d;
23086 }
23087
23088 static void
23089 Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23090 {
23091   slotbuf[0] = 0x60089;
23092 }
23093
23094 static void
23095 Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23096 {
23097   slotbuf[0] = 0x60102;
23098 }
23099
23100 static void
23101 Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23102 {
23103   slotbuf[0] = 0x60006;
23104 }
23105
23106 static void
23107 Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23108 {
23109   slotbuf[0] = 0x64000;
23110 }
23111
23112 static void
23113 Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23114 {
23115   slotbuf[0] = 0x6000f;
23116 }
23117
23118 static void
23119 Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23120 {
23121   slotbuf[0] = 0x60005;
23122 }
23123
23124 static void
23125 Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23126 {
23127   slotbuf[0] = 0x60100;
23128 }
23129
23130 static void
23131 Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23132 {
23133   slotbuf[0] = 0x6000e;
23134 }
23135
23136 static void
23137 Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23138 {
23139   slotbuf[0] = 0x60003;
23140 }
23141
23142 static void
23143 Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23144 {
23145   slotbuf[0] = 0x60080;
23146 }
23147
23148 static void
23149 Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23150 {
23151   slotbuf[0] = 0x6000d;
23152 }
23153
23154 static void
23155 Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23156 {
23157   slotbuf[0] = 0x68000;
23158 }
23159
23160 static void
23161 Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23162 {
23163   slotbuf[0] = 0x60008;
23164 }
23165
23166 static void
23167 Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23168 {
23169   slotbuf[0] = 0x6000b;
23170 }
23171
23172 static void
23173 Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23174 {
23175   slotbuf[0] = 0x60181;
23176 }
23177
23178 static void
23179 Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23180 {
23181   slotbuf[0] = 0x6010b;
23182 }
23183
23184 static void
23185 Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23186 {
23187   slotbuf[0] = 0x60189;
23188 }
23189
23190 static void
23191 Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23192 {
23193   slotbuf[0] = 0x6010f;
23194 }
23195
23196 static void
23197 Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23198 {
23199   slotbuf[0] = 0x6010c;
23200 }
23201
23202 static void
23203 Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23204 {
23205   slotbuf[0] = 0x60187;
23206 }
23207
23208 static void
23209 Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23210 {
23211   slotbuf[0] = 0x6010e;
23212 }
23213
23214 static void
23215 Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23216 {
23217   slotbuf[0] = 0x6010a;
23218 }
23219
23220 static void
23221 Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23222 {
23223   slotbuf[0] = 0x60186;
23224 }
23225
23226 static void
23227 Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23228 {
23229   slotbuf[0] = 0x6010d;
23230 }
23231
23232 static void
23233 Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23234 {
23235   slotbuf[0] = 0x60109;
23236 }
23237
23238 static void
23239 Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23240 {
23241   slotbuf[0] = 0x60185;
23242 }
23243
23244 static void
23245 Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23246 {
23247   slotbuf[0] = 0x6000c;
23248 }
23249
23250 static void
23251 Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23252 {
23253   slotbuf[0] = 0x60088;
23254 }
23255
23256 static void
23257 Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23258 {
23259   slotbuf[0] = 0x6000a;
23260 }
23261
23262 static void
23263 Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23264 {
23265   slotbuf[0] = 0x60084;
23266 }
23267
23268 static void
23269 Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23270 {
23271   slotbuf[0] = 0x60009;
23272 }
23273
23274 static void
23275 Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23276 {
23277   slotbuf[0] = 0x60082;
23278 }
23279
23280 static void
23281 Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23282 {
23283   slotbuf[0] = 0x60007;
23284 }
23285
23286 static void
23287 Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23288 {
23289   slotbuf[0] = 0x60081;
23290 }
23291
23292 static void
23293 Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23294 {
23295   slotbuf[0] = 0x60183;
23296 }
23297
23298 static void
23299 Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23300 {
23301   slotbuf[0] = 0x6018d;
23302 }
23303
23304 static void
23305 Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23306 {
23307   slotbuf[0] = 0x60188;
23308 }
23309
23310 static void
23311 Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23312 {
23313   slotbuf[0] = 0x6018b;
23314 }
23315
23316 static void
23317 Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23318 {
23319   slotbuf[0] = 0x60184;
23320 }
23321
23322 static void
23323 Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23324 {
23325   slotbuf[0] = 0x6018c;
23326 }
23327
23328 static void
23329 Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23330 {
23331   slotbuf[0] = 0x60182;
23332 }
23333
23334 static void
23335 Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23336 {
23337   slotbuf[0] = 0x6018a;
23338 }
23339
23340 static void
23341 Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23342 {
23343   slotbuf[0] = 0x15807;
23344 }
23345
23346 static void
23347 Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23348 {
23349   slotbuf[0] = 0x15806;
23350 }
23351
23352 static void
23353 Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23354 {
23355   slotbuf[0] = 0x1580a;
23356 }
23357
23358 static void
23359 Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23360 {
23361   slotbuf[0] = 0x15809;
23362 }
23363
23364 static void
23365 Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23366 {
23367   slotbuf[0] = 0x1580b;
23368 }
23369
23370 static void
23371 Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23372 {
23373   slotbuf[0] = 0x1580c;
23374 }
23375
23376 static void
23377 Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23378 {
23379   slotbuf[0] = 0x1580e;
23380 }
23381
23382 static void
23383 Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23384 {
23385   slotbuf[0] = 0x1580d;
23386 }
23387
23388 static void
23389 Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23390 {
23391   slotbuf[0] = 0x15800;
23392 }
23393
23394 static void
23395 Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23396 {
23397   slotbuf[0] = 0x16000;
23398 }
23399
23400 static void
23401 Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23402 {
23403   slotbuf[0] = 0x15802;
23404 }
23405
23406 static void
23407 Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23408 {
23409   slotbuf[0] = 0x15801;
23410 }
23411
23412 static void
23413 Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23414 {
23415   slotbuf[0] = 0x15808;
23416 }
23417
23418 static void
23419 Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23420 {
23421   slotbuf[0] = 0x15804;
23422 }
23423
23424 static void
23425 Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23426 {
23427   slotbuf[0] = 0x15805;
23428 }
23429
23430 static void
23431 Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23432 {
23433   slotbuf[0] = 0x15803;
23434 }
23435
23436 static void
23437 Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23438 {
23439   slotbuf[0] = 0x16001;
23440 }
23441
23442 static void
23443 Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23444 {
23445   slotbuf[0] = 0x1580f;
23446 }
23447
23448 static void
23449 Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23450 {
23451   slotbuf[0] = 0x16004;
23452 }
23453
23454 static void
23455 Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23456 {
23457   slotbuf[0] = 0x16002;
23458 }
23459
23460 static void
23461 Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23462 {
23463   slotbuf[0] = 0x16800;
23464 }
23465
23466 static void
23467 Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23468 {
23469   slotbuf[0] = 0x16008;
23470 }
23471
23472 static void
23473 Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23474 {
23475   slotbuf[0] = 0x16003;
23476 }
23477
23478 static void
23479 Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23480 {
23481   slotbuf[0] = 0x17000;
23482 }
23483
23484 static void
23485 Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23486 {
23487   slotbuf[0] = 0x20007;
23488 }
23489
23490 static void
23491 Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23492 {
23493   slotbuf[0] = 0x20002;
23494 }
23495
23496 static void
23497 Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23498 {
23499   slotbuf[0] = 0x2000c;
23500 }
23501
23502 static void
23503 Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23504 {
23505   slotbuf[0] = 0x20003;
23506 }
23507
23508 static void
23509 Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23510 {
23511   slotbuf[0] = 0x20005;
23512 }
23513
23514 static void
23515 Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23516 {
23517   slotbuf[0] = 0x20000;
23518 }
23519
23520 static void
23521 Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23522 {
23523   slotbuf[0] = 0x20009;
23524 }
23525
23526 static void
23527 Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23528 {
23529   slotbuf[0] = 0x20004;
23530 }
23531
23532 static void
23533 Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23534 {
23535   slotbuf[0] = 0x20006;
23536 }
23537
23538 static void
23539 Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23540 {
23541   slotbuf[0] = 0x20001;
23542 }
23543
23544 static void
23545 Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23546 {
23547   slotbuf[0] = 0x2000a;
23548 }
23549
23550 static void
23551 Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23552 {
23553   slotbuf[0] = 0x20008;
23554 }
23555
23556 static void
23557 Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23558 {
23559   slotbuf[0] = 0x30008;
23560 }
23561
23562 static void
23563 Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23564 {
23565   slotbuf[0] = 0x2000e;
23566 }
23567
23568 static void
23569 Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23570 {
23571   slotbuf[0] = 0x30006;
23572 }
23573
23574 static void
23575 Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23576 {
23577   slotbuf[0] = 0x30001;
23578 }
23579
23580 static void
23581 Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23582 {
23583   slotbuf[0] = 0x30002;
23584 }
23585
23586 static void
23587 Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23588 {
23589   slotbuf[0] = 0x2000b;
23590 }
23591
23592 static void
23593 Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23594 {
23595   slotbuf[0] = 0x30003;
23596 }
23597
23598 static void
23599 Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23600 {
23601   slotbuf[0] = 0x2000f;
23602 }
23603
23604 static void
23605 Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23606 {
23607   slotbuf[0] = 0x30004;
23608 }
23609
23610 static void
23611 Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23612 {
23613   slotbuf[0] = 0x2000d;
23614 }
23615
23616 static void
23617 Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23618 {
23619   slotbuf[0] = 0x30005;
23620 }
23621
23622 static void
23623 Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23624 {
23625   slotbuf[0] = 0x30000;
23626 }
23627
23628 static void
23629 Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23630 {
23631   slotbuf[0] = 0x40000;
23632 }
23633
23634 static void
23635 Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23636 {
23637   slotbuf[0] = 0x3000a;
23638 }
23639
23640 static void
23641 Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23642 {
23643   slotbuf[0] = 0x40004;
23644 }
23645
23646 static void
23647 Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23648 {
23649   slotbuf[0] = 0x3000d;
23650 }
23651
23652 static void
23653 Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23654 {
23655   slotbuf[0] = 0x3000e;
23656 }
23657
23658 static void
23659 Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23660 {
23661   slotbuf[0] = 0x30007;
23662 }
23663
23664 static void
23665 Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23666 {
23667   slotbuf[0] = 0x40001;
23668 }
23669
23670 static void
23671 Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23672 {
23673   slotbuf[0] = 0x3000c;
23674 }
23675
23676 static void
23677 Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23678 {
23679   slotbuf[0] = 0x3000f;
23680 }
23681
23682 static void
23683 Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23684 {
23685   slotbuf[0] = 0x30009;
23686 }
23687
23688 static void
23689 Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23690 {
23691   slotbuf[0] = 0x40002;
23692 }
23693
23694 static void
23695 Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23696 {
23697   slotbuf[0] = 0x3000b;
23698 }
23699
23700 static void
23701 Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23702 {
23703   slotbuf[0] = 0x4000b;
23704 }
23705
23706 static void
23707 Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23708 {
23709   slotbuf[0] = 0x40005;
23710 }
23711
23712 static void
23713 Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23714 {
23715   slotbuf[0] = 0x4000f;
23716 }
23717
23718 static void
23719 Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23720 {
23721   slotbuf[0] = 0x40009;
23722 }
23723
23724 static void
23725 Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23726 {
23727   slotbuf[0] = 0x4000a;
23728 }
23729
23730 static void
23731 Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23732 {
23733   slotbuf[0] = 0x40008;
23734 }
23735
23736 static void
23737 Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23738 {
23739   slotbuf[0] = 0x4000d;
23740 }
23741
23742 static void
23743 Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23744 {
23745   slotbuf[0] = 0x40006;
23746 }
23747
23748 static void
23749 Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23750 {
23751   slotbuf[0] = 0x4000c;
23752 }
23753
23754 static void
23755 Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23756 {
23757   slotbuf[0] = 0x40003;
23758 }
23759
23760 static void
23761 Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23762 {
23763   slotbuf[0] = 0x4000e;
23764 }
23765
23766 static void
23767 Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23768 {
23769   slotbuf[0] = 0x40007;
23770 }
23771
23772 static void
23773 Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23774 {
23775   slotbuf[0] = 0x64004;
23776 }
23777
23778 static void
23779 Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23780 {
23781   slotbuf[0] = 0x64080;
23782 }
23783
23784 static void
23785 Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23786 {
23787   slotbuf[0] = 0x64008;
23788 }
23789
23790 static void
23791 Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23792 {
23793   slotbuf[0] = 0x64100;
23794 }
23795
23796 static void
23797 Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23798 {
23799   slotbuf[0] = 0x64003;
23800 }
23801
23802 static void
23803 Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23804 {
23805   slotbuf[0] = 0x64006;
23806 }
23807
23808 static void
23809 Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23810 {
23811   slotbuf[0] = 0x64005;
23812 }
23813
23814 static void
23815 Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23816 {
23817   slotbuf[0] = 0x64007;
23818 }
23819
23820 static void
23821 Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23822 {
23823   slotbuf[0] = 0x64009;
23824 }
23825
23826 static void
23827 Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23828 {
23829   slotbuf[0] = 0x6400c;
23830 }
23831
23832 static void
23833 Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23834 {
23835   slotbuf[0] = 0x6400a;
23836 }
23837
23838 static void
23839 Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23840 {
23841   slotbuf[0] = 0x6400b;
23842 }
23843
23844 static void
23845 Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23846 {
23847   slotbuf[0] = 0x6400d;
23848 }
23849
23850 static void
23851 Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23852 {
23853   slotbuf[0] = 0x6400f;
23854 }
23855
23856 static void
23857 Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23858 {
23859   slotbuf[0] = 0x6400e;
23860 }
23861
23862 static void
23863 Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23864 {
23865   slotbuf[0] = 0x64081;
23866 }
23867
23868 static void
23869 Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23870 {
23871   slotbuf[0] = 0x60000;
23872 }
23873
23874 static void
23875 Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23876 {
23877   slotbuf[0] = 0x60002;
23878 }
23879
23880 static void
23881 Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23882 {
23883   slotbuf[0] = 0x60001;
23884 }
23885
23886 static void
23887 Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23888 {
23889   slotbuf[0] = 0x60004;
23890 }
23891
23892 static void
23893 Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23894 {
23895   slotbuf[0] = 0x60083;
23896 }
23897
23898 static void
23899 Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23900 {
23901   slotbuf[0] = 0x60086;
23902 }
23903
23904 static void
23905 Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23906 {
23907   slotbuf[0] = 0x60085;
23908 }
23909
23910 static void
23911 Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23912 {
23913   slotbuf[0] = 0x60087;
23914 }
23915
23916 static void
23917 Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23918 {
23919   slotbuf[0] = 0x60103;
23920 }
23921
23922 static void
23923 Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23924 {
23925   slotbuf[0] = 0x60106;
23926 }
23927
23928 static void
23929 Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23930 {
23931   slotbuf[0] = 0x60105;
23932 }
23933
23934 static void
23935 Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23936 {
23937   slotbuf[0] = 0x60107;
23938 }
23939
23940 static void
23941 Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23942 {
23943   slotbuf[0] = 0x6018e;
23944 }
23945
23946 static void
23947 Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23948 {
23949   slotbuf[0] = 0x64001;
23950 }
23951
23952 static void
23953 Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23954 {
23955   slotbuf[0] = 0x6018f;
23956 }
23957
23958 static void
23959 Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23960 {
23961   slotbuf[0] = 0x64002;
23962 }
23963
23964 static void
23965 Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf)
23966 {
23967   slotbuf[0] = 0xe00014;
23968 }
23969
23970 static void
23971 Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
23972 {
23973   slotbuf[0] = 0xa00004;
23974 }
23975
23976 static void
23977 Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
23978 {
23979   slotbuf[0] = 0xa10004;
23980 }
23981
23982 static void
23983 Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
23984 {
23985   slotbuf[0] = 0xe7e014;
23986 }
23987
23988 static void
23989 Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf)
23990 {
23991   slotbuf[0] = 0xca8004;
23992 }
23993
23994 static void
23995 Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23996 {
23997   slotbuf[0] = 0xc60004;
23998 }
23999
24000 static void
24001 Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
24002 {
24003   slotbuf[0] = 0xe00024;
24004 }
24005
24006 static void
24007 Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf)
24008 {
24009   slotbuf[0] = 0xa20004;
24010 }
24011
24012 static void
24013 Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf)
24014 {
24015   slotbuf[0] = 0xe00004;
24016 }
24017
24018 static void
24019 Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf)
24020 {
24021   slotbuf[0] = 0xf01004;
24022 }
24023
24024 static void
24025 Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
24026 {
24027   slotbuf[0] = 0xf02004;
24028 }
24029
24030 static void
24031 Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
24032 {
24033   slotbuf[0] = 0xa30004;
24034 }
24035
24036 static void
24037 Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
24038 {
24039   slotbuf[0] = 0xa40004;
24040 }
24041
24042 static void
24043 Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf)
24044 {
24045   slotbuf[0] = 0xf11004;
24046 }
24047
24048 static void
24049 Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
24050 {
24051   slotbuf[0] = 0xf00004;
24052 }
24053
24054 static void
24055 Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
24056 {
24057   slotbuf[0] = 0xe7c014;
24058 }
24059
24060 static void
24061 Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf)
24062 {
24063   slotbuf[0] = 0xe7d014;
24064 }
24065
24066 static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
24067   Opcode_excw_Slot_inst_encode, 0, 0, 0, 0
24068 };
24069
24070 static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
24071   Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0
24072 };
24073
24074 static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
24075   Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0
24076 };
24077
24078 static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
24079   Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0
24080 };
24081
24082 static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
24083   Opcode_call12_Slot_inst_encode, 0, 0, 0, 0
24084 };
24085
24086 static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
24087   Opcode_call8_Slot_inst_encode, 0, 0, 0, 0
24088 };
24089
24090 static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
24091   Opcode_call4_Slot_inst_encode, 0, 0, 0, 0
24092 };
24093
24094 static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
24095   Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0
24096 };
24097
24098 static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
24099   Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0
24100 };
24101
24102 static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
24103   Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0
24104 };
24105
24106 static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
24107   Opcode_entry_Slot_inst_encode, 0, 0, 0, 0
24108 };
24109
24110 static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
24111   Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0
24112 };
24113
24114 static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
24115   Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0
24116 };
24117
24118 static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
24119   Opcode_retw_Slot_inst_encode, 0, 0, 0, 0
24120 };
24121
24122 static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
24123   0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0
24124 };
24125
24126 static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
24127   Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0
24128 };
24129
24130 static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
24131   Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0
24132 };
24133
24134 static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
24135   Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0
24136 };
24137
24138 static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
24139   Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0
24140 };
24141
24142 static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
24143   Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
24144 };
24145
24146 static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
24147   Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
24148 };
24149
24150 static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
24151   Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
24152 };
24153
24154 static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
24155   Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
24156 };
24157
24158 static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
24159   Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
24160 };
24161
24162 static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
24163   Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
24164 };
24165
24166 static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
24167   0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0
24168 };
24169
24170 static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
24171   0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0
24172 };
24173
24174 static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
24175   0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0
24176 };
24177
24178 static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
24179   0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0
24180 };
24181
24182 static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
24183   0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0
24184 };
24185
24186 static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
24187   0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0
24188 };
24189
24190 static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
24191   0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0
24192 };
24193
24194 static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
24195   0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0
24196 };
24197
24198 static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
24199   0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0
24200 };
24201
24202 static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
24203   0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0
24204 };
24205
24206 static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
24207   0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0
24208 };
24209
24210 static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
24211   Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0
24212 };
24213
24214 static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
24215   Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0
24216 };
24217
24218 static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
24219   Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode
24220 };
24221
24222 static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
24223   Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode
24224 };
24225
24226 static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
24227   Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode
24228 };
24229
24230 static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
24231   Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode
24232 };
24233
24234 static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
24235   Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode
24236 };
24237
24238 static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
24239   Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode
24240 };
24241
24242 static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
24243   Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode
24244 };
24245
24246 static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
24247   Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode
24248 };
24249
24250 static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
24251   Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode
24252 };
24253
24254 static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
24255   Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode
24256 };
24257
24258 static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
24259   Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode
24260 };
24261
24262 static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
24263   Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode
24264 };
24265
24266 static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
24267   Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode
24268 };
24269
24270 static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
24271   Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode
24272 };
24273
24274 static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
24275   Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode
24276 };
24277
24278 static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
24279   Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode
24280 };
24281
24282 static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
24283   Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode
24284 };
24285
24286 static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
24287   Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode
24288 };
24289
24290 static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
24291   Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode
24292 };
24293
24294 static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
24295   Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode
24296 };
24297
24298 static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
24299   Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode
24300 };
24301
24302 static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
24303   Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode
24304 };
24305
24306 static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
24307   Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode
24308 };
24309
24310 static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
24311   Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode
24312 };
24313
24314 static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
24315   Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode
24316 };
24317
24318 static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
24319   Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode
24320 };
24321
24322 static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
24323   Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode
24324 };
24325
24326 static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
24327   Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode
24328 };
24329
24330 static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
24331   Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode
24332 };
24333
24334 static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
24335   Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode
24336 };
24337
24338 static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
24339   Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode
24340 };
24341
24342 static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
24343   Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode
24344 };
24345
24346 static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
24347   Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode
24348 };
24349
24350 static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
24351   Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode
24352 };
24353
24354 static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
24355   Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode
24356 };
24357
24358 static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
24359   Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode
24360 };
24361
24362 static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
24363   Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode
24364 };
24365
24366 static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
24367   Opcode_call0_Slot_inst_encode, 0, 0, 0, 0
24368 };
24369
24370 static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
24371   Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0
24372 };
24373
24374 static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
24375   Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode
24376 };
24377
24378 static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
24379   Opcode_ill_Slot_inst_encode, 0, 0, 0, 0
24380 };
24381
24382 static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
24383   Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode
24384 };
24385
24386 static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
24387   Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode
24388 };
24389
24390 static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
24391   Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode
24392 };
24393
24394 static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
24395   Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode
24396 };
24397
24398 static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
24399   Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode
24400 };
24401
24402 static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
24403   Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode
24404 };
24405
24406 static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
24407   Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode
24408 };
24409
24410 static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
24411   Opcode_loop_Slot_inst_encode, 0, 0, 0, 0
24412 };
24413
24414 static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
24415   Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0
24416 };
24417
24418 static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
24419   Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0
24420 };
24421
24422 static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
24423   Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode
24424 };
24425
24426 static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
24427   Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode
24428 };
24429
24430 static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
24431   Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode
24432 };
24433
24434 static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
24435   Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode
24436 };
24437
24438 static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
24439   Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode
24440 };
24441
24442 static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
24443   Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode
24444 };
24445
24446 static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
24447   Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode
24448 };
24449
24450 static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
24451   Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode
24452 };
24453
24454 static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
24455   Opcode_ret_Slot_inst_encode, 0, 0, 0, 0
24456 };
24457
24458 static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
24459   Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0
24460 };
24461
24462 static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
24463   Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode
24464 };
24465
24466 static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
24467   Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode
24468 };
24469
24470 static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
24471   Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode
24472 };
24473
24474 static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
24475   Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode
24476 };
24477
24478 static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
24479   Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode
24480 };
24481
24482 static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
24483   Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode
24484 };
24485
24486 static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
24487   Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode
24488 };
24489
24490 static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
24491   Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode
24492 };
24493
24494 static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
24495   Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode
24496 };
24497
24498 static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
24499   Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode
24500 };
24501
24502 static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
24503   Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode
24504 };
24505
24506 static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
24507   Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode
24508 };
24509
24510 static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
24511   Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode
24512 };
24513
24514 static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
24515   Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode
24516 };
24517
24518 static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
24519   Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode
24520 };
24521
24522 static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
24523   Opcode_memw_Slot_inst_encode, 0, 0, 0, 0
24524 };
24525
24526 static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
24527   Opcode_extw_Slot_inst_encode, 0, 0, 0, 0
24528 };
24529
24530 static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
24531   Opcode_isync_Slot_inst_encode, 0, 0, 0, 0
24532 };
24533
24534 static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
24535   Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0
24536 };
24537
24538 static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
24539   Opcode_esync_Slot_inst_encode, 0, 0, 0, 0
24540 };
24541
24542 static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
24543   Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0
24544 };
24545
24546 static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
24547   Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0
24548 };
24549
24550 static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
24551   Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0
24552 };
24553
24554 static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
24555   Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0
24556 };
24557
24558 static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
24559   Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0
24560 };
24561
24562 static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
24563   Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0
24564 };
24565
24566 static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
24567   Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0
24568 };
24569
24570 static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
24571   Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0
24572 };
24573
24574 static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
24575   Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
24576 };
24577
24578 static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
24579   Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
24580 };
24581
24582 static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
24583   Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
24584 };
24585
24586 static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
24587   Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0
24588 };
24589
24590 static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
24591   Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0
24592 };
24593
24594 static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
24595   Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0
24596 };
24597
24598 static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
24599   Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0
24600 };
24601
24602 static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
24603   Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0
24604 };
24605
24606 static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
24607   Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0
24608 };
24609
24610 static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
24611   Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0
24612 };
24613
24614 static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
24615   Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0
24616 };
24617
24618 static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
24619   Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0
24620 };
24621
24622 static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
24623   Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0
24624 };
24625
24626 static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
24627   Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0
24628 };
24629
24630 static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
24631   Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0
24632 };
24633
24634 static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
24635   Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0
24636 };
24637
24638 static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
24639   Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0
24640 };
24641
24642 static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
24643   Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0
24644 };
24645
24646 static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
24647   Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
24648 };
24649
24650 static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
24651   Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
24652 };
24653
24654 static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
24655   Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
24656 };
24657
24658 static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
24659   Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0
24660 };
24661
24662 static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
24663   Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0
24664 };
24665
24666 static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
24667   Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0
24668 };
24669
24670 static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
24671   Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
24672 };
24673
24674 static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
24675   Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
24676 };
24677
24678 static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
24679   Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
24680 };
24681
24682 static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
24683   Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0
24684 };
24685
24686 static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
24687   Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0
24688 };
24689
24690 static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
24691   Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0
24692 };
24693
24694 static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
24695   Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
24696 };
24697
24698 static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
24699   Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
24700 };
24701
24702 static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
24703   Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
24704 };
24705
24706 static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
24707   Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0
24708 };
24709
24710 static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
24711   Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0
24712 };
24713
24714 static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
24715   Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0
24716 };
24717
24718 static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
24719   Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0
24720 };
24721
24722 static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
24723   Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0
24724 };
24725
24726 static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
24727   Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0
24728 };
24729
24730 static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
24731   Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0
24732 };
24733
24734 static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
24735   Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0
24736 };
24737
24738 static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
24739   Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0
24740 };
24741
24742 static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
24743   Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0
24744 };
24745
24746 static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
24747   Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0
24748 };
24749
24750 static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
24751   Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0
24752 };
24753
24754 static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
24755   Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0
24756 };
24757
24758 static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
24759   Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
24760 };
24761
24762 static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
24763   Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
24764 };
24765
24766 static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
24767   Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
24768 };
24769
24770 static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
24771   Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0
24772 };
24773
24774 static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
24775   Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0
24776 };
24777
24778 static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
24779   Opcode_mull_Slot_inst_encode, 0, 0, 0, 0
24780 };
24781
24782 static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
24783   Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0
24784 };
24785
24786 static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
24787   Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0
24788 };
24789
24790 static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
24791   Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0
24792 };
24793
24794 static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
24795   Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0
24796 };
24797
24798 static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
24799   Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0
24800 };
24801
24802 static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
24803   Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0
24804 };
24805
24806 static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
24807   Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0
24808 };
24809
24810 static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
24811   Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0
24812 };
24813
24814 static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
24815   Opcode_break_Slot_inst_encode, 0, 0, 0, 0
24816 };
24817
24818 static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
24819   0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0
24820 };
24821
24822 static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
24823   Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
24824 };
24825
24826 static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
24827   Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
24828 };
24829
24830 static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
24831   Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
24832 };
24833
24834 static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
24835   Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0
24836 };
24837
24838 static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
24839   Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0
24840 };
24841
24842 static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
24843   Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0
24844 };
24845
24846 static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
24847   Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
24848 };
24849
24850 static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
24851   Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
24852 };
24853
24854 static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
24855   Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
24856 };
24857
24858 static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
24859   Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0
24860 };
24861
24862 static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
24863   Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0
24864 };
24865
24866 static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
24867   Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0
24868 };
24869
24870 static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
24871   Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0
24872 };
24873
24874 static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
24875   Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0
24876 };
24877
24878 static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
24879   Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode
24880 };
24881
24882 static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
24883   Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode
24884 };
24885
24886 static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
24887   Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode
24888 };
24889
24890 static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
24891   Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode
24892 };
24893
24894 static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
24895   Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode
24896 };
24897
24898 static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
24899   Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode
24900 };
24901
24902 static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
24903   Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode
24904 };
24905
24906 static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
24907   Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode
24908 };
24909
24910 static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
24911   Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode
24912 };
24913
24914 static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
24915   Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode
24916 };
24917
24918 static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
24919   Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode
24920 };
24921
24922 static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
24923   Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode
24924 };
24925
24926 static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
24927   Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode
24928 };
24929
24930 static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
24931   Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0
24932 };
24933
24934 static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
24935   Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0
24936 };
24937
24938 static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
24939   Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0
24940 };
24941
24942 static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
24943   Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0
24944 };
24945
24946 static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
24947   Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0
24948 };
24949
24950 static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
24951   Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0
24952 };
24953
24954 static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
24955   Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
24956 };
24957
24958 static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
24959   Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
24960 };
24961
24962 static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
24963   Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
24964 };
24965
24966 static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
24967   Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
24968 };
24969
24970 static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
24971   Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
24972 };
24973
24974 static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
24975   Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
24976 };
24977
24978 static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
24979   Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0
24980 };
24981
24982 static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
24983   Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0
24984 };
24985
24986 static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
24987   Opcode_iii_Slot_inst_encode, 0, 0, 0, 0
24988 };
24989
24990 static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
24991   Opcode_lict_Slot_inst_encode, 0, 0, 0, 0
24992 };
24993
24994 static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
24995   Opcode_licw_Slot_inst_encode, 0, 0, 0, 0
24996 };
24997
24998 static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
24999   Opcode_sict_Slot_inst_encode, 0, 0, 0, 0
25000 };
25001
25002 static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
25003   Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0
25004 };
25005
25006 static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
25007   Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0
25008 };
25009
25010 static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
25011   Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0
25012 };
25013
25014 static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
25015   Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0
25016 };
25017
25018 static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
25019   Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0
25020 };
25021
25022 static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
25023   Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0
25024 };
25025
25026 static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
25027   Opcode_dii_Slot_inst_encode, 0, 0, 0, 0
25028 };
25029
25030 static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
25031   Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0
25032 };
25033
25034 static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
25035   Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0
25036 };
25037
25038 static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
25039   Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0
25040 };
25041
25042 static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
25043   Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0
25044 };
25045
25046 static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
25047   Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0
25048 };
25049
25050 static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
25051   Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0
25052 };
25053
25054 static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
25055   Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
25056 };
25057
25058 static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
25059   Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
25060 };
25061
25062 static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
25063   Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
25064 };
25065
25066 static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
25067   Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0
25068 };
25069
25070 static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
25071   Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0
25072 };
25073
25074 static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
25075   Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0
25076 };
25077
25078 static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
25079   Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
25080 };
25081
25082 static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
25083   Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
25084 };
25085
25086 static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
25087   Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
25088 };
25089
25090 static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
25091   Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
25092 };
25093
25094 static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
25095   Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
25096 };
25097
25098 static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
25099   Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
25100 };
25101
25102 static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
25103   Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0
25104 };
25105
25106 static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
25107   Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0
25108 };
25109
25110 static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
25111   Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0
25112 };
25113
25114 static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
25115   Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0
25116 };
25117
25118 static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
25119   Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0
25120 };
25121
25122 static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
25123   Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0
25124 };
25125
25126 static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
25127   Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0
25128 };
25129
25130 static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
25131   Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0
25132 };
25133
25134 static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
25135   Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0
25136 };
25137
25138 static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
25139   Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0
25140 };
25141
25142 static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
25143   Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0
25144 };
25145
25146 static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
25147   Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0
25148 };
25149
25150 static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
25151   Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0
25152 };
25153
25154 static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
25155   Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
25156 };
25157
25158 static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
25159   Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
25160 };
25161
25162 static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
25163   Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
25164 };
25165
25166 static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
25167   Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode
25168 };
25169
25170 static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
25171   Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode
25172 };
25173
25174 static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
25175   Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode
25176 };
25177
25178 static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
25179   Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode
25180 };
25181
25182 static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
25183   Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode
25184 };
25185
25186 static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
25187   Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0
25188 };
25189
25190 static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
25191   Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0
25192 };
25193
25194 static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
25195   Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode
25196 };
25197
25198 static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
25199   Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0
25200 };
25201
25202 static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
25203   Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0
25204 };
25205
25206 static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
25207   Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0
25208 };
25209
25210 static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
25211   Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
25212 };
25213
25214 static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
25215   Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
25216 };
25217
25218 static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
25219   Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
25220 };
25221
25222 static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
25223   Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
25224 };
25225
25226 static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
25227   Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
25228 };
25229
25230 static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
25231   Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
25232 };
25233
25234 static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
25235   Opcode_rer_Slot_inst_encode, 0, 0, 0, 0
25236 };
25237
25238 static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
25239   Opcode_wer_Slot_inst_encode, 0, 0, 0, 0
25240 };
25241
25242 static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = {
25243   Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
25244 };
25245
25246 static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = {
25247   Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
25248 };
25249
25250 static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = {
25251   Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
25252 };
25253
25254 static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = {
25255   Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
25256 };
25257
25258 static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = {
25259   Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
25260 };
25261
25262 static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = {
25263   Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
25264 };
25265
25266 static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = {
25267   Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
25268 };
25269
25270 static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = {
25271   Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
25272 };
25273
25274 static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = {
25275   Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
25276 };
25277
25278 static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = {
25279   Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
25280 };
25281
25282 static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = {
25283   Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
25284 };
25285
25286 static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = {
25287   Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
25288 };
25289
25290 static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = {
25291   Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
25292 };
25293
25294 static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = {
25295   Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
25296 };
25297
25298 static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = {
25299   Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
25300 };
25301
25302 static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = {
25303   Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
25304 };
25305
25306 static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = {
25307   Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
25308 };
25309
25310 static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = {
25311   Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
25312 };
25313
25314 static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = {
25315   Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
25316 };
25317
25318 static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = {
25319   Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
25320 };
25321
25322 static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = {
25323   Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
25324 };
25325
25326 static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = {
25327   Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
25328 };
25329
25330 static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = {
25331   Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
25332 };
25333
25334 static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = {
25335   Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
25336 };
25337
25338 static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = {
25339   Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode
25340 };
25341
25342 static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = {
25343   Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode
25344 };
25345
25346 static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = {
25347   Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode
25348 };
25349
25350 static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = {
25351   Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode
25352 };
25353
25354 static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = {
25355   Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode
25356 };
25357
25358 static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = {
25359   Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode
25360 };
25361
25362 static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = {
25363   Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode
25364 };
25365
25366 static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = {
25367   Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode
25368 };
25369
25370 static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = {
25371   Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode
25372 };
25373
25374 static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = {
25375   Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode
25376 };
25377
25378 static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = {
25379   Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode
25380 };
25381
25382 static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = {
25383   Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode
25384 };
25385
25386 static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = {
25387   Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode
25388 };
25389
25390 static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = {
25391   Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode
25392 };
25393
25394 static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = {
25395   Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode
25396 };
25397
25398 static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = {
25399   Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode
25400 };
25401
25402 static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = {
25403   Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode
25404 };
25405
25406 static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = {
25407   Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode
25408 };
25409
25410 static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = {
25411   Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode
25412 };
25413
25414 static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = {
25415   Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode
25416 };
25417
25418 static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = {
25419   Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode
25420 };
25421
25422 static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = {
25423   Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode
25424 };
25425
25426 static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = {
25427   Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode
25428 };
25429
25430 static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = {
25431   Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode
25432 };
25433
25434 static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = {
25435   Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode
25436 };
25437
25438 static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = {
25439   Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode
25440 };
25441
25442 static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = {
25443   Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode
25444 };
25445
25446 static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = {
25447   Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode
25448 };
25449
25450 static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = {
25451   Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode
25452 };
25453
25454 static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = {
25455   Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode
25456 };
25457
25458 static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = {
25459   Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode
25460 };
25461
25462 static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = {
25463   Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode
25464 };
25465
25466 static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = {
25467   Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode
25468 };
25469
25470 static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = {
25471   Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode
25472 };
25473
25474 static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = {
25475   Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode
25476 };
25477
25478 static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = {
25479   Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode
25480 };
25481
25482 static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = {
25483   Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode
25484 };
25485
25486 static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = {
25487   Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode
25488 };
25489
25490 static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = {
25491   Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode
25492 };
25493
25494 static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = {
25495   Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode
25496 };
25497
25498 static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = {
25499   Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode
25500 };
25501
25502 static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = {
25503   Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode
25504 };
25505
25506 static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = {
25507   Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode
25508 };
25509
25510 static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = {
25511   Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode
25512 };
25513
25514 static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = {
25515   Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode
25516 };
25517
25518 static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = {
25519   Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode
25520 };
25521
25522 static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = {
25523   Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode
25524 };
25525
25526 static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = {
25527   Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode
25528 };
25529
25530 static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = {
25531   Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode
25532 };
25533
25534 static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = {
25535   Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode
25536 };
25537
25538 static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = {
25539   Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode
25540 };
25541
25542 static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = {
25543   Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode
25544 };
25545
25546 static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = {
25547   Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode
25548 };
25549
25550 static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = {
25551   Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode
25552 };
25553
25554 static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = {
25555   Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode
25556 };
25557
25558 static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = {
25559   Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode
25560 };
25561
25562 static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = {
25563   Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode
25564 };
25565
25566 static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = {
25567   Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode
25568 };
25569
25570 static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = {
25571   Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode
25572 };
25573
25574 static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = {
25575   Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode
25576 };
25577
25578 static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = {
25579   Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode
25580 };
25581
25582 static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = {
25583   Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode
25584 };
25585
25586 static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = {
25587   Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode
25588 };
25589
25590 static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = {
25591   Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode
25592 };
25593
25594 static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = {
25595   0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0
25596 };
25597
25598 static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = {
25599   Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode
25600 };
25601
25602 static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = {
25603   0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, 0
25604 };
25605
25606 static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = {
25607   0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, 0
25608 };
25609
25610 static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = {
25611   0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, 0
25612 };
25613
25614 static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = {
25615   0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, 0
25616 };
25617
25618 static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = {
25619   0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0
25620 };
25621
25622 static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = {
25623   0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0
25624 };
25625
25626 static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = {
25627   0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0
25628 };
25629
25630 static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = {
25631   0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0
25632 };
25633
25634 static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = {
25635   Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode
25636 };
25637
25638 static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = {
25639   Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode
25640 };
25641
25642 static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = {
25643   Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode
25644 };
25645
25646 static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = {
25647   Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode
25648 };
25649
25650 static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = {
25651   Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode
25652 };
25653
25654 static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = {
25655   Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode
25656 };
25657
25658 static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = {
25659   Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode
25660 };
25661
25662 static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = {
25663   Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode
25664 };
25665
25666 static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = {
25667   0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0
25668 };
25669
25670 static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = {
25671   0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0
25672 };
25673
25674 static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = {
25675   0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0
25676 };
25677
25678 static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = {
25679   0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0
25680 };
25681
25682 static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = {
25683   0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0
25684 };
25685
25686 static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = {
25687   0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0
25688 };
25689
25690 static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = {
25691   0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0
25692 };
25693
25694 static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = {
25695   0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0
25696 };
25697
25698 static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = {
25699   0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0
25700 };
25701
25702 static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = {
25703   Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode
25704 };
25705
25706 static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = {
25707   Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode
25708 };
25709
25710 static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = {
25711   Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode
25712 };
25713
25714 static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = {
25715   Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode
25716 };
25717
25718 static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = {
25719   0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0
25720 };
25721
25722 static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = {
25723   0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0
25724 };
25725
25726 static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = {
25727   0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0
25728 };
25729
25730 static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = {
25731   0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0
25732 };
25733
25734 static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = {
25735   0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0
25736 };
25737
25738 static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = {
25739   0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0
25740 };
25741
25742 static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = {
25743   Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode
25744 };
25745
25746 static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = {
25747   Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode
25748 };
25749
25750 static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = {
25751   Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode
25752 };
25753
25754 static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = {
25755   Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode
25756 };
25757
25758 static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = {
25759   Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode
25760 };
25761
25762 static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = {
25763   0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0
25764 };
25765
25766 static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = {
25767   0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0
25768 };
25769
25770 static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = {
25771   0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0
25772 };
25773
25774 static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = {
25775   0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0
25776 };
25777
25778 static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = {
25779   0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0
25780 };
25781
25782 static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = {
25783   0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0
25784 };
25785
25786 static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = {
25787   0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0
25788 };
25789
25790 static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = {
25791   0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0
25792 };
25793
25794 static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = {
25795   0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0
25796 };
25797
25798 static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = {
25799   0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0
25800 };
25801
25802 static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = {
25803   0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0
25804 };
25805
25806 static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = {
25807   0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0
25808 };
25809
25810 static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = {
25811   0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0
25812 };
25813
25814 static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = {
25815   0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0
25816 };
25817
25818 static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = {
25819   0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0
25820 };
25821
25822 static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = {
25823   0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0
25824 };
25825
25826 static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = {
25827   0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0
25828 };
25829
25830 static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = {
25831   0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0
25832 };
25833
25834 static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = {
25835   0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0
25836 };
25837
25838 static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = {
25839   0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0
25840 };
25841
25842 static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = {
25843   0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0
25844 };
25845
25846 static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = {
25847   0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0
25848 };
25849
25850 static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = {
25851   0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0
25852 };
25853
25854 static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = {
25855   0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0
25856 };
25857
25858 static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = {
25859   0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0
25860 };
25861
25862 static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = {
25863   0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0
25864 };
25865
25866 static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = {
25867   0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0
25868 };
25869
25870 static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = {
25871   0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0
25872 };
25873
25874 static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = {
25875   0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0
25876 };
25877
25878 static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = {
25879   0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0
25880 };
25881
25882 static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = {
25883   0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0
25884 };
25885
25886 static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = {
25887   0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0
25888 };
25889
25890 static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = {
25891   0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0
25892 };
25893
25894 static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = {
25895   0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0
25896 };
25897
25898 static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = {
25899   0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0
25900 };
25901
25902 static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = {
25903   0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0
25904 };
25905
25906 static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = {
25907   0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0
25908 };
25909
25910 static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = {
25911   0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0
25912 };
25913
25914 static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = {
25915   0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0
25916 };
25917
25918 static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = {
25919   0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0
25920 };
25921
25922 static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = {
25923   0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0
25924 };
25925
25926 static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = {
25927   0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0
25928 };
25929
25930 static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = {
25931   0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0
25932 };
25933
25934 static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = {
25935   Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode
25936 };
25937
25938 static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = {
25939   Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode
25940 };
25941
25942 static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = {
25943   Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode
25944 };
25945
25946 static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = {
25947   Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode
25948 };
25949
25950 static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = {
25951   Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode
25952 };
25953
25954 static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = {
25955   Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode
25956 };
25957
25958 static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = {
25959   Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode
25960 };
25961
25962 static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = {
25963   Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode
25964 };
25965
25966 static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = {
25967   Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode
25968 };
25969
25970 static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = {
25971   Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode
25972 };
25973
25974 static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = {
25975   Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode
25976 };
25977
25978 static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = {
25979   Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode
25980 };
25981
25982 static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = {
25983   0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0
25984 };
25985
25986 static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = {
25987   0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0
25988 };
25989
25990 static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = {
25991   0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0
25992 };
25993
25994 static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = {
25995   Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode
25996 };
25997
25998 static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = {
25999   0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0
26000 };
26001
26002 static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = {
26003   0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0
26004 };
26005
26006 static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = {
26007   0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0
26008 };
26009
26010 static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = {
26011   0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0
26012 };
26013
26014 static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = {
26015   0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0
26016 };
26017
26018 static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = {
26019   0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0
26020 };
26021
26022 static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = {
26023   0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0
26024 };
26025
26026 static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = {
26027   0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0
26028 };
26029
26030 static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = {
26031   0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0
26032 };
26033
26034 static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = {
26035   0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0
26036 };
26037
26038 static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = {
26039   0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0
26040 };
26041
26042 static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = {
26043   0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0
26044 };
26045
26046 static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = {
26047   0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0
26048 };
26049
26050 static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = {
26051   0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0
26052 };
26053
26054 static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = {
26055   0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0
26056 };
26057
26058 static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = {
26059   0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0
26060 };
26061
26062 static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = {
26063   0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0
26064 };
26065
26066 static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = {
26067   0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0
26068 };
26069
26070 static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = {
26071   0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0
26072 };
26073
26074 static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = {
26075   0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0
26076 };
26077
26078 static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = {
26079   0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0
26080 };
26081
26082 static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = {
26083   0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0
26084 };
26085
26086 static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = {
26087   0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0
26088 };
26089
26090 static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = {
26091   0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0
26092 };
26093
26094 static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = {
26095   0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0
26096 };
26097
26098 static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = {
26099   0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0
26100 };
26101
26102 static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = {
26103   0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0
26104 };
26105
26106 static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = {
26107   0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0
26108 };
26109
26110 static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = {
26111   0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0
26112 };
26113
26114 static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = {
26115   0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0
26116 };
26117
26118 static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = {
26119   0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0
26120 };
26121
26122 static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = {
26123   0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0
26124 };
26125
26126 static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = {
26127   0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0
26128 };
26129
26130 static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = {
26131   0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0
26132 };
26133
26134 static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = {
26135   0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0
26136 };
26137
26138 static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = {
26139   0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0
26140 };
26141
26142 static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = {
26143   0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0
26144 };
26145
26146 static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = {
26147   0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0
26148 };
26149
26150 static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = {
26151   0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0
26152 };
26153
26154 static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = {
26155   0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0
26156 };
26157
26158 static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = {
26159   0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0
26160 };
26161
26162 static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = {
26163   0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0
26164 };
26165
26166 static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = {
26167   0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0
26168 };
26169
26170 static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = {
26171   0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0
26172 };
26173
26174 static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = {
26175   0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0
26176 };
26177
26178 static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = {
26179   0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0
26180 };
26181
26182 static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = {
26183   0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0
26184 };
26185
26186 static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = {
26187   0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0
26188 };
26189
26190 static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = {
26191   0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0
26192 };
26193
26194 static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = {
26195   0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0
26196 };
26197
26198 static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = {
26199   0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0
26200 };
26201
26202 static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = {
26203   0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0
26204 };
26205
26206 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = {
26207   0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0
26208 };
26209
26210 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = {
26211   0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0
26212 };
26213
26214 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = {
26215   0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0
26216 };
26217
26218 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = {
26219   0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0
26220 };
26221
26222 static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = {
26223   0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0
26224 };
26225
26226 static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = {
26227   0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0
26228 };
26229
26230 static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = {
26231   0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0
26232 };
26233
26234 static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = {
26235   0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0
26236 };
26237
26238 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = {
26239   0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0
26240 };
26241
26242 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = {
26243   0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0
26244 };
26245
26246 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = {
26247   0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0
26248 };
26249
26250 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = {
26251   0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0
26252 };
26253
26254 static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = {
26255   0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0
26256 };
26257
26258 static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = {
26259   0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0
26260 };
26261
26262 static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = {
26263   0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0
26264 };
26265
26266 static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = {
26267   0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0
26268 };
26269
26270 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = {
26271   0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0
26272 };
26273
26274 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = {
26275   0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0
26276 };
26277
26278 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = {
26279   0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0
26280 };
26281
26282 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = {
26283   0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0
26284 };
26285
26286 static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = {
26287   0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0
26288 };
26289
26290 static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = {
26291   0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0
26292 };
26293
26294 static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = {
26295   0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0
26296 };
26297
26298 static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = {
26299   0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0
26300 };
26301
26302 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = {
26303   0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0
26304 };
26305
26306 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = {
26307   0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0
26308 };
26309
26310 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = {
26311   0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0
26312 };
26313
26314 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = {
26315   0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0
26316 };
26317
26318 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = {
26319   0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0
26320 };
26321
26322 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = {
26323   0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0
26324 };
26325
26326 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = {
26327   0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0
26328 };
26329
26330 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = {
26331   0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0
26332 };
26333
26334 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = {
26335   0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0
26336 };
26337
26338 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = {
26339   0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0
26340 };
26341
26342 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = {
26343   0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0
26344 };
26345
26346 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = {
26347   0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0
26348 };
26349
26350 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = {
26351   0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0
26352 };
26353
26354 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = {
26355   0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0
26356 };
26357
26358 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = {
26359   0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0
26360 };
26361
26362 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = {
26363   0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0
26364 };
26365
26366 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = {
26367   0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0
26368 };
26369
26370 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = {
26371   0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0
26372 };
26373
26374 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = {
26375   0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0
26376 };
26377
26378 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = {
26379   0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0
26380 };
26381
26382 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = {
26383   0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0
26384 };
26385
26386 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = {
26387   0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0
26388 };
26389
26390 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = {
26391   0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0
26392 };
26393
26394 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = {
26395   0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0
26396 };
26397
26398 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = {
26399   0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0
26400 };
26401
26402 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = {
26403   0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0
26404 };
26405
26406 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = {
26407   0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0
26408 };
26409
26410 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = {
26411   0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0
26412 };
26413
26414 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = {
26415   0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0
26416 };
26417
26418 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = {
26419   0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0
26420 };
26421
26422 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = {
26423   0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0
26424 };
26425
26426 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = {
26427   0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0
26428 };
26429
26430 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = {
26431   0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0
26432 };
26433
26434 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = {
26435   0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0
26436 };
26437
26438 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = {
26439   0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0
26440 };
26441
26442 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = {
26443   0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0
26444 };
26445
26446 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = {
26447   0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0
26448 };
26449
26450 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = {
26451   0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0
26452 };
26453
26454 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = {
26455   0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0
26456 };
26457
26458 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = {
26459   0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0
26460 };
26461
26462 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = {
26463   0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0
26464 };
26465
26466 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = {
26467   0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0
26468 };
26469
26470 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = {
26471   0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0
26472 };
26473
26474 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = {
26475   0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0
26476 };
26477
26478 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = {
26479   0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0
26480 };
26481
26482 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = {
26483   0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0
26484 };
26485
26486 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = {
26487   0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0
26488 };
26489
26490 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = {
26491   0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0
26492 };
26493
26494 static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = {
26495   0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0
26496 };
26497
26498 static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = {
26499   0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0
26500 };
26501
26502 static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = {
26503   0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0
26504 };
26505
26506 static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = {
26507   0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0
26508 };
26509
26510 static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = {
26511   0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0
26512 };
26513
26514 static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = {
26515   0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0
26516 };
26517
26518 static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = {
26519   0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0
26520 };
26521
26522 static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = {
26523   0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0
26524 };
26525
26526 static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = {
26527   0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0
26528 };
26529
26530 static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = {
26531   0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0
26532 };
26533
26534 static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = {
26535   0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0
26536 };
26537
26538 static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = {
26539   0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0
26540 };
26541
26542 static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = {
26543   0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0
26544 };
26545
26546 static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = {
26547   0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0
26548 };
26549
26550 static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = {
26551   0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0
26552 };
26553
26554 static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = {
26555   0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0
26556 };
26557
26558 static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = {
26559   0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0
26560 };
26561
26562 static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = {
26563   0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0
26564 };
26565
26566 static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = {
26567   0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0
26568 };
26569
26570 static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = {
26571   0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0
26572 };
26573
26574 static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = {
26575   0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0
26576 };
26577
26578 static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = {
26579   0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0
26580 };
26581
26582 static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = {
26583   0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0
26584 };
26585
26586 static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = {
26587   0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0
26588 };
26589
26590 static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = {
26591   0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0
26592 };
26593
26594 static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = {
26595   0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0
26596 };
26597
26598 static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = {
26599   0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0
26600 };
26601
26602 static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = {
26603   0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0
26604 };
26605
26606 static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = {
26607   0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0
26608 };
26609
26610 static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = {
26611   0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0
26612 };
26613
26614 static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = {
26615   0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0
26616 };
26617
26618 static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = {
26619   0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0
26620 };
26621
26622 static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = {
26623   Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0
26624 };
26625
26626 static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = {
26627   Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0
26628 };
26629
26630 static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = {
26631   Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0
26632 };
26633
26634 static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = {
26635   Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0
26636 };
26637
26638 static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = {
26639   Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0
26640 };
26641
26642 static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = {
26643   Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0
26644 };
26645
26646 static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = {
26647   Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0
26648 };
26649
26650 static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = {
26651   Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0
26652 };
26653
26654 static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = {
26655   Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0
26656 };
26657
26658 static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = {
26659   Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0
26660 };
26661
26662 static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = {
26663   Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0
26664 };
26665
26666 static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = {
26667   Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0
26668 };
26669
26670 static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = {
26671   Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0
26672 };
26673
26674 static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = {
26675   Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0
26676 };
26677
26678 static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = {
26679   Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0
26680 };
26681
26682 static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = {
26683   Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0
26684 };
26685
26686 static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = {
26687   Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0
26688 };
26689
26690 \f
26691 /* Opcode table.  */
26692
26693 static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = {
26694   { FUNCUNIT_ae_add32, 3 }
26695 };
26696
26697 static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = {
26698   { FUNCUNIT_ae_add32, 3 }
26699 };
26700
26701 static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = {
26702   { FUNCUNIT_ae_shift32x4, 2 },
26703   { FUNCUNIT_ae_shift32x5, 3 },
26704   { FUNCUNIT_ae_add32, 3 }
26705 };
26706
26707 static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = {
26708   { FUNCUNIT_ae_shift32x4, 2 },
26709   { FUNCUNIT_ae_shift32x5, 3 },
26710   { FUNCUNIT_ae_add32, 3 }
26711 };
26712
26713 static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = {
26714   { FUNCUNIT_ae_subshift, 2 }
26715 };
26716
26717 static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = {
26718   { FUNCUNIT_ae_subshift, 2 }
26719 };
26720
26721 static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = {
26722   { FUNCUNIT_ae_subshift, 2 }
26723 };
26724
26725 static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = {
26726   { FUNCUNIT_ae_subshift, 2 }
26727 };
26728
26729 static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = {
26730   { FUNCUNIT_ae_shift32x4, 2 },
26731   { FUNCUNIT_ae_subshift, 2 }
26732 };
26733
26734 static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = {
26735   { FUNCUNIT_ae_shift32x4, 2 },
26736   { FUNCUNIT_ae_subshift, 2 }
26737 };
26738
26739 static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = {
26740   { FUNCUNIT_ae_add32, 3 }
26741 };
26742
26743 static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = {
26744   { FUNCUNIT_ae_add32, 3 }
26745 };
26746
26747 static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = {
26748   { FUNCUNIT_ae_shift32x4, 2 },
26749   { FUNCUNIT_ae_subshift, 2 }
26750 };
26751
26752 static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = {
26753   { FUNCUNIT_ae_shift32x4, 2 },
26754   { FUNCUNIT_ae_subshift, 2 }
26755 };
26756
26757 static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = {
26758   { FUNCUNIT_ae_shift32x4, 2 },
26759   { FUNCUNIT_ae_subshift, 2 }
26760 };
26761
26762 static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = {
26763   { FUNCUNIT_ae_shift32x4, 2 },
26764   { FUNCUNIT_ae_subshift, 2 }
26765 };
26766
26767 static xtensa_opcode_internal opcodes[] = {
26768   { "excw", ICLASS_xt_iclass_excw,
26769     0,
26770     Opcode_excw_encode_fns, 0, 0 },
26771   { "rfe", ICLASS_xt_iclass_rfe,
26772     XTENSA_OPCODE_IS_JUMP,
26773     Opcode_rfe_encode_fns, 0, 0 },
26774   { "rfde", ICLASS_xt_iclass_rfde,
26775     XTENSA_OPCODE_IS_JUMP,
26776     Opcode_rfde_encode_fns, 0, 0 },
26777   { "syscall", ICLASS_xt_iclass_syscall,
26778     0,
26779     Opcode_syscall_encode_fns, 0, 0 },
26780   { "call12", ICLASS_xt_iclass_call12,
26781     XTENSA_OPCODE_IS_CALL,
26782     Opcode_call12_encode_fns, 0, 0 },
26783   { "call8", ICLASS_xt_iclass_call8,
26784     XTENSA_OPCODE_IS_CALL,
26785     Opcode_call8_encode_fns, 0, 0 },
26786   { "call4", ICLASS_xt_iclass_call4,
26787     XTENSA_OPCODE_IS_CALL,
26788     Opcode_call4_encode_fns, 0, 0 },
26789   { "callx12", ICLASS_xt_iclass_callx12,
26790     XTENSA_OPCODE_IS_CALL,
26791     Opcode_callx12_encode_fns, 0, 0 },
26792   { "callx8", ICLASS_xt_iclass_callx8,
26793     XTENSA_OPCODE_IS_CALL,
26794     Opcode_callx8_encode_fns, 0, 0 },
26795   { "callx4", ICLASS_xt_iclass_callx4,
26796     XTENSA_OPCODE_IS_CALL,
26797     Opcode_callx4_encode_fns, 0, 0 },
26798   { "entry", ICLASS_xt_iclass_entry,
26799     0,
26800     Opcode_entry_encode_fns, 0, 0 },
26801   { "movsp", ICLASS_xt_iclass_movsp,
26802     0,
26803     Opcode_movsp_encode_fns, 0, 0 },
26804   { "rotw", ICLASS_xt_iclass_rotw,
26805     0,
26806     Opcode_rotw_encode_fns, 0, 0 },
26807   { "retw", ICLASS_xt_iclass_retw,
26808     XTENSA_OPCODE_IS_JUMP,
26809     Opcode_retw_encode_fns, 0, 0 },
26810   { "retw.n", ICLASS_xt_iclass_retw,
26811     XTENSA_OPCODE_IS_JUMP,
26812     Opcode_retw_n_encode_fns, 0, 0 },
26813   { "rfwo", ICLASS_xt_iclass_rfwou,
26814     XTENSA_OPCODE_IS_JUMP,
26815     Opcode_rfwo_encode_fns, 0, 0 },
26816   { "rfwu", ICLASS_xt_iclass_rfwou,
26817     XTENSA_OPCODE_IS_JUMP,
26818     Opcode_rfwu_encode_fns, 0, 0 },
26819   { "l32e", ICLASS_xt_iclass_l32e,
26820     0,
26821     Opcode_l32e_encode_fns, 0, 0 },
26822   { "s32e", ICLASS_xt_iclass_s32e,
26823     0,
26824     Opcode_s32e_encode_fns, 0, 0 },
26825   { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
26826     0,
26827     Opcode_rsr_windowbase_encode_fns, 0, 0 },
26828   { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
26829     0,
26830     Opcode_wsr_windowbase_encode_fns, 0, 0 },
26831   { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
26832     0,
26833     Opcode_xsr_windowbase_encode_fns, 0, 0 },
26834   { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
26835     0,
26836     Opcode_rsr_windowstart_encode_fns, 0, 0 },
26837   { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
26838     0,
26839     Opcode_wsr_windowstart_encode_fns, 0, 0 },
26840   { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
26841     0,
26842     Opcode_xsr_windowstart_encode_fns, 0, 0 },
26843   { "add.n", ICLASS_xt_iclass_add_n,
26844     0,
26845     Opcode_add_n_encode_fns, 0, 0 },
26846   { "addi.n", ICLASS_xt_iclass_addi_n,
26847     0,
26848     Opcode_addi_n_encode_fns, 0, 0 },
26849   { "beqz.n", ICLASS_xt_iclass_bz6,
26850     XTENSA_OPCODE_IS_BRANCH,
26851     Opcode_beqz_n_encode_fns, 0, 0 },
26852   { "bnez.n", ICLASS_xt_iclass_bz6,
26853     XTENSA_OPCODE_IS_BRANCH,
26854     Opcode_bnez_n_encode_fns, 0, 0 },
26855   { "ill.n", ICLASS_xt_iclass_ill_n,
26856     0,
26857     Opcode_ill_n_encode_fns, 0, 0 },
26858   { "l32i.n", ICLASS_xt_iclass_loadi4,
26859     0,
26860     Opcode_l32i_n_encode_fns, 0, 0 },
26861   { "mov.n", ICLASS_xt_iclass_mov_n,
26862     0,
26863     Opcode_mov_n_encode_fns, 0, 0 },
26864   { "movi.n", ICLASS_xt_iclass_movi_n,
26865     0,
26866     Opcode_movi_n_encode_fns, 0, 0 },
26867   { "nop.n", ICLASS_xt_iclass_nopn,
26868     0,
26869     Opcode_nop_n_encode_fns, 0, 0 },
26870   { "ret.n", ICLASS_xt_iclass_retn,
26871     XTENSA_OPCODE_IS_JUMP,
26872     Opcode_ret_n_encode_fns, 0, 0 },
26873   { "s32i.n", ICLASS_xt_iclass_storei4,
26874     0,
26875     Opcode_s32i_n_encode_fns, 0, 0 },
26876   { "rur.threadptr", ICLASS_rur_threadptr,
26877     0,
26878     Opcode_rur_threadptr_encode_fns, 0, 0 },
26879   { "wur.threadptr", ICLASS_wur_threadptr,
26880     0,
26881     Opcode_wur_threadptr_encode_fns, 0, 0 },
26882   { "addi", ICLASS_xt_iclass_addi,
26883     0,
26884     Opcode_addi_encode_fns, 0, 0 },
26885   { "addmi", ICLASS_xt_iclass_addmi,
26886     0,
26887     Opcode_addmi_encode_fns, 0, 0 },
26888   { "add", ICLASS_xt_iclass_addsub,
26889     0,
26890     Opcode_add_encode_fns, 0, 0 },
26891   { "sub", ICLASS_xt_iclass_addsub,
26892     0,
26893     Opcode_sub_encode_fns, 0, 0 },
26894   { "addx2", ICLASS_xt_iclass_addsub,
26895     0,
26896     Opcode_addx2_encode_fns, 0, 0 },
26897   { "addx4", ICLASS_xt_iclass_addsub,
26898     0,
26899     Opcode_addx4_encode_fns, 0, 0 },
26900   { "addx8", ICLASS_xt_iclass_addsub,
26901     0,
26902     Opcode_addx8_encode_fns, 0, 0 },
26903   { "subx2", ICLASS_xt_iclass_addsub,
26904     0,
26905     Opcode_subx2_encode_fns, 0, 0 },
26906   { "subx4", ICLASS_xt_iclass_addsub,
26907     0,
26908     Opcode_subx4_encode_fns, 0, 0 },
26909   { "subx8", ICLASS_xt_iclass_addsub,
26910     0,
26911     Opcode_subx8_encode_fns, 0, 0 },
26912   { "and", ICLASS_xt_iclass_bit,
26913     0,
26914     Opcode_and_encode_fns, 0, 0 },
26915   { "or", ICLASS_xt_iclass_bit,
26916     0,
26917     Opcode_or_encode_fns, 0, 0 },
26918   { "xor", ICLASS_xt_iclass_bit,
26919     0,
26920     Opcode_xor_encode_fns, 0, 0 },
26921   { "beqi", ICLASS_xt_iclass_bsi8,
26922     XTENSA_OPCODE_IS_BRANCH,
26923     Opcode_beqi_encode_fns, 0, 0 },
26924   { "bnei", ICLASS_xt_iclass_bsi8,
26925     XTENSA_OPCODE_IS_BRANCH,
26926     Opcode_bnei_encode_fns, 0, 0 },
26927   { "bgei", ICLASS_xt_iclass_bsi8,
26928     XTENSA_OPCODE_IS_BRANCH,
26929     Opcode_bgei_encode_fns, 0, 0 },
26930   { "blti", ICLASS_xt_iclass_bsi8,
26931     XTENSA_OPCODE_IS_BRANCH,
26932     Opcode_blti_encode_fns, 0, 0 },
26933   { "bbci", ICLASS_xt_iclass_bsi8b,
26934     XTENSA_OPCODE_IS_BRANCH,
26935     Opcode_bbci_encode_fns, 0, 0 },
26936   { "bbsi", ICLASS_xt_iclass_bsi8b,
26937     XTENSA_OPCODE_IS_BRANCH,
26938     Opcode_bbsi_encode_fns, 0, 0 },
26939   { "bgeui", ICLASS_xt_iclass_bsi8u,
26940     XTENSA_OPCODE_IS_BRANCH,
26941     Opcode_bgeui_encode_fns, 0, 0 },
26942   { "bltui", ICLASS_xt_iclass_bsi8u,
26943     XTENSA_OPCODE_IS_BRANCH,
26944     Opcode_bltui_encode_fns, 0, 0 },
26945   { "beq", ICLASS_xt_iclass_bst8,
26946     XTENSA_OPCODE_IS_BRANCH,
26947     Opcode_beq_encode_fns, 0, 0 },
26948   { "bne", ICLASS_xt_iclass_bst8,
26949     XTENSA_OPCODE_IS_BRANCH,
26950     Opcode_bne_encode_fns, 0, 0 },
26951   { "bge", ICLASS_xt_iclass_bst8,
26952     XTENSA_OPCODE_IS_BRANCH,
26953     Opcode_bge_encode_fns, 0, 0 },
26954   { "blt", ICLASS_xt_iclass_bst8,
26955     XTENSA_OPCODE_IS_BRANCH,
26956     Opcode_blt_encode_fns, 0, 0 },
26957   { "bgeu", ICLASS_xt_iclass_bst8,
26958     XTENSA_OPCODE_IS_BRANCH,
26959     Opcode_bgeu_encode_fns, 0, 0 },
26960   { "bltu", ICLASS_xt_iclass_bst8,
26961     XTENSA_OPCODE_IS_BRANCH,
26962     Opcode_bltu_encode_fns, 0, 0 },
26963   { "bany", ICLASS_xt_iclass_bst8,
26964     XTENSA_OPCODE_IS_BRANCH,
26965     Opcode_bany_encode_fns, 0, 0 },
26966   { "bnone", ICLASS_xt_iclass_bst8,
26967     XTENSA_OPCODE_IS_BRANCH,
26968     Opcode_bnone_encode_fns, 0, 0 },
26969   { "ball", ICLASS_xt_iclass_bst8,
26970     XTENSA_OPCODE_IS_BRANCH,
26971     Opcode_ball_encode_fns, 0, 0 },
26972   { "bnall", ICLASS_xt_iclass_bst8,
26973     XTENSA_OPCODE_IS_BRANCH,
26974     Opcode_bnall_encode_fns, 0, 0 },
26975   { "bbc", ICLASS_xt_iclass_bst8,
26976     XTENSA_OPCODE_IS_BRANCH,
26977     Opcode_bbc_encode_fns, 0, 0 },
26978   { "bbs", ICLASS_xt_iclass_bst8,
26979     XTENSA_OPCODE_IS_BRANCH,
26980     Opcode_bbs_encode_fns, 0, 0 },
26981   { "beqz", ICLASS_xt_iclass_bsz12,
26982     XTENSA_OPCODE_IS_BRANCH,
26983     Opcode_beqz_encode_fns, 0, 0 },
26984   { "bnez", ICLASS_xt_iclass_bsz12,
26985     XTENSA_OPCODE_IS_BRANCH,
26986     Opcode_bnez_encode_fns, 0, 0 },
26987   { "bgez", ICLASS_xt_iclass_bsz12,
26988     XTENSA_OPCODE_IS_BRANCH,
26989     Opcode_bgez_encode_fns, 0, 0 },
26990   { "bltz", ICLASS_xt_iclass_bsz12,
26991     XTENSA_OPCODE_IS_BRANCH,
26992     Opcode_bltz_encode_fns, 0, 0 },
26993   { "call0", ICLASS_xt_iclass_call0,
26994     XTENSA_OPCODE_IS_CALL,
26995     Opcode_call0_encode_fns, 0, 0 },
26996   { "callx0", ICLASS_xt_iclass_callx0,
26997     XTENSA_OPCODE_IS_CALL,
26998     Opcode_callx0_encode_fns, 0, 0 },
26999   { "extui", ICLASS_xt_iclass_exti,
27000     0,
27001     Opcode_extui_encode_fns, 0, 0 },
27002   { "ill", ICLASS_xt_iclass_ill,
27003     0,
27004     Opcode_ill_encode_fns, 0, 0 },
27005   { "j", ICLASS_xt_iclass_jump,
27006     XTENSA_OPCODE_IS_JUMP,
27007     Opcode_j_encode_fns, 0, 0 },
27008   { "jx", ICLASS_xt_iclass_jumpx,
27009     XTENSA_OPCODE_IS_JUMP,
27010     Opcode_jx_encode_fns, 0, 0 },
27011   { "l16ui", ICLASS_xt_iclass_l16ui,
27012     0,
27013     Opcode_l16ui_encode_fns, 0, 0 },
27014   { "l16si", ICLASS_xt_iclass_l16si,
27015     0,
27016     Opcode_l16si_encode_fns, 0, 0 },
27017   { "l32i", ICLASS_xt_iclass_l32i,
27018     0,
27019     Opcode_l32i_encode_fns, 0, 0 },
27020   { "l32r", ICLASS_xt_iclass_l32r,
27021     0,
27022     Opcode_l32r_encode_fns, 0, 0 },
27023   { "l8ui", ICLASS_xt_iclass_l8i,
27024     0,
27025     Opcode_l8ui_encode_fns, 0, 0 },
27026   { "loop", ICLASS_xt_iclass_loop,
27027     XTENSA_OPCODE_IS_LOOP,
27028     Opcode_loop_encode_fns, 0, 0 },
27029   { "loopnez", ICLASS_xt_iclass_loopz,
27030     XTENSA_OPCODE_IS_LOOP,
27031     Opcode_loopnez_encode_fns, 0, 0 },
27032   { "loopgtz", ICLASS_xt_iclass_loopz,
27033     XTENSA_OPCODE_IS_LOOP,
27034     Opcode_loopgtz_encode_fns, 0, 0 },
27035   { "movi", ICLASS_xt_iclass_movi,
27036     0,
27037     Opcode_movi_encode_fns, 0, 0 },
27038   { "moveqz", ICLASS_xt_iclass_movz,
27039     0,
27040     Opcode_moveqz_encode_fns, 0, 0 },
27041   { "movnez", ICLASS_xt_iclass_movz,
27042     0,
27043     Opcode_movnez_encode_fns, 0, 0 },
27044   { "movltz", ICLASS_xt_iclass_movz,
27045     0,
27046     Opcode_movltz_encode_fns, 0, 0 },
27047   { "movgez", ICLASS_xt_iclass_movz,
27048     0,
27049     Opcode_movgez_encode_fns, 0, 0 },
27050   { "neg", ICLASS_xt_iclass_neg,
27051     0,
27052     Opcode_neg_encode_fns, 0, 0 },
27053   { "abs", ICLASS_xt_iclass_neg,
27054     0,
27055     Opcode_abs_encode_fns, 0, 0 },
27056   { "nop", ICLASS_xt_iclass_nop,
27057     0,
27058     Opcode_nop_encode_fns, 0, 0 },
27059   { "ret", ICLASS_xt_iclass_return,
27060     XTENSA_OPCODE_IS_JUMP,
27061     Opcode_ret_encode_fns, 0, 0 },
27062   { "simcall", ICLASS_xt_iclass_simcall,
27063     0,
27064     Opcode_simcall_encode_fns, 0, 0 },
27065   { "s16i", ICLASS_xt_iclass_s16i,
27066     0,
27067     Opcode_s16i_encode_fns, 0, 0 },
27068   { "s32i", ICLASS_xt_iclass_s32i,
27069     0,
27070     Opcode_s32i_encode_fns, 0, 0 },
27071   { "s8i", ICLASS_xt_iclass_s8i,
27072     0,
27073     Opcode_s8i_encode_fns, 0, 0 },
27074   { "ssr", ICLASS_xt_iclass_sar,
27075     0,
27076     Opcode_ssr_encode_fns, 0, 0 },
27077   { "ssl", ICLASS_xt_iclass_sar,
27078     0,
27079     Opcode_ssl_encode_fns, 0, 0 },
27080   { "ssa8l", ICLASS_xt_iclass_sar,
27081     0,
27082     Opcode_ssa8l_encode_fns, 0, 0 },
27083   { "ssa8b", ICLASS_xt_iclass_sar,
27084     0,
27085     Opcode_ssa8b_encode_fns, 0, 0 },
27086   { "ssai", ICLASS_xt_iclass_sari,
27087     0,
27088     Opcode_ssai_encode_fns, 0, 0 },
27089   { "sll", ICLASS_xt_iclass_shifts,
27090     0,
27091     Opcode_sll_encode_fns, 0, 0 },
27092   { "src", ICLASS_xt_iclass_shiftst,
27093     0,
27094     Opcode_src_encode_fns, 0, 0 },
27095   { "srl", ICLASS_xt_iclass_shiftt,
27096     0,
27097     Opcode_srl_encode_fns, 0, 0 },
27098   { "sra", ICLASS_xt_iclass_shiftt,
27099     0,
27100     Opcode_sra_encode_fns, 0, 0 },
27101   { "slli", ICLASS_xt_iclass_slli,
27102     0,
27103     Opcode_slli_encode_fns, 0, 0 },
27104   { "srai", ICLASS_xt_iclass_srai,
27105     0,
27106     Opcode_srai_encode_fns, 0, 0 },
27107   { "srli", ICLASS_xt_iclass_srli,
27108     0,
27109     Opcode_srli_encode_fns, 0, 0 },
27110   { "memw", ICLASS_xt_iclass_memw,
27111     0,
27112     Opcode_memw_encode_fns, 0, 0 },
27113   { "extw", ICLASS_xt_iclass_extw,
27114     0,
27115     Opcode_extw_encode_fns, 0, 0 },
27116   { "isync", ICLASS_xt_iclass_isync,
27117     0,
27118     Opcode_isync_encode_fns, 0, 0 },
27119   { "rsync", ICLASS_xt_iclass_sync,
27120     0,
27121     Opcode_rsync_encode_fns, 0, 0 },
27122   { "esync", ICLASS_xt_iclass_sync,
27123     0,
27124     Opcode_esync_encode_fns, 0, 0 },
27125   { "dsync", ICLASS_xt_iclass_sync,
27126     0,
27127     Opcode_dsync_encode_fns, 0, 0 },
27128   { "rsil", ICLASS_xt_iclass_rsil,
27129     0,
27130     Opcode_rsil_encode_fns, 0, 0 },
27131   { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
27132     0,
27133     Opcode_rsr_lend_encode_fns, 0, 0 },
27134   { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
27135     0,
27136     Opcode_wsr_lend_encode_fns, 0, 0 },
27137   { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
27138     0,
27139     Opcode_xsr_lend_encode_fns, 0, 0 },
27140   { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
27141     0,
27142     Opcode_rsr_lcount_encode_fns, 0, 0 },
27143   { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
27144     0,
27145     Opcode_wsr_lcount_encode_fns, 0, 0 },
27146   { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
27147     0,
27148     Opcode_xsr_lcount_encode_fns, 0, 0 },
27149   { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
27150     0,
27151     Opcode_rsr_lbeg_encode_fns, 0, 0 },
27152   { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
27153     0,
27154     Opcode_wsr_lbeg_encode_fns, 0, 0 },
27155   { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
27156     0,
27157     Opcode_xsr_lbeg_encode_fns, 0, 0 },
27158   { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
27159     0,
27160     Opcode_rsr_sar_encode_fns, 0, 0 },
27161   { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
27162     0,
27163     Opcode_wsr_sar_encode_fns, 0, 0 },
27164   { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
27165     0,
27166     Opcode_xsr_sar_encode_fns, 0, 0 },
27167   { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
27168     0,
27169     Opcode_rsr_litbase_encode_fns, 0, 0 },
27170   { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
27171     0,
27172     Opcode_wsr_litbase_encode_fns, 0, 0 },
27173   { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
27174     0,
27175     Opcode_xsr_litbase_encode_fns, 0, 0 },
27176   { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
27177     0,
27178     Opcode_rsr_configid0_encode_fns, 0, 0 },
27179   { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
27180     0,
27181     Opcode_wsr_configid0_encode_fns, 0, 0 },
27182   { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
27183     0,
27184     Opcode_rsr_configid1_encode_fns, 0, 0 },
27185   { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
27186     0,
27187     Opcode_rsr_ps_encode_fns, 0, 0 },
27188   { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
27189     0,
27190     Opcode_wsr_ps_encode_fns, 0, 0 },
27191   { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
27192     0,
27193     Opcode_xsr_ps_encode_fns, 0, 0 },
27194   { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
27195     0,
27196     Opcode_rsr_epc1_encode_fns, 0, 0 },
27197   { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
27198     0,
27199     Opcode_wsr_epc1_encode_fns, 0, 0 },
27200   { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
27201     0,
27202     Opcode_xsr_epc1_encode_fns, 0, 0 },
27203   { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
27204     0,
27205     Opcode_rsr_excsave1_encode_fns, 0, 0 },
27206   { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
27207     0,
27208     Opcode_wsr_excsave1_encode_fns, 0, 0 },
27209   { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
27210     0,
27211     Opcode_xsr_excsave1_encode_fns, 0, 0 },
27212   { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
27213     0,
27214     Opcode_rsr_epc2_encode_fns, 0, 0 },
27215   { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
27216     0,
27217     Opcode_wsr_epc2_encode_fns, 0, 0 },
27218   { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
27219     0,
27220     Opcode_xsr_epc2_encode_fns, 0, 0 },
27221   { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
27222     0,
27223     Opcode_rsr_excsave2_encode_fns, 0, 0 },
27224   { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
27225     0,
27226     Opcode_wsr_excsave2_encode_fns, 0, 0 },
27227   { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
27228     0,
27229     Opcode_xsr_excsave2_encode_fns, 0, 0 },
27230   { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
27231     0,
27232     Opcode_rsr_eps2_encode_fns, 0, 0 },
27233   { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
27234     0,
27235     Opcode_wsr_eps2_encode_fns, 0, 0 },
27236   { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
27237     0,
27238     Opcode_xsr_eps2_encode_fns, 0, 0 },
27239   { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
27240     0,
27241     Opcode_rsr_excvaddr_encode_fns, 0, 0 },
27242   { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
27243     0,
27244     Opcode_wsr_excvaddr_encode_fns, 0, 0 },
27245   { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
27246     0,
27247     Opcode_xsr_excvaddr_encode_fns, 0, 0 },
27248   { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
27249     0,
27250     Opcode_rsr_depc_encode_fns, 0, 0 },
27251   { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
27252     0,
27253     Opcode_wsr_depc_encode_fns, 0, 0 },
27254   { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
27255     0,
27256     Opcode_xsr_depc_encode_fns, 0, 0 },
27257   { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
27258     0,
27259     Opcode_rsr_exccause_encode_fns, 0, 0 },
27260   { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
27261     0,
27262     Opcode_wsr_exccause_encode_fns, 0, 0 },
27263   { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
27264     0,
27265     Opcode_xsr_exccause_encode_fns, 0, 0 },
27266   { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
27267     0,
27268     Opcode_rsr_misc0_encode_fns, 0, 0 },
27269   { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
27270     0,
27271     Opcode_wsr_misc0_encode_fns, 0, 0 },
27272   { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
27273     0,
27274     Opcode_xsr_misc0_encode_fns, 0, 0 },
27275   { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
27276     0,
27277     Opcode_rsr_misc1_encode_fns, 0, 0 },
27278   { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
27279     0,
27280     Opcode_wsr_misc1_encode_fns, 0, 0 },
27281   { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
27282     0,
27283     Opcode_xsr_misc1_encode_fns, 0, 0 },
27284   { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
27285     0,
27286     Opcode_rsr_prid_encode_fns, 0, 0 },
27287   { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
27288     0,
27289     Opcode_rsr_vecbase_encode_fns, 0, 0 },
27290   { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
27291     0,
27292     Opcode_wsr_vecbase_encode_fns, 0, 0 },
27293   { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
27294     0,
27295     Opcode_xsr_vecbase_encode_fns, 0, 0 },
27296   { "mul16u", ICLASS_xt_mul16,
27297     0,
27298     Opcode_mul16u_encode_fns, 0, 0 },
27299   { "mul16s", ICLASS_xt_mul16,
27300     0,
27301     Opcode_mul16s_encode_fns, 0, 0 },
27302   { "mull", ICLASS_xt_mul32,
27303     0,
27304     Opcode_mull_encode_fns, 0, 0 },
27305   { "rfi", ICLASS_xt_iclass_rfi,
27306     XTENSA_OPCODE_IS_JUMP,
27307     Opcode_rfi_encode_fns, 0, 0 },
27308   { "waiti", ICLASS_xt_iclass_wait,
27309     0,
27310     Opcode_waiti_encode_fns, 0, 0 },
27311   { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
27312     0,
27313     Opcode_rsr_interrupt_encode_fns, 0, 0 },
27314   { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
27315     0,
27316     Opcode_wsr_intset_encode_fns, 0, 0 },
27317   { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
27318     0,
27319     Opcode_wsr_intclear_encode_fns, 0, 0 },
27320   { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
27321     0,
27322     Opcode_rsr_intenable_encode_fns, 0, 0 },
27323   { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
27324     0,
27325     Opcode_wsr_intenable_encode_fns, 0, 0 },
27326   { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
27327     0,
27328     Opcode_xsr_intenable_encode_fns, 0, 0 },
27329   { "break", ICLASS_xt_iclass_break,
27330     0,
27331     Opcode_break_encode_fns, 0, 0 },
27332   { "break.n", ICLASS_xt_iclass_break_n,
27333     0,
27334     Opcode_break_n_encode_fns, 0, 0 },
27335   { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
27336     0,
27337     Opcode_rsr_debugcause_encode_fns, 0, 0 },
27338   { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
27339     0,
27340     Opcode_wsr_debugcause_encode_fns, 0, 0 },
27341   { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
27342     0,
27343     Opcode_xsr_debugcause_encode_fns, 0, 0 },
27344   { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
27345     0,
27346     Opcode_rsr_icount_encode_fns, 0, 0 },
27347   { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
27348     0,
27349     Opcode_wsr_icount_encode_fns, 0, 0 },
27350   { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
27351     0,
27352     Opcode_xsr_icount_encode_fns, 0, 0 },
27353   { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
27354     0,
27355     Opcode_rsr_icountlevel_encode_fns, 0, 0 },
27356   { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
27357     0,
27358     Opcode_wsr_icountlevel_encode_fns, 0, 0 },
27359   { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
27360     0,
27361     Opcode_xsr_icountlevel_encode_fns, 0, 0 },
27362   { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
27363     0,
27364     Opcode_rsr_ddr_encode_fns, 0, 0 },
27365   { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
27366     0,
27367     Opcode_wsr_ddr_encode_fns, 0, 0 },
27368   { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
27369     0,
27370     Opcode_xsr_ddr_encode_fns, 0, 0 },
27371   { "rfdo", ICLASS_xt_iclass_rfdo,
27372     XTENSA_OPCODE_IS_JUMP,
27373     Opcode_rfdo_encode_fns, 0, 0 },
27374   { "rfdd", ICLASS_xt_iclass_rfdd,
27375     XTENSA_OPCODE_IS_JUMP,
27376     Opcode_rfdd_encode_fns, 0, 0 },
27377   { "andb", ICLASS_xt_iclass_bbool1,
27378     0,
27379     Opcode_andb_encode_fns, 0, 0 },
27380   { "andbc", ICLASS_xt_iclass_bbool1,
27381     0,
27382     Opcode_andbc_encode_fns, 0, 0 },
27383   { "orb", ICLASS_xt_iclass_bbool1,
27384     0,
27385     Opcode_orb_encode_fns, 0, 0 },
27386   { "orbc", ICLASS_xt_iclass_bbool1,
27387     0,
27388     Opcode_orbc_encode_fns, 0, 0 },
27389   { "xorb", ICLASS_xt_iclass_bbool1,
27390     0,
27391     Opcode_xorb_encode_fns, 0, 0 },
27392   { "any4", ICLASS_xt_iclass_bbool4,
27393     0,
27394     Opcode_any4_encode_fns, 0, 0 },
27395   { "all4", ICLASS_xt_iclass_bbool4,
27396     0,
27397     Opcode_all4_encode_fns, 0, 0 },
27398   { "any8", ICLASS_xt_iclass_bbool8,
27399     0,
27400     Opcode_any8_encode_fns, 0, 0 },
27401   { "all8", ICLASS_xt_iclass_bbool8,
27402     0,
27403     Opcode_all8_encode_fns, 0, 0 },
27404   { "bf", ICLASS_xt_iclass_bbranch,
27405     XTENSA_OPCODE_IS_BRANCH,
27406     Opcode_bf_encode_fns, 0, 0 },
27407   { "bt", ICLASS_xt_iclass_bbranch,
27408     XTENSA_OPCODE_IS_BRANCH,
27409     Opcode_bt_encode_fns, 0, 0 },
27410   { "movf", ICLASS_xt_iclass_bmove,
27411     0,
27412     Opcode_movf_encode_fns, 0, 0 },
27413   { "movt", ICLASS_xt_iclass_bmove,
27414     0,
27415     Opcode_movt_encode_fns, 0, 0 },
27416   { "rsr.br", ICLASS_xt_iclass_RSR_BR,
27417     0,
27418     Opcode_rsr_br_encode_fns, 0, 0 },
27419   { "wsr.br", ICLASS_xt_iclass_WSR_BR,
27420     0,
27421     Opcode_wsr_br_encode_fns, 0, 0 },
27422   { "xsr.br", ICLASS_xt_iclass_XSR_BR,
27423     0,
27424     Opcode_xsr_br_encode_fns, 0, 0 },
27425   { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
27426     0,
27427     Opcode_rsr_ccount_encode_fns, 0, 0 },
27428   { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
27429     0,
27430     Opcode_wsr_ccount_encode_fns, 0, 0 },
27431   { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
27432     0,
27433     Opcode_xsr_ccount_encode_fns, 0, 0 },
27434   { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
27435     0,
27436     Opcode_rsr_ccompare0_encode_fns, 0, 0 },
27437   { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
27438     0,
27439     Opcode_wsr_ccompare0_encode_fns, 0, 0 },
27440   { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
27441     0,
27442     Opcode_xsr_ccompare0_encode_fns, 0, 0 },
27443   { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
27444     0,
27445     Opcode_rsr_ccompare1_encode_fns, 0, 0 },
27446   { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
27447     0,
27448     Opcode_wsr_ccompare1_encode_fns, 0, 0 },
27449   { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
27450     0,
27451     Opcode_xsr_ccompare1_encode_fns, 0, 0 },
27452   { "ipf", ICLASS_xt_iclass_icache,
27453     0,
27454     Opcode_ipf_encode_fns, 0, 0 },
27455   { "ihi", ICLASS_xt_iclass_icache,
27456     0,
27457     Opcode_ihi_encode_fns, 0, 0 },
27458   { "iii", ICLASS_xt_iclass_icache_inv,
27459     0,
27460     Opcode_iii_encode_fns, 0, 0 },
27461   { "lict", ICLASS_xt_iclass_licx,
27462     0,
27463     Opcode_lict_encode_fns, 0, 0 },
27464   { "licw", ICLASS_xt_iclass_licx,
27465     0,
27466     Opcode_licw_encode_fns, 0, 0 },
27467   { "sict", ICLASS_xt_iclass_sicx,
27468     0,
27469     Opcode_sict_encode_fns, 0, 0 },
27470   { "sicw", ICLASS_xt_iclass_sicx,
27471     0,
27472     Opcode_sicw_encode_fns, 0, 0 },
27473   { "dhwb", ICLASS_xt_iclass_dcache,
27474     0,
27475     Opcode_dhwb_encode_fns, 0, 0 },
27476   { "dhwbi", ICLASS_xt_iclass_dcache,
27477     0,
27478     Opcode_dhwbi_encode_fns, 0, 0 },
27479   { "diwb", ICLASS_xt_iclass_dcache_ind,
27480     0,
27481     Opcode_diwb_encode_fns, 0, 0 },
27482   { "diwbi", ICLASS_xt_iclass_dcache_ind,
27483     0,
27484     Opcode_diwbi_encode_fns, 0, 0 },
27485   { "dhi", ICLASS_xt_iclass_dcache_inv,
27486     0,
27487     Opcode_dhi_encode_fns, 0, 0 },
27488   { "dii", ICLASS_xt_iclass_dcache_inv,
27489     0,
27490     Opcode_dii_encode_fns, 0, 0 },
27491   { "dpfr", ICLASS_xt_iclass_dpf,
27492     0,
27493     Opcode_dpfr_encode_fns, 0, 0 },
27494   { "dpfw", ICLASS_xt_iclass_dpf,
27495     0,
27496     Opcode_dpfw_encode_fns, 0, 0 },
27497   { "dpfro", ICLASS_xt_iclass_dpf,
27498     0,
27499     Opcode_dpfro_encode_fns, 0, 0 },
27500   { "dpfwo", ICLASS_xt_iclass_dpf,
27501     0,
27502     Opcode_dpfwo_encode_fns, 0, 0 },
27503   { "sdct", ICLASS_xt_iclass_sdct,
27504     0,
27505     Opcode_sdct_encode_fns, 0, 0 },
27506   { "ldct", ICLASS_xt_iclass_ldct,
27507     0,
27508     Opcode_ldct_encode_fns, 0, 0 },
27509   { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr,
27510     0,
27511     Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
27512   { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr,
27513     0,
27514     Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
27515   { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr,
27516     0,
27517     Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
27518   { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid,
27519     0,
27520     Opcode_rsr_rasid_encode_fns, 0, 0 },
27521   { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid,
27522     0,
27523     Opcode_wsr_rasid_encode_fns, 0, 0 },
27524   { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid,
27525     0,
27526     Opcode_xsr_rasid_encode_fns, 0, 0 },
27527   { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg,
27528     0,
27529     Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
27530   { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg,
27531     0,
27532     Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
27533   { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg,
27534     0,
27535     Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
27536   { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg,
27537     0,
27538     Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
27539   { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg,
27540     0,
27541     Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
27542   { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg,
27543     0,
27544     Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
27545   { "idtlb", ICLASS_xt_iclass_idtlb,
27546     0,
27547     Opcode_idtlb_encode_fns, 0, 0 },
27548   { "pdtlb", ICLASS_xt_iclass_rdtlb,
27549     0,
27550     Opcode_pdtlb_encode_fns, 0, 0 },
27551   { "rdtlb0", ICLASS_xt_iclass_rdtlb,
27552     0,
27553     Opcode_rdtlb0_encode_fns, 0, 0 },
27554   { "rdtlb1", ICLASS_xt_iclass_rdtlb,
27555     0,
27556     Opcode_rdtlb1_encode_fns, 0, 0 },
27557   { "wdtlb", ICLASS_xt_iclass_wdtlb,
27558     0,
27559     Opcode_wdtlb_encode_fns, 0, 0 },
27560   { "iitlb", ICLASS_xt_iclass_iitlb,
27561     0,
27562     Opcode_iitlb_encode_fns, 0, 0 },
27563   { "pitlb", ICLASS_xt_iclass_ritlb,
27564     0,
27565     Opcode_pitlb_encode_fns, 0, 0 },
27566   { "ritlb0", ICLASS_xt_iclass_ritlb,
27567     0,
27568     Opcode_ritlb0_encode_fns, 0, 0 },
27569   { "ritlb1", ICLASS_xt_iclass_ritlb,
27570     0,
27571     Opcode_ritlb1_encode_fns, 0, 0 },
27572   { "witlb", ICLASS_xt_iclass_witlb,
27573     0,
27574     Opcode_witlb_encode_fns, 0, 0 },
27575   { "ldpte", ICLASS_xt_iclass_ldpte,
27576     0,
27577     Opcode_ldpte_encode_fns, 0, 0 },
27578   { "hwwitlba", ICLASS_xt_iclass_hwwitlba,
27579     XTENSA_OPCODE_IS_BRANCH,
27580     Opcode_hwwitlba_encode_fns, 0, 0 },
27581   { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba,
27582     0,
27583     Opcode_hwwdtlba_encode_fns, 0, 0 },
27584   { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
27585     0,
27586     Opcode_rsr_cpenable_encode_fns, 0, 0 },
27587   { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
27588     0,
27589     Opcode_wsr_cpenable_encode_fns, 0, 0 },
27590   { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
27591     0,
27592     Opcode_xsr_cpenable_encode_fns, 0, 0 },
27593   { "clamps", ICLASS_xt_iclass_clamp,
27594     0,
27595     Opcode_clamps_encode_fns, 0, 0 },
27596   { "min", ICLASS_xt_iclass_minmax,
27597     0,
27598     Opcode_min_encode_fns, 0, 0 },
27599   { "max", ICLASS_xt_iclass_minmax,
27600     0,
27601     Opcode_max_encode_fns, 0, 0 },
27602   { "minu", ICLASS_xt_iclass_minmax,
27603     0,
27604     Opcode_minu_encode_fns, 0, 0 },
27605   { "maxu", ICLASS_xt_iclass_minmax,
27606     0,
27607     Opcode_maxu_encode_fns, 0, 0 },
27608   { "nsa", ICLASS_xt_iclass_nsa,
27609     0,
27610     Opcode_nsa_encode_fns, 0, 0 },
27611   { "nsau", ICLASS_xt_iclass_nsa,
27612     0,
27613     Opcode_nsau_encode_fns, 0, 0 },
27614   { "sext", ICLASS_xt_iclass_sx,
27615     0,
27616     Opcode_sext_encode_fns, 0, 0 },
27617   { "l32ai", ICLASS_xt_iclass_l32ai,
27618     0,
27619     Opcode_l32ai_encode_fns, 0, 0 },
27620   { "s32ri", ICLASS_xt_iclass_s32ri,
27621     0,
27622     Opcode_s32ri_encode_fns, 0, 0 },
27623   { "s32c1i", ICLASS_xt_iclass_s32c1i,
27624     0,
27625     Opcode_s32c1i_encode_fns, 0, 0 },
27626   { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
27627     0,
27628     Opcode_rsr_scompare1_encode_fns, 0, 0 },
27629   { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
27630     0,
27631     Opcode_wsr_scompare1_encode_fns, 0, 0 },
27632   { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
27633     0,
27634     Opcode_xsr_scompare1_encode_fns, 0, 0 },
27635   { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
27636     0,
27637     Opcode_rsr_atomctl_encode_fns, 0, 0 },
27638   { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
27639     0,
27640     Opcode_wsr_atomctl_encode_fns, 0, 0 },
27641   { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
27642     0,
27643     Opcode_xsr_atomctl_encode_fns, 0, 0 },
27644   { "rer", ICLASS_xt_iclass_rer,
27645     0,
27646     Opcode_rer_encode_fns, 0, 0 },
27647   { "wer", ICLASS_xt_iclass_wer,
27648     0,
27649     Opcode_wer_encode_fns, 0, 0 },
27650   { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar,
27651     0,
27652     Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 },
27653   { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar,
27654     0,
27655     Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 },
27656   { "rur.ae_bithead", ICLASS_rur_ae_bithead,
27657     0,
27658     Opcode_rur_ae_bithead_encode_fns, 0, 0 },
27659   { "wur.ae_bithead", ICLASS_wur_ae_bithead,
27660     0,
27661     Opcode_wur_ae_bithead_encode_fns, 0, 0 },
27662   { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp,
27663     0,
27664     Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
27665   { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp,
27666     0,
27667     Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
27668   { "rur.ae_sd_no", ICLASS_rur_ae_sd_no,
27669     0,
27670     Opcode_rur_ae_sd_no_encode_fns, 0, 0 },
27671   { "wur.ae_sd_no", ICLASS_wur_ae_sd_no,
27672     0,
27673     Opcode_wur_ae_sd_no_encode_fns, 0, 0 },
27674   { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow,
27675     0,
27676     Opcode_rur_ae_overflow_encode_fns, 0, 0 },
27677   { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow,
27678     0,
27679     Opcode_wur_ae_overflow_encode_fns, 0, 0 },
27680   { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar,
27681     0,
27682     Opcode_rur_ae_sar_encode_fns, 0, 0 },
27683   { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar,
27684     0,
27685     Opcode_wur_ae_sar_encode_fns, 0, 0 },
27686   { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr,
27687     0,
27688     Opcode_rur_ae_bitptr_encode_fns, 0, 0 },
27689   { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr,
27690     0,
27691     Opcode_wur_ae_bitptr_encode_fns, 0, 0 },
27692   { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused,
27693     0,
27694     Opcode_rur_ae_bitsused_encode_fns, 0, 0 },
27695   { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused,
27696     0,
27697     Opcode_wur_ae_bitsused_encode_fns, 0, 0 },
27698   { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize,
27699     0,
27700     Opcode_rur_ae_tablesize_encode_fns, 0, 0 },
27701   { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize,
27702     0,
27703     Opcode_wur_ae_tablesize_encode_fns, 0, 0 },
27704   { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts,
27705     0,
27706     Opcode_rur_ae_first_ts_encode_fns, 0, 0 },
27707   { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts,
27708     0,
27709     Opcode_wur_ae_first_ts_encode_fns, 0, 0 },
27710   { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset,
27711     0,
27712     Opcode_rur_ae_nextoffset_encode_fns, 0, 0 },
27713   { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset,
27714     0,
27715     Opcode_wur_ae_nextoffset_encode_fns, 0, 0 },
27716   { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone,
27717     0,
27718     Opcode_rur_ae_searchdone_encode_fns, 0, 0 },
27719   { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone,
27720     0,
27721     Opcode_wur_ae_searchdone_encode_fns, 0, 0 },
27722   { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i,
27723     0,
27724     Opcode_ae_lp16f_i_encode_fns, 0, 0 },
27725   { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu,
27726     0,
27727     Opcode_ae_lp16f_iu_encode_fns, 0, 0 },
27728   { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x,
27729     0,
27730     Opcode_ae_lp16f_x_encode_fns, 0, 0 },
27731   { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu,
27732     0,
27733     Opcode_ae_lp16f_xu_encode_fns, 0, 0 },
27734   { "ae_lp24.i", ICLASS_ae_iclass_lp24_i,
27735     0,
27736     Opcode_ae_lp24_i_encode_fns, 0, 0 },
27737   { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu,
27738     0,
27739     Opcode_ae_lp24_iu_encode_fns, 0, 0 },
27740   { "ae_lp24.x", ICLASS_ae_iclass_lp24_x,
27741     0,
27742     Opcode_ae_lp24_x_encode_fns, 0, 0 },
27743   { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu,
27744     0,
27745     Opcode_ae_lp24_xu_encode_fns, 0, 0 },
27746   { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i,
27747     0,
27748     Opcode_ae_lp24f_i_encode_fns, 0, 0 },
27749   { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu,
27750     0,
27751     Opcode_ae_lp24f_iu_encode_fns, 0, 0 },
27752   { "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x,
27753     0,
27754     Opcode_ae_lp24f_x_encode_fns, 0, 0 },
27755   { "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu,
27756     0,
27757     Opcode_ae_lp24f_xu_encode_fns, 0, 0 },
27758   { "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i,
27759     0,
27760     Opcode_ae_lp16x2f_i_encode_fns, 0, 0 },
27761   { "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu,
27762     0,
27763     Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 },
27764   { "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x,
27765     0,
27766     Opcode_ae_lp16x2f_x_encode_fns, 0, 0 },
27767   { "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu,
27768     0,
27769     Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 },
27770   { "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i,
27771     0,
27772     Opcode_ae_lp24x2f_i_encode_fns, 0, 0 },
27773   { "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu,
27774     0,
27775     Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 },
27776   { "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x,
27777     0,
27778     Opcode_ae_lp24x2f_x_encode_fns, 0, 0 },
27779   { "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu,
27780     0,
27781     Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 },
27782   { "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i,
27783     0,
27784     Opcode_ae_lp24x2_i_encode_fns, 0, 0 },
27785   { "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu,
27786     0,
27787     Opcode_ae_lp24x2_iu_encode_fns, 0, 0 },
27788   { "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x,
27789     0,
27790     Opcode_ae_lp24x2_x_encode_fns, 0, 0 },
27791   { "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu,
27792     0,
27793     Opcode_ae_lp24x2_xu_encode_fns, 0, 0 },
27794   { "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i,
27795     0,
27796     Opcode_ae_sp16x2f_i_encode_fns, 0, 0 },
27797   { "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu,
27798     0,
27799     Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 },
27800   { "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x,
27801     0,
27802     Opcode_ae_sp16x2f_x_encode_fns, 0, 0 },
27803   { "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu,
27804     0,
27805     Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 },
27806   { "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i,
27807     0,
27808     Opcode_ae_sp24x2s_i_encode_fns, 0, 0 },
27809   { "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu,
27810     0,
27811     Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 },
27812   { "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x,
27813     0,
27814     Opcode_ae_sp24x2s_x_encode_fns, 0, 0 },
27815   { "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu,
27816     0,
27817     Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 },
27818   { "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i,
27819     0,
27820     Opcode_ae_sp24x2f_i_encode_fns, 0, 0 },
27821   { "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu,
27822     0,
27823     Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 },
27824   { "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x,
27825     0,
27826     Opcode_ae_sp24x2f_x_encode_fns, 0, 0 },
27827   { "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu,
27828     0,
27829     Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 },
27830   { "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i,
27831     0,
27832     Opcode_ae_sp16f_l_i_encode_fns, 0, 0 },
27833   { "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu,
27834     0,
27835     Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 },
27836   { "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x,
27837     0,
27838     Opcode_ae_sp16f_l_x_encode_fns, 0, 0 },
27839   { "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu,
27840     0,
27841     Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 },
27842   { "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i,
27843     0,
27844     Opcode_ae_sp24s_l_i_encode_fns, 0, 0 },
27845   { "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu,
27846     0,
27847     Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 },
27848   { "ae_sp24s.l.x", ICLASS_ae_iclass_sp24s_l_x,
27849     0,
27850     Opcode_ae_sp24s_l_x_encode_fns, 0, 0 },
27851   { "ae_sp24s.l.xu", ICLASS_ae_iclass_sp24s_l_xu,
27852     0,
27853     Opcode_ae_sp24s_l_xu_encode_fns, 0, 0 },
27854   { "ae_sp24f.l.i", ICLASS_ae_iclass_sp24f_l_i,
27855     0,
27856     Opcode_ae_sp24f_l_i_encode_fns, 0, 0 },
27857   { "ae_sp24f.l.iu", ICLASS_ae_iclass_sp24f_l_iu,
27858     0,
27859     Opcode_ae_sp24f_l_iu_encode_fns, 0, 0 },
27860   { "ae_sp24f.l.x", ICLASS_ae_iclass_sp24f_l_x,
27861     0,
27862     Opcode_ae_sp24f_l_x_encode_fns, 0, 0 },
27863   { "ae_sp24f.l.xu", ICLASS_ae_iclass_sp24f_l_xu,
27864     0,
27865     Opcode_ae_sp24f_l_xu_encode_fns, 0, 0 },
27866   { "ae_lq56.i", ICLASS_ae_iclass_lq56_i,
27867     0,
27868     Opcode_ae_lq56_i_encode_fns, 0, 0 },
27869   { "ae_lq56.iu", ICLASS_ae_iclass_lq56_iu,
27870     0,
27871     Opcode_ae_lq56_iu_encode_fns, 0, 0 },
27872   { "ae_lq56.x", ICLASS_ae_iclass_lq56_x,
27873     0,
27874     Opcode_ae_lq56_x_encode_fns, 0, 0 },
27875   { "ae_lq56.xu", ICLASS_ae_iclass_lq56_xu,
27876     0,
27877     Opcode_ae_lq56_xu_encode_fns, 0, 0 },
27878   { "ae_lq32f.i", ICLASS_ae_iclass_lq32f_i,
27879     0,
27880     Opcode_ae_lq32f_i_encode_fns, 0, 0 },
27881   { "ae_lq32f.iu", ICLASS_ae_iclass_lq32f_iu,
27882     0,
27883     Opcode_ae_lq32f_iu_encode_fns, 0, 0 },
27884   { "ae_lq32f.x", ICLASS_ae_iclass_lq32f_x,
27885     0,
27886     Opcode_ae_lq32f_x_encode_fns, 0, 0 },
27887   { "ae_lq32f.xu", ICLASS_ae_iclass_lq32f_xu,
27888     0,
27889     Opcode_ae_lq32f_xu_encode_fns, 0, 0 },
27890   { "ae_sq56s.i", ICLASS_ae_iclass_sq56s_i,
27891     0,
27892     Opcode_ae_sq56s_i_encode_fns, 0, 0 },
27893   { "ae_sq56s.iu", ICLASS_ae_iclass_sq56s_iu,
27894     0,
27895     Opcode_ae_sq56s_iu_encode_fns, 0, 0 },
27896   { "ae_sq56s.x", ICLASS_ae_iclass_sq56s_x,
27897     0,
27898     Opcode_ae_sq56s_x_encode_fns, 0, 0 },
27899   { "ae_sq56s.xu", ICLASS_ae_iclass_sq56s_xu,
27900     0,
27901     Opcode_ae_sq56s_xu_encode_fns, 0, 0 },
27902   { "ae_sq32f.i", ICLASS_ae_iclass_sq32f_i,
27903     0,
27904     Opcode_ae_sq32f_i_encode_fns, 0, 0 },
27905   { "ae_sq32f.iu", ICLASS_ae_iclass_sq32f_iu,
27906     0,
27907     Opcode_ae_sq32f_iu_encode_fns, 0, 0 },
27908   { "ae_sq32f.x", ICLASS_ae_iclass_sq32f_x,
27909     0,
27910     Opcode_ae_sq32f_x_encode_fns, 0, 0 },
27911   { "ae_sq32f.xu", ICLASS_ae_iclass_sq32f_xu,
27912     0,
27913     Opcode_ae_sq32f_xu_encode_fns, 0, 0 },
27914   { "ae_zerop48", ICLASS_ae_iclass_zerop48,
27915     0,
27916     Opcode_ae_zerop48_encode_fns, 0, 0 },
27917   { "ae_movp48", ICLASS_ae_iclass_movp48,
27918     0,
27919     Opcode_ae_movp48_encode_fns, 0, 0 },
27920   { "ae_selp24.ll", ICLASS_ae_iclass_selp24_ll,
27921     0,
27922     Opcode_ae_selp24_ll_encode_fns, 0, 0 },
27923   { "ae_selp24.lh", ICLASS_ae_iclass_selp24_lh,
27924     0,
27925     Opcode_ae_selp24_lh_encode_fns, 0, 0 },
27926   { "ae_selp24.hl", ICLASS_ae_iclass_selp24_hl,
27927     0,
27928     Opcode_ae_selp24_hl_encode_fns, 0, 0 },
27929   { "ae_selp24.hh", ICLASS_ae_iclass_selp24_hh,
27930     0,
27931     Opcode_ae_selp24_hh_encode_fns, 0, 0 },
27932   { "ae_movtp24x2", ICLASS_ae_iclass_movtp24x2,
27933     0,
27934     Opcode_ae_movtp24x2_encode_fns, 0, 0 },
27935   { "ae_movfp24x2", ICLASS_ae_iclass_movfp24x2,
27936     0,
27937     Opcode_ae_movfp24x2_encode_fns, 0, 0 },
27938   { "ae_movtp48", ICLASS_ae_iclass_movtp48,
27939     0,
27940     Opcode_ae_movtp48_encode_fns, 0, 0 },
27941   { "ae_movfp48", ICLASS_ae_iclass_movfp48,
27942     0,
27943     Opcode_ae_movfp48_encode_fns, 0, 0 },
27944   { "ae_movpa24x2", ICLASS_ae_iclass_movpa24x2,
27945     0,
27946     Opcode_ae_movpa24x2_encode_fns, 0, 0 },
27947   { "ae_truncp24a32x2", ICLASS_ae_iclass_truncp24a32x2,
27948     0,
27949     Opcode_ae_truncp24a32x2_encode_fns, 0, 0 },
27950   { "ae_cvta32p24.l", ICLASS_ae_iclass_cvta32p24_l,
27951     0,
27952     Opcode_ae_cvta32p24_l_encode_fns, 0, 0 },
27953   { "ae_cvta32p24.h", ICLASS_ae_iclass_cvta32p24_h,
27954     0,
27955     Opcode_ae_cvta32p24_h_encode_fns, 0, 0 },
27956   { "ae_cvtp24a16x2.ll", ICLASS_ae_iclass_cvtp24a16x2_ll,
27957     0,
27958     Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 },
27959   { "ae_cvtp24a16x2.lh", ICLASS_ae_iclass_cvtp24a16x2_lh,
27960     0,
27961     Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 },
27962   { "ae_cvtp24a16x2.hl", ICLASS_ae_iclass_cvtp24a16x2_hl,
27963     0,
27964     Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 },
27965   { "ae_cvtp24a16x2.hh", ICLASS_ae_iclass_cvtp24a16x2_hh,
27966     0,
27967     Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 },
27968   { "ae_truncp24q48x2", ICLASS_ae_iclass_truncp24q48x2,
27969     0,
27970     Opcode_ae_truncp24q48x2_encode_fns, 0, 0 },
27971   { "ae_truncp16", ICLASS_ae_iclass_truncp16,
27972     0,
27973     Opcode_ae_truncp16_encode_fns, 0, 0 },
27974   { "ae_roundsp24q48sym", ICLASS_ae_iclass_roundsp24q48sym,
27975     0,
27976     Opcode_ae_roundsp24q48sym_encode_fns, 0, 0 },
27977   { "ae_roundsp24q48asym", ICLASS_ae_iclass_roundsp24q48asym,
27978     0,
27979     Opcode_ae_roundsp24q48asym_encode_fns, 0, 0 },
27980   { "ae_roundsp16q48sym", ICLASS_ae_iclass_roundsp16q48sym,
27981     0,
27982     Opcode_ae_roundsp16q48sym_encode_fns, 0, 0 },
27983   { "ae_roundsp16q48asym", ICLASS_ae_iclass_roundsp16q48asym,
27984     0,
27985     Opcode_ae_roundsp16q48asym_encode_fns, 0, 0 },
27986   { "ae_roundsp16sym", ICLASS_ae_iclass_roundsp16sym,
27987     0,
27988     Opcode_ae_roundsp16sym_encode_fns, 0, 0 },
27989   { "ae_roundsp16asym", ICLASS_ae_iclass_roundsp16asym,
27990     0,
27991     Opcode_ae_roundsp16asym_encode_fns, 0, 0 },
27992   { "ae_zeroq56", ICLASS_ae_iclass_zeroq56,
27993     0,
27994     Opcode_ae_zeroq56_encode_fns, 0, 0 },
27995   { "ae_movq56", ICLASS_ae_iclass_movq56,
27996     0,
27997     Opcode_ae_movq56_encode_fns, 0, 0 },
27998   { "ae_movtq56", ICLASS_ae_iclass_movtq56,
27999     0,
28000     Opcode_ae_movtq56_encode_fns, 0, 0 },
28001   { "ae_movfq56", ICLASS_ae_iclass_movfq56,
28002     0,
28003     Opcode_ae_movfq56_encode_fns, 0, 0 },
28004   { "ae_cvtq48a32s", ICLASS_ae_iclass_cvtq48a32s,
28005     0,
28006     Opcode_ae_cvtq48a32s_encode_fns, 0, 0 },
28007   { "ae_cvtq48p24s.l", ICLASS_ae_iclass_cvtq48p24s_l,
28008     0,
28009     Opcode_ae_cvtq48p24s_l_encode_fns, 0, 0 },
28010   { "ae_cvtq48p24s.h", ICLASS_ae_iclass_cvtq48p24s_h,
28011     0,
28012     Opcode_ae_cvtq48p24s_h_encode_fns, 0, 0 },
28013   { "ae_satq48s", ICLASS_ae_iclass_satq48s,
28014     0,
28015     Opcode_ae_satq48s_encode_fns, 0, 0 },
28016   { "ae_truncq32", ICLASS_ae_iclass_truncq32,
28017     0,
28018     Opcode_ae_truncq32_encode_fns, 0, 0 },
28019   { "ae_roundsq32sym", ICLASS_ae_iclass_roundsq32sym,
28020     0,
28021     Opcode_ae_roundsq32sym_encode_fns, 0, 0 },
28022   { "ae_roundsq32asym", ICLASS_ae_iclass_roundsq32asym,
28023     0,
28024     Opcode_ae_roundsq32asym_encode_fns, 0, 0 },
28025   { "ae_trunca32q48", ICLASS_ae_iclass_trunca32q48,
28026     0,
28027     Opcode_ae_trunca32q48_encode_fns, 0, 0 },
28028   { "ae_movap24s.l", ICLASS_ae_iclass_movap24s_l,
28029     0,
28030     Opcode_ae_movap24s_l_encode_fns, 0, 0 },
28031   { "ae_movap24s.h", ICLASS_ae_iclass_movap24s_h,
28032     0,
28033     Opcode_ae_movap24s_h_encode_fns, 0, 0 },
28034   { "ae_trunca16p24s.l", ICLASS_ae_iclass_trunca16p24s_l,
28035     0,
28036     Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 },
28037   { "ae_trunca16p24s.h", ICLASS_ae_iclass_trunca16p24s_h,
28038     0,
28039     Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 },
28040   { "ae_addp24", ICLASS_ae_iclass_addp24,
28041     0,
28042     Opcode_ae_addp24_encode_fns, 0, 0 },
28043   { "ae_subp24", ICLASS_ae_iclass_subp24,
28044     0,
28045     Opcode_ae_subp24_encode_fns, 0, 0 },
28046   { "ae_negp24", ICLASS_ae_iclass_negp24,
28047     0,
28048     Opcode_ae_negp24_encode_fns, 0, 0 },
28049   { "ae_absp24", ICLASS_ae_iclass_absp24,
28050     0,
28051     Opcode_ae_absp24_encode_fns, 0, 0 },
28052   { "ae_maxp24s", ICLASS_ae_iclass_maxp24s,
28053     0,
28054     Opcode_ae_maxp24s_encode_fns, 0, 0 },
28055   { "ae_minp24s", ICLASS_ae_iclass_minp24s,
28056     0,
28057     Opcode_ae_minp24s_encode_fns, 0, 0 },
28058   { "ae_maxbp24s", ICLASS_ae_iclass_maxbp24s,
28059     0,
28060     Opcode_ae_maxbp24s_encode_fns, 0, 0 },
28061   { "ae_minbp24s", ICLASS_ae_iclass_minbp24s,
28062     0,
28063     Opcode_ae_minbp24s_encode_fns, 0, 0 },
28064   { "ae_addsp24s", ICLASS_ae_iclass_addsp24s,
28065     0,
28066     Opcode_ae_addsp24s_encode_fns, 0, 0 },
28067   { "ae_subsp24s", ICLASS_ae_iclass_subsp24s,
28068     0,
28069     Opcode_ae_subsp24s_encode_fns, 0, 0 },
28070   { "ae_negsp24s", ICLASS_ae_iclass_negsp24s,
28071     0,
28072     Opcode_ae_negsp24s_encode_fns, 0, 0 },
28073   { "ae_abssp24s", ICLASS_ae_iclass_abssp24s,
28074     0,
28075     Opcode_ae_abssp24s_encode_fns, 0, 0 },
28076   { "ae_andp48", ICLASS_ae_iclass_andp48,
28077     0,
28078     Opcode_ae_andp48_encode_fns, 0, 0 },
28079   { "ae_nandp48", ICLASS_ae_iclass_nandp48,
28080     0,
28081     Opcode_ae_nandp48_encode_fns, 0, 0 },
28082   { "ae_orp48", ICLASS_ae_iclass_orp48,
28083     0,
28084     Opcode_ae_orp48_encode_fns, 0, 0 },
28085   { "ae_xorp48", ICLASS_ae_iclass_xorp48,
28086     0,
28087     Opcode_ae_xorp48_encode_fns, 0, 0 },
28088   { "ae_ltp24s", ICLASS_ae_iclass_ltp24s,
28089     0,
28090     Opcode_ae_ltp24s_encode_fns, 0, 0 },
28091   { "ae_lep24s", ICLASS_ae_iclass_lep24s,
28092     0,
28093     Opcode_ae_lep24s_encode_fns, 0, 0 },
28094   { "ae_eqp24", ICLASS_ae_iclass_eqp24,
28095     0,
28096     Opcode_ae_eqp24_encode_fns, 0, 0 },
28097   { "ae_addq56", ICLASS_ae_iclass_addq56,
28098     0,
28099     Opcode_ae_addq56_encode_fns, 0, 0 },
28100   { "ae_subq56", ICLASS_ae_iclass_subq56,
28101     0,
28102     Opcode_ae_subq56_encode_fns, 0, 0 },
28103   { "ae_negq56", ICLASS_ae_iclass_negq56,
28104     0,
28105     Opcode_ae_negq56_encode_fns, 0, 0 },
28106   { "ae_absq56", ICLASS_ae_iclass_absq56,
28107     0,
28108     Opcode_ae_absq56_encode_fns, 0, 0 },
28109   { "ae_maxq56s", ICLASS_ae_iclass_maxq56s,
28110     0,
28111     Opcode_ae_maxq56s_encode_fns, 0, 0 },
28112   { "ae_minq56s", ICLASS_ae_iclass_minq56s,
28113     0,
28114     Opcode_ae_minq56s_encode_fns, 0, 0 },
28115   { "ae_maxbq56s", ICLASS_ae_iclass_maxbq56s,
28116     0,
28117     Opcode_ae_maxbq56s_encode_fns, 0, 0 },
28118   { "ae_minbq56s", ICLASS_ae_iclass_minbq56s,
28119     0,
28120     Opcode_ae_minbq56s_encode_fns, 0, 0 },
28121   { "ae_addsq56s", ICLASS_ae_iclass_addsq56s,
28122     0,
28123     Opcode_ae_addsq56s_encode_fns, 0, 0 },
28124   { "ae_subsq56s", ICLASS_ae_iclass_subsq56s,
28125     0,
28126     Opcode_ae_subsq56s_encode_fns, 0, 0 },
28127   { "ae_negsq56s", ICLASS_ae_iclass_negsq56s,
28128     0,
28129     Opcode_ae_negsq56s_encode_fns, 0, 0 },
28130   { "ae_abssq56s", ICLASS_ae_iclass_abssq56s,
28131     0,
28132     Opcode_ae_abssq56s_encode_fns, 0, 0 },
28133   { "ae_andq56", ICLASS_ae_iclass_andq56,
28134     0,
28135     Opcode_ae_andq56_encode_fns, 0, 0 },
28136   { "ae_nandq56", ICLASS_ae_iclass_nandq56,
28137     0,
28138     Opcode_ae_nandq56_encode_fns, 0, 0 },
28139   { "ae_orq56", ICLASS_ae_iclass_orq56,
28140     0,
28141     Opcode_ae_orq56_encode_fns, 0, 0 },
28142   { "ae_xorq56", ICLASS_ae_iclass_xorq56,
28143     0,
28144     Opcode_ae_xorq56_encode_fns, 0, 0 },
28145   { "ae_sllip24", ICLASS_ae_iclass_sllip24,
28146     0,
28147     Opcode_ae_sllip24_encode_fns, 0, 0 },
28148   { "ae_srlip24", ICLASS_ae_iclass_srlip24,
28149     0,
28150     Opcode_ae_srlip24_encode_fns, 0, 0 },
28151   { "ae_sraip24", ICLASS_ae_iclass_sraip24,
28152     0,
28153     Opcode_ae_sraip24_encode_fns, 0, 0 },
28154   { "ae_sllsp24", ICLASS_ae_iclass_sllsp24,
28155     0,
28156     Opcode_ae_sllsp24_encode_fns, 0, 0 },
28157   { "ae_srlsp24", ICLASS_ae_iclass_srlsp24,
28158     0,
28159     Opcode_ae_srlsp24_encode_fns, 0, 0 },
28160   { "ae_srasp24", ICLASS_ae_iclass_srasp24,
28161     0,
28162     Opcode_ae_srasp24_encode_fns, 0, 0 },
28163   { "ae_sllisp24s", ICLASS_ae_iclass_sllisp24s,
28164     0,
28165     Opcode_ae_sllisp24s_encode_fns, 0, 0 },
28166   { "ae_sllssp24s", ICLASS_ae_iclass_sllssp24s,
28167     0,
28168     Opcode_ae_sllssp24s_encode_fns, 0, 0 },
28169   { "ae_slliq56", ICLASS_ae_iclass_slliq56,
28170     0,
28171     Opcode_ae_slliq56_encode_fns, 0, 0 },
28172   { "ae_srliq56", ICLASS_ae_iclass_srliq56,
28173     0,
28174     Opcode_ae_srliq56_encode_fns, 0, 0 },
28175   { "ae_sraiq56", ICLASS_ae_iclass_sraiq56,
28176     0,
28177     Opcode_ae_sraiq56_encode_fns, 0, 0 },
28178   { "ae_sllsq56", ICLASS_ae_iclass_sllsq56,
28179     0,
28180     Opcode_ae_sllsq56_encode_fns, 0, 0 },
28181   { "ae_srlsq56", ICLASS_ae_iclass_srlsq56,
28182     0,
28183     Opcode_ae_srlsq56_encode_fns, 0, 0 },
28184   { "ae_srasq56", ICLASS_ae_iclass_srasq56,
28185     0,
28186     Opcode_ae_srasq56_encode_fns, 0, 0 },
28187   { "ae_sllaq56", ICLASS_ae_iclass_sllaq56,
28188     0,
28189     Opcode_ae_sllaq56_encode_fns, 0, 0 },
28190   { "ae_srlaq56", ICLASS_ae_iclass_srlaq56,
28191     0,
28192     Opcode_ae_srlaq56_encode_fns, 0, 0 },
28193   { "ae_sraaq56", ICLASS_ae_iclass_sraaq56,
28194     0,
28195     Opcode_ae_sraaq56_encode_fns, 0, 0 },
28196   { "ae_sllisq56s", ICLASS_ae_iclass_sllisq56s,
28197     0,
28198     Opcode_ae_sllisq56s_encode_fns, 0, 0 },
28199   { "ae_sllssq56s", ICLASS_ae_iclass_sllssq56s,
28200     0,
28201     Opcode_ae_sllssq56s_encode_fns, 0, 0 },
28202   { "ae_sllasq56s", ICLASS_ae_iclass_sllasq56s,
28203     0,
28204     Opcode_ae_sllasq56s_encode_fns, 0, 0 },
28205   { "ae_ltq56s", ICLASS_ae_iclass_ltq56s,
28206     0,
28207     Opcode_ae_ltq56s_encode_fns, 0, 0 },
28208   { "ae_leq56s", ICLASS_ae_iclass_leq56s,
28209     0,
28210     Opcode_ae_leq56s_encode_fns, 0, 0 },
28211   { "ae_eqq56", ICLASS_ae_iclass_eqq56,
28212     0,
28213     Opcode_ae_eqq56_encode_fns, 0, 0 },
28214   { "ae_nsaq56s", ICLASS_ae_iclass_nsaq56s,
28215     0,
28216     Opcode_ae_nsaq56s_encode_fns, 0, 0 },
28217   { "ae_mulfs32p16s.ll", ICLASS_ae_iclass_mulfs32p16s_ll,
28218     0,
28219     Opcode_ae_mulfs32p16s_ll_encode_fns, 0, 0 },
28220   { "ae_mulfp24s.ll", ICLASS_ae_iclass_mulfp24s_ll,
28221     0,
28222     Opcode_ae_mulfp24s_ll_encode_fns, 0, 0 },
28223   { "ae_mulp24s.ll", ICLASS_ae_iclass_mulp24s_ll,
28224     0,
28225     Opcode_ae_mulp24s_ll_encode_fns, 0, 0 },
28226   { "ae_mulfs32p16s.lh", ICLASS_ae_iclass_mulfs32p16s_lh,
28227     0,
28228     Opcode_ae_mulfs32p16s_lh_encode_fns, 0, 0 },
28229   { "ae_mulfp24s.lh", ICLASS_ae_iclass_mulfp24s_lh,
28230     0,
28231     Opcode_ae_mulfp24s_lh_encode_fns, 0, 0 },
28232   { "ae_mulp24s.lh", ICLASS_ae_iclass_mulp24s_lh,
28233     0,
28234     Opcode_ae_mulp24s_lh_encode_fns, 0, 0 },
28235   { "ae_mulfs32p16s.hl", ICLASS_ae_iclass_mulfs32p16s_hl,
28236     0,
28237     Opcode_ae_mulfs32p16s_hl_encode_fns, 0, 0 },
28238   { "ae_mulfp24s.hl", ICLASS_ae_iclass_mulfp24s_hl,
28239     0,
28240     Opcode_ae_mulfp24s_hl_encode_fns, 0, 0 },
28241   { "ae_mulp24s.hl", ICLASS_ae_iclass_mulp24s_hl,
28242     0,
28243     Opcode_ae_mulp24s_hl_encode_fns, 0, 0 },
28244   { "ae_mulfs32p16s.hh", ICLASS_ae_iclass_mulfs32p16s_hh,
28245     0,
28246     Opcode_ae_mulfs32p16s_hh_encode_fns, 0, 0 },
28247   { "ae_mulfp24s.hh", ICLASS_ae_iclass_mulfp24s_hh,
28248     0,
28249     Opcode_ae_mulfp24s_hh_encode_fns, 0, 0 },
28250   { "ae_mulp24s.hh", ICLASS_ae_iclass_mulp24s_hh,
28251     0,
28252     Opcode_ae_mulp24s_hh_encode_fns, 0, 0 },
28253   { "ae_mulafs32p16s.ll", ICLASS_ae_iclass_mulafs32p16s_ll,
28254     0,
28255     Opcode_ae_mulafs32p16s_ll_encode_fns, 0, 0 },
28256   { "ae_mulafp24s.ll", ICLASS_ae_iclass_mulafp24s_ll,
28257     0,
28258     Opcode_ae_mulafp24s_ll_encode_fns, 0, 0 },
28259   { "ae_mulap24s.ll", ICLASS_ae_iclass_mulap24s_ll,
28260     0,
28261     Opcode_ae_mulap24s_ll_encode_fns, 0, 0 },
28262   { "ae_mulafs32p16s.lh", ICLASS_ae_iclass_mulafs32p16s_lh,
28263     0,
28264     Opcode_ae_mulafs32p16s_lh_encode_fns, 0, 0 },
28265   { "ae_mulafp24s.lh", ICLASS_ae_iclass_mulafp24s_lh,
28266     0,
28267     Opcode_ae_mulafp24s_lh_encode_fns, 0, 0 },
28268   { "ae_mulap24s.lh", ICLASS_ae_iclass_mulap24s_lh,
28269     0,
28270     Opcode_ae_mulap24s_lh_encode_fns, 0, 0 },
28271   { "ae_mulafs32p16s.hl", ICLASS_ae_iclass_mulafs32p16s_hl,
28272     0,
28273     Opcode_ae_mulafs32p16s_hl_encode_fns, 0, 0 },
28274   { "ae_mulafp24s.hl", ICLASS_ae_iclass_mulafp24s_hl,
28275     0,
28276     Opcode_ae_mulafp24s_hl_encode_fns, 0, 0 },
28277   { "ae_mulap24s.hl", ICLASS_ae_iclass_mulap24s_hl,
28278     0,
28279     Opcode_ae_mulap24s_hl_encode_fns, 0, 0 },
28280   { "ae_mulafs32p16s.hh", ICLASS_ae_iclass_mulafs32p16s_hh,
28281     0,
28282     Opcode_ae_mulafs32p16s_hh_encode_fns, 0, 0 },
28283   { "ae_mulafp24s.hh", ICLASS_ae_iclass_mulafp24s_hh,
28284     0,
28285     Opcode_ae_mulafp24s_hh_encode_fns, 0, 0 },
28286   { "ae_mulap24s.hh", ICLASS_ae_iclass_mulap24s_hh,
28287     0,
28288     Opcode_ae_mulap24s_hh_encode_fns, 0, 0 },
28289   { "ae_mulsfs32p16s.ll", ICLASS_ae_iclass_mulsfs32p16s_ll,
28290     0,
28291     Opcode_ae_mulsfs32p16s_ll_encode_fns, 0, 0 },
28292   { "ae_mulsfp24s.ll", ICLASS_ae_iclass_mulsfp24s_ll,
28293     0,
28294     Opcode_ae_mulsfp24s_ll_encode_fns, 0, 0 },
28295   { "ae_mulsp24s.ll", ICLASS_ae_iclass_mulsp24s_ll,
28296     0,
28297     Opcode_ae_mulsp24s_ll_encode_fns, 0, 0 },
28298   { "ae_mulsfs32p16s.lh", ICLASS_ae_iclass_mulsfs32p16s_lh,
28299     0,
28300     Opcode_ae_mulsfs32p16s_lh_encode_fns, 0, 0 },
28301   { "ae_mulsfp24s.lh", ICLASS_ae_iclass_mulsfp24s_lh,
28302     0,
28303     Opcode_ae_mulsfp24s_lh_encode_fns, 0, 0 },
28304   { "ae_mulsp24s.lh", ICLASS_ae_iclass_mulsp24s_lh,
28305     0,
28306     Opcode_ae_mulsp24s_lh_encode_fns, 0, 0 },
28307   { "ae_mulsfs32p16s.hl", ICLASS_ae_iclass_mulsfs32p16s_hl,
28308     0,
28309     Opcode_ae_mulsfs32p16s_hl_encode_fns, 0, 0 },
28310   { "ae_mulsfp24s.hl", ICLASS_ae_iclass_mulsfp24s_hl,
28311     0,
28312     Opcode_ae_mulsfp24s_hl_encode_fns, 0, 0 },
28313   { "ae_mulsp24s.hl", ICLASS_ae_iclass_mulsp24s_hl,
28314     0,
28315     Opcode_ae_mulsp24s_hl_encode_fns, 0, 0 },
28316   { "ae_mulsfs32p16s.hh", ICLASS_ae_iclass_mulsfs32p16s_hh,
28317     0,
28318     Opcode_ae_mulsfs32p16s_hh_encode_fns, 0, 0 },
28319   { "ae_mulsfp24s.hh", ICLASS_ae_iclass_mulsfp24s_hh,
28320     0,
28321     Opcode_ae_mulsfp24s_hh_encode_fns, 0, 0 },
28322   { "ae_mulsp24s.hh", ICLASS_ae_iclass_mulsp24s_hh,
28323     0,
28324     Opcode_ae_mulsp24s_hh_encode_fns, 0, 0 },
28325   { "ae_mulafs56p24s.ll", ICLASS_ae_iclass_mulafs56p24s_ll,
28326     0,
28327     Opcode_ae_mulafs56p24s_ll_encode_fns, 0, 0 },
28328   { "ae_mulas56p24s.ll", ICLASS_ae_iclass_mulas56p24s_ll,
28329     0,
28330     Opcode_ae_mulas56p24s_ll_encode_fns, 0, 0 },
28331   { "ae_mulafs56p24s.lh", ICLASS_ae_iclass_mulafs56p24s_lh,
28332     0,
28333     Opcode_ae_mulafs56p24s_lh_encode_fns, 0, 0 },
28334   { "ae_mulas56p24s.lh", ICLASS_ae_iclass_mulas56p24s_lh,
28335     0,
28336     Opcode_ae_mulas56p24s_lh_encode_fns, 0, 0 },
28337   { "ae_mulafs56p24s.hl", ICLASS_ae_iclass_mulafs56p24s_hl,
28338     0,
28339     Opcode_ae_mulafs56p24s_hl_encode_fns, 0, 0 },
28340   { "ae_mulas56p24s.hl", ICLASS_ae_iclass_mulas56p24s_hl,
28341     0,
28342     Opcode_ae_mulas56p24s_hl_encode_fns, 0, 0 },
28343   { "ae_mulafs56p24s.hh", ICLASS_ae_iclass_mulafs56p24s_hh,
28344     0,
28345     Opcode_ae_mulafs56p24s_hh_encode_fns, 0, 0 },
28346   { "ae_mulas56p24s.hh", ICLASS_ae_iclass_mulas56p24s_hh,
28347     0,
28348     Opcode_ae_mulas56p24s_hh_encode_fns, 0, 0 },
28349   { "ae_mulsfs56p24s.ll", ICLASS_ae_iclass_mulsfs56p24s_ll,
28350     0,
28351     Opcode_ae_mulsfs56p24s_ll_encode_fns, 0, 0 },
28352   { "ae_mulss56p24s.ll", ICLASS_ae_iclass_mulss56p24s_ll,
28353     0,
28354     Opcode_ae_mulss56p24s_ll_encode_fns, 0, 0 },
28355   { "ae_mulsfs56p24s.lh", ICLASS_ae_iclass_mulsfs56p24s_lh,
28356     0,
28357     Opcode_ae_mulsfs56p24s_lh_encode_fns, 0, 0 },
28358   { "ae_mulss56p24s.lh", ICLASS_ae_iclass_mulss56p24s_lh,
28359     0,
28360     Opcode_ae_mulss56p24s_lh_encode_fns, 0, 0 },
28361   { "ae_mulsfs56p24s.hl", ICLASS_ae_iclass_mulsfs56p24s_hl,
28362     0,
28363     Opcode_ae_mulsfs56p24s_hl_encode_fns, 0, 0 },
28364   { "ae_mulss56p24s.hl", ICLASS_ae_iclass_mulss56p24s_hl,
28365     0,
28366     Opcode_ae_mulss56p24s_hl_encode_fns, 0, 0 },
28367   { "ae_mulsfs56p24s.hh", ICLASS_ae_iclass_mulsfs56p24s_hh,
28368     0,
28369     Opcode_ae_mulsfs56p24s_hh_encode_fns, 0, 0 },
28370   { "ae_mulss56p24s.hh", ICLASS_ae_iclass_mulss56p24s_hh,
28371     0,
28372     Opcode_ae_mulss56p24s_hh_encode_fns, 0, 0 },
28373   { "ae_mulfq32sp16s.l", ICLASS_ae_iclass_mulfq32sp16s_l,
28374     0,
28375     Opcode_ae_mulfq32sp16s_l_encode_fns, 0, 0 },
28376   { "ae_mulfq32sp16s.h", ICLASS_ae_iclass_mulfq32sp16s_h,
28377     0,
28378     Opcode_ae_mulfq32sp16s_h_encode_fns, 0, 0 },
28379   { "ae_mulfq32sp16u.l", ICLASS_ae_iclass_mulfq32sp16u_l,
28380     0,
28381     Opcode_ae_mulfq32sp16u_l_encode_fns, 0, 0 },
28382   { "ae_mulfq32sp16u.h", ICLASS_ae_iclass_mulfq32sp16u_h,
28383     0,
28384     Opcode_ae_mulfq32sp16u_h_encode_fns, 0, 0 },
28385   { "ae_mulq32sp16s.l", ICLASS_ae_iclass_mulq32sp16s_l,
28386     0,
28387     Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 },
28388   { "ae_mulq32sp16s.h", ICLASS_ae_iclass_mulq32sp16s_h,
28389     0,
28390     Opcode_ae_mulq32sp16s_h_encode_fns, 0, 0 },
28391   { "ae_mulq32sp16u.l", ICLASS_ae_iclass_mulq32sp16u_l,
28392     0,
28393     Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 },
28394   { "ae_mulq32sp16u.h", ICLASS_ae_iclass_mulq32sp16u_h,
28395     0,
28396     Opcode_ae_mulq32sp16u_h_encode_fns, 0, 0 },
28397   { "ae_mulafq32sp16s.l", ICLASS_ae_iclass_mulafq32sp16s_l,
28398     0,
28399     Opcode_ae_mulafq32sp16s_l_encode_fns, 0, 0 },
28400   { "ae_mulafq32sp16s.h", ICLASS_ae_iclass_mulafq32sp16s_h,
28401     0,
28402     Opcode_ae_mulafq32sp16s_h_encode_fns, 0, 0 },
28403   { "ae_mulafq32sp16u.l", ICLASS_ae_iclass_mulafq32sp16u_l,
28404     0,
28405     Opcode_ae_mulafq32sp16u_l_encode_fns, 0, 0 },
28406   { "ae_mulafq32sp16u.h", ICLASS_ae_iclass_mulafq32sp16u_h,
28407     0,
28408     Opcode_ae_mulafq32sp16u_h_encode_fns, 0, 0 },
28409   { "ae_mulaq32sp16s.l", ICLASS_ae_iclass_mulaq32sp16s_l,
28410     0,
28411     Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 },
28412   { "ae_mulaq32sp16s.h", ICLASS_ae_iclass_mulaq32sp16s_h,
28413     0,
28414     Opcode_ae_mulaq32sp16s_h_encode_fns, 0, 0 },
28415   { "ae_mulaq32sp16u.l", ICLASS_ae_iclass_mulaq32sp16u_l,
28416     0,
28417     Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 },
28418   { "ae_mulaq32sp16u.h", ICLASS_ae_iclass_mulaq32sp16u_h,
28419     0,
28420     Opcode_ae_mulaq32sp16u_h_encode_fns, 0, 0 },
28421   { "ae_mulsfq32sp16s.l", ICLASS_ae_iclass_mulsfq32sp16s_l,
28422     0,
28423     Opcode_ae_mulsfq32sp16s_l_encode_fns, 0, 0 },
28424   { "ae_mulsfq32sp16s.h", ICLASS_ae_iclass_mulsfq32sp16s_h,
28425     0,
28426     Opcode_ae_mulsfq32sp16s_h_encode_fns, 0, 0 },
28427   { "ae_mulsfq32sp16u.l", ICLASS_ae_iclass_mulsfq32sp16u_l,
28428     0,
28429     Opcode_ae_mulsfq32sp16u_l_encode_fns, 0, 0 },
28430   { "ae_mulsfq32sp16u.h", ICLASS_ae_iclass_mulsfq32sp16u_h,
28431     0,
28432     Opcode_ae_mulsfq32sp16u_h_encode_fns, 0, 0 },
28433   { "ae_mulsq32sp16s.l", ICLASS_ae_iclass_mulsq32sp16s_l,
28434     0,
28435     Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 },
28436   { "ae_mulsq32sp16s.h", ICLASS_ae_iclass_mulsq32sp16s_h,
28437     0,
28438     Opcode_ae_mulsq32sp16s_h_encode_fns, 0, 0 },
28439   { "ae_mulsq32sp16u.l", ICLASS_ae_iclass_mulsq32sp16u_l,
28440     0,
28441     Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 },
28442   { "ae_mulsq32sp16u.h", ICLASS_ae_iclass_mulsq32sp16u_h,
28443     0,
28444     Opcode_ae_mulsq32sp16u_h_encode_fns, 0, 0 },
28445   { "ae_mulzaaq32sp16s.ll", ICLASS_ae_iclass_mulzaaq32sp16s_ll,
28446     0,
28447     Opcode_ae_mulzaaq32sp16s_ll_encode_fns, 0, 0 },
28448   { "ae_mulzaafq32sp16s.ll", ICLASS_ae_iclass_mulzaafq32sp16s_ll,
28449     0,
28450     Opcode_ae_mulzaafq32sp16s_ll_encode_fns, 0, 0 },
28451   { "ae_mulzaaq32sp16u.ll", ICLASS_ae_iclass_mulzaaq32sp16u_ll,
28452     0,
28453     Opcode_ae_mulzaaq32sp16u_ll_encode_fns, 0, 0 },
28454   { "ae_mulzaafq32sp16u.ll", ICLASS_ae_iclass_mulzaafq32sp16u_ll,
28455     0,
28456     Opcode_ae_mulzaafq32sp16u_ll_encode_fns, 0, 0 },
28457   { "ae_mulzaaq32sp16s.hh", ICLASS_ae_iclass_mulzaaq32sp16s_hh,
28458     0,
28459     Opcode_ae_mulzaaq32sp16s_hh_encode_fns, 0, 0 },
28460   { "ae_mulzaafq32sp16s.hh", ICLASS_ae_iclass_mulzaafq32sp16s_hh,
28461     0,
28462     Opcode_ae_mulzaafq32sp16s_hh_encode_fns, 0, 0 },
28463   { "ae_mulzaaq32sp16u.hh", ICLASS_ae_iclass_mulzaaq32sp16u_hh,
28464     0,
28465     Opcode_ae_mulzaaq32sp16u_hh_encode_fns, 0, 0 },
28466   { "ae_mulzaafq32sp16u.hh", ICLASS_ae_iclass_mulzaafq32sp16u_hh,
28467     0,
28468     Opcode_ae_mulzaafq32sp16u_hh_encode_fns, 0, 0 },
28469   { "ae_mulzaaq32sp16s.lh", ICLASS_ae_iclass_mulzaaq32sp16s_lh,
28470     0,
28471     Opcode_ae_mulzaaq32sp16s_lh_encode_fns, 0, 0 },
28472   { "ae_mulzaafq32sp16s.lh", ICLASS_ae_iclass_mulzaafq32sp16s_lh,
28473     0,
28474     Opcode_ae_mulzaafq32sp16s_lh_encode_fns, 0, 0 },
28475   { "ae_mulzaaq32sp16u.lh", ICLASS_ae_iclass_mulzaaq32sp16u_lh,
28476     0,
28477     Opcode_ae_mulzaaq32sp16u_lh_encode_fns, 0, 0 },
28478   { "ae_mulzaafq32sp16u.lh", ICLASS_ae_iclass_mulzaafq32sp16u_lh,
28479     0,
28480     Opcode_ae_mulzaafq32sp16u_lh_encode_fns, 0, 0 },
28481   { "ae_mulzasq32sp16s.ll", ICLASS_ae_iclass_mulzasq32sp16s_ll,
28482     0,
28483     Opcode_ae_mulzasq32sp16s_ll_encode_fns, 0, 0 },
28484   { "ae_mulzasfq32sp16s.ll", ICLASS_ae_iclass_mulzasfq32sp16s_ll,
28485     0,
28486     Opcode_ae_mulzasfq32sp16s_ll_encode_fns, 0, 0 },
28487   { "ae_mulzasq32sp16u.ll", ICLASS_ae_iclass_mulzasq32sp16u_ll,
28488     0,
28489     Opcode_ae_mulzasq32sp16u_ll_encode_fns, 0, 0 },
28490   { "ae_mulzasfq32sp16u.ll", ICLASS_ae_iclass_mulzasfq32sp16u_ll,
28491     0,
28492     Opcode_ae_mulzasfq32sp16u_ll_encode_fns, 0, 0 },
28493   { "ae_mulzasq32sp16s.hh", ICLASS_ae_iclass_mulzasq32sp16s_hh,
28494     0,
28495     Opcode_ae_mulzasq32sp16s_hh_encode_fns, 0, 0 },
28496   { "ae_mulzasfq32sp16s.hh", ICLASS_ae_iclass_mulzasfq32sp16s_hh,
28497     0,
28498     Opcode_ae_mulzasfq32sp16s_hh_encode_fns, 0, 0 },
28499   { "ae_mulzasq32sp16u.hh", ICLASS_ae_iclass_mulzasq32sp16u_hh,
28500     0,
28501     Opcode_ae_mulzasq32sp16u_hh_encode_fns, 0, 0 },
28502   { "ae_mulzasfq32sp16u.hh", ICLASS_ae_iclass_mulzasfq32sp16u_hh,
28503     0,
28504     Opcode_ae_mulzasfq32sp16u_hh_encode_fns, 0, 0 },
28505   { "ae_mulzasq32sp16s.lh", ICLASS_ae_iclass_mulzasq32sp16s_lh,
28506     0,
28507     Opcode_ae_mulzasq32sp16s_lh_encode_fns, 0, 0 },
28508   { "ae_mulzasfq32sp16s.lh", ICLASS_ae_iclass_mulzasfq32sp16s_lh,
28509     0,
28510     Opcode_ae_mulzasfq32sp16s_lh_encode_fns, 0, 0 },
28511   { "ae_mulzasq32sp16u.lh", ICLASS_ae_iclass_mulzasq32sp16u_lh,
28512     0,
28513     Opcode_ae_mulzasq32sp16u_lh_encode_fns, 0, 0 },
28514   { "ae_mulzasfq32sp16u.lh", ICLASS_ae_iclass_mulzasfq32sp16u_lh,
28515     0,
28516     Opcode_ae_mulzasfq32sp16u_lh_encode_fns, 0, 0 },
28517   { "ae_mulzsaq32sp16s.ll", ICLASS_ae_iclass_mulzsaq32sp16s_ll,
28518     0,
28519     Opcode_ae_mulzsaq32sp16s_ll_encode_fns, 0, 0 },
28520   { "ae_mulzsafq32sp16s.ll", ICLASS_ae_iclass_mulzsafq32sp16s_ll,
28521     0,
28522     Opcode_ae_mulzsafq32sp16s_ll_encode_fns, 0, 0 },
28523   { "ae_mulzsaq32sp16u.ll", ICLASS_ae_iclass_mulzsaq32sp16u_ll,
28524     0,
28525     Opcode_ae_mulzsaq32sp16u_ll_encode_fns, 0, 0 },
28526   { "ae_mulzsafq32sp16u.ll", ICLASS_ae_iclass_mulzsafq32sp16u_ll,
28527     0,
28528     Opcode_ae_mulzsafq32sp16u_ll_encode_fns, 0, 0 },
28529   { "ae_mulzsaq32sp16s.hh", ICLASS_ae_iclass_mulzsaq32sp16s_hh,
28530     0,
28531     Opcode_ae_mulzsaq32sp16s_hh_encode_fns, 0, 0 },
28532   { "ae_mulzsafq32sp16s.hh", ICLASS_ae_iclass_mulzsafq32sp16s_hh,
28533     0,
28534     Opcode_ae_mulzsafq32sp16s_hh_encode_fns, 0, 0 },
28535   { "ae_mulzsaq32sp16u.hh", ICLASS_ae_iclass_mulzsaq32sp16u_hh,
28536     0,
28537     Opcode_ae_mulzsaq32sp16u_hh_encode_fns, 0, 0 },
28538   { "ae_mulzsafq32sp16u.hh", ICLASS_ae_iclass_mulzsafq32sp16u_hh,
28539     0,
28540     Opcode_ae_mulzsafq32sp16u_hh_encode_fns, 0, 0 },
28541   { "ae_mulzsaq32sp16s.lh", ICLASS_ae_iclass_mulzsaq32sp16s_lh,
28542     0,
28543     Opcode_ae_mulzsaq32sp16s_lh_encode_fns, 0, 0 },
28544   { "ae_mulzsafq32sp16s.lh", ICLASS_ae_iclass_mulzsafq32sp16s_lh,
28545     0,
28546     Opcode_ae_mulzsafq32sp16s_lh_encode_fns, 0, 0 },
28547   { "ae_mulzsaq32sp16u.lh", ICLASS_ae_iclass_mulzsaq32sp16u_lh,
28548     0,
28549     Opcode_ae_mulzsaq32sp16u_lh_encode_fns, 0, 0 },
28550   { "ae_mulzsafq32sp16u.lh", ICLASS_ae_iclass_mulzsafq32sp16u_lh,
28551     0,
28552     Opcode_ae_mulzsafq32sp16u_lh_encode_fns, 0, 0 },
28553   { "ae_mulzssq32sp16s.ll", ICLASS_ae_iclass_mulzssq32sp16s_ll,
28554     0,
28555     Opcode_ae_mulzssq32sp16s_ll_encode_fns, 0, 0 },
28556   { "ae_mulzssfq32sp16s.ll", ICLASS_ae_iclass_mulzssfq32sp16s_ll,
28557     0,
28558     Opcode_ae_mulzssfq32sp16s_ll_encode_fns, 0, 0 },
28559   { "ae_mulzssq32sp16u.ll", ICLASS_ae_iclass_mulzssq32sp16u_ll,
28560     0,
28561     Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 },
28562   { "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll,
28563     0,
28564     Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 },
28565   { "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh,
28566     0,
28567     Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 },
28568   { "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh,
28569     0,
28570     Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 },
28571   { "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh,
28572     0,
28573     Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 },
28574   { "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh,
28575     0,
28576     Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 },
28577   { "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh,
28578     0,
28579     Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 },
28580   { "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh,
28581     0,
28582     Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 },
28583   { "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh,
28584     0,
28585     Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 },
28586   { "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh,
28587     0,
28588     Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 },
28589   { "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll,
28590     0,
28591     Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 },
28592   { "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll,
28593     0,
28594     Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 },
28595   { "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh,
28596     0,
28597     Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 },
28598   { "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh,
28599     0,
28600     Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 },
28601   { "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll,
28602     0,
28603     Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 },
28604   { "ae_mulzasp24s.hh.ll", ICLASS_ae_iclass_mulzasp24s_hh_ll,
28605     0,
28606     Opcode_ae_mulzasp24s_hh_ll_encode_fns, 0, 0 },
28607   { "ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh,
28608     0,
28609     Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 },
28610   { "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh,
28611     0,
28612     Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 },
28613   { "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll,
28614     0,
28615     Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 },
28616   { "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll,
28617     0,
28618     Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 },
28619   { "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh,
28620     0,
28621     Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 },
28622   { "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh,
28623     0,
28624     Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 },
28625   { "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll,
28626     0,
28627     Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 },
28628   { "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll,
28629     0,
28630     Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 },
28631   { "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh,
28632     0,
28633     Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 },
28634   { "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh,
28635     0,
28636     Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 },
28637   { "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll,
28638     0,
28639     Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 },
28640   { "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll,
28641     0,
28642     Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 },
28643   { "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh,
28644     0,
28645     Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 },
28646   { "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh,
28647     0,
28648     Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 },
28649   { "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll,
28650     0,
28651     Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 },
28652   { "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll,
28653     0,
28654     Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 },
28655   { "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh,
28656     0,
28657     Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 },
28658   { "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh,
28659     0,
28660     Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 },
28661   { "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll,
28662     0,
28663     Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 },
28664   { "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll,
28665     0,
28666     Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 },
28667   { "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh,
28668     0,
28669     Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 },
28670   { "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh,
28671     0,
28672     Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 },
28673   { "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll,
28674     0,
28675     Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 },
28676   { "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll,
28677     0,
28678     Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 },
28679   { "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh,
28680     0,
28681     Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 },
28682   { "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh,
28683     0,
28684     Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 },
28685   { "ae_sha32", ICLASS_ae_iclass_sha32,
28686     0,
28687     Opcode_ae_sha32_encode_fns, 0, 0 },
28688   { "ae_vldl32t", ICLASS_ae_iclass_vldl32t,
28689     0,
28690     Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses },
28691   { "ae_vldl16t", ICLASS_ae_iclass_vldl16t,
28692     0,
28693     Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses },
28694   { "ae_vldl16c", ICLASS_ae_iclass_vldl16c,
28695     0,
28696     Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses },
28697   { "ae_vldsht", ICLASS_ae_iclass_vldsht,
28698     0,
28699     Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses },
28700   { "ae_lb", ICLASS_ae_iclass_lb,
28701     0,
28702     Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses },
28703   { "ae_lbi", ICLASS_ae_iclass_lbi,
28704     0,
28705     Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses },
28706   { "ae_lbk", ICLASS_ae_iclass_lbk,
28707     0,
28708     Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses },
28709   { "ae_lbki", ICLASS_ae_iclass_lbki,
28710     0,
28711     Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses },
28712   { "ae_db", ICLASS_ae_iclass_db,
28713     0,
28714     Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses },
28715   { "ae_dbi", ICLASS_ae_iclass_dbi,
28716     0,
28717     Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses },
28718   { "ae_vlel32t", ICLASS_ae_iclass_vlel32t,
28719     0,
28720     Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses },
28721   { "ae_vlel16t", ICLASS_ae_iclass_vlel16t,
28722     0,
28723     Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses },
28724   { "ae_sb", ICLASS_ae_iclass_sb,
28725     0,
28726     Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses },
28727   { "ae_sbi", ICLASS_ae_iclass_sbi,
28728     0,
28729     Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses },
28730   { "ae_vles16c", ICLASS_ae_iclass_vles16c,
28731     0,
28732     Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses },
28733   { "ae_sbf", ICLASS_ae_iclass_sbf,
28734     0,
28735     Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses }
28736 };
28737
28738 enum xtensa_opcode_id {
28739   OPCODE_EXCW,
28740   OPCODE_RFE,
28741   OPCODE_RFDE,
28742   OPCODE_SYSCALL,
28743   OPCODE_CALL12,
28744   OPCODE_CALL8,
28745   OPCODE_CALL4,
28746   OPCODE_CALLX12,
28747   OPCODE_CALLX8,
28748   OPCODE_CALLX4,
28749   OPCODE_ENTRY,
28750   OPCODE_MOVSP,
28751   OPCODE_ROTW,
28752   OPCODE_RETW,
28753   OPCODE_RETW_N,
28754   OPCODE_RFWO,
28755   OPCODE_RFWU,
28756   OPCODE_L32E,
28757   OPCODE_S32E,
28758   OPCODE_RSR_WINDOWBASE,
28759   OPCODE_WSR_WINDOWBASE,
28760   OPCODE_XSR_WINDOWBASE,
28761   OPCODE_RSR_WINDOWSTART,
28762   OPCODE_WSR_WINDOWSTART,
28763   OPCODE_XSR_WINDOWSTART,
28764   OPCODE_ADD_N,
28765   OPCODE_ADDI_N,
28766   OPCODE_BEQZ_N,
28767   OPCODE_BNEZ_N,
28768   OPCODE_ILL_N,
28769   OPCODE_L32I_N,
28770   OPCODE_MOV_N,
28771   OPCODE_MOVI_N,
28772   OPCODE_NOP_N,
28773   OPCODE_RET_N,
28774   OPCODE_S32I_N,
28775   OPCODE_RUR_THREADPTR,
28776   OPCODE_WUR_THREADPTR,
28777   OPCODE_ADDI,
28778   OPCODE_ADDMI,
28779   OPCODE_ADD,
28780   OPCODE_SUB,
28781   OPCODE_ADDX2,
28782   OPCODE_ADDX4,
28783   OPCODE_ADDX8,
28784   OPCODE_SUBX2,
28785   OPCODE_SUBX4,
28786   OPCODE_SUBX8,
28787   OPCODE_AND,
28788   OPCODE_OR,
28789   OPCODE_XOR,
28790   OPCODE_BEQI,
28791   OPCODE_BNEI,
28792   OPCODE_BGEI,
28793   OPCODE_BLTI,
28794   OPCODE_BBCI,
28795   OPCODE_BBSI,
28796   OPCODE_BGEUI,
28797   OPCODE_BLTUI,
28798   OPCODE_BEQ,
28799   OPCODE_BNE,
28800   OPCODE_BGE,
28801   OPCODE_BLT,
28802   OPCODE_BGEU,
28803   OPCODE_BLTU,
28804   OPCODE_BANY,
28805   OPCODE_BNONE,
28806   OPCODE_BALL,
28807   OPCODE_BNALL,
28808   OPCODE_BBC,
28809   OPCODE_BBS,
28810   OPCODE_BEQZ,
28811   OPCODE_BNEZ,
28812   OPCODE_BGEZ,
28813   OPCODE_BLTZ,
28814   OPCODE_CALL0,
28815   OPCODE_CALLX0,
28816   OPCODE_EXTUI,
28817   OPCODE_ILL,
28818   OPCODE_J,
28819   OPCODE_JX,
28820   OPCODE_L16UI,
28821   OPCODE_L16SI,
28822   OPCODE_L32I,
28823   OPCODE_L32R,
28824   OPCODE_L8UI,
28825   OPCODE_LOOP,
28826   OPCODE_LOOPNEZ,
28827   OPCODE_LOOPGTZ,
28828   OPCODE_MOVI,
28829   OPCODE_MOVEQZ,
28830   OPCODE_MOVNEZ,
28831   OPCODE_MOVLTZ,
28832   OPCODE_MOVGEZ,
28833   OPCODE_NEG,
28834   OPCODE_ABS,
28835   OPCODE_NOP,
28836   OPCODE_RET,
28837   OPCODE_SIMCALL,
28838   OPCODE_S16I,
28839   OPCODE_S32I,
28840   OPCODE_S8I,
28841   OPCODE_SSR,
28842   OPCODE_SSL,
28843   OPCODE_SSA8L,
28844   OPCODE_SSA8B,
28845   OPCODE_SSAI,
28846   OPCODE_SLL,
28847   OPCODE_SRC,
28848   OPCODE_SRL,
28849   OPCODE_SRA,
28850   OPCODE_SLLI,
28851   OPCODE_SRAI,
28852   OPCODE_SRLI,
28853   OPCODE_MEMW,
28854   OPCODE_EXTW,
28855   OPCODE_ISYNC,
28856   OPCODE_RSYNC,
28857   OPCODE_ESYNC,
28858   OPCODE_DSYNC,
28859   OPCODE_RSIL,
28860   OPCODE_RSR_LEND,
28861   OPCODE_WSR_LEND,
28862   OPCODE_XSR_LEND,
28863   OPCODE_RSR_LCOUNT,
28864   OPCODE_WSR_LCOUNT,
28865   OPCODE_XSR_LCOUNT,
28866   OPCODE_RSR_LBEG,
28867   OPCODE_WSR_LBEG,
28868   OPCODE_XSR_LBEG,
28869   OPCODE_RSR_SAR,
28870   OPCODE_WSR_SAR,
28871   OPCODE_XSR_SAR,
28872   OPCODE_RSR_LITBASE,
28873   OPCODE_WSR_LITBASE,
28874   OPCODE_XSR_LITBASE,
28875   OPCODE_RSR_CONFIGID0,
28876   OPCODE_WSR_CONFIGID0,
28877   OPCODE_RSR_CONFIGID1,
28878   OPCODE_RSR_PS,
28879   OPCODE_WSR_PS,
28880   OPCODE_XSR_PS,
28881   OPCODE_RSR_EPC1,
28882   OPCODE_WSR_EPC1,
28883   OPCODE_XSR_EPC1,
28884   OPCODE_RSR_EXCSAVE1,
28885   OPCODE_WSR_EXCSAVE1,
28886   OPCODE_XSR_EXCSAVE1,
28887   OPCODE_RSR_EPC2,
28888   OPCODE_WSR_EPC2,
28889   OPCODE_XSR_EPC2,
28890   OPCODE_RSR_EXCSAVE2,
28891   OPCODE_WSR_EXCSAVE2,
28892   OPCODE_XSR_EXCSAVE2,
28893   OPCODE_RSR_EPS2,
28894   OPCODE_WSR_EPS2,
28895   OPCODE_XSR_EPS2,
28896   OPCODE_RSR_EXCVADDR,
28897   OPCODE_WSR_EXCVADDR,
28898   OPCODE_XSR_EXCVADDR,
28899   OPCODE_RSR_DEPC,
28900   OPCODE_WSR_DEPC,
28901   OPCODE_XSR_DEPC,
28902   OPCODE_RSR_EXCCAUSE,
28903   OPCODE_WSR_EXCCAUSE,
28904   OPCODE_XSR_EXCCAUSE,
28905   OPCODE_RSR_MISC0,
28906   OPCODE_WSR_MISC0,
28907   OPCODE_XSR_MISC0,
28908   OPCODE_RSR_MISC1,
28909   OPCODE_WSR_MISC1,
28910   OPCODE_XSR_MISC1,
28911   OPCODE_RSR_PRID,
28912   OPCODE_RSR_VECBASE,
28913   OPCODE_WSR_VECBASE,
28914   OPCODE_XSR_VECBASE,
28915   OPCODE_MUL16U,
28916   OPCODE_MUL16S,
28917   OPCODE_MULL,
28918   OPCODE_RFI,
28919   OPCODE_WAITI,
28920   OPCODE_RSR_INTERRUPT,
28921   OPCODE_WSR_INTSET,
28922   OPCODE_WSR_INTCLEAR,
28923   OPCODE_RSR_INTENABLE,
28924   OPCODE_WSR_INTENABLE,
28925   OPCODE_XSR_INTENABLE,
28926   OPCODE_BREAK,
28927   OPCODE_BREAK_N,
28928   OPCODE_RSR_DEBUGCAUSE,
28929   OPCODE_WSR_DEBUGCAUSE,
28930   OPCODE_XSR_DEBUGCAUSE,
28931   OPCODE_RSR_ICOUNT,
28932   OPCODE_WSR_ICOUNT,
28933   OPCODE_XSR_ICOUNT,
28934   OPCODE_RSR_ICOUNTLEVEL,
28935   OPCODE_WSR_ICOUNTLEVEL,
28936   OPCODE_XSR_ICOUNTLEVEL,
28937   OPCODE_RSR_DDR,
28938   OPCODE_WSR_DDR,
28939   OPCODE_XSR_DDR,
28940   OPCODE_RFDO,
28941   OPCODE_RFDD,
28942   OPCODE_ANDB,
28943   OPCODE_ANDBC,
28944   OPCODE_ORB,
28945   OPCODE_ORBC,
28946   OPCODE_XORB,
28947   OPCODE_ANY4,
28948   OPCODE_ALL4,
28949   OPCODE_ANY8,
28950   OPCODE_ALL8,
28951   OPCODE_BF,
28952   OPCODE_BT,
28953   OPCODE_MOVF,
28954   OPCODE_MOVT,
28955   OPCODE_RSR_BR,
28956   OPCODE_WSR_BR,
28957   OPCODE_XSR_BR,
28958   OPCODE_RSR_CCOUNT,
28959   OPCODE_WSR_CCOUNT,
28960   OPCODE_XSR_CCOUNT,
28961   OPCODE_RSR_CCOMPARE0,
28962   OPCODE_WSR_CCOMPARE0,
28963   OPCODE_XSR_CCOMPARE0,
28964   OPCODE_RSR_CCOMPARE1,
28965   OPCODE_WSR_CCOMPARE1,
28966   OPCODE_XSR_CCOMPARE1,
28967   OPCODE_IPF,
28968   OPCODE_IHI,
28969   OPCODE_III,
28970   OPCODE_LICT,
28971   OPCODE_LICW,
28972   OPCODE_SICT,
28973   OPCODE_SICW,
28974   OPCODE_DHWB,
28975   OPCODE_DHWBI,
28976   OPCODE_DIWB,
28977   OPCODE_DIWBI,
28978   OPCODE_DHI,
28979   OPCODE_DII,
28980   OPCODE_DPFR,
28981   OPCODE_DPFW,
28982   OPCODE_DPFRO,
28983   OPCODE_DPFWO,
28984   OPCODE_SDCT,
28985   OPCODE_LDCT,
28986   OPCODE_WSR_PTEVADDR,
28987   OPCODE_RSR_PTEVADDR,
28988   OPCODE_XSR_PTEVADDR,
28989   OPCODE_RSR_RASID,
28990   OPCODE_WSR_RASID,
28991   OPCODE_XSR_RASID,
28992   OPCODE_RSR_ITLBCFG,
28993   OPCODE_WSR_ITLBCFG,
28994   OPCODE_XSR_ITLBCFG,
28995   OPCODE_RSR_DTLBCFG,
28996   OPCODE_WSR_DTLBCFG,
28997   OPCODE_XSR_DTLBCFG,
28998   OPCODE_IDTLB,
28999   OPCODE_PDTLB,
29000   OPCODE_RDTLB0,
29001   OPCODE_RDTLB1,
29002   OPCODE_WDTLB,
29003   OPCODE_IITLB,
29004   OPCODE_PITLB,
29005   OPCODE_RITLB0,
29006   OPCODE_RITLB1,
29007   OPCODE_WITLB,
29008   OPCODE_LDPTE,
29009   OPCODE_HWWITLBA,
29010   OPCODE_HWWDTLBA,
29011   OPCODE_RSR_CPENABLE,
29012   OPCODE_WSR_CPENABLE,
29013   OPCODE_XSR_CPENABLE,
29014   OPCODE_CLAMPS,
29015   OPCODE_MIN,
29016   OPCODE_MAX,
29017   OPCODE_MINU,
29018   OPCODE_MAXU,
29019   OPCODE_NSA,
29020   OPCODE_NSAU,
29021   OPCODE_SEXT,
29022   OPCODE_L32AI,
29023   OPCODE_S32RI,
29024   OPCODE_S32C1I,
29025   OPCODE_RSR_SCOMPARE1,
29026   OPCODE_WSR_SCOMPARE1,
29027   OPCODE_XSR_SCOMPARE1,
29028   OPCODE_RSR_ATOMCTL,
29029   OPCODE_WSR_ATOMCTL,
29030   OPCODE_XSR_ATOMCTL,
29031   OPCODE_RER,
29032   OPCODE_WER,
29033   OPCODE_RUR_AE_OVF_SAR,
29034   OPCODE_WUR_AE_OVF_SAR,
29035   OPCODE_RUR_AE_BITHEAD,
29036   OPCODE_WUR_AE_BITHEAD,
29037   OPCODE_RUR_AE_TS_FTS_BU_BP,
29038   OPCODE_WUR_AE_TS_FTS_BU_BP,
29039   OPCODE_RUR_AE_SD_NO,
29040   OPCODE_WUR_AE_SD_NO,
29041   OPCODE_RUR_AE_OVERFLOW,
29042   OPCODE_WUR_AE_OVERFLOW,
29043   OPCODE_RUR_AE_SAR,
29044   OPCODE_WUR_AE_SAR,
29045   OPCODE_RUR_AE_BITPTR,
29046   OPCODE_WUR_AE_BITPTR,
29047   OPCODE_RUR_AE_BITSUSED,
29048   OPCODE_WUR_AE_BITSUSED,
29049   OPCODE_RUR_AE_TABLESIZE,
29050   OPCODE_WUR_AE_TABLESIZE,
29051   OPCODE_RUR_AE_FIRST_TS,
29052   OPCODE_WUR_AE_FIRST_TS,
29053   OPCODE_RUR_AE_NEXTOFFSET,
29054   OPCODE_WUR_AE_NEXTOFFSET,
29055   OPCODE_RUR_AE_SEARCHDONE,
29056   OPCODE_WUR_AE_SEARCHDONE,
29057   OPCODE_AE_LP16F_I,
29058   OPCODE_AE_LP16F_IU,
29059   OPCODE_AE_LP16F_X,
29060   OPCODE_AE_LP16F_XU,
29061   OPCODE_AE_LP24_I,
29062   OPCODE_AE_LP24_IU,
29063   OPCODE_AE_LP24_X,
29064   OPCODE_AE_LP24_XU,
29065   OPCODE_AE_LP24F_I,
29066   OPCODE_AE_LP24F_IU,
29067   OPCODE_AE_LP24F_X,
29068   OPCODE_AE_LP24F_XU,
29069   OPCODE_AE_LP16X2F_I,
29070   OPCODE_AE_LP16X2F_IU,
29071   OPCODE_AE_LP16X2F_X,
29072   OPCODE_AE_LP16X2F_XU,
29073   OPCODE_AE_LP24X2F_I,
29074   OPCODE_AE_LP24X2F_IU,
29075   OPCODE_AE_LP24X2F_X,
29076   OPCODE_AE_LP24X2F_XU,
29077   OPCODE_AE_LP24X2_I,
29078   OPCODE_AE_LP24X2_IU,
29079   OPCODE_AE_LP24X2_X,
29080   OPCODE_AE_LP24X2_XU,
29081   OPCODE_AE_SP16X2F_I,
29082   OPCODE_AE_SP16X2F_IU,
29083   OPCODE_AE_SP16X2F_X,
29084   OPCODE_AE_SP16X2F_XU,
29085   OPCODE_AE_SP24X2S_I,
29086   OPCODE_AE_SP24X2S_IU,
29087   OPCODE_AE_SP24X2S_X,
29088   OPCODE_AE_SP24X2S_XU,
29089   OPCODE_AE_SP24X2F_I,
29090   OPCODE_AE_SP24X2F_IU,
29091   OPCODE_AE_SP24X2F_X,
29092   OPCODE_AE_SP24X2F_XU,
29093   OPCODE_AE_SP16F_L_I,
29094   OPCODE_AE_SP16F_L_IU,
29095   OPCODE_AE_SP16F_L_X,
29096   OPCODE_AE_SP16F_L_XU,
29097   OPCODE_AE_SP24S_L_I,
29098   OPCODE_AE_SP24S_L_IU,
29099   OPCODE_AE_SP24S_L_X,
29100   OPCODE_AE_SP24S_L_XU,
29101   OPCODE_AE_SP24F_L_I,
29102   OPCODE_AE_SP24F_L_IU,
29103   OPCODE_AE_SP24F_L_X,
29104   OPCODE_AE_SP24F_L_XU,
29105   OPCODE_AE_LQ56_I,
29106   OPCODE_AE_LQ56_IU,
29107   OPCODE_AE_LQ56_X,
29108   OPCODE_AE_LQ56_XU,
29109   OPCODE_AE_LQ32F_I,
29110   OPCODE_AE_LQ32F_IU,
29111   OPCODE_AE_LQ32F_X,
29112   OPCODE_AE_LQ32F_XU,
29113   OPCODE_AE_SQ56S_I,
29114   OPCODE_AE_SQ56S_IU,
29115   OPCODE_AE_SQ56S_X,
29116   OPCODE_AE_SQ56S_XU,
29117   OPCODE_AE_SQ32F_I,
29118   OPCODE_AE_SQ32F_IU,
29119   OPCODE_AE_SQ32F_X,
29120   OPCODE_AE_SQ32F_XU,
29121   OPCODE_AE_ZEROP48,
29122   OPCODE_AE_MOVP48,
29123   OPCODE_AE_SELP24_LL,
29124   OPCODE_AE_SELP24_LH,
29125   OPCODE_AE_SELP24_HL,
29126   OPCODE_AE_SELP24_HH,
29127   OPCODE_AE_MOVTP24X2,
29128   OPCODE_AE_MOVFP24X2,
29129   OPCODE_AE_MOVTP48,
29130   OPCODE_AE_MOVFP48,
29131   OPCODE_AE_MOVPA24X2,
29132   OPCODE_AE_TRUNCP24A32X2,
29133   OPCODE_AE_CVTA32P24_L,
29134   OPCODE_AE_CVTA32P24_H,
29135   OPCODE_AE_CVTP24A16X2_LL,
29136   OPCODE_AE_CVTP24A16X2_LH,
29137   OPCODE_AE_CVTP24A16X2_HL,
29138   OPCODE_AE_CVTP24A16X2_HH,
29139   OPCODE_AE_TRUNCP24Q48X2,
29140   OPCODE_AE_TRUNCP16,
29141   OPCODE_AE_ROUNDSP24Q48SYM,
29142   OPCODE_AE_ROUNDSP24Q48ASYM,
29143   OPCODE_AE_ROUNDSP16Q48SYM,
29144   OPCODE_AE_ROUNDSP16Q48ASYM,
29145   OPCODE_AE_ROUNDSP16SYM,
29146   OPCODE_AE_ROUNDSP16ASYM,
29147   OPCODE_AE_ZEROQ56,
29148   OPCODE_AE_MOVQ56,
29149   OPCODE_AE_MOVTQ56,
29150   OPCODE_AE_MOVFQ56,
29151   OPCODE_AE_CVTQ48A32S,
29152   OPCODE_AE_CVTQ48P24S_L,
29153   OPCODE_AE_CVTQ48P24S_H,
29154   OPCODE_AE_SATQ48S,
29155   OPCODE_AE_TRUNCQ32,
29156   OPCODE_AE_ROUNDSQ32SYM,
29157   OPCODE_AE_ROUNDSQ32ASYM,
29158   OPCODE_AE_TRUNCA32Q48,
29159   OPCODE_AE_MOVAP24S_L,
29160   OPCODE_AE_MOVAP24S_H,
29161   OPCODE_AE_TRUNCA16P24S_L,
29162   OPCODE_AE_TRUNCA16P24S_H,
29163   OPCODE_AE_ADDP24,
29164   OPCODE_AE_SUBP24,
29165   OPCODE_AE_NEGP24,
29166   OPCODE_AE_ABSP24,
29167   OPCODE_AE_MAXP24S,
29168   OPCODE_AE_MINP24S,
29169   OPCODE_AE_MAXBP24S,
29170   OPCODE_AE_MINBP24S,
29171   OPCODE_AE_ADDSP24S,
29172   OPCODE_AE_SUBSP24S,
29173   OPCODE_AE_NEGSP24S,
29174   OPCODE_AE_ABSSP24S,
29175   OPCODE_AE_ANDP48,
29176   OPCODE_AE_NANDP48,
29177   OPCODE_AE_ORP48,
29178   OPCODE_AE_XORP48,
29179   OPCODE_AE_LTP24S,
29180   OPCODE_AE_LEP24S,
29181   OPCODE_AE_EQP24,
29182   OPCODE_AE_ADDQ56,
29183   OPCODE_AE_SUBQ56,
29184   OPCODE_AE_NEGQ56,
29185   OPCODE_AE_ABSQ56,
29186   OPCODE_AE_MAXQ56S,
29187   OPCODE_AE_MINQ56S,
29188   OPCODE_AE_MAXBQ56S,
29189   OPCODE_AE_MINBQ56S,
29190   OPCODE_AE_ADDSQ56S,
29191   OPCODE_AE_SUBSQ56S,
29192   OPCODE_AE_NEGSQ56S,
29193   OPCODE_AE_ABSSQ56S,
29194   OPCODE_AE_ANDQ56,
29195   OPCODE_AE_NANDQ56,
29196   OPCODE_AE_ORQ56,
29197   OPCODE_AE_XORQ56,
29198   OPCODE_AE_SLLIP24,
29199   OPCODE_AE_SRLIP24,
29200   OPCODE_AE_SRAIP24,
29201   OPCODE_AE_SLLSP24,
29202   OPCODE_AE_SRLSP24,
29203   OPCODE_AE_SRASP24,
29204   OPCODE_AE_SLLISP24S,
29205   OPCODE_AE_SLLSSP24S,
29206   OPCODE_AE_SLLIQ56,
29207   OPCODE_AE_SRLIQ56,
29208   OPCODE_AE_SRAIQ56,
29209   OPCODE_AE_SLLSQ56,
29210   OPCODE_AE_SRLSQ56,
29211   OPCODE_AE_SRASQ56,
29212   OPCODE_AE_SLLAQ56,
29213   OPCODE_AE_SRLAQ56,
29214   OPCODE_AE_SRAAQ56,
29215   OPCODE_AE_SLLISQ56S,
29216   OPCODE_AE_SLLSSQ56S,
29217   OPCODE_AE_SLLASQ56S,
29218   OPCODE_AE_LTQ56S,
29219   OPCODE_AE_LEQ56S,
29220   OPCODE_AE_EQQ56,
29221   OPCODE_AE_NSAQ56S,
29222   OPCODE_AE_MULFS32P16S_LL,
29223   OPCODE_AE_MULFP24S_LL,
29224   OPCODE_AE_MULP24S_LL,
29225   OPCODE_AE_MULFS32P16S_LH,
29226   OPCODE_AE_MULFP24S_LH,
29227   OPCODE_AE_MULP24S_LH,
29228   OPCODE_AE_MULFS32P16S_HL,
29229   OPCODE_AE_MULFP24S_HL,
29230   OPCODE_AE_MULP24S_HL,
29231   OPCODE_AE_MULFS32P16S_HH,
29232   OPCODE_AE_MULFP24S_HH,
29233   OPCODE_AE_MULP24S_HH,
29234   OPCODE_AE_MULAFS32P16S_LL,
29235   OPCODE_AE_MULAFP24S_LL,
29236   OPCODE_AE_MULAP24S_LL,
29237   OPCODE_AE_MULAFS32P16S_LH,
29238   OPCODE_AE_MULAFP24S_LH,
29239   OPCODE_AE_MULAP24S_LH,
29240   OPCODE_AE_MULAFS32P16S_HL,
29241   OPCODE_AE_MULAFP24S_HL,
29242   OPCODE_AE_MULAP24S_HL,
29243   OPCODE_AE_MULAFS32P16S_HH,
29244   OPCODE_AE_MULAFP24S_HH,
29245   OPCODE_AE_MULAP24S_HH,
29246   OPCODE_AE_MULSFS32P16S_LL,
29247   OPCODE_AE_MULSFP24S_LL,
29248   OPCODE_AE_MULSP24S_LL,
29249   OPCODE_AE_MULSFS32P16S_LH,
29250   OPCODE_AE_MULSFP24S_LH,
29251   OPCODE_AE_MULSP24S_LH,
29252   OPCODE_AE_MULSFS32P16S_HL,
29253   OPCODE_AE_MULSFP24S_HL,
29254   OPCODE_AE_MULSP24S_HL,
29255   OPCODE_AE_MULSFS32P16S_HH,
29256   OPCODE_AE_MULSFP24S_HH,
29257   OPCODE_AE_MULSP24S_HH,
29258   OPCODE_AE_MULAFS56P24S_LL,
29259   OPCODE_AE_MULAS56P24S_LL,
29260   OPCODE_AE_MULAFS56P24S_LH,
29261   OPCODE_AE_MULAS56P24S_LH,
29262   OPCODE_AE_MULAFS56P24S_HL,
29263   OPCODE_AE_MULAS56P24S_HL,
29264   OPCODE_AE_MULAFS56P24S_HH,
29265   OPCODE_AE_MULAS56P24S_HH,
29266   OPCODE_AE_MULSFS56P24S_LL,
29267   OPCODE_AE_MULSS56P24S_LL,
29268   OPCODE_AE_MULSFS56P24S_LH,
29269   OPCODE_AE_MULSS56P24S_LH,
29270   OPCODE_AE_MULSFS56P24S_HL,
29271   OPCODE_AE_MULSS56P24S_HL,
29272   OPCODE_AE_MULSFS56P24S_HH,
29273   OPCODE_AE_MULSS56P24S_HH,
29274   OPCODE_AE_MULFQ32SP16S_L,
29275   OPCODE_AE_MULFQ32SP16S_H,
29276   OPCODE_AE_MULFQ32SP16U_L,
29277   OPCODE_AE_MULFQ32SP16U_H,
29278   OPCODE_AE_MULQ32SP16S_L,
29279   OPCODE_AE_MULQ32SP16S_H,
29280   OPCODE_AE_MULQ32SP16U_L,
29281   OPCODE_AE_MULQ32SP16U_H,
29282   OPCODE_AE_MULAFQ32SP16S_L,
29283   OPCODE_AE_MULAFQ32SP16S_H,
29284   OPCODE_AE_MULAFQ32SP16U_L,
29285   OPCODE_AE_MULAFQ32SP16U_H,
29286   OPCODE_AE_MULAQ32SP16S_L,
29287   OPCODE_AE_MULAQ32SP16S_H,
29288   OPCODE_AE_MULAQ32SP16U_L,
29289   OPCODE_AE_MULAQ32SP16U_H,
29290   OPCODE_AE_MULSFQ32SP16S_L,
29291   OPCODE_AE_MULSFQ32SP16S_H,
29292   OPCODE_AE_MULSFQ32SP16U_L,
29293   OPCODE_AE_MULSFQ32SP16U_H,
29294   OPCODE_AE_MULSQ32SP16S_L,
29295   OPCODE_AE_MULSQ32SP16S_H,
29296   OPCODE_AE_MULSQ32SP16U_L,
29297   OPCODE_AE_MULSQ32SP16U_H,
29298   OPCODE_AE_MULZAAQ32SP16S_LL,
29299   OPCODE_AE_MULZAAFQ32SP16S_LL,
29300   OPCODE_AE_MULZAAQ32SP16U_LL,
29301   OPCODE_AE_MULZAAFQ32SP16U_LL,
29302   OPCODE_AE_MULZAAQ32SP16S_HH,
29303   OPCODE_AE_MULZAAFQ32SP16S_HH,
29304   OPCODE_AE_MULZAAQ32SP16U_HH,
29305   OPCODE_AE_MULZAAFQ32SP16U_HH,
29306   OPCODE_AE_MULZAAQ32SP16S_LH,
29307   OPCODE_AE_MULZAAFQ32SP16S_LH,
29308   OPCODE_AE_MULZAAQ32SP16U_LH,
29309   OPCODE_AE_MULZAAFQ32SP16U_LH,
29310   OPCODE_AE_MULZASQ32SP16S_LL,
29311   OPCODE_AE_MULZASFQ32SP16S_LL,
29312   OPCODE_AE_MULZASQ32SP16U_LL,
29313   OPCODE_AE_MULZASFQ32SP16U_LL,
29314   OPCODE_AE_MULZASQ32SP16S_HH,
29315   OPCODE_AE_MULZASFQ32SP16S_HH,
29316   OPCODE_AE_MULZASQ32SP16U_HH,
29317   OPCODE_AE_MULZASFQ32SP16U_HH,
29318   OPCODE_AE_MULZASQ32SP16S_LH,
29319   OPCODE_AE_MULZASFQ32SP16S_LH,
29320   OPCODE_AE_MULZASQ32SP16U_LH,
29321   OPCODE_AE_MULZASFQ32SP16U_LH,
29322   OPCODE_AE_MULZSAQ32SP16S_LL,
29323   OPCODE_AE_MULZSAFQ32SP16S_LL,
29324   OPCODE_AE_MULZSAQ32SP16U_LL,
29325   OPCODE_AE_MULZSAFQ32SP16U_LL,
29326   OPCODE_AE_MULZSAQ32SP16S_HH,
29327   OPCODE_AE_MULZSAFQ32SP16S_HH,
29328   OPCODE_AE_MULZSAQ32SP16U_HH,
29329   OPCODE_AE_MULZSAFQ32SP16U_HH,
29330   OPCODE_AE_MULZSAQ32SP16S_LH,
29331   OPCODE_AE_MULZSAFQ32SP16S_LH,
29332   OPCODE_AE_MULZSAQ32SP16U_LH,
29333   OPCODE_AE_MULZSAFQ32SP16U_LH,
29334   OPCODE_AE_MULZSSQ32SP16S_LL,
29335   OPCODE_AE_MULZSSFQ32SP16S_LL,
29336   OPCODE_AE_MULZSSQ32SP16U_LL,
29337   OPCODE_AE_MULZSSFQ32SP16U_LL,
29338   OPCODE_AE_MULZSSQ32SP16S_HH,
29339   OPCODE_AE_MULZSSFQ32SP16S_HH,
29340   OPCODE_AE_MULZSSQ32SP16U_HH,
29341   OPCODE_AE_MULZSSFQ32SP16U_HH,
29342   OPCODE_AE_MULZSSQ32SP16S_LH,
29343   OPCODE_AE_MULZSSFQ32SP16S_LH,
29344   OPCODE_AE_MULZSSQ32SP16U_LH,
29345   OPCODE_AE_MULZSSFQ32SP16U_LH,
29346   OPCODE_AE_MULZAAFP24S_HH_LL,
29347   OPCODE_AE_MULZAAP24S_HH_LL,
29348   OPCODE_AE_MULZAAFP24S_HL_LH,
29349   OPCODE_AE_MULZAAP24S_HL_LH,
29350   OPCODE_AE_MULZASFP24S_HH_LL,
29351   OPCODE_AE_MULZASP24S_HH_LL,
29352   OPCODE_AE_MULZASFP24S_HL_LH,
29353   OPCODE_AE_MULZASP24S_HL_LH,
29354   OPCODE_AE_MULZSAFP24S_HH_LL,
29355   OPCODE_AE_MULZSAP24S_HH_LL,
29356   OPCODE_AE_MULZSAFP24S_HL_LH,
29357   OPCODE_AE_MULZSAP24S_HL_LH,
29358   OPCODE_AE_MULZSSFP24S_HH_LL,
29359   OPCODE_AE_MULZSSP24S_HH_LL,
29360   OPCODE_AE_MULZSSFP24S_HL_LH,
29361   OPCODE_AE_MULZSSP24S_HL_LH,
29362   OPCODE_AE_MULAAFP24S_HH_LL,
29363   OPCODE_AE_MULAAP24S_HH_LL,
29364   OPCODE_AE_MULAAFP24S_HL_LH,
29365   OPCODE_AE_MULAAP24S_HL_LH,
29366   OPCODE_AE_MULASFP24S_HH_LL,
29367   OPCODE_AE_MULASP24S_HH_LL,
29368   OPCODE_AE_MULASFP24S_HL_LH,
29369   OPCODE_AE_MULASP24S_HL_LH,
29370   OPCODE_AE_MULSAFP24S_HH_LL,
29371   OPCODE_AE_MULSAP24S_HH_LL,
29372   OPCODE_AE_MULSAFP24S_HL_LH,
29373   OPCODE_AE_MULSAP24S_HL_LH,
29374   OPCODE_AE_MULSSFP24S_HH_LL,
29375   OPCODE_AE_MULSSP24S_HH_LL,
29376   OPCODE_AE_MULSSFP24S_HL_LH,
29377   OPCODE_AE_MULSSP24S_HL_LH,
29378   OPCODE_AE_SHA32,
29379   OPCODE_AE_VLDL32T,
29380   OPCODE_AE_VLDL16T,
29381   OPCODE_AE_VLDL16C,
29382   OPCODE_AE_VLDSHT,
29383   OPCODE_AE_LB,
29384   OPCODE_AE_LBI,
29385   OPCODE_AE_LBK,
29386   OPCODE_AE_LBKI,
29387   OPCODE_AE_DB,
29388   OPCODE_AE_DBI,
29389   OPCODE_AE_VLEL32T,
29390   OPCODE_AE_VLEL16T,
29391   OPCODE_AE_SB,
29392   OPCODE_AE_SBI,
29393   OPCODE_AE_VLES16C,
29394   OPCODE_AE_SBF
29395 };
29396
29397 \f
29398 /* Slot-specific opcode decode functions.  */
29399
29400 static int
29401 Slot_inst_decode (const xtensa_insnbuf insn)
29402 {
29403   if (Field_op0_Slot_inst_get (insn) == 0)
29404     {
29405       if (Field_op1_Slot_inst_get (insn) == 0)
29406         {
29407           if (Field_op2_Slot_inst_get (insn) == 0)
29408             {
29409               if (Field_r_Slot_inst_get (insn) == 0)
29410                 {
29411                   if (Field_m_Slot_inst_get (insn) == 0 &&
29412                       Field_s_Slot_inst_get (insn) == 0 &&
29413                       Field_n_Slot_inst_get (insn) == 0)
29414                     return OPCODE_ILL;
29415                   if (Field_m_Slot_inst_get (insn) == 2)
29416                     {
29417                       if (Field_n_Slot_inst_get (insn) == 0)
29418                         return OPCODE_RET;
29419                       if (Field_n_Slot_inst_get (insn) == 1)
29420                         return OPCODE_RETW;
29421                       if (Field_n_Slot_inst_get (insn) == 2)
29422                         return OPCODE_JX;
29423                     }
29424                   if (Field_m_Slot_inst_get (insn) == 3)
29425                     {
29426                       if (Field_n_Slot_inst_get (insn) == 0)
29427                         return OPCODE_CALLX0;
29428                       if (Field_n_Slot_inst_get (insn) == 1)
29429                         return OPCODE_CALLX4;
29430                       if (Field_n_Slot_inst_get (insn) == 2)
29431                         return OPCODE_CALLX8;
29432                       if (Field_n_Slot_inst_get (insn) == 3)
29433                         return OPCODE_CALLX12;
29434                     }
29435                 }
29436               if (Field_r_Slot_inst_get (insn) == 1)
29437                 return OPCODE_MOVSP;
29438               if (Field_r_Slot_inst_get (insn) == 2)
29439                 {
29440                   if (Field_s_Slot_inst_get (insn) == 0)
29441                     {
29442                       if (Field_t_Slot_inst_get (insn) == 0)
29443                         return OPCODE_ISYNC;
29444                       if (Field_t_Slot_inst_get (insn) == 1)
29445                         return OPCODE_RSYNC;
29446                       if (Field_t_Slot_inst_get (insn) == 2)
29447                         return OPCODE_ESYNC;
29448                       if (Field_t_Slot_inst_get (insn) == 3)
29449                         return OPCODE_DSYNC;
29450                       if (Field_t_Slot_inst_get (insn) == 8)
29451                         return OPCODE_EXCW;
29452                       if (Field_t_Slot_inst_get (insn) == 12)
29453                         return OPCODE_MEMW;
29454                       if (Field_t_Slot_inst_get (insn) == 13)
29455                         return OPCODE_EXTW;
29456                       if (Field_t_Slot_inst_get (insn) == 15)
29457                         return OPCODE_NOP;
29458                     }
29459                 }
29460               if (Field_r_Slot_inst_get (insn) == 3)
29461                 {
29462                   if (Field_t_Slot_inst_get (insn) == 0)
29463                     {
29464                       if (Field_s_Slot_inst_get (insn) == 0)
29465                         return OPCODE_RFE;
29466                       if (Field_s_Slot_inst_get (insn) == 2)
29467                         return OPCODE_RFDE;
29468                       if (Field_s_Slot_inst_get (insn) == 4)
29469                         return OPCODE_RFWO;
29470                       if (Field_s_Slot_inst_get (insn) == 5)
29471                         return OPCODE_RFWU;
29472                     }
29473                   if (Field_t_Slot_inst_get (insn) == 1)
29474                     return OPCODE_RFI;
29475                 }
29476               if (Field_r_Slot_inst_get (insn) == 4)
29477                 return OPCODE_BREAK;
29478               if (Field_r_Slot_inst_get (insn) == 5)
29479                 {
29480                   if (Field_s_Slot_inst_get (insn) == 0 &&
29481                       Field_t_Slot_inst_get (insn) == 0)
29482                     return OPCODE_SYSCALL;
29483                   if (Field_s_Slot_inst_get (insn) == 1 &&
29484                       Field_t_Slot_inst_get (insn) == 0)
29485                     return OPCODE_SIMCALL;
29486                 }
29487               if (Field_r_Slot_inst_get (insn) == 6)
29488                 return OPCODE_RSIL;
29489               if (Field_r_Slot_inst_get (insn) == 7 &&
29490                   Field_t_Slot_inst_get (insn) == 0)
29491                 return OPCODE_WAITI;
29492               if (Field_r_Slot_inst_get (insn) == 8)
29493                 return OPCODE_ANY4;
29494               if (Field_r_Slot_inst_get (insn) == 9)
29495                 return OPCODE_ALL4;
29496               if (Field_r_Slot_inst_get (insn) == 10)
29497                 return OPCODE_ANY8;
29498               if (Field_r_Slot_inst_get (insn) == 11)
29499                 return OPCODE_ALL8;
29500             }
29501           if (Field_op2_Slot_inst_get (insn) == 1)
29502             return OPCODE_AND;
29503           if (Field_op2_Slot_inst_get (insn) == 2)
29504             return OPCODE_OR;
29505           if (Field_op2_Slot_inst_get (insn) == 3)
29506             return OPCODE_XOR;
29507           if (Field_op2_Slot_inst_get (insn) == 4)
29508             {
29509               if (Field_r_Slot_inst_get (insn) == 0 &&
29510                   Field_t_Slot_inst_get (insn) == 0)
29511                 return OPCODE_SSR;
29512               if (Field_r_Slot_inst_get (insn) == 1 &&
29513                   Field_t_Slot_inst_get (insn) == 0)
29514                 return OPCODE_SSL;
29515               if (Field_r_Slot_inst_get (insn) == 2 &&
29516                   Field_t_Slot_inst_get (insn) == 0)
29517                 return OPCODE_SSA8L;
29518               if (Field_r_Slot_inst_get (insn) == 3 &&
29519                   Field_t_Slot_inst_get (insn) == 0)
29520                 return OPCODE_SSA8B;
29521               if (Field_r_Slot_inst_get (insn) == 4 &&
29522                   Field_thi3_Slot_inst_get (insn) == 0)
29523                 return OPCODE_SSAI;
29524               if (Field_r_Slot_inst_get (insn) == 6)
29525                 return OPCODE_RER;
29526               if (Field_r_Slot_inst_get (insn) == 7)
29527                 return OPCODE_WER;
29528               if (Field_r_Slot_inst_get (insn) == 8 &&
29529                   Field_s_Slot_inst_get (insn) == 0)
29530                 return OPCODE_ROTW;
29531               if (Field_r_Slot_inst_get (insn) == 14)
29532                 return OPCODE_NSA;
29533               if (Field_r_Slot_inst_get (insn) == 15)
29534                 return OPCODE_NSAU;
29535             }
29536           if (Field_op2_Slot_inst_get (insn) == 5)
29537             {
29538               if (Field_r_Slot_inst_get (insn) == 1)
29539                 return OPCODE_HWWITLBA;
29540               if (Field_r_Slot_inst_get (insn) == 3)
29541                 return OPCODE_RITLB0;
29542               if (Field_r_Slot_inst_get (insn) == 4 &&
29543                   Field_t_Slot_inst_get (insn) == 0)
29544                 return OPCODE_IITLB;
29545               if (Field_r_Slot_inst_get (insn) == 5)
29546                 return OPCODE_PITLB;
29547               if (Field_r_Slot_inst_get (insn) == 6)
29548                 return OPCODE_WITLB;
29549               if (Field_r_Slot_inst_get (insn) == 7)
29550                 return OPCODE_RITLB1;
29551               if (Field_r_Slot_inst_get (insn) == 9)
29552                 return OPCODE_HWWDTLBA;
29553               if (Field_r_Slot_inst_get (insn) == 11)
29554                 return OPCODE_RDTLB0;
29555               if (Field_r_Slot_inst_get (insn) == 12 &&
29556                   Field_t_Slot_inst_get (insn) == 0)
29557                 return OPCODE_IDTLB;
29558               if (Field_r_Slot_inst_get (insn) == 13)
29559                 return OPCODE_PDTLB;
29560               if (Field_r_Slot_inst_get (insn) == 14)
29561                 return OPCODE_WDTLB;
29562               if (Field_r_Slot_inst_get (insn) == 15)
29563                 return OPCODE_RDTLB1;
29564             }
29565           if (Field_op2_Slot_inst_get (insn) == 6)
29566             {
29567               if (Field_s_Slot_inst_get (insn) == 0)
29568                 return OPCODE_NEG;
29569               if (Field_s_Slot_inst_get (insn) == 1)
29570                 return OPCODE_ABS;
29571             }
29572           if (Field_op2_Slot_inst_get (insn) == 8)
29573             return OPCODE_ADD;
29574           if (Field_op2_Slot_inst_get (insn) == 9)
29575             return OPCODE_ADDX2;
29576           if (Field_op2_Slot_inst_get (insn) == 10)
29577             return OPCODE_ADDX4;
29578           if (Field_op2_Slot_inst_get (insn) == 11)
29579             return OPCODE_ADDX8;
29580           if (Field_op2_Slot_inst_get (insn) == 12)
29581             return OPCODE_SUB;
29582           if (Field_op2_Slot_inst_get (insn) == 13)
29583             return OPCODE_SUBX2;
29584           if (Field_op2_Slot_inst_get (insn) == 14)
29585             return OPCODE_SUBX4;
29586           if (Field_op2_Slot_inst_get (insn) == 15)
29587             return OPCODE_SUBX8;
29588         }
29589       if (Field_op1_Slot_inst_get (insn) == 1)
29590         {
29591           if ((Field_op2_Slot_inst_get (insn) == 0 ||
29592                Field_op2_Slot_inst_get (insn) == 1))
29593             return OPCODE_SLLI;
29594           if ((Field_op2_Slot_inst_get (insn) == 2 ||
29595                Field_op2_Slot_inst_get (insn) == 3))
29596             return OPCODE_SRAI;
29597           if (Field_op2_Slot_inst_get (insn) == 4)
29598             return OPCODE_SRLI;
29599           if (Field_op2_Slot_inst_get (insn) == 6)
29600             {
29601               if (Field_sr_Slot_inst_get (insn) == 0)
29602                 return OPCODE_XSR_LBEG;
29603               if (Field_sr_Slot_inst_get (insn) == 1)
29604                 return OPCODE_XSR_LEND;
29605               if (Field_sr_Slot_inst_get (insn) == 2)
29606                 return OPCODE_XSR_LCOUNT;
29607               if (Field_sr_Slot_inst_get (insn) == 3)
29608                 return OPCODE_XSR_SAR;
29609               if (Field_sr_Slot_inst_get (insn) == 4)
29610                 return OPCODE_XSR_BR;
29611               if (Field_sr_Slot_inst_get (insn) == 5)
29612                 return OPCODE_XSR_LITBASE;
29613               if (Field_sr_Slot_inst_get (insn) == 12)
29614                 return OPCODE_XSR_SCOMPARE1;
29615               if (Field_sr_Slot_inst_get (insn) == 72)
29616                 return OPCODE_XSR_WINDOWBASE;
29617               if (Field_sr_Slot_inst_get (insn) == 73)
29618                 return OPCODE_XSR_WINDOWSTART;
29619               if (Field_sr_Slot_inst_get (insn) == 83)
29620                 return OPCODE_XSR_PTEVADDR;
29621               if (Field_sr_Slot_inst_get (insn) == 90)
29622                 return OPCODE_XSR_RASID;
29623               if (Field_sr_Slot_inst_get (insn) == 91)
29624                 return OPCODE_XSR_ITLBCFG;
29625               if (Field_sr_Slot_inst_get (insn) == 92)
29626                 return OPCODE_XSR_DTLBCFG;
29627               if (Field_sr_Slot_inst_get (insn) == 99)
29628                 return OPCODE_XSR_ATOMCTL;
29629               if (Field_sr_Slot_inst_get (insn) == 104)
29630                 return OPCODE_XSR_DDR;
29631               if (Field_sr_Slot_inst_get (insn) == 177)
29632                 return OPCODE_XSR_EPC1;
29633               if (Field_sr_Slot_inst_get (insn) == 178)
29634                 return OPCODE_XSR_EPC2;
29635               if (Field_sr_Slot_inst_get (insn) == 192)
29636                 return OPCODE_XSR_DEPC;
29637               if (Field_sr_Slot_inst_get (insn) == 194)
29638                 return OPCODE_XSR_EPS2;
29639               if (Field_sr_Slot_inst_get (insn) == 209)
29640                 return OPCODE_XSR_EXCSAVE1;
29641               if (Field_sr_Slot_inst_get (insn) == 210)
29642                 return OPCODE_XSR_EXCSAVE2;
29643               if (Field_sr_Slot_inst_get (insn) == 224)
29644                 return OPCODE_XSR_CPENABLE;
29645               if (Field_sr_Slot_inst_get (insn) == 228)
29646                 return OPCODE_XSR_INTENABLE;
29647               if (Field_sr_Slot_inst_get (insn) == 230)
29648                 return OPCODE_XSR_PS;
29649               if (Field_sr_Slot_inst_get (insn) == 231)
29650                 return OPCODE_XSR_VECBASE;
29651               if (Field_sr_Slot_inst_get (insn) == 232)
29652                 return OPCODE_XSR_EXCCAUSE;
29653               if (Field_sr_Slot_inst_get (insn) == 233)
29654                 return OPCODE_XSR_DEBUGCAUSE;
29655               if (Field_sr_Slot_inst_get (insn) == 234)
29656                 return OPCODE_XSR_CCOUNT;
29657               if (Field_sr_Slot_inst_get (insn) == 236)
29658                 return OPCODE_XSR_ICOUNT;
29659               if (Field_sr_Slot_inst_get (insn) == 237)
29660                 return OPCODE_XSR_ICOUNTLEVEL;
29661               if (Field_sr_Slot_inst_get (insn) == 238)
29662                 return OPCODE_XSR_EXCVADDR;
29663               if (Field_sr_Slot_inst_get (insn) == 240)
29664                 return OPCODE_XSR_CCOMPARE0;
29665               if (Field_sr_Slot_inst_get (insn) == 241)
29666                 return OPCODE_XSR_CCOMPARE1;
29667               if (Field_sr_Slot_inst_get (insn) == 244)
29668                 return OPCODE_XSR_MISC0;
29669               if (Field_sr_Slot_inst_get (insn) == 245)
29670                 return OPCODE_XSR_MISC1;
29671             }
29672           if (Field_op2_Slot_inst_get (insn) == 8)
29673             return OPCODE_SRC;
29674           if (Field_op2_Slot_inst_get (insn) == 9 &&
29675               Field_s_Slot_inst_get (insn) == 0)
29676             return OPCODE_SRL;
29677           if (Field_op2_Slot_inst_get (insn) == 10 &&
29678               Field_t_Slot_inst_get (insn) == 0)
29679             return OPCODE_SLL;
29680           if (Field_op2_Slot_inst_get (insn) == 11 &&
29681               Field_s_Slot_inst_get (insn) == 0)
29682             return OPCODE_SRA;
29683           if (Field_op2_Slot_inst_get (insn) == 12)
29684             return OPCODE_MUL16U;
29685           if (Field_op2_Slot_inst_get (insn) == 13)
29686             return OPCODE_MUL16S;
29687           if (Field_op2_Slot_inst_get (insn) == 15)
29688             {
29689               if (Field_r_Slot_inst_get (insn) == 0)
29690                 return OPCODE_LICT;
29691               if (Field_r_Slot_inst_get (insn) == 1)
29692                 return OPCODE_SICT;
29693               if (Field_r_Slot_inst_get (insn) == 2)
29694                 return OPCODE_LICW;
29695               if (Field_r_Slot_inst_get (insn) == 3)
29696                 return OPCODE_SICW;
29697               if (Field_r_Slot_inst_get (insn) == 8)
29698                 return OPCODE_LDCT;
29699               if (Field_r_Slot_inst_get (insn) == 9)
29700                 return OPCODE_SDCT;
29701               if (Field_r_Slot_inst_get (insn) == 14 &&
29702                   Field_t_Slot_inst_get (insn) == 0)
29703                 return OPCODE_RFDO;
29704               if (Field_r_Slot_inst_get (insn) == 14 &&
29705                   Field_t_Slot_inst_get (insn) == 1)
29706                 return OPCODE_RFDD;
29707               if (Field_r_Slot_inst_get (insn) == 15)
29708                 return OPCODE_LDPTE;
29709             }
29710         }
29711       if (Field_op1_Slot_inst_get (insn) == 2)
29712         {
29713           if (Field_op2_Slot_inst_get (insn) == 0)
29714             return OPCODE_ANDB;
29715           if (Field_op2_Slot_inst_get (insn) == 1)
29716             return OPCODE_ANDBC;
29717           if (Field_op2_Slot_inst_get (insn) == 2)
29718             return OPCODE_ORB;
29719           if (Field_op2_Slot_inst_get (insn) == 3)
29720             return OPCODE_ORBC;
29721           if (Field_op2_Slot_inst_get (insn) == 4)
29722             return OPCODE_XORB;
29723           if (Field_op2_Slot_inst_get (insn) == 8)
29724             return OPCODE_MULL;
29725         }
29726       if (Field_op1_Slot_inst_get (insn) == 3)
29727         {
29728           if (Field_op2_Slot_inst_get (insn) == 0)
29729             {
29730               if (Field_sr_Slot_inst_get (insn) == 0)
29731                 return OPCODE_RSR_LBEG;
29732               if (Field_sr_Slot_inst_get (insn) == 1)
29733                 return OPCODE_RSR_LEND;
29734               if (Field_sr_Slot_inst_get (insn) == 2)
29735                 return OPCODE_RSR_LCOUNT;
29736               if (Field_sr_Slot_inst_get (insn) == 3)
29737                 return OPCODE_RSR_SAR;
29738               if (Field_sr_Slot_inst_get (insn) == 4)
29739                 return OPCODE_RSR_BR;
29740               if (Field_sr_Slot_inst_get (insn) == 5)
29741                 return OPCODE_RSR_LITBASE;
29742               if (Field_sr_Slot_inst_get (insn) == 12)
29743                 return OPCODE_RSR_SCOMPARE1;
29744               if (Field_sr_Slot_inst_get (insn) == 72)
29745                 return OPCODE_RSR_WINDOWBASE;
29746               if (Field_sr_Slot_inst_get (insn) == 73)
29747                 return OPCODE_RSR_WINDOWSTART;
29748               if (Field_sr_Slot_inst_get (insn) == 83)
29749                 return OPCODE_RSR_PTEVADDR;
29750               if (Field_sr_Slot_inst_get (insn) == 90)
29751                 return OPCODE_RSR_RASID;
29752               if (Field_sr_Slot_inst_get (insn) == 91)
29753                 return OPCODE_RSR_ITLBCFG;
29754               if (Field_sr_Slot_inst_get (insn) == 92)
29755                 return OPCODE_RSR_DTLBCFG;
29756               if (Field_sr_Slot_inst_get (insn) == 99)
29757                 return OPCODE_RSR_ATOMCTL;
29758               if (Field_sr_Slot_inst_get (insn) == 104)
29759                 return OPCODE_RSR_DDR;
29760               if (Field_sr_Slot_inst_get (insn) == 176)
29761                 return OPCODE_RSR_CONFIGID0;
29762               if (Field_sr_Slot_inst_get (insn) == 177)
29763                 return OPCODE_RSR_EPC1;
29764               if (Field_sr_Slot_inst_get (insn) == 178)
29765                 return OPCODE_RSR_EPC2;
29766               if (Field_sr_Slot_inst_get (insn) == 192)
29767                 return OPCODE_RSR_DEPC;
29768               if (Field_sr_Slot_inst_get (insn) == 194)
29769                 return OPCODE_RSR_EPS2;
29770               if (Field_sr_Slot_inst_get (insn) == 208)
29771                 return OPCODE_RSR_CONFIGID1;
29772               if (Field_sr_Slot_inst_get (insn) == 209)
29773                 return OPCODE_RSR_EXCSAVE1;
29774               if (Field_sr_Slot_inst_get (insn) == 210)
29775                 return OPCODE_RSR_EXCSAVE2;
29776               if (Field_sr_Slot_inst_get (insn) == 224)
29777                 return OPCODE_RSR_CPENABLE;
29778               if (Field_sr_Slot_inst_get (insn) == 226)
29779                 return OPCODE_RSR_INTERRUPT;
29780               if (Field_sr_Slot_inst_get (insn) == 228)
29781                 return OPCODE_RSR_INTENABLE;
29782               if (Field_sr_Slot_inst_get (insn) == 230)
29783                 return OPCODE_RSR_PS;
29784               if (Field_sr_Slot_inst_get (insn) == 231)
29785                 return OPCODE_RSR_VECBASE;
29786               if (Field_sr_Slot_inst_get (insn) == 232)
29787                 return OPCODE_RSR_EXCCAUSE;
29788               if (Field_sr_Slot_inst_get (insn) == 233)
29789                 return OPCODE_RSR_DEBUGCAUSE;
29790               if (Field_sr_Slot_inst_get (insn) == 234)
29791                 return OPCODE_RSR_CCOUNT;
29792               if (Field_sr_Slot_inst_get (insn) == 235)
29793                 return OPCODE_RSR_PRID;
29794               if (Field_sr_Slot_inst_get (insn) == 236)
29795                 return OPCODE_RSR_ICOUNT;
29796               if (Field_sr_Slot_inst_get (insn) == 237)
29797                 return OPCODE_RSR_ICOUNTLEVEL;
29798               if (Field_sr_Slot_inst_get (insn) == 238)
29799                 return OPCODE_RSR_EXCVADDR;
29800               if (Field_sr_Slot_inst_get (insn) == 240)
29801                 return OPCODE_RSR_CCOMPARE0;
29802               if (Field_sr_Slot_inst_get (insn) == 241)
29803                 return OPCODE_RSR_CCOMPARE1;
29804               if (Field_sr_Slot_inst_get (insn) == 244)
29805                 return OPCODE_RSR_MISC0;
29806               if (Field_sr_Slot_inst_get (insn) == 245)
29807                 return OPCODE_RSR_MISC1;
29808             }
29809           if (Field_op2_Slot_inst_get (insn) == 1)
29810             {
29811               if (Field_sr_Slot_inst_get (insn) == 0)
29812                 return OPCODE_WSR_LBEG;
29813               if (Field_sr_Slot_inst_get (insn) == 1)
29814                 return OPCODE_WSR_LEND;
29815               if (Field_sr_Slot_inst_get (insn) == 2)
29816                 return OPCODE_WSR_LCOUNT;
29817               if (Field_sr_Slot_inst_get (insn) == 3)
29818                 return OPCODE_WSR_SAR;
29819               if (Field_sr_Slot_inst_get (insn) == 4)
29820                 return OPCODE_WSR_BR;
29821               if (Field_sr_Slot_inst_get (insn) == 5)
29822                 return OPCODE_WSR_LITBASE;
29823               if (Field_sr_Slot_inst_get (insn) == 12)
29824                 return OPCODE_WSR_SCOMPARE1;
29825               if (Field_sr_Slot_inst_get (insn) == 72)
29826                 return OPCODE_WSR_WINDOWBASE;
29827               if (Field_sr_Slot_inst_get (insn) == 73)
29828                 return OPCODE_WSR_WINDOWSTART;
29829               if (Field_sr_Slot_inst_get (insn) == 83)
29830                 return OPCODE_WSR_PTEVADDR;
29831               if (Field_sr_Slot_inst_get (insn) == 90)
29832                 return OPCODE_WSR_RASID;
29833               if (Field_sr_Slot_inst_get (insn) == 91)
29834                 return OPCODE_WSR_ITLBCFG;
29835               if (Field_sr_Slot_inst_get (insn) == 92)
29836                 return OPCODE_WSR_DTLBCFG;
29837               if (Field_sr_Slot_inst_get (insn) == 99)
29838                 return OPCODE_WSR_ATOMCTL;
29839               if (Field_sr_Slot_inst_get (insn) == 104)
29840                 return OPCODE_WSR_DDR;
29841               if (Field_sr_Slot_inst_get (insn) == 176)
29842                 return OPCODE_WSR_CONFIGID0;
29843               if (Field_sr_Slot_inst_get (insn) == 177)
29844                 return OPCODE_WSR_EPC1;
29845               if (Field_sr_Slot_inst_get (insn) == 178)
29846                 return OPCODE_WSR_EPC2;
29847               if (Field_sr_Slot_inst_get (insn) == 192)
29848                 return OPCODE_WSR_DEPC;
29849               if (Field_sr_Slot_inst_get (insn) == 194)
29850                 return OPCODE_WSR_EPS2;
29851               if (Field_sr_Slot_inst_get (insn) == 209)
29852                 return OPCODE_WSR_EXCSAVE1;
29853               if (Field_sr_Slot_inst_get (insn) == 210)
29854                 return OPCODE_WSR_EXCSAVE2;
29855               if (Field_sr_Slot_inst_get (insn) == 224)
29856                 return OPCODE_WSR_CPENABLE;
29857               if (Field_sr_Slot_inst_get (insn) == 226)
29858                 return OPCODE_WSR_INTSET;
29859               if (Field_sr_Slot_inst_get (insn) == 227)
29860                 return OPCODE_WSR_INTCLEAR;
29861               if (Field_sr_Slot_inst_get (insn) == 228)
29862                 return OPCODE_WSR_INTENABLE;
29863               if (Field_sr_Slot_inst_get (insn) == 230)
29864                 return OPCODE_WSR_PS;
29865               if (Field_sr_Slot_inst_get (insn) == 231)
29866                 return OPCODE_WSR_VECBASE;
29867               if (Field_sr_Slot_inst_get (insn) == 232)
29868                 return OPCODE_WSR_EXCCAUSE;
29869               if (Field_sr_Slot_inst_get (insn) == 233)
29870                 return OPCODE_WSR_DEBUGCAUSE;
29871               if (Field_sr_Slot_inst_get (insn) == 234)
29872                 return OPCODE_WSR_CCOUNT;
29873               if (Field_sr_Slot_inst_get (insn) == 236)
29874                 return OPCODE_WSR_ICOUNT;
29875               if (Field_sr_Slot_inst_get (insn) == 237)
29876                 return OPCODE_WSR_ICOUNTLEVEL;
29877               if (Field_sr_Slot_inst_get (insn) == 238)
29878                 return OPCODE_WSR_EXCVADDR;
29879               if (Field_sr_Slot_inst_get (insn) == 240)
29880                 return OPCODE_WSR_CCOMPARE0;
29881               if (Field_sr_Slot_inst_get (insn) == 241)
29882                 return OPCODE_WSR_CCOMPARE1;
29883               if (Field_sr_Slot_inst_get (insn) == 244)
29884                 return OPCODE_WSR_MISC0;
29885               if (Field_sr_Slot_inst_get (insn) == 245)
29886                 return OPCODE_WSR_MISC1;
29887             }
29888           if (Field_op2_Slot_inst_get (insn) == 2)
29889             return OPCODE_SEXT;
29890           if (Field_op2_Slot_inst_get (insn) == 3)
29891             return OPCODE_CLAMPS;
29892           if (Field_op2_Slot_inst_get (insn) == 4)
29893             return OPCODE_MIN;
29894           if (Field_op2_Slot_inst_get (insn) == 5)
29895             return OPCODE_MAX;
29896           if (Field_op2_Slot_inst_get (insn) == 6)
29897             return OPCODE_MINU;
29898           if (Field_op2_Slot_inst_get (insn) == 7)
29899             return OPCODE_MAXU;
29900           if (Field_op2_Slot_inst_get (insn) == 8)
29901             return OPCODE_MOVEQZ;
29902           if (Field_op2_Slot_inst_get (insn) == 9)
29903             return OPCODE_MOVNEZ;
29904           if (Field_op2_Slot_inst_get (insn) == 10)
29905             return OPCODE_MOVLTZ;
29906           if (Field_op2_Slot_inst_get (insn) == 11)
29907             return OPCODE_MOVGEZ;
29908           if (Field_op2_Slot_inst_get (insn) == 12)
29909             return OPCODE_MOVF;
29910           if (Field_op2_Slot_inst_get (insn) == 13)
29911             return OPCODE_MOVT;
29912           if (Field_op2_Slot_inst_get (insn) == 14)
29913             {
29914               if (Field_st_Slot_inst_get (insn) == 231)
29915                 return OPCODE_RUR_THREADPTR;
29916               if (Field_st_Slot_inst_get (insn) == 240)
29917                 return OPCODE_RUR_AE_OVF_SAR;
29918               if (Field_st_Slot_inst_get (insn) == 241)
29919                 return OPCODE_RUR_AE_BITHEAD;
29920               if (Field_st_Slot_inst_get (insn) == 242)
29921                 return OPCODE_RUR_AE_TS_FTS_BU_BP;
29922               if (Field_st_Slot_inst_get (insn) == 243)
29923                 return OPCODE_RUR_AE_SD_NO;
29924             }
29925           if (Field_op2_Slot_inst_get (insn) == 15)
29926             {
29927               if (Field_sr_Slot_inst_get (insn) == 231)
29928                 return OPCODE_WUR_THREADPTR;
29929               if (Field_sr_Slot_inst_get (insn) == 240)
29930                 return OPCODE_WUR_AE_OVF_SAR;
29931               if (Field_sr_Slot_inst_get (insn) == 241)
29932                 return OPCODE_WUR_AE_BITHEAD;
29933               if (Field_sr_Slot_inst_get (insn) == 242)
29934                 return OPCODE_WUR_AE_TS_FTS_BU_BP;
29935               if (Field_sr_Slot_inst_get (insn) == 243)
29936                 return OPCODE_WUR_AE_SD_NO;
29937             }
29938         }
29939       if ((Field_op1_Slot_inst_get (insn) == 4 ||
29940            Field_op1_Slot_inst_get (insn) == 5))
29941         return OPCODE_EXTUI;
29942       if (Field_op1_Slot_inst_get (insn) == 9)
29943         {
29944           if (Field_op2_Slot_inst_get (insn) == 0)
29945             return OPCODE_L32E;
29946           if (Field_op2_Slot_inst_get (insn) == 4)
29947             return OPCODE_S32E;
29948         }
29949     }
29950   if (Field_op0_Slot_inst_get (insn) == 1)
29951     return OPCODE_L32R;
29952   if (Field_op0_Slot_inst_get (insn) == 2)
29953     {
29954       if (Field_r_Slot_inst_get (insn) == 0)
29955         return OPCODE_L8UI;
29956       if (Field_r_Slot_inst_get (insn) == 1)
29957         return OPCODE_L16UI;
29958       if (Field_r_Slot_inst_get (insn) == 2)
29959         return OPCODE_L32I;
29960       if (Field_r_Slot_inst_get (insn) == 4)
29961         return OPCODE_S8I;
29962       if (Field_r_Slot_inst_get (insn) == 5)
29963         return OPCODE_S16I;
29964       if (Field_r_Slot_inst_get (insn) == 6)
29965         return OPCODE_S32I;
29966       if (Field_r_Slot_inst_get (insn) == 7)
29967         {
29968           if (Field_t_Slot_inst_get (insn) == 0)
29969             return OPCODE_DPFR;
29970           if (Field_t_Slot_inst_get (insn) == 1)
29971             return OPCODE_DPFW;
29972           if (Field_t_Slot_inst_get (insn) == 2)
29973             return OPCODE_DPFRO;
29974           if (Field_t_Slot_inst_get (insn) == 3)
29975             return OPCODE_DPFWO;
29976           if (Field_t_Slot_inst_get (insn) == 4)
29977             return OPCODE_DHWB;
29978           if (Field_t_Slot_inst_get (insn) == 5)
29979             return OPCODE_DHWBI;
29980           if (Field_t_Slot_inst_get (insn) == 6)
29981             return OPCODE_DHI;
29982           if (Field_t_Slot_inst_get (insn) == 7)
29983             return OPCODE_DII;
29984           if (Field_t_Slot_inst_get (insn) == 8)
29985             {
29986               if (Field_op1_Slot_inst_get (insn) == 4)
29987                 return OPCODE_DIWB;
29988               if (Field_op1_Slot_inst_get (insn) == 5)
29989                 return OPCODE_DIWBI;
29990             }
29991           if (Field_t_Slot_inst_get (insn) == 12)
29992             return OPCODE_IPF;
29993           if (Field_t_Slot_inst_get (insn) == 14)
29994             return OPCODE_IHI;
29995           if (Field_t_Slot_inst_get (insn) == 15)
29996             return OPCODE_III;
29997         }
29998       if (Field_r_Slot_inst_get (insn) == 9)
29999         return OPCODE_L16SI;
30000       if (Field_r_Slot_inst_get (insn) == 10)
30001         return OPCODE_MOVI;
30002       if (Field_r_Slot_inst_get (insn) == 11)
30003         return OPCODE_L32AI;
30004       if (Field_r_Slot_inst_get (insn) == 12)
30005         return OPCODE_ADDI;
30006       if (Field_r_Slot_inst_get (insn) == 13)
30007         return OPCODE_ADDMI;
30008       if (Field_r_Slot_inst_get (insn) == 14)
30009         return OPCODE_S32C1I;
30010       if (Field_r_Slot_inst_get (insn) == 15)
30011         return OPCODE_S32RI;
30012     }
30013   if (Field_op0_Slot_inst_get (insn) == 4)
30014     {
30015       if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
30016           Field_op1_Slot_inst_get (insn) == 1 &&
30017           Field_op2_Slot_inst_get (insn) == 12)
30018         return OPCODE_AE_LQ56_I;
30019       if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
30020           Field_op1_Slot_inst_get (insn) == 2 &&
30021           Field_op2_Slot_inst_get (insn) == 12)
30022         return OPCODE_AE_LQ56_X;
30023       if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
30024           Field_op1_Slot_inst_get (insn) == 1 &&
30025           Field_op2_Slot_inst_get (insn) == 12)
30026         return OPCODE_AE_LQ32F_I;
30027       if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
30028           Field_op1_Slot_inst_get (insn) == 2 &&
30029           Field_op2_Slot_inst_get (insn) == 12)
30030         return OPCODE_AE_LQ32F_X;
30031       if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
30032           Field_op1_Slot_inst_get (insn) == 1 &&
30033           Field_op2_Slot_inst_get (insn) == 12)
30034         return OPCODE_AE_LQ56_IU;
30035       if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
30036           Field_op1_Slot_inst_get (insn) == 2 &&
30037           Field_op2_Slot_inst_get (insn) == 12)
30038         return OPCODE_AE_LQ56_XU;
30039       if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
30040           Field_op1_Slot_inst_get (insn) == 7 &&
30041           Field_t_Slot_inst_get (insn) == 3 &&
30042           Field_op2_Slot_inst_get (insn) == 14)
30043         return OPCODE_AE_CVTQ48A32S;
30044       if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
30045           Field_op1_Slot_inst_get (insn) == 1 &&
30046           Field_op2_Slot_inst_get (insn) == 12)
30047         return OPCODE_AE_LQ32F_IU;
30048       if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
30049           Field_op1_Slot_inst_get (insn) == 2 &&
30050           Field_op2_Slot_inst_get (insn) == 12)
30051         return OPCODE_AE_LQ32F_XU;
30052       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30053           Field_op1_Slot_inst_get (insn) == 5 &&
30054           Field_op2_Slot_inst_get (insn) == 10)
30055         return OPCODE_AE_LP16F_I;
30056       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30057           Field_op1_Slot_inst_get (insn) == 9 &&
30058           Field_op2_Slot_inst_get (insn) == 10)
30059         return OPCODE_AE_LP16F_IU;
30060       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30061           Field_op1_Slot_inst_get (insn) == 12 &&
30062           Field_op2_Slot_inst_get (insn) == 10)
30063         return OPCODE_AE_LP16F_X;
30064       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30065           Field_op1_Slot_inst_get (insn) == 15 &&
30066           Field_op2_Slot_inst_get (insn) == 10)
30067         return OPCODE_AE_LP16F_XU;
30068       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30069           Field_op1_Slot_inst_get (insn) == 6 &&
30070           Field_op2_Slot_inst_get (insn) == 10)
30071         return OPCODE_AE_LP24F_I;
30072       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30073           Field_op1_Slot_inst_get (insn) == 10 &&
30074           Field_op2_Slot_inst_get (insn) == 10)
30075         return OPCODE_AE_LP24F_IU;
30076       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30077           Field_op1_Slot_inst_get (insn) == 13 &&
30078           Field_op2_Slot_inst_get (insn) == 10)
30079         return OPCODE_AE_LP24F_X;
30080       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30081           Field_op1_Slot_inst_get (insn) == 0 &&
30082           Field_op2_Slot_inst_get (insn) == 11)
30083         return OPCODE_AE_LP24F_XU;
30084       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30085           Field_op1_Slot_inst_get (insn) == 7 &&
30086           Field_op2_Slot_inst_get (insn) == 10)
30087         return OPCODE_AE_LP24X2F_I;
30088       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30089           Field_op1_Slot_inst_get (insn) == 11 &&
30090           Field_op2_Slot_inst_get (insn) == 10)
30091         return OPCODE_AE_LP24X2F_IU;
30092       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30093           Field_op1_Slot_inst_get (insn) == 14 &&
30094           Field_op2_Slot_inst_get (insn) == 10)
30095         return OPCODE_AE_LP24X2F_X;
30096       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30097           Field_op1_Slot_inst_get (insn) == 1 &&
30098           Field_op2_Slot_inst_get (insn) == 11)
30099         return OPCODE_AE_LP24X2F_XU;
30100       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30101           Field_op1_Slot_inst_get (insn) == 2 &&
30102           Field_op2_Slot_inst_get (insn) == 11)
30103         return OPCODE_AE_SP16X2F_I;
30104       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30105           Field_op1_Slot_inst_get (insn) == 5 &&
30106           Field_op2_Slot_inst_get (insn) == 11)
30107         return OPCODE_AE_SP16X2F_IU;
30108       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30109           Field_op1_Slot_inst_get (insn) == 8 &&
30110           Field_op2_Slot_inst_get (insn) == 11)
30111         return OPCODE_AE_SP16X2F_X;
30112       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30113           Field_op1_Slot_inst_get (insn) == 11 &&
30114           Field_op2_Slot_inst_get (insn) == 11)
30115         return OPCODE_AE_SP16X2F_XU;
30116       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30117           Field_op1_Slot_inst_get (insn) == 3 &&
30118           Field_op2_Slot_inst_get (insn) == 11)
30119         return OPCODE_AE_SP24X2F_I;
30120       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30121           Field_op1_Slot_inst_get (insn) == 6 &&
30122           Field_op2_Slot_inst_get (insn) == 11)
30123         return OPCODE_AE_SP24X2F_IU;
30124       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30125           Field_op1_Slot_inst_get (insn) == 9 &&
30126           Field_op2_Slot_inst_get (insn) == 11)
30127         return OPCODE_AE_SP24X2F_X;
30128       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30129           Field_op1_Slot_inst_get (insn) == 12 &&
30130           Field_op2_Slot_inst_get (insn) == 11)
30131         return OPCODE_AE_SP24X2F_XU;
30132       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30133           Field_op1_Slot_inst_get (insn) == 4 &&
30134           Field_op2_Slot_inst_get (insn) == 11)
30135         return OPCODE_AE_SP24S_L_I;
30136       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30137           Field_op1_Slot_inst_get (insn) == 7 &&
30138           Field_op2_Slot_inst_get (insn) == 11)
30139         return OPCODE_AE_SP24S_L_IU;
30140       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30141           Field_op1_Slot_inst_get (insn) == 10 &&
30142           Field_op2_Slot_inst_get (insn) == 11)
30143         return OPCODE_AE_SP24S_L_X;
30144       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30145           Field_op1_Slot_inst_get (insn) == 13 &&
30146           Field_op2_Slot_inst_get (insn) == 11)
30147         return OPCODE_AE_SP24S_L_XU;
30148       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30149           Field_ae_s3_Slot_inst_get (insn) == 0 &&
30150           Field_t_Slot_inst_get (insn) == 0 &&
30151           Field_op1_Slot_inst_get (insn) == 9 &&
30152           Field_op2_Slot_inst_get (insn) == 12)
30153         return OPCODE_AE_MOVP48;
30154       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30155           Field_op1_Slot_inst_get (insn) == 0 &&
30156           Field_op2_Slot_inst_get (insn) == 12)
30157         return OPCODE_AE_MOVPA24X2;
30158       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30159           Field_t_Slot_inst_get (insn) == 0 &&
30160           Field_op1_Slot_inst_get (insn) == 11 &&
30161           Field_op2_Slot_inst_get (insn) == 12)
30162         return OPCODE_AE_CVTA32P24_L;
30163       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30164           Field_op1_Slot_inst_get (insn) == 14 &&
30165           Field_op2_Slot_inst_get (insn) == 11)
30166         return OPCODE_AE_CVTP24A16X2_LL;
30167       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30168           Field_op1_Slot_inst_get (insn) == 15 &&
30169           Field_op2_Slot_inst_get (insn) == 11)
30170         return OPCODE_AE_CVTP24A16X2_HL;
30171       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30172           Field_t_Slot_inst_get (insn) == 0 &&
30173           Field_op1_Slot_inst_get (insn) == 7 &&
30174           Field_op2_Slot_inst_get (insn) == 12)
30175         return OPCODE_AE_MOVAP24S_L;
30176       if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30177           Field_t_Slot_inst_get (insn) == 0 &&
30178           Field_op1_Slot_inst_get (insn) == 8 &&
30179           Field_op2_Slot_inst_get (insn) == 12)
30180         return OPCODE_AE_TRUNCA16P24S_L;
30181       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30182           Field_op1_Slot_inst_get (insn) == 5 &&
30183           Field_op2_Slot_inst_get (insn) == 10)
30184         return OPCODE_AE_LP24_I;
30185       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30186           Field_op1_Slot_inst_get (insn) == 9 &&
30187           Field_op2_Slot_inst_get (insn) == 10)
30188         return OPCODE_AE_LP24_IU;
30189       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30190           Field_op1_Slot_inst_get (insn) == 12 &&
30191           Field_op2_Slot_inst_get (insn) == 10)
30192         return OPCODE_AE_LP24_X;
30193       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30194           Field_op1_Slot_inst_get (insn) == 15 &&
30195           Field_op2_Slot_inst_get (insn) == 10)
30196         return OPCODE_AE_LP24_XU;
30197       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30198           Field_op1_Slot_inst_get (insn) == 6 &&
30199           Field_op2_Slot_inst_get (insn) == 10)
30200         return OPCODE_AE_LP16X2F_I;
30201       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30202           Field_op1_Slot_inst_get (insn) == 10 &&
30203           Field_op2_Slot_inst_get (insn) == 10)
30204         return OPCODE_AE_LP16X2F_IU;
30205       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30206           Field_op1_Slot_inst_get (insn) == 13 &&
30207           Field_op2_Slot_inst_get (insn) == 10)
30208         return OPCODE_AE_LP16X2F_X;
30209       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30210           Field_op1_Slot_inst_get (insn) == 0 &&
30211           Field_op2_Slot_inst_get (insn) == 11)
30212         return OPCODE_AE_LP16X2F_XU;
30213       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30214           Field_op1_Slot_inst_get (insn) == 7 &&
30215           Field_op2_Slot_inst_get (insn) == 10)
30216         return OPCODE_AE_LP24X2_I;
30217       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30218           Field_op1_Slot_inst_get (insn) == 11 &&
30219           Field_op2_Slot_inst_get (insn) == 10)
30220         return OPCODE_AE_LP24X2_IU;
30221       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30222           Field_op1_Slot_inst_get (insn) == 14 &&
30223           Field_op2_Slot_inst_get (insn) == 10)
30224         return OPCODE_AE_LP24X2_X;
30225       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30226           Field_op1_Slot_inst_get (insn) == 1 &&
30227           Field_op2_Slot_inst_get (insn) == 11)
30228         return OPCODE_AE_LP24X2_XU;
30229       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30230           Field_op1_Slot_inst_get (insn) == 2 &&
30231           Field_op2_Slot_inst_get (insn) == 11)
30232         return OPCODE_AE_SP24X2S_I;
30233       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30234           Field_op1_Slot_inst_get (insn) == 5 &&
30235           Field_op2_Slot_inst_get (insn) == 11)
30236         return OPCODE_AE_SP24X2S_IU;
30237       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30238           Field_op1_Slot_inst_get (insn) == 8 &&
30239           Field_op2_Slot_inst_get (insn) == 11)
30240         return OPCODE_AE_SP24X2S_X;
30241       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30242           Field_op1_Slot_inst_get (insn) == 11 &&
30243           Field_op2_Slot_inst_get (insn) == 11)
30244         return OPCODE_AE_SP24X2S_XU;
30245       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30246           Field_op1_Slot_inst_get (insn) == 3 &&
30247           Field_op2_Slot_inst_get (insn) == 11)
30248         return OPCODE_AE_SP16F_L_I;
30249       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30250           Field_op1_Slot_inst_get (insn) == 6 &&
30251           Field_op2_Slot_inst_get (insn) == 11)
30252         return OPCODE_AE_SP16F_L_IU;
30253       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30254           Field_op1_Slot_inst_get (insn) == 9 &&
30255           Field_op2_Slot_inst_get (insn) == 11)
30256         return OPCODE_AE_SP16F_L_X;
30257       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30258           Field_op1_Slot_inst_get (insn) == 12 &&
30259           Field_op2_Slot_inst_get (insn) == 11)
30260         return OPCODE_AE_SP16F_L_XU;
30261       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30262           Field_op1_Slot_inst_get (insn) == 4 &&
30263           Field_op2_Slot_inst_get (insn) == 11)
30264         return OPCODE_AE_SP24F_L_I;
30265       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30266           Field_op1_Slot_inst_get (insn) == 7 &&
30267           Field_op2_Slot_inst_get (insn) == 11)
30268         return OPCODE_AE_SP24F_L_IU;
30269       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30270           Field_op1_Slot_inst_get (insn) == 10 &&
30271           Field_op2_Slot_inst_get (insn) == 11)
30272         return OPCODE_AE_SP24F_L_X;
30273       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30274           Field_op1_Slot_inst_get (insn) == 13 &&
30275           Field_op2_Slot_inst_get (insn) == 11)
30276         return OPCODE_AE_SP24F_L_XU;
30277       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30278           Field_op1_Slot_inst_get (insn) == 0 &&
30279           Field_op2_Slot_inst_get (insn) == 12)
30280         return OPCODE_AE_TRUNCP24A32X2;
30281       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30282           Field_t_Slot_inst_get (insn) == 0 &&
30283           Field_op1_Slot_inst_get (insn) == 11 &&
30284           Field_op2_Slot_inst_get (insn) == 12)
30285         return OPCODE_AE_CVTA32P24_H;
30286       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30287           Field_op1_Slot_inst_get (insn) == 14 &&
30288           Field_op2_Slot_inst_get (insn) == 11)
30289         return OPCODE_AE_CVTP24A16X2_LH;
30290       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30291           Field_op1_Slot_inst_get (insn) == 15 &&
30292           Field_op2_Slot_inst_get (insn) == 11)
30293         return OPCODE_AE_CVTP24A16X2_HH;
30294       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30295           Field_t_Slot_inst_get (insn) == 0 &&
30296           Field_op1_Slot_inst_get (insn) == 7 &&
30297           Field_op2_Slot_inst_get (insn) == 12)
30298         return OPCODE_AE_MOVAP24S_H;
30299       if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30300           Field_t_Slot_inst_get (insn) == 0 &&
30301           Field_op1_Slot_inst_get (insn) == 8 &&
30302           Field_op2_Slot_inst_get (insn) == 12)
30303         return OPCODE_AE_TRUNCA16P24S_H;
30304       if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
30305           Field_op1_Slot_inst_get (insn) == 3 &&
30306           Field_op2_Slot_inst_get (insn) == 12)
30307         return OPCODE_AE_SQ56S_I;
30308       if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
30309           Field_op1_Slot_inst_get (insn) == 4 &&
30310           Field_op2_Slot_inst_get (insn) == 12)
30311         return OPCODE_AE_SQ56S_X;
30312       if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
30313           Field_op1_Slot_inst_get (insn) == 7 &&
30314           Field_t_Slot_inst_get (insn) == 1 &&
30315           Field_op2_Slot_inst_get (insn) == 14)
30316         return OPCODE_AE_TRUNCA32Q48;
30317       if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
30318           Field_op1_Slot_inst_get (insn) == 3 &&
30319           Field_op2_Slot_inst_get (insn) == 12)
30320         return OPCODE_AE_SQ32F_I;
30321       if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
30322           Field_op1_Slot_inst_get (insn) == 4 &&
30323           Field_op2_Slot_inst_get (insn) == 12)
30324         return OPCODE_AE_SQ32F_X;
30325       if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
30326           Field_op1_Slot_inst_get (insn) == 7 &&
30327           Field_t_Slot_inst_get (insn) == 1 &&
30328           Field_op2_Slot_inst_get (insn) == 14)
30329         return OPCODE_AE_NSAQ56S;
30330       if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
30331           Field_op1_Slot_inst_get (insn) == 3 &&
30332           Field_op2_Slot_inst_get (insn) == 12)
30333         return OPCODE_AE_SQ56S_IU;
30334       if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
30335           Field_op1_Slot_inst_get (insn) == 4 &&
30336           Field_op2_Slot_inst_get (insn) == 12)
30337         return OPCODE_AE_SQ56S_XU;
30338       if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
30339           Field_op1_Slot_inst_get (insn) == 3 &&
30340           Field_op2_Slot_inst_get (insn) == 12)
30341         return OPCODE_AE_SQ32F_IU;
30342       if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
30343           Field_op1_Slot_inst_get (insn) == 4 &&
30344           Field_op2_Slot_inst_get (insn) == 12)
30345         return OPCODE_AE_SQ32F_XU;
30346       if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 &&
30347           Field_op1_Slot_inst_get (insn) == 5 &&
30348           Field_op2_Slot_inst_get (insn) == 12)
30349         return OPCODE_AE_SLLIQ56;
30350       if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 &&
30351           Field_op1_Slot_inst_get (insn) == 5 &&
30352           Field_op2_Slot_inst_get (insn) == 12)
30353         return OPCODE_AE_SRLIQ56;
30354       if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 &&
30355           Field_op1_Slot_inst_get (insn) == 5 &&
30356           Field_op2_Slot_inst_get (insn) == 12)
30357         return OPCODE_AE_SRAIQ56;
30358       if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 &&
30359           Field_op1_Slot_inst_get (insn) == 5 &&
30360           Field_op2_Slot_inst_get (insn) == 12)
30361         return OPCODE_AE_SLLISQ56S;
30362       if (Field_op1_Slot_inst_get (insn) == 0 &&
30363           Field_t_Slot_inst_get (insn) == 1 &&
30364           Field_op2_Slot_inst_get (insn) == 14)
30365         return OPCODE_AE_SHA32;
30366       if (Field_op1_Slot_inst_get (insn) == 0 &&
30367           Field_op2_Slot_inst_get (insn) == 10)
30368         return OPCODE_AE_VLDL32T;
30369       if (Field_op1_Slot_inst_get (insn) == 1 &&
30370           Field_t_Slot_inst_get (insn) == 1 &&
30371           Field_op2_Slot_inst_get (insn) == 14)
30372         return OPCODE_AE_SLLAQ56;
30373       if (Field_op1_Slot_inst_get (insn) == 1 &&
30374           Field_op2_Slot_inst_get (insn) == 10)
30375         return OPCODE_AE_VLDL16T;
30376       if (Field_op1_Slot_inst_get (insn) == 2 &&
30377           Field_t_Slot_inst_get (insn) == 1 &&
30378           Field_op2_Slot_inst_get (insn) == 14)
30379         return OPCODE_AE_SRLAQ56;
30380       if (Field_op1_Slot_inst_get (insn) == 2 &&
30381           Field_op2_Slot_inst_get (insn) == 10)
30382         return OPCODE_AE_LBK;
30383       if (Field_op1_Slot_inst_get (insn) == 3 &&
30384           Field_t_Slot_inst_get (insn) == 1 &&
30385           Field_op2_Slot_inst_get (insn) == 14)
30386         return OPCODE_AE_SRAAQ56;
30387       if (Field_op1_Slot_inst_get (insn) == 3 &&
30388           Field_op2_Slot_inst_get (insn) == 10)
30389         return OPCODE_AE_VLEL32T;
30390       if (Field_op1_Slot_inst_get (insn) == 4 &&
30391           Field_t_Slot_inst_get (insn) == 1 &&
30392           Field_op2_Slot_inst_get (insn) == 14)
30393         return OPCODE_AE_SLLASQ56S;
30394       if (Field_op1_Slot_inst_get (insn) == 4 &&
30395           Field_op2_Slot_inst_get (insn) == 10)
30396         return OPCODE_AE_VLEL16T;
30397       if (Field_op1_Slot_inst_get (insn) == 5 &&
30398           Field_t_Slot_inst_get (insn) == 1 &&
30399           Field_op2_Slot_inst_get (insn) == 14)
30400         return OPCODE_AE_MOVTQ56;
30401       if (Field_op1_Slot_inst_get (insn) == 6 &&
30402           Field_t_Slot_inst_get (insn) == 1 &&
30403           Field_op2_Slot_inst_get (insn) == 14)
30404         return OPCODE_AE_MOVFQ56;
30405       if (Field_r_Slot_inst_get (insn) == 0 &&
30406           Field_s_Slot_inst_get (insn) == 0 &&
30407           Field_op1_Slot_inst_get (insn) == 10 &&
30408           Field_op2_Slot_inst_get (insn) == 12)
30409         return OPCODE_WUR_AE_OVERFLOW;
30410       if (Field_r_Slot_inst_get (insn) == 0 &&
30411           Field_op2_Slot_inst_get (insn) == 15)
30412         return OPCODE_AE_SBI;
30413       if (Field_r_Slot_inst_get (insn) == 1 &&
30414           Field_s_Slot_inst_get (insn) == 0 &&
30415           Field_op1_Slot_inst_get (insn) == 10 &&
30416           Field_op2_Slot_inst_get (insn) == 12)
30417         return OPCODE_WUR_AE_SAR;
30418       if (Field_r_Slot_inst_get (insn) == 1 &&
30419           Field_op1_Slot_inst_get (insn) == 0 &&
30420           Field_op2_Slot_inst_get (insn) == 15)
30421         return OPCODE_AE_DB;
30422       if (Field_r_Slot_inst_get (insn) == 1 &&
30423           Field_op1_Slot_inst_get (insn) == 1 &&
30424           Field_op2_Slot_inst_get (insn) == 15)
30425         return OPCODE_AE_SB;
30426       if (Field_r_Slot_inst_get (insn) == 2 &&
30427           Field_s_Slot_inst_get (insn) == 0 &&
30428           Field_op1_Slot_inst_get (insn) == 10 &&
30429           Field_op2_Slot_inst_get (insn) == 12)
30430         return OPCODE_WUR_AE_BITPTR;
30431       if (Field_r_Slot_inst_get (insn) == 3 &&
30432           Field_s_Slot_inst_get (insn) == 0 &&
30433           Field_op1_Slot_inst_get (insn) == 10 &&
30434           Field_op2_Slot_inst_get (insn) == 12)
30435         return OPCODE_WUR_AE_BITSUSED;
30436       if (Field_r_Slot_inst_get (insn) == 4 &&
30437           Field_s_Slot_inst_get (insn) == 0 &&
30438           Field_op1_Slot_inst_get (insn) == 10 &&
30439           Field_op2_Slot_inst_get (insn) == 12)
30440         return OPCODE_WUR_AE_TABLESIZE;
30441       if (Field_r_Slot_inst_get (insn) == 5 &&
30442           Field_s_Slot_inst_get (insn) == 0 &&
30443           Field_op1_Slot_inst_get (insn) == 10 &&
30444           Field_op2_Slot_inst_get (insn) == 12)
30445         return OPCODE_WUR_AE_FIRST_TS;
30446       if (Field_r_Slot_inst_get (insn) == 6 &&
30447           Field_s_Slot_inst_get (insn) == 0 &&
30448           Field_op1_Slot_inst_get (insn) == 10 &&
30449           Field_op2_Slot_inst_get (insn) == 12)
30450         return OPCODE_WUR_AE_NEXTOFFSET;
30451       if (Field_r_Slot_inst_get (insn) == 7 &&
30452           Field_s_Slot_inst_get (insn) == 0 &&
30453           Field_op1_Slot_inst_get (insn) == 10 &&
30454           Field_op2_Slot_inst_get (insn) == 12)
30455         return OPCODE_WUR_AE_SEARCHDONE;
30456       if (Field_r_Slot_inst_get (insn) == 8 &&
30457           Field_s_Slot_inst_get (insn) == 0 &&
30458           Field_op1_Slot_inst_get (insn) == 10 &&
30459           Field_op2_Slot_inst_get (insn) == 12)
30460         return OPCODE_AE_VLDSHT;
30461       if (Field_r_Slot_inst_get (insn) == 12 &&
30462           Field_op1_Slot_inst_get (insn) == 7 &&
30463           Field_t_Slot_inst_get (insn) == 1 &&
30464           Field_op2_Slot_inst_get (insn) == 14)
30465         return OPCODE_AE_VLES16C;
30466       if (Field_r_Slot_inst_get (insn) == 13 &&
30467           Field_op1_Slot_inst_get (insn) == 7 &&
30468           Field_t_Slot_inst_get (insn) == 1 &&
30469           Field_op2_Slot_inst_get (insn) == 14)
30470         return OPCODE_AE_SBF;
30471       if (Field_r_Slot_inst_get (insn) == 14 &&
30472           Field_op1_Slot_inst_get (insn) == 7 &&
30473           Field_t_Slot_inst_get (insn) == 1 &&
30474           Field_op2_Slot_inst_get (insn) == 14)
30475         return OPCODE_AE_VLDL16C;
30476       if (Field_s_Slot_inst_get (insn) == 0 &&
30477           Field_t_Slot_inst_get (insn) == 1 &&
30478           Field_op1_Slot_inst_get (insn) == 9 &&
30479           Field_op2_Slot_inst_get (insn) == 12)
30480         return OPCODE_AE_SLLSQ56;
30481       if (Field_s_Slot_inst_get (insn) == 0 &&
30482           Field_op1_Slot_inst_get (insn) == 6 &&
30483           Field_op2_Slot_inst_get (insn) == 12)
30484         return OPCODE_AE_LB;
30485       if (Field_s_Slot_inst_get (insn) == 1 &&
30486           Field_t_Slot_inst_get (insn) == 1 &&
30487           Field_op1_Slot_inst_get (insn) == 9 &&
30488           Field_op2_Slot_inst_get (insn) == 12)
30489         return OPCODE_AE_SRLSQ56;
30490       if (Field_s_Slot_inst_get (insn) == 2 &&
30491           Field_t_Slot_inst_get (insn) == 1 &&
30492           Field_op1_Slot_inst_get (insn) == 9 &&
30493           Field_op2_Slot_inst_get (insn) == 12)
30494         return OPCODE_AE_SRASQ56;
30495       if (Field_s_Slot_inst_get (insn) == 3 &&
30496           Field_t_Slot_inst_get (insn) == 1 &&
30497           Field_op1_Slot_inst_get (insn) == 9 &&
30498           Field_op2_Slot_inst_get (insn) == 12)
30499         return OPCODE_AE_SLLSSQ56S;
30500       if (Field_s_Slot_inst_get (insn) == 4 &&
30501           Field_t_Slot_inst_get (insn) == 1 &&
30502           Field_op1_Slot_inst_get (insn) == 9 &&
30503           Field_op2_Slot_inst_get (insn) == 12)
30504         return OPCODE_AE_MOVQ56;
30505       if (Field_s_Slot_inst_get (insn) == 8 &&
30506           Field_t_Slot_inst_get (insn) == 0 &&
30507           Field_op1_Slot_inst_get (insn) == 9 &&
30508           Field_op2_Slot_inst_get (insn) == 12)
30509         return OPCODE_RUR_AE_OVERFLOW;
30510       if (Field_s_Slot_inst_get (insn) == 9 &&
30511           Field_t_Slot_inst_get (insn) == 0 &&
30512           Field_op1_Slot_inst_get (insn) == 9 &&
30513           Field_op2_Slot_inst_get (insn) == 12)
30514         return OPCODE_RUR_AE_SAR;
30515       if (Field_s_Slot_inst_get (insn) == 10 &&
30516           Field_t_Slot_inst_get (insn) == 0 &&
30517           Field_op1_Slot_inst_get (insn) == 9 &&
30518           Field_op2_Slot_inst_get (insn) == 12)
30519         return OPCODE_RUR_AE_BITPTR;
30520       if (Field_s_Slot_inst_get (insn) == 11 &&
30521           Field_t_Slot_inst_get (insn) == 0 &&
30522           Field_op1_Slot_inst_get (insn) == 9 &&
30523           Field_op2_Slot_inst_get (insn) == 12)
30524         return OPCODE_RUR_AE_BITSUSED;
30525       if (Field_s_Slot_inst_get (insn) == 12 &&
30526           Field_t_Slot_inst_get (insn) == 0 &&
30527           Field_op1_Slot_inst_get (insn) == 9 &&
30528           Field_op2_Slot_inst_get (insn) == 12)
30529         return OPCODE_RUR_AE_TABLESIZE;
30530       if (Field_s_Slot_inst_get (insn) == 13 &&
30531           Field_t_Slot_inst_get (insn) == 0 &&
30532           Field_op1_Slot_inst_get (insn) == 9 &&
30533           Field_op2_Slot_inst_get (insn) == 12)
30534         return OPCODE_RUR_AE_FIRST_TS;
30535       if (Field_s_Slot_inst_get (insn) == 14 &&
30536           Field_t_Slot_inst_get (insn) == 0 &&
30537           Field_op1_Slot_inst_get (insn) == 9 &&
30538           Field_op2_Slot_inst_get (insn) == 12)
30539         return OPCODE_RUR_AE_NEXTOFFSET;
30540       if (Field_s_Slot_inst_get (insn) == 15 &&
30541           Field_t_Slot_inst_get (insn) == 0 &&
30542           Field_op1_Slot_inst_get (insn) == 9 &&
30543           Field_op2_Slot_inst_get (insn) == 12)
30544         return OPCODE_RUR_AE_SEARCHDONE;
30545       if (Field_t_Slot_inst_get (insn) == 0 &&
30546           Field_op2_Slot_inst_get (insn) == 14)
30547         return OPCODE_AE_LBKI;
30548       if (Field_t_Slot_inst_get (insn) == 0 &&
30549           Field_r_Slot_inst_get (insn) == 2 &&
30550           Field_op2_Slot_inst_get (insn) == 15)
30551         return OPCODE_AE_DBI;
30552       if (Field_t_Slot_inst_get (insn) == 2 &&
30553           Field_s_Slot_inst_get (insn) == 0 &&
30554           Field_op2_Slot_inst_get (insn) == 14)
30555         return OPCODE_AE_LBI;
30556     }
30557   if (Field_op0_Slot_inst_get (insn) == 5)
30558     {
30559       if (Field_n_Slot_inst_get (insn) == 0)
30560         return OPCODE_CALL0;
30561       if (Field_n_Slot_inst_get (insn) == 1)
30562         return OPCODE_CALL4;
30563       if (Field_n_Slot_inst_get (insn) == 2)
30564         return OPCODE_CALL8;
30565       if (Field_n_Slot_inst_get (insn) == 3)
30566         return OPCODE_CALL12;
30567     }
30568   if (Field_op0_Slot_inst_get (insn) == 6)
30569     {
30570       if (Field_n_Slot_inst_get (insn) == 0)
30571         return OPCODE_J;
30572       if (Field_n_Slot_inst_get (insn) == 1)
30573         {
30574           if (Field_m_Slot_inst_get (insn) == 0)
30575             return OPCODE_BEQZ;
30576           if (Field_m_Slot_inst_get (insn) == 1)
30577             return OPCODE_BNEZ;
30578           if (Field_m_Slot_inst_get (insn) == 2)
30579             return OPCODE_BLTZ;
30580           if (Field_m_Slot_inst_get (insn) == 3)
30581             return OPCODE_BGEZ;
30582         }
30583       if (Field_n_Slot_inst_get (insn) == 2)
30584         {
30585           if (Field_m_Slot_inst_get (insn) == 0)
30586             return OPCODE_BEQI;
30587           if (Field_m_Slot_inst_get (insn) == 1)
30588             return OPCODE_BNEI;
30589           if (Field_m_Slot_inst_get (insn) == 2)
30590             return OPCODE_BLTI;
30591           if (Field_m_Slot_inst_get (insn) == 3)
30592             return OPCODE_BGEI;
30593         }
30594       if (Field_n_Slot_inst_get (insn) == 3)
30595         {
30596           if (Field_m_Slot_inst_get (insn) == 0)
30597             return OPCODE_ENTRY;
30598           if (Field_m_Slot_inst_get (insn) == 1)
30599             {
30600               if (Field_r_Slot_inst_get (insn) == 0)
30601                 return OPCODE_BF;
30602               if (Field_r_Slot_inst_get (insn) == 1)
30603                 return OPCODE_BT;
30604               if (Field_r_Slot_inst_get (insn) == 8)
30605                 return OPCODE_LOOP;
30606               if (Field_r_Slot_inst_get (insn) == 9)
30607                 return OPCODE_LOOPNEZ;
30608               if (Field_r_Slot_inst_get (insn) == 10)
30609                 return OPCODE_LOOPGTZ;
30610             }
30611           if (Field_m_Slot_inst_get (insn) == 2)
30612             return OPCODE_BLTUI;
30613           if (Field_m_Slot_inst_get (insn) == 3)
30614             return OPCODE_BGEUI;
30615         }
30616     }
30617   if (Field_op0_Slot_inst_get (insn) == 7)
30618     {
30619       if (Field_r_Slot_inst_get (insn) == 0)
30620         return OPCODE_BNONE;
30621       if (Field_r_Slot_inst_get (insn) == 1)
30622         return OPCODE_BEQ;
30623       if (Field_r_Slot_inst_get (insn) == 2)
30624         return OPCODE_BLT;
30625       if (Field_r_Slot_inst_get (insn) == 3)
30626         return OPCODE_BLTU;
30627       if (Field_r_Slot_inst_get (insn) == 4)
30628         return OPCODE_BALL;
30629       if (Field_r_Slot_inst_get (insn) == 5)
30630         return OPCODE_BBC;
30631       if ((Field_r_Slot_inst_get (insn) == 6 ||
30632            Field_r_Slot_inst_get (insn) == 7))
30633         return OPCODE_BBCI;
30634       if (Field_r_Slot_inst_get (insn) == 8)
30635         return OPCODE_BANY;
30636       if (Field_r_Slot_inst_get (insn) == 9)
30637         return OPCODE_BNE;
30638       if (Field_r_Slot_inst_get (insn) == 10)
30639         return OPCODE_BGE;
30640       if (Field_r_Slot_inst_get (insn) == 11)
30641         return OPCODE_BGEU;
30642       if (Field_r_Slot_inst_get (insn) == 12)
30643         return OPCODE_BNALL;
30644       if (Field_r_Slot_inst_get (insn) == 13)
30645         return OPCODE_BBS;
30646       if ((Field_r_Slot_inst_get (insn) == 14 ||
30647            Field_r_Slot_inst_get (insn) == 15))
30648         return OPCODE_BBSI;
30649     }
30650   return XTENSA_UNDEFINED;
30651 }
30652
30653 static int
30654 Slot_inst16b_decode (const xtensa_insnbuf insn)
30655 {
30656   if (Field_op0_Slot_inst16b_get (insn) == 12)
30657     {
30658       if (Field_i_Slot_inst16b_get (insn) == 0)
30659         return OPCODE_MOVI_N;
30660       if (Field_i_Slot_inst16b_get (insn) == 1)
30661         {
30662           if (Field_z_Slot_inst16b_get (insn) == 0)
30663             return OPCODE_BEQZ_N;
30664           if (Field_z_Slot_inst16b_get (insn) == 1)
30665             return OPCODE_BNEZ_N;
30666         }
30667     }
30668   if (Field_op0_Slot_inst16b_get (insn) == 13)
30669     {
30670       if (Field_r_Slot_inst16b_get (insn) == 0)
30671         return OPCODE_MOV_N;
30672       if (Field_r_Slot_inst16b_get (insn) == 15)
30673         {
30674           if (Field_t_Slot_inst16b_get (insn) == 0)
30675             return OPCODE_RET_N;
30676           if (Field_t_Slot_inst16b_get (insn) == 1)
30677             return OPCODE_RETW_N;
30678           if (Field_t_Slot_inst16b_get (insn) == 2)
30679             return OPCODE_BREAK_N;
30680           if (Field_t_Slot_inst16b_get (insn) == 3 &&
30681               Field_s_Slot_inst16b_get (insn) == 0)
30682             return OPCODE_NOP_N;
30683           if (Field_t_Slot_inst16b_get (insn) == 6 &&
30684               Field_s_Slot_inst16b_get (insn) == 0)
30685             return OPCODE_ILL_N;
30686         }
30687     }
30688   return XTENSA_UNDEFINED;
30689 }
30690
30691 static int
30692 Slot_inst16a_decode (const xtensa_insnbuf insn)
30693 {
30694   if (Field_op0_Slot_inst16a_get (insn) == 8)
30695     return OPCODE_L32I_N;
30696   if (Field_op0_Slot_inst16a_get (insn) == 9)
30697     return OPCODE_S32I_N;
30698   if (Field_op0_Slot_inst16a_get (insn) == 10)
30699     return OPCODE_ADD_N;
30700   if (Field_op0_Slot_inst16a_get (insn) == 11)
30701     return OPCODE_ADDI_N;
30702   return XTENSA_UNDEFINED;
30703 }
30704
30705 static int
30706 Slot_ae_slot0_decode (const xtensa_insnbuf insn)
30707 {
30708   if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
30709       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30710     return OPCODE_J;
30711   if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 &&
30712       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30713     return OPCODE_EXTUI;
30714   if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 6 &&
30715       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30716     return OPCODE_BGEZ;
30717   if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 &&
30718       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30719     return OPCODE_BLTZ;
30720   if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 8 &&
30721       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30722     return OPCODE_BEQZ;
30723   if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 9 &&
30724       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30725     return OPCODE_BNEZ;
30726   if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 &&
30727       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30728     return OPCODE_MOVI;
30729   if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 88 &&
30730       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30731     return OPCODE_SRAI;
30732   if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 96 &&
30733       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30734     return OPCODE_SLLI;
30735   if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 123 &&
30736       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30737       Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0)
30738     return OPCODE_AE_MOVTQ56;
30739   if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 &&
30740       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30741     return OPCODE_AE_CVTP24A16X2_HH;
30742   if (Field_ftsf217_Slot_ae_slot0_get (insn) == 1 &&
30743       Field_op0_s4_Slot_ae_slot0_get (insn) == 4 &&
30744       Field_ae_r20_Slot_ae_slot0_get (insn) == 0)
30745     return OPCODE_L32I;
30746   if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 419 &&
30747       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30748     return OPCODE_AE_LP16F_I;
30749   if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 420 &&
30750       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30751     return OPCODE_AE_CVTP24A16X2_HL;
30752   if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 421 &&
30753       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30754     return OPCODE_AE_LP16F_IU;
30755   if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 422 &&
30756       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30757     return OPCODE_AE_LP16F_X;
30758   if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 423 &&
30759       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30760     return OPCODE_AE_LP16F_XU;
30761   if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 424 &&
30762       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30763     return OPCODE_AE_CVTP24A16X2_LH;
30764   if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 425 &&
30765       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30766     return OPCODE_AE_LP16X2F_I;
30767   if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 426 &&
30768       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30769     return OPCODE_AE_LP16X2F_IU;
30770   if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 427 &&
30771       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30772     return OPCODE_AE_LP16X2F_XU;
30773   if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 428 &&
30774       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30775     return OPCODE_AE_LP16X2F_X;
30776   if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 429 &&
30777       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30778     return OPCODE_AE_LP24_I;
30779   if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 430 &&
30780       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30781     return OPCODE_AE_LP24_IU;
30782   if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 431 &&
30783       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30784     return OPCODE_AE_LP24_X;
30785   if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 432 &&
30786       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30787     return OPCODE_AE_CVTP24A16X2_LL;
30788   if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 433 &&
30789       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30790     return OPCODE_AE_LP24_XU;
30791   if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 434 &&
30792       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30793     return OPCODE_AE_LP24F_I;
30794   if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 435 &&
30795       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30796     return OPCODE_AE_LP24F_XU;
30797   if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 436 &&
30798       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30799     return OPCODE_AE_LP24F_IU;
30800   if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 437 &&
30801       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30802     return OPCODE_AE_LP24X2_I;
30803   if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 438 &&
30804       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30805     return OPCODE_AE_LP24X2_IU;
30806   if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 439 &&
30807       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30808     return OPCODE_AE_LP24X2_X;
30809   if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 440 &&
30810       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30811     return OPCODE_AE_LP24F_X;
30812   if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 441 &&
30813       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30814     return OPCODE_AE_LP24X2_XU;
30815   if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 442 &&
30816       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30817     return OPCODE_AE_LP24X2F_I;
30818   if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 443 &&
30819       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30820     return OPCODE_AE_LP24X2F_X;
30821   if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 444 &&
30822       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30823     return OPCODE_AE_LP24X2F_IU;
30824   if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 445 &&
30825       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30826     return OPCODE_AE_LP24X2F_XU;
30827   if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 446 &&
30828       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30829     return OPCODE_AE_MOVPA24X2;
30830   if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
30831       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30832     return OPCODE_AE_SP16F_L_I;
30833   if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 450 &&
30834       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30835     return OPCODE_AE_SP16F_L_IU;
30836   if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 451 &&
30837       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30838     return OPCODE_AE_SP16X2F_X;
30839   if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 452 &&
30840       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30841     return OPCODE_AE_SP16F_L_X;
30842   if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 453 &&
30843       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30844     return OPCODE_AE_SP16X2F_XU;
30845   if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 454 &&
30846       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30847     return OPCODE_AE_SP24F_L_I;
30848   if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 455 &&
30849       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30850     return OPCODE_AE_SP24F_L_IU;
30851   if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 456 &&
30852       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30853     return OPCODE_AE_SP16F_L_XU;
30854   if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 457 &&
30855       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30856     return OPCODE_AE_SP24F_L_X;
30857   if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 458 &&
30858       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30859     return OPCODE_AE_SP24F_L_XU;
30860   if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 459 &&
30861       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30862     return OPCODE_AE_SP24S_L_IU;
30863   if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 460 &&
30864       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30865     return OPCODE_AE_SP24S_L_I;
30866   if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 461 &&
30867       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30868     return OPCODE_AE_SP24S_L_X;
30869   if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 462 &&
30870       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30871     return OPCODE_AE_SP24S_L_XU;
30872   if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 463 &&
30873       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30874     return OPCODE_AE_SP24X2F_I;
30875   if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 464 &&
30876       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30877     return OPCODE_AE_SP16X2F_I;
30878   if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 465 &&
30879       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30880     return OPCODE_AE_SP24X2F_IU;
30881   if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 466 &&
30882       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30883     return OPCODE_AE_SP24X2F_X;
30884   if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 467 &&
30885       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30886     return OPCODE_AE_SP24X2S_IU;
30887   if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 468 &&
30888       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30889     return OPCODE_AE_SP24X2F_XU;
30890   if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 469 &&
30891       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30892     return OPCODE_AE_SP24X2S_X;
30893   if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 470 &&
30894       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30895     return OPCODE_AE_SP24X2S_XU;
30896   if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 471 &&
30897       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30898     return OPCODE_AE_TRUNCP24A32X2;
30899   if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 472 &&
30900       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30901     return OPCODE_AE_SP24X2S_I;
30902   if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 946 &&
30903       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30904     return OPCODE_AE_SQ32F_I;
30905   if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 947 &&
30906       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30907     return OPCODE_AE_SQ32F_IU;
30908   if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 948 &&
30909       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30910     return OPCODE_AE_LQ32F_I;
30911   if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 949 &&
30912       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30913     return OPCODE_AE_LQ32F_X;
30914   if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 950 &&
30915       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30916     return OPCODE_AE_LQ32F_XU;
30917   if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 951 &&
30918       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30919     return OPCODE_AE_LQ56_I;
30920   if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 952 &&
30921       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30922     return OPCODE_AE_LQ32F_IU;
30923   if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 953 &&
30924       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30925     return OPCODE_AE_LQ56_IU;
30926   if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 954 &&
30927       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30928     return OPCODE_AE_LQ56_X;
30929   if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 15280 &&
30930       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30931     return OPCODE_AE_CVTQ48A32S;
30932   if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 60977 &&
30933       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30934     return OPCODE_JX;
30935   if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 61041 &&
30936       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30937     return OPCODE_SSR;
30938   if (Field_ftsf283ae_slot0_Slot_ae_slot0_get (insn) == 30577 &&
30939       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30940       Field_ftsf352ae_slot0_Slot_ae_slot0_get (insn) == 0)
30941     return OPCODE_NOP;
30942   if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 7641 &&
30943       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30944       Field_ftsf354ae_slot0_Slot_ae_slot0_get (insn) == 0)
30945     return OPCODE_SSA8B;
30946   if (Field_ftsf286ae_slot0_Slot_ae_slot0_get (insn) == 3821 &&
30947       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30948       Field_ftsf356ae_slot0_Slot_ae_slot0_get (insn) == 0)
30949     return OPCODE_SSA8L;
30950   if (Field_ftsf288ae_slot0_Slot_ae_slot0_get (insn) == 1911 &&
30951       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30952       Field_ftsf359ae_slot0_Slot_ae_slot0_get (insn) == 0)
30953     return OPCODE_SSL;
30954   if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 478 &&
30955       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30956       Field_s8_Slot_ae_slot0_get (insn) == 0)
30957     return OPCODE_AE_LQ56_XU;
30958   if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 1913 &&
30959       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30960       Field_s_Slot_ae_slot0_get (insn) == 0)
30961     return OPCODE_ALL8;
30962   if (Field_ftsf293_Slot_ae_slot0_get (insn) == 0 &&
30963       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
30964     return OPCODE_BBCI;
30965   if (Field_ftsf293_Slot_ae_slot0_get (insn) == 1 &&
30966       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
30967     return OPCODE_BBSI;
30968   if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 &&
30969       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30970       Field_s_Slot_ae_slot0_get (insn) == 0)
30971     return OPCODE_ANY8;
30972   if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 959 &&
30973       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30974       Field_ftsf358ae_slot0_Slot_ae_slot0_get (insn) == 0)
30975     return OPCODE_SSAI;
30976   if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 480 &&
30977       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30978     return OPCODE_AE_SP16X2F_IU;
30979   if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 962 &&
30980       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30981     return OPCODE_AE_SQ56S_I;
30982   if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 &&
30983       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30984     return OPCODE_AE_SQ56S_IU;
30985   if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 964 &&
30986       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30987     return OPCODE_AE_SLLIQ56;
30988   if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 965 &&
30989       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30990     return OPCODE_AE_SRAIQ56;
30991   if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 966 &&
30992       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30993     return OPCODE_AE_SRLIQ56;
30994   if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 968 &&
30995       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30996     return OPCODE_AE_SLLISQ56S;
30997   if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3868 &&
30998       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30999     return OPCODE_ABS;
31000   if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3869 &&
31001       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31002     return OPCODE_NEG;
31003   if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3870 &&
31004       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31005     return OPCODE_SRA;
31006   if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3871 &&
31007       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31008     return OPCODE_SRL;
31009   if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7752 &&
31010       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31011       Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
31012     return OPCODE_AE_MOVP48;
31013   if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7753 &&
31014       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31015       Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
31016     return OPCODE_ANY4;
31017   if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 &&
31018       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31019       Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
31020     return OPCODE_AE_MOVQ56;
31021   if (Field_ftsf303ae_slot0_Slot_ae_slot0_get (insn) == 31017 &&
31022       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31023       Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
31024     return OPCODE_AE_SLLSSQ56S;
31025   if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 15509 &&
31026       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31027       Field_ftsf369ae_slot0_Slot_ae_slot0_get (insn) == 0)
31028     return OPCODE_AE_SRASQ56;
31029   if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 7755 &&
31030       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31031       Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0)
31032     return OPCODE_AE_SRLSQ56;
31033   if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 1939 &&
31034       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31035       Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0)
31036     return OPCODE_AE_SLLSQ56;
31037   if (Field_ftsf309ae_slot0_Slot_ae_slot0_get (insn) == 485 &&
31038       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31039       Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0)
31040     return OPCODE_ALL4;
31041   if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 972 &&
31042       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31043     return OPCODE_AE_SQ56S_X;
31044   if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 973 &&
31045       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31046     return OPCODE_AE_SQ56S_XU;
31047   if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 7792 &&
31048       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31049     return OPCODE_AE_CVTA32P24_H;
31050   if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 7793 &&
31051       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31052     return OPCODE_AE_CVTA32P24_L;
31053   if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 7794 &&
31054       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31055     return OPCODE_AE_MOVAP24S_H;
31056   if (Field_ftsf315ae_slot0_Slot_ae_slot0_get (insn) == 7795 &&
31057       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31058     return OPCODE_AE_TRUNCA16P24S_L;
31059   if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 7796 &&
31060       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31061     return OPCODE_AE_MOVAP24S_L;
31062   if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 7797 &&
31063       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31064       Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
31065     return OPCODE_AE_NSAQ56S;
31066   if (Field_ftsf318ae_slot0_Slot_ae_slot0_get (insn) == 3899 &&
31067       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31068       Field_ftsf365ae_slot0_Slot_ae_slot0_get (insn) == 0)
31069     return OPCODE_AE_TRUNCA32Q48;
31070   if (Field_ftsf319_Slot_ae_slot0_get (insn) == 3 &&
31071       Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
31072       Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0)
31073     return OPCODE_BT;
31074   if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 975 &&
31075       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31076       Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
31077     return OPCODE_AE_TRUNCA16P24S_H;
31078   if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 &&
31079       Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
31080       Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
31081     return OPCODE_BLTUI;
31082   if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 3920 &&
31083       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31084     return OPCODE_AE_MOVFQ56;
31085   if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 3921 &&
31086       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31087     return OPCODE_AE_SLLAQ56;
31088   if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 3922 &&
31089       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31090     return OPCODE_AE_SLLASQ56S;
31091   if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 3923 &&
31092       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31093     return OPCODE_SLL;
31094   if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 981 &&
31095       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31096       Field_ftsf357_Slot_ae_slot0_get (insn) == 0)
31097     return OPCODE_AE_SRAAQ56;
31098   if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 491 &&
31099       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31100       Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
31101     return OPCODE_AE_SRLAQ56;
31102   if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 &&
31103       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31104       Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0)
31105     return OPCODE_AE_SQ32F_XU;
31106   if (Field_imm8_Slot_ae_slot0_get (insn) == 178 &&
31107       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31108     return OPCODE_ADD;
31109   if (Field_imm8_Slot_ae_slot0_get (insn) == 179 &&
31110       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31111     return OPCODE_ADDX8;
31112   if (Field_imm8_Slot_ae_slot0_get (insn) == 180 &&
31113       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31114     return OPCODE_ADDX2;
31115   if (Field_imm8_Slot_ae_slot0_get (insn) == 181 &&
31116       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31117     return OPCODE_AND;
31118   if (Field_imm8_Slot_ae_slot0_get (insn) == 182 &&
31119       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31120     return OPCODE_ANDB;
31121   if (Field_imm8_Slot_ae_slot0_get (insn) == 183 &&
31122       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31123     return OPCODE_ANDBC;
31124   if (Field_imm8_Slot_ae_slot0_get (insn) == 184 &&
31125       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31126     return OPCODE_ADDX4;
31127   if (Field_imm8_Slot_ae_slot0_get (insn) == 185 &&
31128       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31129     return OPCODE_CLAMPS;
31130   if (Field_imm8_Slot_ae_slot0_get (insn) == 186 &&
31131       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31132     return OPCODE_MAX;
31133   if (Field_imm8_Slot_ae_slot0_get (insn) == 187 &&
31134       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31135     return OPCODE_MIN;
31136   if (Field_imm8_Slot_ae_slot0_get (insn) == 188 &&
31137       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31138     return OPCODE_MAXU;
31139   if (Field_imm8_Slot_ae_slot0_get (insn) == 189 &&
31140       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31141     return OPCODE_MINU;
31142   if (Field_imm8_Slot_ae_slot0_get (insn) == 190 &&
31143       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31144     return OPCODE_MOVEQZ;
31145   if (Field_imm8_Slot_ae_slot0_get (insn) == 191 &&
31146       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31147     return OPCODE_MOVF;
31148   if (Field_imm8_Slot_ae_slot0_get (insn) == 194 &&
31149       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31150     return OPCODE_MOVGEZ;
31151   if (Field_imm8_Slot_ae_slot0_get (insn) == 195 &&
31152       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31153     return OPCODE_ORB;
31154   if (Field_imm8_Slot_ae_slot0_get (insn) == 196 &&
31155       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31156     return OPCODE_MOVLTZ;
31157   if (Field_imm8_Slot_ae_slot0_get (insn) == 197 &&
31158       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31159     return OPCODE_ORBC;
31160   if (Field_imm8_Slot_ae_slot0_get (insn) == 198 &&
31161       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31162     return OPCODE_SEXT;
31163   if (Field_imm8_Slot_ae_slot0_get (insn) == 199 &&
31164       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31165     return OPCODE_SRC;
31166   if (Field_imm8_Slot_ae_slot0_get (insn) == 200 &&
31167       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31168     return OPCODE_MOVNEZ;
31169   if (Field_imm8_Slot_ae_slot0_get (insn) == 201 &&
31170       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31171     return OPCODE_SRLI;
31172   if (Field_imm8_Slot_ae_slot0_get (insn) == 202 &&
31173       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31174     return OPCODE_SUB;
31175   if (Field_imm8_Slot_ae_slot0_get (insn) == 203 &&
31176       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31177     return OPCODE_SUBX4;
31178   if (Field_imm8_Slot_ae_slot0_get (insn) == 204 &&
31179       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31180     return OPCODE_SUBX2;
31181   if (Field_imm8_Slot_ae_slot0_get (insn) == 205 &&
31182       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31183     return OPCODE_SUBX8;
31184   if (Field_imm8_Slot_ae_slot0_get (insn) == 206 &&
31185       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31186     return OPCODE_XOR;
31187   if (Field_imm8_Slot_ae_slot0_get (insn) == 207 &&
31188       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31189     return OPCODE_XORB;
31190   if (Field_imm8_Slot_ae_slot0_get (insn) == 208 &&
31191       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31192     return OPCODE_MOVT;
31193   if (Field_imm8_Slot_ae_slot0_get (insn) == 224 &&
31194       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31195     return OPCODE_OR;
31196   if (Field_imm8_Slot_ae_slot0_get (insn) == 244 &&
31197       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31198       Field_ae_r32_Slot_ae_slot0_get (insn) == 0)
31199     return OPCODE_AE_SQ32F_X;
31200   if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5)
31201     return OPCODE_L32R;
31202   if (Field_r_Slot_ae_slot0_get (insn) == 0 &&
31203       Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31204     return OPCODE_BNE;
31205   if (Field_r_Slot_ae_slot0_get (insn) == 1 &&
31206       Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31207     return OPCODE_BNONE;
31208   if (Field_r_Slot_ae_slot0_get (insn) == 2 &&
31209       Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31210     return OPCODE_L16SI;
31211   if (Field_r_Slot_ae_slot0_get (insn) == 3 &&
31212       Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31213     return OPCODE_L8UI;
31214   if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
31215       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31216     return OPCODE_ADDI;
31217   if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
31218       Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31219     return OPCODE_L16UI;
31220   if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
31221       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31222     return OPCODE_BALL;
31223   if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
31224       Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31225     return OPCODE_S16I;
31226   if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
31227       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31228     return OPCODE_BANY;
31229   if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
31230       Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31231     return OPCODE_S32I;
31232   if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
31233       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31234     return OPCODE_BBC;
31235   if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
31236       Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31237     return OPCODE_S8I;
31238   if (Field_r_Slot_ae_slot0_get (insn) == 8 &&
31239       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31240     return OPCODE_ADDMI;
31241   if (Field_r_Slot_ae_slot0_get (insn) == 9 &&
31242       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31243     return OPCODE_BBS;
31244   if (Field_r_Slot_ae_slot0_get (insn) == 10 &&
31245       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31246     return OPCODE_BEQ;
31247   if (Field_r_Slot_ae_slot0_get (insn) == 11 &&
31248       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31249     return OPCODE_BGEU;
31250   if (Field_r_Slot_ae_slot0_get (insn) == 12 &&
31251       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31252     return OPCODE_BGE;
31253   if (Field_r_Slot_ae_slot0_get (insn) == 13 &&
31254       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31255     return OPCODE_BLT;
31256   if (Field_r_Slot_ae_slot0_get (insn) == 14 &&
31257       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31258     return OPCODE_BLTU;
31259   if (Field_r_Slot_ae_slot0_get (insn) == 15 &&
31260       Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31261     return OPCODE_BNALL;
31262   if (Field_t_Slot_ae_slot0_get (insn) == 0 &&
31263       Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31264     return OPCODE_BEQI;
31265   if (Field_t_Slot_ae_slot0_get (insn) == 1 &&
31266       Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31267     return OPCODE_BGEI;
31268   if (Field_t_Slot_ae_slot0_get (insn) == 2 &&
31269       Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31270     return OPCODE_BGEUI;
31271   if (Field_t_Slot_ae_slot0_get (insn) == 3 &&
31272       Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31273     return OPCODE_BNEI;
31274   if (Field_t_Slot_ae_slot0_get (insn) == 4 &&
31275       Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31276     return OPCODE_BLTI;
31277   if (Field_t_Slot_ae_slot0_get (insn) == 5 &&
31278       Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
31279       Field_r_Slot_ae_slot0_get (insn) == 0)
31280     return OPCODE_BF;
31281   return XTENSA_UNDEFINED;
31282 }
31283
31284 static int
31285 Slot_ae_slot1_decode (const xtensa_insnbuf insn)
31286 {
31287   if (Field_ftsf100ae_slot1_Slot_ae_slot1_get (insn) == 115 &&
31288       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31289       Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
31290     return OPCODE_AE_NEGSP24S;
31291   if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
31292       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31293       Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0)
31294     return OPCODE_AE_ABSSP24S;
31295   if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
31296       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31297       Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0)
31298     return OPCODE_AE_NEGP24;
31299   if (Field_ftsf104ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
31300       Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31301     return OPCODE_AE_MAXBQ56S;
31302   if (Field_ftsf105ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31303       Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31304     return OPCODE_AE_MINBQ56S;
31305   if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
31306       Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31307       Field_ae_r32_Slot_ae_slot1_get (insn) == 0)
31308     return OPCODE_AE_EQQ56;
31309   if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 48 &&
31310       Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31311     return OPCODE_AE_ADDSQ56S;
31312   if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
31313       Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31314     return OPCODE_AE_ANDQ56;
31315   if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 50 &&
31316       Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31317     return OPCODE_AE_MAXQ56S;
31318   if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 51 &&
31319       Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31320     return OPCODE_AE_ORQ56;
31321   if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
31322       Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31323     return OPCODE_AE_MINQ56S;
31324   if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
31325       Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31326     return OPCODE_AE_SUBQ56;
31327   if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 54 &&
31328       Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31329     return OPCODE_AE_SUBSQ56S;
31330   if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 55 &&
31331       Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31332     return OPCODE_AE_XORQ56;
31333   if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 56 &&
31334       Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31335     return OPCODE_AE_NANDQ56;
31336   if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 57 &&
31337       Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31338     return OPCODE_AE_ABSQ56;
31339   if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
31340       Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31341     return OPCODE_AE_NEGSQ56S;
31342   if (Field_ftsf119ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
31343       Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31344       Field_ftsf338_Slot_ae_slot1_get (insn) == 0)
31345     return OPCODE_AE_SATQ48S;
31346   if (Field_ftsf12_Slot_ae_slot1_get (insn) == 1 &&
31347       Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31348       Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0)
31349     return OPCODE_AE_LTQ56S;
31350   if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
31351       Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31352       Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0)
31353     return OPCODE_AE_ABSSQ56S;
31354   if (Field_ftsf122ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
31355       Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31356       Field_ftsf346ae_slot1_Slot_ae_slot1_get (insn) == 0)
31357     return OPCODE_AE_NEGQ56;
31358   if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31359       Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31360       Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0)
31361     return OPCODE_AE_LEQ56S;
31362   if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31363       Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31364       Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0)
31365     return OPCODE_AE_TRUNCP24Q48X2;
31366   if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31367       Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31368       Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0)
31369     return OPCODE_AE_ADDQ56;
31370   if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
31371       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31372     return OPCODE_AE_MULAAFP24S_HH_LL;
31373   if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31374       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31375     return OPCODE_AE_MULAAFP24S_HL_LH;
31376   if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
31377       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31378     return OPCODE_AE_MULAAP24S_HH_LL;
31379   if (Field_ftsf13_Slot_ae_slot1_get (insn) == 2 &&
31380       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31381       Field_ftsf12_Slot_ae_slot1_get (insn) == 0)
31382     return OPCODE_AE_SLLISP24S;
31383   if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
31384       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31385     return OPCODE_AE_MULAFS32P16S_HL;
31386   if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 4 &&
31387       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31388     return OPCODE_AE_MULAAP24S_HL_LH;
31389   if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 5 &&
31390       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31391     return OPCODE_AE_MULAFS32P16S_LH;
31392   if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 6 &&
31393       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31394     return OPCODE_AE_MULAFS32P16S_LL;
31395   if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
31396       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31397     return OPCODE_AE_MULAFS56P24S_HH;
31398   if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
31399       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31400     return OPCODE_AE_MULAFP24S_HH;
31401   if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
31402       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31403     return OPCODE_AE_MULAFS56P24S_HL;
31404   if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
31405       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31406     return OPCODE_AE_MULAFS56P24S_LH;
31407   if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
31408       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31409     return OPCODE_AE_MULAP24S_HH;
31410   if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 12 &&
31411       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31412     return OPCODE_AE_MULAFS56P24S_LL;
31413   if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 13 &&
31414       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31415     return OPCODE_AE_MULAP24S_HL;
31416   if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 14 &&
31417       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31418     return OPCODE_AE_MULAP24S_LH;
31419   if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
31420       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31421     return OPCODE_AE_MULAP24S_LL;
31422   if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 16 &&
31423       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31424     return OPCODE_AE_MULAFP24S_HL;
31425   if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 17 &&
31426       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31427     return OPCODE_AE_MULAS56P24S_HH;
31428   if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 18 &&
31429       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31430     return OPCODE_AE_MULAS56P24S_HL;
31431   if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 19 &&
31432       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31433     return OPCODE_AE_MULASFP24S_HH_LL;
31434   if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
31435       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31436     return OPCODE_AE_MULAS56P24S_LH;
31437   if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
31438       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31439     return OPCODE_AE_MULASFP24S_HL_LH;
31440   if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 22 &&
31441       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31442     return OPCODE_AE_MULASP24S_HH_LL;
31443   if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 23 &&
31444       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31445     return OPCODE_AE_MULASP24S_HL_LH;
31446   if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
31447       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31448     return OPCODE_AE_MULAS56P24S_LL;
31449   if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
31450       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31451     return OPCODE_AE_MULFP24S_HH;
31452   if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
31453       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31454     return OPCODE_AE_MULFP24S_HL;
31455   if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 27 &&
31456       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31457     return OPCODE_AE_MULFP24S_LL;
31458   if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 28 &&
31459       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31460     return OPCODE_AE_MULFP24S_LH;
31461   if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
31462       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31463     return OPCODE_AE_MULFS32P16S_HH;
31464   if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 30 &&
31465       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31466     return OPCODE_AE_MULFS32P16S_HL;
31467   if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
31468       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31469     return OPCODE_AE_MULFS32P16S_LH;
31470   if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 32 &&
31471       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31472     return OPCODE_AE_MULAFP24S_LH;
31473   if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 33 &&
31474       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31475     return OPCODE_AE_MULFS32P16S_LL;
31476   if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 34 &&
31477       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31478     return OPCODE_AE_MULP24S_HH;
31479   if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 35 &&
31480       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31481     return OPCODE_AE_MULSAFP24S_HH_LL;
31482   if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 36 &&
31483       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31484     return OPCODE_AE_MULP24S_HL;
31485   if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 37 &&
31486       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31487     return OPCODE_AE_MULSAFP24S_HL_LH;
31488   if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 38 &&
31489       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31490     return OPCODE_AE_MULSAP24S_HH_LL;
31491   if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 39 &&
31492       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31493     return OPCODE_AE_MULSAP24S_HL_LH;
31494   if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 40 &&
31495       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31496     return OPCODE_AE_MULP24S_LH;
31497   if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 41 &&
31498       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31499     return OPCODE_AE_MULSFP24S_HH;
31500   if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 42 &&
31501       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31502     return OPCODE_AE_MULSFP24S_HL;
31503   if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 43 &&
31504       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31505     return OPCODE_AE_MULSFP24S_LL;
31506   if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 44 &&
31507       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31508     return OPCODE_AE_MULSFP24S_LH;
31509   if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 45 &&
31510       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31511     return OPCODE_AE_MULSFS32P16S_HH;
31512   if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 46 &&
31513       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31514     return OPCODE_AE_MULSFS32P16S_HL;
31515   if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 47 &&
31516       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31517     return OPCODE_AE_MULSFS32P16S_LH;
31518   if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 48 &&
31519       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31520     return OPCODE_AE_MULP24S_LL;
31521   if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
31522       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31523     return OPCODE_AE_MULSFS32P16S_LL;
31524   if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 50 &&
31525       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31526     return OPCODE_AE_MULSFS56P24S_HH;
31527   if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 51 &&
31528       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31529     return OPCODE_AE_MULSFS56P24S_LL;
31530   if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
31531       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31532     return OPCODE_AE_MULSFS56P24S_HL;
31533   if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
31534       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31535     return OPCODE_AE_MULSP24S_HH;
31536   if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 54 &&
31537       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31538     return OPCODE_AE_MULSP24S_HL;
31539   if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 55 &&
31540       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31541     return OPCODE_AE_MULSP24S_LH;
31542   if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 56 &&
31543       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31544     return OPCODE_AE_MULSFS56P24S_LH;
31545   if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 57 &&
31546       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31547     return OPCODE_AE_MULSP24S_LL;
31548   if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 58 &&
31549       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31550     return OPCODE_AE_MULSS56P24S_HH;
31551   if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 59 &&
31552       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31553     return OPCODE_AE_MULSS56P24S_LH;
31554   if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 60 &&
31555       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31556     return OPCODE_AE_MULSS56P24S_HL;
31557   if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 61 &&
31558       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31559     return OPCODE_AE_MULSS56P24S_LL;
31560   if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 62 &&
31561       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31562     return OPCODE_AE_MULSSFP24S_HH_LL;
31563   if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 63 &&
31564       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31565     return OPCODE_AE_MULSSFP24S_HL_LH;
31566   if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 64 &&
31567       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31568     return OPCODE_AE_MULAFP24S_LL;
31569   if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 65 &&
31570       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31571     return OPCODE_AE_MULSSP24S_HH_LL;
31572   if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 66 &&
31573       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31574     return OPCODE_AE_MULSSP24S_HL_LH;
31575   if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 67 &&
31576       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31577     return OPCODE_AE_MULZASFP24S_HH_LL;
31578   if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 68 &&
31579       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31580     return OPCODE_AE_MULZAAFP24S_HH_LL;
31581   if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 69 &&
31582       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31583     return OPCODE_AE_MULZASFP24S_HL_LH;
31584   if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 70 &&
31585       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31586     return OPCODE_AE_MULZASP24S_HH_LL;
31587   if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 71 &&
31588       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31589     return OPCODE_AE_MULZASP24S_HL_LH;
31590   if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 72 &&
31591       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31592     return OPCODE_AE_MULZAAFP24S_HL_LH;
31593   if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 73 &&
31594       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31595     return OPCODE_AE_MULZSAFP24S_HH_LL;
31596   if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 74 &&
31597       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31598     return OPCODE_AE_MULZSAFP24S_HL_LH;
31599   if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 75 &&
31600       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31601     return OPCODE_AE_MULZSAP24S_HL_LH;
31602   if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 76 &&
31603       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31604     return OPCODE_AE_MULZSAP24S_HH_LL;
31605   if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 77 &&
31606       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31607     return OPCODE_AE_MULZSSFP24S_HH_LL;
31608   if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 78 &&
31609       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31610     return OPCODE_AE_MULZSSFP24S_HL_LH;
31611   if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 79 &&
31612       Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31613     return OPCODE_AE_MULZSSP24S_HH_LL;
31614   if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
31615       Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
31616       Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0)
31617     return OPCODE_AE_MULZAAP24S_HH_LL;
31618   if (Field_ftsf209ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
31619       Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
31620       Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0)
31621     return OPCODE_AE_MULZSSP24S_HL_LH;
31622   if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
31623       Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
31624       Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0)
31625     return OPCODE_AE_MULZAAP24S_HL_LH;
31626   if (Field_ftsf211ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31627       Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
31628       Field_ftsf332ae_slot1_Slot_ae_slot1_get (insn) == 0)
31629     return OPCODE_AE_MULAFS32P16S_HH;
31630   if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
31631       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31632     return OPCODE_AE_MAXBP24S;
31633   if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31634       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31635     return OPCODE_AE_MINBP24S;
31636   if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
31637       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31638     return OPCODE_AE_MOVFP48;
31639   if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
31640       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31641     return OPCODE_AE_MOVTP48;
31642   if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
31643       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31644     return OPCODE_AE_ADDP24;
31645   if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
31646       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31647     return OPCODE_AE_ANDP48;
31648   if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 22 &&
31649       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31650     return OPCODE_AE_MAXP24S;
31651   if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 23 &&
31652       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31653     return OPCODE_AE_MINP24S;
31654   if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
31655       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31656     return OPCODE_AE_ADDSP24S;
31657   if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
31658       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31659     return OPCODE_AE_NANDP48;
31660   if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
31661       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31662     return OPCODE_AE_ORP48;
31663   if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 27 &&
31664       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31665     return OPCODE_AE_SELP24_HL;
31666   if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 28 &&
31667       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31668     return OPCODE_AE_SELP24_HH;
31669   if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
31670       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31671     return OPCODE_AE_SELP24_LH;
31672   if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 30 &&
31673       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31674     return OPCODE_AE_SELP24_LL;
31675   if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
31676       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31677     return OPCODE_AE_SUBP24;
31678   if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
31679       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31680     return OPCODE_AE_SLLIP24;
31681   if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
31682       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31683     return OPCODE_AE_SRAIP24;
31684   if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
31685       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31686     return OPCODE_AE_SRLIP24;
31687   if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 &&
31688       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31689     return OPCODE_AE_MULAFQ32SP16S_L;
31690   if (Field_ftsf39ae_slot1_Slot_ae_slot1_get (insn) == 177 &&
31691       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31692     return OPCODE_AE_MULAFQ32SP16U_H;
31693   if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 178 &&
31694       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31695     return OPCODE_AE_MULAFQ32SP16U_L;
31696   if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 179 &&
31697       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31698     return OPCODE_AE_MULAQ32SP16U_H;
31699   if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 180 &&
31700       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31701     return OPCODE_AE_MULAQ32SP16S_H;
31702   if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 181 &&
31703       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31704     return OPCODE_AE_MULAQ32SP16U_L;
31705   if (Field_ftsf44ae_slot1_Slot_ae_slot1_get (insn) == 182 &&
31706       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31707     return OPCODE_AE_MULFQ32SP16S_H;
31708   if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 183 &&
31709       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31710     return OPCODE_AE_MULFQ32SP16S_L;
31711   if (Field_ftsf46ae_slot1_Slot_ae_slot1_get (insn) == 184 &&
31712       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31713     return OPCODE_AE_MULAQ32SP16S_L;
31714   if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
31715       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31716     return OPCODE_AE_MULFQ32SP16U_H;
31717   if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 186 &&
31718       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31719     return OPCODE_AE_MULFQ32SP16U_L;
31720   if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 187 &&
31721       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31722     return OPCODE_AE_MULQ32SP16S_L;
31723   if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 188 &&
31724       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31725     return OPCODE_AE_MULQ32SP16S_H;
31726   if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 189 &&
31727       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31728     return OPCODE_AE_MULQ32SP16U_H;
31729   if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 190 &&
31730       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31731     return OPCODE_AE_MULQ32SP16U_L;
31732   if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 191 &&
31733       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31734     return OPCODE_AE_MULSFQ32SP16S_H;
31735   if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 192 &&
31736       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31737     return OPCODE_AE_MULAFQ32SP16S_H;
31738   if (Field_ftsf55ae_slot1_Slot_ae_slot1_get (insn) == 193 &&
31739       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31740     return OPCODE_AE_MULSFQ32SP16S_L;
31741   if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 194 &&
31742       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31743     return OPCODE_AE_MULSFQ32SP16U_H;
31744   if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 195 &&
31745       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31746     return OPCODE_AE_MULSQ32SP16U_L;
31747   if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 196 &&
31748       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31749     return OPCODE_AE_MULSFQ32SP16U_L;
31750   if (Field_ftsf59ae_slot1_Slot_ae_slot1_get (insn) == 773 &&
31751       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31752     return OPCODE_AE_CVTQ48P24S_H;
31753   if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 789 &&
31754       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31755       Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
31756     return OPCODE_AE_ZEROQ56;
31757   if (Field_ftsf61ae_slot1_Slot_ae_slot1_get (insn) == 405 &&
31758       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31759       Field_ftsf330ae_slot1_Slot_ae_slot1_get (insn) == 0)
31760     return OPCODE_NOP;
31761   if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 198 &&
31762       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31763       Field_ae_r10_Slot_ae_slot1_get (insn) == 0)
31764     return OPCODE_AE_CVTQ48P24S_L;
31765   if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 1543 &&
31766       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31767     return OPCODE_AE_MOVQ56;
31768   if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 1559 &&
31769       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31770     return OPCODE_AE_ROUNDSQ32ASYM;
31771   if (Field_ftsf67ae_slot1_Slot_ae_slot1_get (insn) == 791 &&
31772       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31773       Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0)
31774     return OPCODE_AE_ROUNDSQ32SYM;
31775   if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 407 &&
31776       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31777       Field_ftsf340_Slot_ae_slot1_get (insn) == 0)
31778     return OPCODE_AE_TRUNCQ32;
31779   if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
31780       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31781       Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
31782     return OPCODE_AE_MULSQ32SP16S_H;
31783   if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
31784       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31785       Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
31786     return OPCODE_AE_MULSQ32SP16S_L;
31787   if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 417 &&
31788       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31789     return OPCODE_AE_MOVP48;
31790   if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 419 &&
31791       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31792     return OPCODE_AE_ROUNDSP16ASYM;
31793   if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 421 &&
31794       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31795     return OPCODE_AE_ROUNDSP16SYM;
31796   if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 423 &&
31797       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31798     return OPCODE_AE_SRASP24;
31799   if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 425 &&
31800       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31801     return OPCODE_AE_SLLSP24;
31802   if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 427 &&
31803       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31804     return OPCODE_AE_SRLSP24;
31805   if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 429 &&
31806       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31807     return OPCODE_AE_TRUNCP16;
31808   if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 431 &&
31809       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31810       Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
31811     return OPCODE_AE_ZEROP48;
31812   if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 109 &&
31813       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31814       Field_ae_r10_Slot_ae_slot1_get (insn) == 0)
31815     return OPCODE_AE_SLLSSP24S;
31816   if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 881 &&
31817       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31818     return OPCODE_AE_ROUNDSP16Q48ASYM;
31819   if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 883 &&
31820       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31821     return OPCODE_AE_ROUNDSP16Q48SYM;
31822   if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 443 &&
31823       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31824       Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0)
31825     return OPCODE_AE_ROUNDSP24Q48ASYM;
31826   if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 223 &&
31827       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31828       Field_ftsf340_Slot_ae_slot1_get (insn) == 0)
31829     return OPCODE_AE_ROUNDSP24Q48SYM;
31830   if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
31831       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31832       Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0)
31833     return OPCODE_AE_MULSQ32SP16U_H;
31834   if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 96 &&
31835       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31836     return OPCODE_AE_EQP24;
31837   if (Field_ftsf91ae_slot1_Slot_ae_slot1_get (insn) == 97 &&
31838       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31839     return OPCODE_AE_LEP24S;
31840   if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
31841       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31842       Field_ftsf208_Slot_ae_slot1_get (insn) == 0)
31843     return OPCODE_AE_LTP24S;
31844   if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
31845       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31846       Field_ftsf347_Slot_ae_slot1_get (insn) == 0)
31847     return OPCODE_AE_MOVFP24X2;
31848   if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 13 &&
31849       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31850       Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
31851     return OPCODE_AE_MOVTP24X2;
31852   if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 112 &&
31853       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31854     return OPCODE_AE_SUBSP24S;
31855   if (Field_ftsf98ae_slot1_Slot_ae_slot1_get (insn) == 113 &&
31856       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31857     return OPCODE_AE_XORP48;
31858   if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 114 &&
31859       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31860       Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
31861     return OPCODE_AE_ABSP24;
31862   if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
31863       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31864     return OPCODE_AE_MULZAAFQ32SP16S_HH;
31865   if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
31866       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31867     return OPCODE_AE_MULZASFQ32SP16U_LH;
31868   if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
31869       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31870     return OPCODE_AE_MULZSAQ32SP16S_LL;
31871   if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
31872       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31873     return OPCODE_AE_MULZAAFQ32SP16S_LH;
31874   if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
31875       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31876     return OPCODE_AE_MULZASFQ32SP16U_LL;
31877   if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
31878       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31879     return OPCODE_AE_MULZSAQ32SP16U_HH;
31880   if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
31881       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31882     return OPCODE_AE_MULZAAFQ32SP16S_LL;
31883   if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
31884       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31885     return OPCODE_AE_MULZASQ32SP16S_HH;
31886   if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
31887       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31888     return OPCODE_AE_MULZSAQ32SP16U_LH;
31889   if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
31890       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31891     return OPCODE_AE_MULZAAFQ32SP16U_LL;
31892   if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
31893       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31894     return OPCODE_AE_MULZASQ32SP16U_HH;
31895   if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
31896       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31897     return OPCODE_AE_MULZSSFQ32SP16S_LH;
31898   if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
31899       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31900     return OPCODE_AE_MULZAAFQ32SP16U_HH;
31901   if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
31902       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31903     return OPCODE_AE_MULZASQ32SP16S_LH;
31904   if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
31905       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31906     return OPCODE_AE_MULZSAQ32SP16U_LL;
31907   if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
31908       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31909     return OPCODE_AE_MULZAAQ32SP16S_HH;
31910   if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
31911       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31912     return OPCODE_AE_MULZASQ32SP16U_LH;
31913   if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
31914       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31915     return OPCODE_AE_MULZSSFQ32SP16S_LL;
31916   if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
31917       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31918     return OPCODE_AE_MULZAAQ32SP16S_LH;
31919   if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
31920       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31921     return OPCODE_AE_MULZASQ32SP16U_LL;
31922   if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
31923       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31924     return OPCODE_AE_MULZSSFQ32SP16U_HH;
31925   if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
31926       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31927     return OPCODE_AE_MULZAAQ32SP16S_LL;
31928   if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
31929       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31930     return OPCODE_AE_MULZSAFQ32SP16S_HH;
31931   if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
31932       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31933     return OPCODE_AE_MULZSSFQ32SP16U_LH;
31934   if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
31935       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31936     return OPCODE_AE_MULZAAFQ32SP16U_LH;
31937   if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
31938       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31939     return OPCODE_AE_MULZASQ32SP16S_LL;
31940   if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
31941       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31942     return OPCODE_AE_MULZSSFQ32SP16S_HH;
31943   if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
31944       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31945     return OPCODE_AE_MULZAAQ32SP16U_HH;
31946   if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
31947       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31948     return OPCODE_AE_MULZSAFQ32SP16S_LH;
31949   if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
31950       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31951     return OPCODE_AE_MULZSSFQ32SP16U_LL;
31952   if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
31953       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31954     return OPCODE_AE_MULZAAQ32SP16U_LH;
31955   if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
31956       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31957     return OPCODE_AE_MULZSAFQ32SP16S_LL;
31958   if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
31959       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31960     return OPCODE_AE_MULZSSQ32SP16S_HH;
31961   if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
31962       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31963     return OPCODE_AE_MULZASFQ32SP16S_HH;
31964   if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
31965       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31966     return OPCODE_AE_MULZSAFQ32SP16U_LH;
31967   if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
31968       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31969     return OPCODE_AE_MULZSSQ32SP16S_LL;
31970   if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
31971       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31972     return OPCODE_AE_MULZAAQ32SP16U_LL;
31973   if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
31974       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31975     return OPCODE_AE_MULZSAFQ32SP16U_HH;
31976   if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
31977       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31978     return OPCODE_AE_MULZSSQ32SP16S_LH;
31979   if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
31980       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31981     return OPCODE_AE_MULZASFQ32SP16S_LH;
31982   if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
31983       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31984     return OPCODE_AE_MULZSAFQ32SP16U_LL;
31985   if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
31986       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31987     return OPCODE_AE_MULZSSQ32SP16U_HH;
31988   if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
31989       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31990     return OPCODE_AE_MULZASFQ32SP16S_LL;
31991   if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
31992       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31993     return OPCODE_AE_MULZSAQ32SP16S_HH;
31994   if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
31995       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31996     return OPCODE_AE_MULZSSQ32SP16U_LH;
31997   if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
31998       Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31999     return OPCODE_AE_MULZASFQ32SP16U_HH;
32000   if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
32001       Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32002     return OPCODE_AE_MULZSAQ32SP16S_LH;
32003   if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
32004       Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32005     return OPCODE_AE_MULZSSQ32SP16U_LL;
32006   return XTENSA_UNDEFINED;
32007 }
32008
32009 \f
32010 /* Instruction slots.  */
32011
32012 static void
32013 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
32014                             xtensa_insnbuf slotbuf)
32015 {
32016   slotbuf[1] = 0;
32017   slotbuf[0] = (insn[0] & 0xffffff);
32018 }
32019
32020 static void
32021 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
32022                             const xtensa_insnbuf slotbuf)
32023 {
32024   insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
32025 }
32026
32027 static void
32028 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
32029                                 xtensa_insnbuf slotbuf)
32030 {
32031   slotbuf[1] = 0;
32032   slotbuf[0] = (insn[0] & 0xffff);
32033 }
32034
32035 static void
32036 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
32037                                 const xtensa_insnbuf slotbuf)
32038 {
32039   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
32040 }
32041
32042 static void
32043 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
32044                                 xtensa_insnbuf slotbuf)
32045 {
32046   slotbuf[1] = 0;
32047   slotbuf[0] = (insn[0] & 0xffff);
32048 }
32049
32050 static void
32051 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
32052                                 const xtensa_insnbuf slotbuf)
32053 {
32054   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
32055 }
32056
32057 static void
32058 Slot_ae_format_Format_ae_slot1_31_get (const xtensa_insnbuf insn,
32059                                       xtensa_insnbuf slotbuf)
32060 {
32061   slotbuf[1] = 0;
32062   slotbuf[0] = ((insn[0] & 0x80000000) >> 31);
32063   slotbuf[0] = (slotbuf[0] & ~0x7ffffe) | ((insn[1] & 0x3fffff) << 1);
32064 }
32065
32066 static void
32067 Slot_ae_format_Format_ae_slot1_31_set (xtensa_insnbuf insn,
32068                                       const xtensa_insnbuf slotbuf)
32069 {
32070   insn[0] = (insn[0] & ~0x80000000) | ((slotbuf[0] & 0x1) << 31);
32071   insn[1] = (insn[1] & ~0x3fffff) | ((slotbuf[0] & 0x7ffffe) >> 1);
32072 }
32073
32074 static void
32075 Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn,
32076                                       xtensa_insnbuf slotbuf)
32077 {
32078   slotbuf[1] = 0;
32079   slotbuf[0] = ((insn[0] & 0x7ffffff0) >> 4);
32080 }
32081
32082 static void
32083 Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn,
32084                                       const xtensa_insnbuf slotbuf)
32085 {
32086   insn[0] = (insn[0] & ~0x7ffffff0) | ((slotbuf[0] & 0x7ffffff) << 4);
32087 }
32088
32089 static xtensa_get_field_fn
32090 Slot_inst_get_field_fns[] = {
32091   Field_t_Slot_inst_get,
32092   Field_bbi4_Slot_inst_get,
32093   Field_bbi_Slot_inst_get,
32094   Field_imm12_Slot_inst_get,
32095   Field_imm8_Slot_inst_get,
32096   Field_s_Slot_inst_get,
32097   Field_imm12b_Slot_inst_get,
32098   Field_imm16_Slot_inst_get,
32099   Field_m_Slot_inst_get,
32100   Field_n_Slot_inst_get,
32101   Field_offset_Slot_inst_get,
32102   Field_op0_Slot_inst_get,
32103   Field_op1_Slot_inst_get,
32104   Field_op2_Slot_inst_get,
32105   Field_r_Slot_inst_get,
32106   Field_sa4_Slot_inst_get,
32107   Field_sae4_Slot_inst_get,
32108   Field_sae_Slot_inst_get,
32109   Field_sal_Slot_inst_get,
32110   Field_sargt_Slot_inst_get,
32111   Field_sas4_Slot_inst_get,
32112   Field_sas_Slot_inst_get,
32113   Field_sr_Slot_inst_get,
32114   Field_st_Slot_inst_get,
32115   Field_thi3_Slot_inst_get,
32116   Field_imm4_Slot_inst_get,
32117   Field_mn_Slot_inst_get,
32118   0,
32119   0,
32120   0,
32121   0,
32122   0,
32123   0,
32124   0,
32125   0,
32126   Field_t2_Slot_inst_get,
32127   Field_s2_Slot_inst_get,
32128   Field_r2_Slot_inst_get,
32129   Field_t4_Slot_inst_get,
32130   Field_s4_Slot_inst_get,
32131   Field_r4_Slot_inst_get,
32132   Field_t8_Slot_inst_get,
32133   Field_s8_Slot_inst_get,
32134   Field_r8_Slot_inst_get,
32135   Field_xt_wbr15_imm_Slot_inst_get,
32136   Field_xt_wbr18_imm_Slot_inst_get,
32137   Field_ae_r3_Slot_inst_get,
32138   Field_ae_s_non_samt_Slot_inst_get,
32139   Field_ae_s3_Slot_inst_get,
32140   Field_ae_r32_Slot_inst_get,
32141   Field_ae_samt_s_t_Slot_inst_get,
32142   Field_ae_r20_Slot_inst_get,
32143   Field_ae_r10_Slot_inst_get,
32144   Field_ae_s20_Slot_inst_get,
32145   Field_ae_fld_ohba_Slot_inst_get,
32146   Field_ae_fld_ohba2_Slot_inst_get,
32147   0,
32148   Field_ftsf12_Slot_inst_get,
32149   Field_ftsf13_Slot_inst_get,
32150   0,
32151   0,
32152   0,
32153   0,
32154   0,
32155   0,
32156   0,
32157   0,
32158   0,
32159   0,
32160   0,
32161   0,
32162   0,
32163   0,
32164   0,
32165   0,
32166   0,
32167   0,
32168   0,
32169   0,
32170   0,
32171   0,
32172   0,
32173   0,
32174   0,
32175   0,
32176   0,
32177   0,
32178   0,
32179   0,
32180   0,
32181   0,
32182   0,
32183   0,
32184   0,
32185   0,
32186   0,
32187   0,
32188   0,
32189   0,
32190   0,
32191   0,
32192   0,
32193   0,
32194   0,
32195   0,
32196   0,
32197   0,
32198   0,
32199   0,
32200   0,
32201   0,
32202   0,
32203   0,
32204   0,
32205   0,
32206   0,
32207   0,
32208   0,
32209   0,
32210   0,
32211   0,
32212   0,
32213   0,
32214   0,
32215   0,
32216   0,
32217   0,
32218   0,
32219   0,
32220   0,
32221   0,
32222   0,
32223   0,
32224   0,
32225   0,
32226   0,
32227   0,
32228   0,
32229   0,
32230   0,
32231   0,
32232   0,
32233   0,
32234   0,
32235   0,
32236   0,
32237   0,
32238   0,
32239   0,
32240   0,
32241   0,
32242   0,
32243   0,
32244   0,
32245   0,
32246   0,
32247   0,
32248   0,
32249   0,
32250   0,
32251   0,
32252   0,
32253   0,
32254   0,
32255   0,
32256   0,
32257   0,
32258   0,
32259   0,
32260   0,
32261   0,
32262   0,
32263   0,
32264   0,
32265   0,
32266   0,
32267   0,
32268   0,
32269   0,
32270   0,
32271   0,
32272   0,
32273   0,
32274   0,
32275   0,
32276   0,
32277   0,
32278   0,
32279   0,
32280   0,
32281   0,
32282   0,
32283   0,
32284   0,
32285   0,
32286   0,
32287   0,
32288   0,
32289   0,
32290   0,
32291   0,
32292   0,
32293   0,
32294   0,
32295   0,
32296   0,
32297   0,
32298   0,
32299   0,
32300   0,
32301   0,
32302   0,
32303   0,
32304   0,
32305   0,
32306   0,
32307   0,
32308   0,
32309   0,
32310   0,
32311   0,
32312   0,
32313   0,
32314   0,
32315   0,
32316   0,
32317   0,
32318   0,
32319   0,
32320   0,
32321   0,
32322   0,
32323   0,
32324   0,
32325   0,
32326   0,
32327   0,
32328   0,
32329   0,
32330   0,
32331   0,
32332   0,
32333   0,
32334   0,
32335   0,
32336   0,
32337   0,
32338   0,
32339   0,
32340   0,
32341   0,
32342   0,
32343   0,
32344   0,
32345   0,
32346   0,
32347   0,
32348   0,
32349   0,
32350   0,
32351   0,
32352   0,
32353   0,
32354   0,
32355   0,
32356   0,
32357   0,
32358   0,
32359   0,
32360   0,
32361   0,
32362   0,
32363   0,
32364   0,
32365   0,
32366   0,
32367   0,
32368   0,
32369   0,
32370   0,
32371   0,
32372   0,
32373   0,
32374   0,
32375   0,
32376   0,
32377   0,
32378   0,
32379   0,
32380   0,
32381   0,
32382   0,
32383   0,
32384   0,
32385   0,
32386   0,
32387   0,
32388   0,
32389   0,
32390   0,
32391   0,
32392   0,
32393   0,
32394   0,
32395   0,
32396   0,
32397   0,
32398   0,
32399   0,
32400   0,
32401   0,
32402   0,
32403   0,
32404   0,
32405   0,
32406   0,
32407   0,
32408   0,
32409   0,
32410   0,
32411   0,
32412   0,
32413   0,
32414   0,
32415   0,
32416   0,
32417   0,
32418   0,
32419   0,
32420   0,
32421   0,
32422   0,
32423   0,
32424   0,
32425   0,
32426   0,
32427   0,
32428   0,
32429   0,
32430   0,
32431   0,
32432   0,
32433   0,
32434   0,
32435   0,
32436   0,
32437   0,
32438   0,
32439   0,
32440   0,
32441   0,
32442   0,
32443   0,
32444   0,
32445   0,
32446   0,
32447   0,
32448   0,
32449   0,
32450   0,
32451   0,
32452   0,
32453   0,
32454   0,
32455   0,
32456   0,
32457   0,
32458   0,
32459   0,
32460   0,
32461   0,
32462   0,
32463   0,
32464   0,
32465   0,
32466   0,
32467   0,
32468   0,
32469   0,
32470   0,
32471   0,
32472   Implicit_Field_ar0_get,
32473   Implicit_Field_ar4_get,
32474   Implicit_Field_ar8_get,
32475   Implicit_Field_ar12_get,
32476   Implicit_Field_bt16_get,
32477   Implicit_Field_bs16_get,
32478   Implicit_Field_br16_get,
32479   Implicit_Field_brall_get
32480 };
32481
32482 static xtensa_set_field_fn
32483 Slot_inst_set_field_fns[] = {
32484   Field_t_Slot_inst_set,
32485   Field_bbi4_Slot_inst_set,
32486   Field_bbi_Slot_inst_set,
32487   Field_imm12_Slot_inst_set,
32488   Field_imm8_Slot_inst_set,
32489   Field_s_Slot_inst_set,
32490   Field_imm12b_Slot_inst_set,
32491   Field_imm16_Slot_inst_set,
32492   Field_m_Slot_inst_set,
32493   Field_n_Slot_inst_set,
32494   Field_offset_Slot_inst_set,
32495   Field_op0_Slot_inst_set,
32496   Field_op1_Slot_inst_set,
32497   Field_op2_Slot_inst_set,
32498   Field_r_Slot_inst_set,
32499   Field_sa4_Slot_inst_set,
32500   Field_sae4_Slot_inst_set,
32501   Field_sae_Slot_inst_set,
32502   Field_sal_Slot_inst_set,
32503   Field_sargt_Slot_inst_set,
32504   Field_sas4_Slot_inst_set,
32505   Field_sas_Slot_inst_set,
32506   Field_sr_Slot_inst_set,
32507   Field_st_Slot_inst_set,
32508   Field_thi3_Slot_inst_set,
32509   Field_imm4_Slot_inst_set,
32510   Field_mn_Slot_inst_set,
32511   0,
32512   0,
32513   0,
32514   0,
32515   0,
32516   0,
32517   0,
32518   0,
32519   Field_t2_Slot_inst_set,
32520   Field_s2_Slot_inst_set,
32521   Field_r2_Slot_inst_set,
32522   Field_t4_Slot_inst_set,
32523   Field_s4_Slot_inst_set,
32524   Field_r4_Slot_inst_set,
32525   Field_t8_Slot_inst_set,
32526   Field_s8_Slot_inst_set,
32527   Field_r8_Slot_inst_set,
32528   Field_xt_wbr15_imm_Slot_inst_set,
32529   Field_xt_wbr18_imm_Slot_inst_set,
32530   Field_ae_r3_Slot_inst_set,
32531   Field_ae_s_non_samt_Slot_inst_set,
32532   Field_ae_s3_Slot_inst_set,
32533   Field_ae_r32_Slot_inst_set,
32534   Field_ae_samt_s_t_Slot_inst_set,
32535   Field_ae_r20_Slot_inst_set,
32536   Field_ae_r10_Slot_inst_set,
32537   Field_ae_s20_Slot_inst_set,
32538   Field_ae_fld_ohba_Slot_inst_set,
32539   Field_ae_fld_ohba2_Slot_inst_set,
32540   0,
32541   Field_ftsf12_Slot_inst_set,
32542   Field_ftsf13_Slot_inst_set,
32543   0,
32544   0,
32545   0,
32546   0,
32547   0,
32548   0,
32549   0,
32550   0,
32551   0,
32552   0,
32553   0,
32554   0,
32555   0,
32556   0,
32557   0,
32558   0,
32559   0,
32560   0,
32561   0,
32562   0,
32563   0,
32564   0,
32565   0,
32566   0,
32567   0,
32568   0,
32569   0,
32570   0,
32571   0,
32572   0,
32573   0,
32574   0,
32575   0,
32576   0,
32577   0,
32578   0,
32579   0,
32580   0,
32581   0,
32582   0,
32583   0,
32584   0,
32585   0,
32586   0,
32587   0,
32588   0,
32589   0,
32590   0,
32591   0,
32592   0,
32593   0,
32594   0,
32595   0,
32596   0,
32597   0,
32598   0,
32599   0,
32600   0,
32601   0,
32602   0,
32603   0,
32604   0,
32605   0,
32606   0,
32607   0,
32608   0,
32609   0,
32610   0,
32611   0,
32612   0,
32613   0,
32614   0,
32615   0,
32616   0,
32617   0,
32618   0,
32619   0,
32620   0,
32621   0,
32622   0,
32623   0,
32624   0,
32625   0,
32626   0,
32627   0,
32628   0,
32629   0,
32630   0,
32631   0,
32632   0,
32633   0,
32634   0,
32635   0,
32636   0,
32637   0,
32638   0,
32639   0,
32640   0,
32641   0,
32642   0,
32643   0,
32644   0,
32645   0,
32646   0,
32647   0,
32648   0,
32649   0,
32650   0,
32651   0,
32652   0,
32653   0,
32654   0,
32655   0,
32656   0,
32657   0,
32658   0,
32659   0,
32660   0,
32661   0,
32662   0,
32663   0,
32664   0,
32665   0,
32666   0,
32667   0,
32668   0,
32669   0,
32670   0,
32671   0,
32672   0,
32673   0,
32674   0,
32675   0,
32676   0,
32677   0,
32678   0,
32679   0,
32680   0,
32681   0,
32682   0,
32683   0,
32684   0,
32685   0,
32686   0,
32687   0,
32688   0,
32689   0,
32690   0,
32691   0,
32692   0,
32693   0,
32694   0,
32695   0,
32696   0,
32697   0,
32698   0,
32699   0,
32700   0,
32701   0,
32702   0,
32703   0,
32704   0,
32705   0,
32706   0,
32707   0,
32708   0,
32709   0,
32710   0,
32711   0,
32712   0,
32713   0,
32714   0,
32715   0,
32716   0,
32717   0,
32718   0,
32719   0,
32720   0,
32721   0,
32722   0,
32723   0,
32724   0,
32725   0,
32726   0,
32727   0,
32728   0,
32729   0,
32730   0,
32731   0,
32732   0,
32733   0,
32734   0,
32735   0,
32736   0,
32737   0,
32738   0,
32739   0,
32740   0,
32741   0,
32742   0,
32743   0,
32744   0,
32745   0,
32746   0,
32747   0,
32748   0,
32749   0,
32750   0,
32751   0,
32752   0,
32753   0,
32754   0,
32755   0,
32756   0,
32757   0,
32758   0,
32759   0,
32760   0,
32761   0,
32762   0,
32763   0,
32764   0,
32765   0,
32766   0,
32767   0,
32768   0,
32769   0,
32770   0,
32771   0,
32772   0,
32773   0,
32774   0,
32775   0,
32776   0,
32777   0,
32778   0,
32779   0,
32780   0,
32781   0,
32782   0,
32783   0,
32784   0,
32785   0,
32786   0,
32787   0,
32788   0,
32789   0,
32790   0,
32791   0,
32792   0,
32793   0,
32794   0,
32795   0,
32796   0,
32797   0,
32798   0,
32799   0,
32800   0,
32801   0,
32802   0,
32803   0,
32804   0,
32805   0,
32806   0,
32807   0,
32808   0,
32809   0,
32810   0,
32811   0,
32812   0,
32813   0,
32814   0,
32815   0,
32816   0,
32817   0,
32818   0,
32819   0,
32820   0,
32821   0,
32822   0,
32823   0,
32824   0,
32825   0,
32826   0,
32827   0,
32828   0,
32829   0,
32830   0,
32831   0,
32832   0,
32833   0,
32834   0,
32835   0,
32836   0,
32837   0,
32838   0,
32839   0,
32840   0,
32841   0,
32842   0,
32843   0,
32844   0,
32845   0,
32846   0,
32847   0,
32848   0,
32849   0,
32850   0,
32851   0,
32852   0,
32853   0,
32854   0,
32855   0,
32856   0,
32857   0,
32858   0,
32859   0,
32860   0,
32861   0,
32862   0,
32863   0,
32864   0,
32865   Implicit_Field_set,
32866   Implicit_Field_set,
32867   Implicit_Field_set,
32868   Implicit_Field_set,
32869   Implicit_Field_set,
32870   Implicit_Field_set,
32871   Implicit_Field_set,
32872   Implicit_Field_set
32873 };
32874
32875 static xtensa_get_field_fn
32876 Slot_inst16a_get_field_fns[] = {
32877   Field_t_Slot_inst16a_get,
32878   0,
32879   0,
32880   0,
32881   0,
32882   Field_s_Slot_inst16a_get,
32883   0,
32884   0,
32885   0,
32886   0,
32887   0,
32888   Field_op0_Slot_inst16a_get,
32889   0,
32890   0,
32891   Field_r_Slot_inst16a_get,
32892   0,
32893   0,
32894   0,
32895   0,
32896   0,
32897   0,
32898   0,
32899   Field_sr_Slot_inst16a_get,
32900   Field_st_Slot_inst16a_get,
32901   0,
32902   Field_imm4_Slot_inst16a_get,
32903   0,
32904   Field_i_Slot_inst16a_get,
32905   Field_imm6lo_Slot_inst16a_get,
32906   Field_imm6hi_Slot_inst16a_get,
32907   Field_imm7lo_Slot_inst16a_get,
32908   Field_imm7hi_Slot_inst16a_get,
32909   Field_z_Slot_inst16a_get,
32910   Field_imm6_Slot_inst16a_get,
32911   Field_imm7_Slot_inst16a_get,
32912   Field_t2_Slot_inst16a_get,
32913   Field_s2_Slot_inst16a_get,
32914   Field_r2_Slot_inst16a_get,
32915   Field_t4_Slot_inst16a_get,
32916   Field_s4_Slot_inst16a_get,
32917   Field_r4_Slot_inst16a_get,
32918   Field_t8_Slot_inst16a_get,
32919   Field_s8_Slot_inst16a_get,
32920   Field_r8_Slot_inst16a_get,
32921   0,
32922   0,
32923   0,
32924   0,
32925   0,
32926   0,
32927   0,
32928   0,
32929   0,
32930   0,
32931   0,
32932   0,
32933   0,
32934   0,
32935   0,
32936   0,
32937   0,
32938   0,
32939   0,
32940   0,
32941   0,
32942   0,
32943   0,
32944   0,
32945   0,
32946   0,
32947   0,
32948   0,
32949   0,
32950   0,
32951   0,
32952   0,
32953   0,
32954   0,
32955   0,
32956   0,
32957   0,
32958   0,
32959   0,
32960   0,
32961   0,
32962   0,
32963   0,
32964   0,
32965   0,
32966   0,
32967   0,
32968   0,
32969   0,
32970   0,
32971   0,
32972   0,
32973   0,
32974   0,
32975   0,
32976   0,
32977   0,
32978   0,
32979   0,
32980   0,
32981   0,
32982   0,
32983   0,
32984   0,
32985   0,
32986   0,
32987   0,
32988   0,
32989   0,
32990   0,
32991   0,
32992   0,
32993   0,
32994   0,
32995   0,
32996   0,
32997   0,
32998   0,
32999   0,
33000   0,
33001   0,
33002   0,
33003   0,
33004   0,
33005   0,
33006   0,
33007   0,
33008   0,
33009   0,
33010   0,
33011   0,
33012   0,
33013   0,
33014   0,
33015   0,
33016   0,
33017   0,
33018   0,
33019   0,
33020   0,
33021   0,
33022   0,
33023   0,
33024   0,
33025   0,
33026   0,
33027   0,
33028   0,
33029   0,
33030   0,
33031   0,
33032   0,
33033   0,
33034   0,
33035   0,
33036   0,
33037   0,
33038   0,
33039   0,
33040   0,
33041   0,
33042   0,
33043   0,
33044   0,
33045   0,
33046   0,
33047   0,
33048   0,
33049   0,
33050   0,
33051   0,
33052   0,
33053   0,
33054   0,
33055   0,
33056   0,
33057   0,
33058   0,
33059   0,
33060   0,
33061   0,
33062   0,
33063   0,
33064   0,
33065   0,
33066   0,
33067   0,
33068   0,
33069   0,
33070   0,
33071   0,
33072   0,
33073   0,
33074   0,
33075   0,
33076   0,
33077   0,
33078   0,
33079   0,
33080   0,
33081   0,
33082   0,
33083   0,
33084   0,
33085   0,
33086   0,
33087   0,
33088   0,
33089   0,
33090   0,
33091   0,
33092   0,
33093   0,
33094   0,
33095   0,
33096   0,
33097   0,
33098   0,
33099   0,
33100   0,
33101   0,
33102   0,
33103   0,
33104   0,
33105   0,
33106   0,
33107   0,
33108   0,
33109   0,
33110   0,
33111   0,
33112   0,
33113   0,
33114   0,
33115   0,
33116   0,
33117   0,
33118   0,
33119   0,
33120   0,
33121   0,
33122   0,
33123   0,
33124   0,
33125   0,
33126   0,
33127   0,
33128   0,
33129   0,
33130   0,
33131   0,
33132   0,
33133   0,
33134   0,
33135   0,
33136   0,
33137   0,
33138   0,
33139   0,
33140   0,
33141   0,
33142   0,
33143   0,
33144   0,
33145   0,
33146   0,
33147   0,
33148   0,
33149   0,
33150   0,
33151   0,
33152   0,
33153   0,
33154   0,
33155   0,
33156   0,
33157   0,
33158   0,
33159   0,
33160   0,
33161   0,
33162   0,
33163   0,
33164   0,
33165   0,
33166   0,
33167   0,
33168   0,
33169   0,
33170   0,
33171   0,
33172   0,
33173   0,
33174   0,
33175   0,
33176   0,
33177   0,
33178   0,
33179   0,
33180   0,
33181   0,
33182   0,
33183   0,
33184   0,
33185   0,
33186   0,
33187   0,
33188   0,
33189   0,
33190   0,
33191   0,
33192   0,
33193   0,
33194   0,
33195   0,
33196   0,
33197   0,
33198   0,
33199   0,
33200   0,
33201   0,
33202   0,
33203   0,
33204   0,
33205   0,
33206   0,
33207   0,
33208   0,
33209   0,
33210   0,
33211   0,
33212   0,
33213   0,
33214   0,
33215   0,
33216   0,
33217   0,
33218   0,
33219   0,
33220   0,
33221   0,
33222   0,
33223   0,
33224   0,
33225   0,
33226   0,
33227   0,
33228   0,
33229   0,
33230   0,
33231   0,
33232   0,
33233   0,
33234   0,
33235   0,
33236   0,
33237   0,
33238   0,
33239   0,
33240   0,
33241   0,
33242   0,
33243   0,
33244   0,
33245   0,
33246   0,
33247   0,
33248   0,
33249   0,
33250   0,
33251   0,
33252   0,
33253   0,
33254   0,
33255   0,
33256   0,
33257   0,
33258   Implicit_Field_ar0_get,
33259   Implicit_Field_ar4_get,
33260   Implicit_Field_ar8_get,
33261   Implicit_Field_ar12_get,
33262   Implicit_Field_bt16_get,
33263   Implicit_Field_bs16_get,
33264   Implicit_Field_br16_get,
33265   Implicit_Field_brall_get
33266 };
33267
33268 static xtensa_set_field_fn
33269 Slot_inst16a_set_field_fns[] = {
33270   Field_t_Slot_inst16a_set,
33271   0,
33272   0,
33273   0,
33274   0,
33275   Field_s_Slot_inst16a_set,
33276   0,
33277   0,
33278   0,
33279   0,
33280   0,
33281   Field_op0_Slot_inst16a_set,
33282   0,
33283   0,
33284   Field_r_Slot_inst16a_set,
33285   0,
33286   0,
33287   0,
33288   0,
33289   0,
33290   0,
33291   0,
33292   Field_sr_Slot_inst16a_set,
33293   Field_st_Slot_inst16a_set,
33294   0,
33295   Field_imm4_Slot_inst16a_set,
33296   0,
33297   Field_i_Slot_inst16a_set,
33298   Field_imm6lo_Slot_inst16a_set,
33299   Field_imm6hi_Slot_inst16a_set,
33300   Field_imm7lo_Slot_inst16a_set,
33301   Field_imm7hi_Slot_inst16a_set,
33302   Field_z_Slot_inst16a_set,
33303   Field_imm6_Slot_inst16a_set,
33304   Field_imm7_Slot_inst16a_set,
33305   Field_t2_Slot_inst16a_set,
33306   Field_s2_Slot_inst16a_set,
33307   Field_r2_Slot_inst16a_set,
33308   Field_t4_Slot_inst16a_set,
33309   Field_s4_Slot_inst16a_set,
33310   Field_r4_Slot_inst16a_set,
33311   Field_t8_Slot_inst16a_set,
33312   Field_s8_Slot_inst16a_set,
33313   Field_r8_Slot_inst16a_set,
33314   0,
33315   0,
33316   0,
33317   0,
33318   0,
33319   0,
33320   0,
33321   0,
33322   0,
33323   0,
33324   0,
33325   0,
33326   0,
33327   0,
33328   0,
33329   0,
33330   0,
33331   0,
33332   0,
33333   0,
33334   0,
33335   0,
33336   0,
33337   0,
33338   0,
33339   0,
33340   0,
33341   0,
33342   0,
33343   0,
33344   0,
33345   0,
33346   0,
33347   0,
33348   0,
33349   0,
33350   0,
33351   0,
33352   0,
33353   0,
33354   0,
33355   0,
33356   0,
33357   0,
33358   0,
33359   0,
33360   0,
33361   0,
33362   0,
33363   0,
33364   0,
33365   0,
33366   0,
33367   0,
33368   0,
33369   0,
33370   0,
33371   0,
33372   0,
33373   0,
33374   0,
33375   0,
33376   0,
33377   0,
33378   0,
33379   0,
33380   0,
33381   0,
33382   0,
33383   0,
33384   0,
33385   0,
33386   0,
33387   0,
33388   0,
33389   0,
33390   0,
33391   0,
33392   0,
33393   0,
33394   0,
33395   0,
33396   0,
33397   0,
33398   0,
33399   0,
33400   0,
33401   0,
33402   0,
33403   0,
33404   0,
33405   0,
33406   0,
33407   0,
33408   0,
33409   0,
33410   0,
33411   0,
33412   0,
33413   0,
33414   0,
33415   0,
33416   0,
33417   0,
33418   0,
33419   0,
33420   0,
33421   0,
33422   0,
33423   0,
33424   0,
33425   0,
33426   0,
33427   0,
33428   0,
33429   0,
33430   0,
33431   0,
33432   0,
33433   0,
33434   0,
33435   0,
33436   0,
33437   0,
33438   0,
33439   0,
33440   0,
33441   0,
33442   0,
33443   0,
33444   0,
33445   0,
33446   0,
33447   0,
33448   0,
33449   0,
33450   0,
33451   0,
33452   0,
33453   0,
33454   0,
33455   0,
33456   0,
33457   0,
33458   0,
33459   0,
33460   0,
33461   0,
33462   0,
33463   0,
33464   0,
33465   0,
33466   0,
33467   0,
33468   0,
33469   0,
33470   0,
33471   0,
33472   0,
33473   0,
33474   0,
33475   0,
33476   0,
33477   0,
33478   0,
33479   0,
33480   0,
33481   0,
33482   0,
33483   0,
33484   0,
33485   0,
33486   0,
33487   0,
33488   0,
33489   0,
33490   0,
33491   0,
33492   0,
33493   0,
33494   0,
33495   0,
33496   0,
33497   0,
33498   0,
33499   0,
33500   0,
33501   0,
33502   0,
33503   0,
33504   0,
33505   0,
33506   0,
33507   0,
33508   0,
33509   0,
33510   0,
33511   0,
33512   0,
33513   0,
33514   0,
33515   0,
33516   0,
33517   0,
33518   0,
33519   0,
33520   0,
33521   0,
33522   0,
33523   0,
33524   0,
33525   0,
33526   0,
33527   0,
33528   0,
33529   0,
33530   0,
33531   0,
33532   0,
33533   0,
33534   0,
33535   0,
33536   0,
33537   0,
33538   0,
33539   0,
33540   0,
33541   0,
33542   0,
33543   0,
33544   0,
33545   0,
33546   0,
33547   0,
33548   0,
33549   0,
33550   0,
33551   0,
33552   0,
33553   0,
33554   0,
33555   0,
33556   0,
33557   0,
33558   0,
33559   0,
33560   0,
33561   0,
33562   0,
33563   0,
33564   0,
33565   0,
33566   0,
33567   0,
33568   0,
33569   0,
33570   0,
33571   0,
33572   0,
33573   0,
33574   0,
33575   0,
33576   0,
33577   0,
33578   0,
33579   0,
33580   0,
33581   0,
33582   0,
33583   0,
33584   0,
33585   0,
33586   0,
33587   0,
33588   0,
33589   0,
33590   0,
33591   0,
33592   0,
33593   0,
33594   0,
33595   0,
33596   0,
33597   0,
33598   0,
33599   0,
33600   0,
33601   0,
33602   0,
33603   0,
33604   0,
33605   0,
33606   0,
33607   0,
33608   0,
33609   0,
33610   0,
33611   0,
33612   0,
33613   0,
33614   0,
33615   0,
33616   0,
33617   0,
33618   0,
33619   0,
33620   0,
33621   0,
33622   0,
33623   0,
33624   0,
33625   0,
33626   0,
33627   0,
33628   0,
33629   0,
33630   0,
33631   0,
33632   0,
33633   0,
33634   0,
33635   0,
33636   0,
33637   0,
33638   0,
33639   0,
33640   0,
33641   0,
33642   0,
33643   0,
33644   0,
33645   0,
33646   0,
33647   0,
33648   0,
33649   0,
33650   0,
33651   Implicit_Field_set,
33652   Implicit_Field_set,
33653   Implicit_Field_set,
33654   Implicit_Field_set,
33655   Implicit_Field_set,
33656   Implicit_Field_set,
33657   Implicit_Field_set,
33658   Implicit_Field_set
33659 };
33660
33661 static xtensa_get_field_fn
33662 Slot_inst16b_get_field_fns[] = {
33663   Field_t_Slot_inst16b_get,
33664   0,
33665   0,
33666   0,
33667   0,
33668   Field_s_Slot_inst16b_get,
33669   0,
33670   0,
33671   0,
33672   0,
33673   0,
33674   Field_op0_Slot_inst16b_get,
33675   0,
33676   0,
33677   Field_r_Slot_inst16b_get,
33678   0,
33679   0,
33680   0,
33681   0,
33682   0,
33683   0,
33684   0,
33685   Field_sr_Slot_inst16b_get,
33686   Field_st_Slot_inst16b_get,
33687   0,
33688   Field_imm4_Slot_inst16b_get,
33689   0,
33690   Field_i_Slot_inst16b_get,
33691   Field_imm6lo_Slot_inst16b_get,
33692   Field_imm6hi_Slot_inst16b_get,
33693   Field_imm7lo_Slot_inst16b_get,
33694   Field_imm7hi_Slot_inst16b_get,
33695   Field_z_Slot_inst16b_get,
33696   Field_imm6_Slot_inst16b_get,
33697   Field_imm7_Slot_inst16b_get,
33698   Field_t2_Slot_inst16b_get,
33699   Field_s2_Slot_inst16b_get,
33700   Field_r2_Slot_inst16b_get,
33701   Field_t4_Slot_inst16b_get,
33702   Field_s4_Slot_inst16b_get,
33703   Field_r4_Slot_inst16b_get,
33704   Field_t8_Slot_inst16b_get,
33705   Field_s8_Slot_inst16b_get,
33706   Field_r8_Slot_inst16b_get,
33707   0,
33708   0,
33709   0,
33710   0,
33711   0,
33712   0,
33713   0,
33714   0,
33715   0,
33716   0,
33717   0,
33718   0,
33719   0,
33720   0,
33721   0,
33722   0,
33723   0,
33724   0,
33725   0,
33726   0,
33727   0,
33728   0,
33729   0,
33730   0,
33731   0,
33732   0,
33733   0,
33734   0,
33735   0,
33736   0,
33737   0,
33738   0,
33739   0,
33740   0,
33741   0,
33742   0,
33743   0,
33744   0,
33745   0,
33746   0,
33747   0,
33748   0,
33749   0,
33750   0,
33751   0,
33752   0,
33753   0,
33754   0,
33755   0,
33756   0,
33757   0,
33758   0,
33759   0,
33760   0,
33761   0,
33762   0,
33763   0,
33764   0,
33765   0,
33766   0,
33767   0,
33768   0,
33769   0,
33770   0,
33771   0,
33772   0,
33773   0,
33774   0,
33775   0,
33776   0,
33777   0,
33778   0,
33779   0,
33780   0,
33781   0,
33782   0,
33783   0,
33784   0,
33785   0,
33786   0,
33787   0,
33788   0,
33789   0,
33790   0,
33791   0,
33792   0,
33793   0,
33794   0,
33795   0,
33796   0,
33797   0,
33798   0,
33799   0,
33800   0,
33801   0,
33802   0,
33803   0,
33804   0,
33805   0,
33806   0,
33807   0,
33808   0,
33809   0,
33810   0,
33811   0,
33812   0,
33813   0,
33814   0,
33815   0,
33816   0,
33817   0,
33818   0,
33819   0,
33820   0,
33821   0,
33822   0,
33823   0,
33824   0,
33825   0,
33826   0,
33827   0,
33828   0,
33829   0,
33830   0,
33831   0,
33832   0,
33833   0,
33834   0,
33835   0,
33836   0,
33837   0,
33838   0,
33839   0,
33840   0,
33841   0,
33842   0,
33843   0,
33844   0,
33845   0,
33846   0,
33847   0,
33848   0,
33849   0,
33850   0,
33851   0,
33852   0,
33853   0,
33854   0,
33855   0,
33856   0,
33857   0,
33858   0,
33859   0,
33860   0,
33861   0,
33862   0,
33863   0,
33864   0,
33865   0,
33866   0,
33867   0,
33868   0,
33869   0,
33870   0,
33871   0,
33872   0,
33873   0,
33874   0,
33875   0,
33876   0,
33877   0,
33878   0,
33879   0,
33880   0,
33881   0,
33882   0,
33883   0,
33884   0,
33885   0,
33886   0,
33887   0,
33888   0,
33889   0,
33890   0,
33891   0,
33892   0,
33893   0,
33894   0,
33895   0,
33896   0,
33897   0,
33898   0,
33899   0,
33900   0,
33901   0,
33902   0,
33903   0,
33904   0,
33905   0,
33906   0,
33907   0,
33908   0,
33909   0,
33910   0,
33911   0,
33912   0,
33913   0,
33914   0,
33915   0,
33916   0,
33917   0,
33918   0,
33919   0,
33920   0,
33921   0,
33922   0,
33923   0,
33924   0,
33925   0,
33926   0,
33927   0,
33928   0,
33929   0,
33930   0,
33931   0,
33932   0,
33933   0,
33934   0,
33935   0,
33936   0,
33937   0,
33938   0,
33939   0,
33940   0,
33941   0,
33942   0,
33943   0,
33944   0,
33945   0,
33946   0,
33947   0,
33948   0,
33949   0,
33950   0,
33951   0,
33952   0,
33953   0,
33954   0,
33955   0,
33956   0,
33957   0,
33958   0,
33959   0,
33960   0,
33961   0,
33962   0,
33963   0,
33964   0,
33965   0,
33966   0,
33967   0,
33968   0,
33969   0,
33970   0,
33971   0,
33972   0,
33973   0,
33974   0,
33975   0,
33976   0,
33977   0,
33978   0,
33979   0,
33980   0,
33981   0,
33982   0,
33983   0,
33984   0,
33985   0,
33986   0,
33987   0,
33988   0,
33989   0,
33990   0,
33991   0,
33992   0,
33993   0,
33994   0,
33995   0,
33996   0,
33997   0,
33998   0,
33999   0,
34000   0,
34001   0,
34002   0,
34003   0,
34004   0,
34005   0,
34006   0,
34007   0,
34008   0,
34009   0,
34010   0,
34011   0,
34012   0,
34013   0,
34014   0,
34015   0,
34016   0,
34017   0,
34018   0,
34019   0,
34020   0,
34021   0,
34022   0,
34023   0,
34024   0,
34025   0,
34026   0,
34027   0,
34028   0,
34029   0,
34030   0,
34031   0,
34032   0,
34033   0,
34034   0,
34035   0,
34036   0,
34037   0,
34038   0,
34039   0,
34040   0,
34041   0,
34042   0,
34043   0,
34044   Implicit_Field_ar0_get,
34045   Implicit_Field_ar4_get,
34046   Implicit_Field_ar8_get,
34047   Implicit_Field_ar12_get,
34048   Implicit_Field_bt16_get,
34049   Implicit_Field_bs16_get,
34050   Implicit_Field_br16_get,
34051   Implicit_Field_brall_get
34052 };
34053
34054 static xtensa_set_field_fn
34055 Slot_inst16b_set_field_fns[] = {
34056   Field_t_Slot_inst16b_set,
34057   0,
34058   0,
34059   0,
34060   0,
34061   Field_s_Slot_inst16b_set,
34062   0,
34063   0,
34064   0,
34065   0,
34066   0,
34067   Field_op0_Slot_inst16b_set,
34068   0,
34069   0,
34070   Field_r_Slot_inst16b_set,
34071   0,
34072   0,
34073   0,
34074   0,
34075   0,
34076   0,
34077   0,
34078   Field_sr_Slot_inst16b_set,
34079   Field_st_Slot_inst16b_set,
34080   0,
34081   Field_imm4_Slot_inst16b_set,
34082   0,
34083   Field_i_Slot_inst16b_set,
34084   Field_imm6lo_Slot_inst16b_set,
34085   Field_imm6hi_Slot_inst16b_set,
34086   Field_imm7lo_Slot_inst16b_set,
34087   Field_imm7hi_Slot_inst16b_set,
34088   Field_z_Slot_inst16b_set,
34089   Field_imm6_Slot_inst16b_set,
34090   Field_imm7_Slot_inst16b_set,
34091   Field_t2_Slot_inst16b_set,
34092   Field_s2_Slot_inst16b_set,
34093   Field_r2_Slot_inst16b_set,
34094   Field_t4_Slot_inst16b_set,
34095   Field_s4_Slot_inst16b_set,
34096   Field_r4_Slot_inst16b_set,
34097   Field_t8_Slot_inst16b_set,
34098   Field_s8_Slot_inst16b_set,
34099   Field_r8_Slot_inst16b_set,
34100   0,
34101   0,
34102   0,
34103   0,
34104   0,
34105   0,
34106   0,
34107   0,
34108   0,
34109   0,
34110   0,
34111   0,
34112   0,
34113   0,
34114   0,
34115   0,
34116   0,
34117   0,
34118   0,
34119   0,
34120   0,
34121   0,
34122   0,
34123   0,
34124   0,
34125   0,
34126   0,
34127   0,
34128   0,
34129   0,
34130   0,
34131   0,
34132   0,
34133   0,
34134   0,
34135   0,
34136   0,
34137   0,
34138   0,
34139   0,
34140   0,
34141   0,
34142   0,
34143   0,
34144   0,
34145   0,
34146   0,
34147   0,
34148   0,
34149   0,
34150   0,
34151   0,
34152   0,
34153   0,
34154   0,
34155   0,
34156   0,
34157   0,
34158   0,
34159   0,
34160   0,
34161   0,
34162   0,
34163   0,
34164   0,
34165   0,
34166   0,
34167   0,
34168   0,
34169   0,
34170   0,
34171   0,
34172   0,
34173   0,
34174   0,
34175   0,
34176   0,
34177   0,
34178   0,
34179   0,
34180   0,
34181   0,
34182   0,
34183   0,
34184   0,
34185   0,
34186   0,
34187   0,
34188   0,
34189   0,
34190   0,
34191   0,
34192   0,
34193   0,
34194   0,
34195   0,
34196   0,
34197   0,
34198   0,
34199   0,
34200   0,
34201   0,
34202   0,
34203   0,
34204   0,
34205   0,
34206   0,
34207   0,
34208   0,
34209   0,
34210   0,
34211   0,
34212   0,
34213   0,
34214   0,
34215   0,
34216   0,
34217   0,
34218   0,
34219   0,
34220   0,
34221   0,
34222   0,
34223   0,
34224   0,
34225   0,
34226   0,
34227   0,
34228   0,
34229   0,
34230   0,
34231   0,
34232   0,
34233   0,
34234   0,
34235   0,
34236   0,
34237   0,
34238   0,
34239   0,
34240   0,
34241   0,
34242   0,
34243   0,
34244   0,
34245   0,
34246   0,
34247   0,
34248   0,
34249   0,
34250   0,
34251   0,
34252   0,
34253   0,
34254   0,
34255   0,
34256   0,
34257   0,
34258   0,
34259   0,
34260   0,
34261   0,
34262   0,
34263   0,
34264   0,
34265   0,
34266   0,
34267   0,
34268   0,
34269   0,
34270   0,
34271   0,
34272   0,
34273   0,
34274   0,
34275   0,
34276   0,
34277   0,
34278   0,
34279   0,
34280   0,
34281   0,
34282   0,
34283   0,
34284   0,
34285   0,
34286   0,
34287   0,
34288   0,
34289   0,
34290   0,
34291   0,
34292   0,
34293   0,
34294   0,
34295   0,
34296   0,
34297   0,
34298   0,
34299   0,
34300   0,
34301   0,
34302   0,
34303   0,
34304   0,
34305   0,
34306   0,
34307   0,
34308   0,
34309   0,
34310   0,
34311   0,
34312   0,
34313   0,
34314   0,
34315   0,
34316   0,
34317   0,
34318   0,
34319   0,
34320   0,
34321   0,
34322   0,
34323   0,
34324   0,
34325   0,
34326   0,
34327   0,
34328   0,
34329   0,
34330   0,
34331   0,
34332   0,
34333   0,
34334   0,
34335   0,
34336   0,
34337   0,
34338   0,
34339   0,
34340   0,
34341   0,
34342   0,
34343   0,
34344   0,
34345   0,
34346   0,
34347   0,
34348   0,
34349   0,
34350   0,
34351   0,
34352   0,
34353   0,
34354   0,
34355   0,
34356   0,
34357   0,
34358   0,
34359   0,
34360   0,
34361   0,
34362   0,
34363   0,
34364   0,
34365   0,
34366   0,
34367   0,
34368   0,
34369   0,
34370   0,
34371   0,
34372   0,
34373   0,
34374   0,
34375   0,
34376   0,
34377   0,
34378   0,
34379   0,
34380   0,
34381   0,
34382   0,
34383   0,
34384   0,
34385   0,
34386   0,
34387   0,
34388   0,
34389   0,
34390   0,
34391   0,
34392   0,
34393   0,
34394   0,
34395   0,
34396   0,
34397   0,
34398   0,
34399   0,
34400   0,
34401   0,
34402   0,
34403   0,
34404   0,
34405   0,
34406   0,
34407   0,
34408   0,
34409   0,
34410   0,
34411   0,
34412   0,
34413   0,
34414   0,
34415   0,
34416   0,
34417   0,
34418   0,
34419   0,
34420   0,
34421   0,
34422   0,
34423   0,
34424   0,
34425   0,
34426   0,
34427   0,
34428   0,
34429   0,
34430   0,
34431   0,
34432   0,
34433   0,
34434   0,
34435   0,
34436   0,
34437   Implicit_Field_set,
34438   Implicit_Field_set,
34439   Implicit_Field_set,
34440   Implicit_Field_set,
34441   Implicit_Field_set,
34442   Implicit_Field_set,
34443   Implicit_Field_set,
34444   Implicit_Field_set
34445 };
34446
34447 static xtensa_get_field_fn
34448 Slot_ae_slot1_get_field_fns[] = {
34449   Field_t_Slot_ae_slot1_get,
34450   0,
34451   0,
34452   0,
34453   0,
34454   0,
34455   0,
34456   0,
34457   0,
34458   0,
34459   0,
34460   0,
34461   0,
34462   0,
34463   0,
34464   0,
34465   0,
34466   0,
34467   0,
34468   0,
34469   0,
34470   0,
34471   0,
34472   0,
34473   0,
34474   0,
34475   0,
34476   0,
34477   0,
34478   0,
34479   0,
34480   0,
34481   0,
34482   0,
34483   0,
34484   Field_t2_Slot_ae_slot1_get,
34485   0,
34486   0,
34487   0,
34488   0,
34489   0,
34490   0,
34491   0,
34492   0,
34493   0,
34494   0,
34495   0,
34496   0,
34497   0,
34498   Field_ae_r32_Slot_ae_slot1_get,
34499   0,
34500   Field_ae_r20_Slot_ae_slot1_get,
34501   Field_ae_r10_Slot_ae_slot1_get,
34502   Field_ae_s20_Slot_ae_slot1_get,
34503   0,
34504   0,
34505   Field_op0_s3_Slot_ae_slot1_get,
34506   Field_ftsf12_Slot_ae_slot1_get,
34507   Field_ftsf13_Slot_ae_slot1_get,
34508   Field_ftsf14_Slot_ae_slot1_get,
34509   Field_ftsf21ae_slot1_Slot_ae_slot1_get,
34510   Field_ftsf22ae_slot1_Slot_ae_slot1_get,
34511   Field_ftsf23ae_slot1_Slot_ae_slot1_get,
34512   Field_ftsf24ae_slot1_Slot_ae_slot1_get,
34513   Field_ftsf25ae_slot1_Slot_ae_slot1_get,
34514   Field_ftsf26ae_slot1_Slot_ae_slot1_get,
34515   Field_ftsf27ae_slot1_Slot_ae_slot1_get,
34516   Field_ftsf28ae_slot1_Slot_ae_slot1_get,
34517   Field_ftsf29ae_slot1_Slot_ae_slot1_get,
34518   Field_ftsf30ae_slot1_Slot_ae_slot1_get,
34519   Field_ftsf31ae_slot1_Slot_ae_slot1_get,
34520   Field_ftsf32ae_slot1_Slot_ae_slot1_get,
34521   Field_ftsf33ae_slot1_Slot_ae_slot1_get,
34522   Field_ftsf34ae_slot1_Slot_ae_slot1_get,
34523   Field_ftsf35ae_slot1_Slot_ae_slot1_get,
34524   Field_ftsf36ae_slot1_Slot_ae_slot1_get,
34525   Field_ftsf37ae_slot1_Slot_ae_slot1_get,
34526   Field_ftsf38ae_slot1_Slot_ae_slot1_get,
34527   Field_ftsf39ae_slot1_Slot_ae_slot1_get,
34528   Field_ftsf40ae_slot1_Slot_ae_slot1_get,
34529   Field_ftsf41ae_slot1_Slot_ae_slot1_get,
34530   Field_ftsf42ae_slot1_Slot_ae_slot1_get,
34531   Field_ftsf43ae_slot1_Slot_ae_slot1_get,
34532   Field_ftsf44ae_slot1_Slot_ae_slot1_get,
34533   Field_ftsf45ae_slot1_Slot_ae_slot1_get,
34534   Field_ftsf46ae_slot1_Slot_ae_slot1_get,
34535   Field_ftsf47ae_slot1_Slot_ae_slot1_get,
34536   Field_ftsf48ae_slot1_Slot_ae_slot1_get,
34537   Field_ftsf49ae_slot1_Slot_ae_slot1_get,
34538   Field_ftsf50ae_slot1_Slot_ae_slot1_get,
34539   Field_ftsf51ae_slot1_Slot_ae_slot1_get,
34540   Field_ftsf52ae_slot1_Slot_ae_slot1_get,
34541   Field_ftsf53ae_slot1_Slot_ae_slot1_get,
34542   Field_ftsf54ae_slot1_Slot_ae_slot1_get,
34543   Field_ftsf55ae_slot1_Slot_ae_slot1_get,
34544   Field_ftsf56ae_slot1_Slot_ae_slot1_get,
34545   Field_ftsf57ae_slot1_Slot_ae_slot1_get,
34546   Field_ftsf58ae_slot1_Slot_ae_slot1_get,
34547   Field_ftsf59ae_slot1_Slot_ae_slot1_get,
34548   Field_ftsf60ae_slot1_Slot_ae_slot1_get,
34549   Field_ftsf61ae_slot1_Slot_ae_slot1_get,
34550   Field_ftsf63ae_slot1_Slot_ae_slot1_get,
34551   Field_ftsf64ae_slot1_Slot_ae_slot1_get,
34552   Field_ftsf66ae_slot1_Slot_ae_slot1_get,
34553   Field_ftsf67ae_slot1_Slot_ae_slot1_get,
34554   Field_ftsf69ae_slot1_Slot_ae_slot1_get,
34555   Field_ftsf71ae_slot1_Slot_ae_slot1_get,
34556   Field_ftsf72ae_slot1_Slot_ae_slot1_get,
34557   Field_ftsf73ae_slot1_Slot_ae_slot1_get,
34558   Field_ftsf75ae_slot1_Slot_ae_slot1_get,
34559   Field_ftsf76ae_slot1_Slot_ae_slot1_get,
34560   Field_ftsf77ae_slot1_Slot_ae_slot1_get,
34561   Field_ftsf78ae_slot1_Slot_ae_slot1_get,
34562   Field_ftsf79ae_slot1_Slot_ae_slot1_get,
34563   Field_ftsf80ae_slot1_Slot_ae_slot1_get,
34564   Field_ftsf81ae_slot1_Slot_ae_slot1_get,
34565   Field_ftsf82ae_slot1_Slot_ae_slot1_get,
34566   Field_ftsf84ae_slot1_Slot_ae_slot1_get,
34567   Field_ftsf86ae_slot1_Slot_ae_slot1_get,
34568   Field_ftsf87ae_slot1_Slot_ae_slot1_get,
34569   Field_ftsf88ae_slot1_Slot_ae_slot1_get,
34570   Field_ftsf89ae_slot1_Slot_ae_slot1_get,
34571   Field_ftsf90ae_slot1_Slot_ae_slot1_get,
34572   Field_ftsf91ae_slot1_Slot_ae_slot1_get,
34573   Field_ftsf92ae_slot1_Slot_ae_slot1_get,
34574   Field_ftsf94ae_slot1_Slot_ae_slot1_get,
34575   Field_ftsf96ae_slot1_Slot_ae_slot1_get,
34576   Field_ftsf97ae_slot1_Slot_ae_slot1_get,
34577   Field_ftsf98ae_slot1_Slot_ae_slot1_get,
34578   Field_ftsf99ae_slot1_Slot_ae_slot1_get,
34579   Field_ftsf100ae_slot1_Slot_ae_slot1_get,
34580   Field_ftsf101ae_slot1_Slot_ae_slot1_get,
34581   Field_ftsf103ae_slot1_Slot_ae_slot1_get,
34582   Field_ftsf104ae_slot1_Slot_ae_slot1_get,
34583   Field_ftsf105ae_slot1_Slot_ae_slot1_get,
34584   Field_ftsf106ae_slot1_Slot_ae_slot1_get,
34585   Field_ftsf107ae_slot1_Slot_ae_slot1_get,
34586   Field_ftsf108ae_slot1_Slot_ae_slot1_get,
34587   Field_ftsf109ae_slot1_Slot_ae_slot1_get,
34588   Field_ftsf110ae_slot1_Slot_ae_slot1_get,
34589   Field_ftsf111ae_slot1_Slot_ae_slot1_get,
34590   Field_ftsf112ae_slot1_Slot_ae_slot1_get,
34591   Field_ftsf113ae_slot1_Slot_ae_slot1_get,
34592   Field_ftsf114ae_slot1_Slot_ae_slot1_get,
34593   Field_ftsf115ae_slot1_Slot_ae_slot1_get,
34594   Field_ftsf116ae_slot1_Slot_ae_slot1_get,
34595   Field_ftsf118ae_slot1_Slot_ae_slot1_get,
34596   Field_ftsf119ae_slot1_Slot_ae_slot1_get,
34597   Field_ftsf120ae_slot1_Slot_ae_slot1_get,
34598   Field_ftsf122ae_slot1_Slot_ae_slot1_get,
34599   Field_ftsf124ae_slot1_Slot_ae_slot1_get,
34600   Field_ftsf125ae_slot1_Slot_ae_slot1_get,
34601   Field_ftsf126ae_slot1_Slot_ae_slot1_get,
34602   Field_ftsf127ae_slot1_Slot_ae_slot1_get,
34603   Field_ftsf128ae_slot1_Slot_ae_slot1_get,
34604   Field_ftsf129ae_slot1_Slot_ae_slot1_get,
34605   Field_ftsf130ae_slot1_Slot_ae_slot1_get,
34606   Field_ftsf131ae_slot1_Slot_ae_slot1_get,
34607   Field_ftsf132ae_slot1_Slot_ae_slot1_get,
34608   Field_ftsf133ae_slot1_Slot_ae_slot1_get,
34609   Field_ftsf134ae_slot1_Slot_ae_slot1_get,
34610   Field_ftsf135ae_slot1_Slot_ae_slot1_get,
34611   Field_ftsf136ae_slot1_Slot_ae_slot1_get,
34612   Field_ftsf137ae_slot1_Slot_ae_slot1_get,
34613   Field_ftsf138ae_slot1_Slot_ae_slot1_get,
34614   Field_ftsf139ae_slot1_Slot_ae_slot1_get,
34615   Field_ftsf140ae_slot1_Slot_ae_slot1_get,
34616   Field_ftsf141ae_slot1_Slot_ae_slot1_get,
34617   Field_ftsf142ae_slot1_Slot_ae_slot1_get,
34618   Field_ftsf143ae_slot1_Slot_ae_slot1_get,
34619   Field_ftsf144ae_slot1_Slot_ae_slot1_get,
34620   Field_ftsf145ae_slot1_Slot_ae_slot1_get,
34621   Field_ftsf146ae_slot1_Slot_ae_slot1_get,
34622   Field_ftsf147ae_slot1_Slot_ae_slot1_get,
34623   Field_ftsf148ae_slot1_Slot_ae_slot1_get,
34624   Field_ftsf149ae_slot1_Slot_ae_slot1_get,
34625   Field_ftsf150ae_slot1_Slot_ae_slot1_get,
34626   Field_ftsf151ae_slot1_Slot_ae_slot1_get,
34627   Field_ftsf152ae_slot1_Slot_ae_slot1_get,
34628   Field_ftsf153ae_slot1_Slot_ae_slot1_get,
34629   Field_ftsf154ae_slot1_Slot_ae_slot1_get,
34630   Field_ftsf155ae_slot1_Slot_ae_slot1_get,
34631   Field_ftsf156ae_slot1_Slot_ae_slot1_get,
34632   Field_ftsf157ae_slot1_Slot_ae_slot1_get,
34633   Field_ftsf158ae_slot1_Slot_ae_slot1_get,
34634   Field_ftsf159ae_slot1_Slot_ae_slot1_get,
34635   Field_ftsf160ae_slot1_Slot_ae_slot1_get,
34636   Field_ftsf161ae_slot1_Slot_ae_slot1_get,
34637   Field_ftsf162ae_slot1_Slot_ae_slot1_get,
34638   Field_ftsf163ae_slot1_Slot_ae_slot1_get,
34639   Field_ftsf164ae_slot1_Slot_ae_slot1_get,
34640   Field_ftsf165ae_slot1_Slot_ae_slot1_get,
34641   Field_ftsf166ae_slot1_Slot_ae_slot1_get,
34642   Field_ftsf167ae_slot1_Slot_ae_slot1_get,
34643   Field_ftsf168ae_slot1_Slot_ae_slot1_get,
34644   Field_ftsf169ae_slot1_Slot_ae_slot1_get,
34645   Field_ftsf170ae_slot1_Slot_ae_slot1_get,
34646   Field_ftsf171ae_slot1_Slot_ae_slot1_get,
34647   Field_ftsf172ae_slot1_Slot_ae_slot1_get,
34648   Field_ftsf173ae_slot1_Slot_ae_slot1_get,
34649   Field_ftsf174ae_slot1_Slot_ae_slot1_get,
34650   Field_ftsf175ae_slot1_Slot_ae_slot1_get,
34651   Field_ftsf176ae_slot1_Slot_ae_slot1_get,
34652   Field_ftsf177ae_slot1_Slot_ae_slot1_get,
34653   Field_ftsf178ae_slot1_Slot_ae_slot1_get,
34654   Field_ftsf179ae_slot1_Slot_ae_slot1_get,
34655   Field_ftsf180ae_slot1_Slot_ae_slot1_get,
34656   Field_ftsf181ae_slot1_Slot_ae_slot1_get,
34657   Field_ftsf182ae_slot1_Slot_ae_slot1_get,
34658   Field_ftsf183ae_slot1_Slot_ae_slot1_get,
34659   Field_ftsf184ae_slot1_Slot_ae_slot1_get,
34660   Field_ftsf185ae_slot1_Slot_ae_slot1_get,
34661   Field_ftsf186ae_slot1_Slot_ae_slot1_get,
34662   Field_ftsf187ae_slot1_Slot_ae_slot1_get,
34663   Field_ftsf188ae_slot1_Slot_ae_slot1_get,
34664   Field_ftsf189ae_slot1_Slot_ae_slot1_get,
34665   Field_ftsf190ae_slot1_Slot_ae_slot1_get,
34666   Field_ftsf191ae_slot1_Slot_ae_slot1_get,
34667   Field_ftsf192ae_slot1_Slot_ae_slot1_get,
34668   Field_ftsf193ae_slot1_Slot_ae_slot1_get,
34669   Field_ftsf194ae_slot1_Slot_ae_slot1_get,
34670   Field_ftsf195ae_slot1_Slot_ae_slot1_get,
34671   Field_ftsf196ae_slot1_Slot_ae_slot1_get,
34672   Field_ftsf197ae_slot1_Slot_ae_slot1_get,
34673   Field_ftsf198ae_slot1_Slot_ae_slot1_get,
34674   Field_ftsf199ae_slot1_Slot_ae_slot1_get,
34675   Field_ftsf200ae_slot1_Slot_ae_slot1_get,
34676   Field_ftsf201ae_slot1_Slot_ae_slot1_get,
34677   Field_ftsf202ae_slot1_Slot_ae_slot1_get,
34678   Field_ftsf203ae_slot1_Slot_ae_slot1_get,
34679   Field_ftsf204ae_slot1_Slot_ae_slot1_get,
34680   Field_ftsf205ae_slot1_Slot_ae_slot1_get,
34681   Field_ftsf206ae_slot1_Slot_ae_slot1_get,
34682   Field_ftsf207ae_slot1_Slot_ae_slot1_get,
34683   Field_ftsf208_Slot_ae_slot1_get,
34684   Field_ftsf209ae_slot1_Slot_ae_slot1_get,
34685   Field_ftsf210ae_slot1_Slot_ae_slot1_get,
34686   Field_ftsf211ae_slot1_Slot_ae_slot1_get,
34687   Field_ftsf330ae_slot1_Slot_ae_slot1_get,
34688   Field_ftsf332ae_slot1_Slot_ae_slot1_get,
34689   Field_ftsf334ae_slot1_Slot_ae_slot1_get,
34690   Field_ftsf336ae_slot1_Slot_ae_slot1_get,
34691   Field_ftsf337ae_slot1_Slot_ae_slot1_get,
34692   Field_ftsf338_Slot_ae_slot1_get,
34693   Field_ftsf339ae_slot1_Slot_ae_slot1_get,
34694   Field_ftsf340_Slot_ae_slot1_get,
34695   Field_ftsf341ae_slot1_Slot_ae_slot1_get,
34696   Field_ftsf342ae_slot1_Slot_ae_slot1_get,
34697   Field_ftsf343ae_slot1_Slot_ae_slot1_get,
34698   Field_ftsf344ae_slot1_Slot_ae_slot1_get,
34699   Field_ftsf346ae_slot1_Slot_ae_slot1_get,
34700   Field_ftsf347_Slot_ae_slot1_get,
34701   Field_ftsf348ae_slot1_Slot_ae_slot1_get,
34702   Field_ftsf349ae_slot1_Slot_ae_slot1_get,
34703   Field_ftsf350ae_slot1_Slot_ae_slot1_get,
34704   0,
34705   0,
34706   0,
34707   0,
34708   0,
34709   0,
34710   0,
34711   0,
34712   0,
34713   0,
34714   0,
34715   0,
34716   0,
34717   0,
34718   0,
34719   0,
34720   0,
34721   0,
34722   0,
34723   0,
34724   0,
34725   0,
34726   0,
34727   0,
34728   0,
34729   0,
34730   0,
34731   0,
34732   0,
34733   0,
34734   0,
34735   0,
34736   0,
34737   0,
34738   0,
34739   0,
34740   0,
34741   0,
34742   0,
34743   0,
34744   0,
34745   0,
34746   0,
34747   0,
34748   0,
34749   0,
34750   0,
34751   0,
34752   0,
34753   0,
34754   0,
34755   0,
34756   0,
34757   0,
34758   0,
34759   0,
34760   0,
34761   0,
34762   0,
34763   0,
34764   0,
34765   0,
34766   0,
34767   0,
34768   0,
34769   0,
34770   0,
34771   0,
34772   0,
34773   0,
34774   0,
34775   0,
34776   0,
34777   0,
34778   0,
34779   0,
34780   0,
34781   0,
34782   0,
34783   0,
34784   0,
34785   0,
34786   0,
34787   0,
34788   0,
34789   0,
34790   0,
34791   0,
34792   0,
34793   0,
34794   0,
34795   0,
34796   0,
34797   0,
34798   0,
34799   0,
34800   0,
34801   0,
34802   0,
34803   0,
34804   0,
34805   0,
34806   0,
34807   0,
34808   0,
34809   0,
34810   0,
34811   0,
34812   0,
34813   0,
34814   0,
34815   0,
34816   0,
34817   0,
34818   0,
34819   0,
34820   0,
34821   0,
34822   0,
34823   0,
34824   0,
34825   0,
34826   0,
34827   0,
34828   0,
34829   0,
34830   Implicit_Field_ar0_get,
34831   Implicit_Field_ar4_get,
34832   Implicit_Field_ar8_get,
34833   Implicit_Field_ar12_get,
34834   Implicit_Field_bt16_get,
34835   Implicit_Field_bs16_get,
34836   Implicit_Field_br16_get,
34837   Implicit_Field_brall_get
34838 };
34839
34840 static xtensa_set_field_fn
34841 Slot_ae_slot1_set_field_fns[] = {
34842   Field_t_Slot_ae_slot1_set,
34843   0,
34844   0,
34845   0,
34846   0,
34847   0,
34848   0,
34849   0,
34850   0,
34851   0,
34852   0,
34853   0,
34854   0,
34855   0,
34856   0,
34857   0,
34858   0,
34859   0,
34860   0,
34861   0,
34862   0,
34863   0,
34864   0,
34865   0,
34866   0,
34867   0,
34868   0,
34869   0,
34870   0,
34871   0,
34872   0,
34873   0,
34874   0,
34875   0,
34876   0,
34877   Field_t2_Slot_ae_slot1_set,
34878   0,
34879   0,
34880   0,
34881   0,
34882   0,
34883   0,
34884   0,
34885   0,
34886   0,
34887   0,
34888   0,
34889   0,
34890   0,
34891   Field_ae_r32_Slot_ae_slot1_set,
34892   0,
34893   Field_ae_r20_Slot_ae_slot1_set,
34894   Field_ae_r10_Slot_ae_slot1_set,
34895   Field_ae_s20_Slot_ae_slot1_set,
34896   0,
34897   0,
34898   Field_op0_s3_Slot_ae_slot1_set,
34899   Field_ftsf12_Slot_ae_slot1_set,
34900   Field_ftsf13_Slot_ae_slot1_set,
34901   Field_ftsf14_Slot_ae_slot1_set,
34902   Field_ftsf21ae_slot1_Slot_ae_slot1_set,
34903   Field_ftsf22ae_slot1_Slot_ae_slot1_set,
34904   Field_ftsf23ae_slot1_Slot_ae_slot1_set,
34905   Field_ftsf24ae_slot1_Slot_ae_slot1_set,
34906   Field_ftsf25ae_slot1_Slot_ae_slot1_set,
34907   Field_ftsf26ae_slot1_Slot_ae_slot1_set,
34908   Field_ftsf27ae_slot1_Slot_ae_slot1_set,
34909   Field_ftsf28ae_slot1_Slot_ae_slot1_set,
34910   Field_ftsf29ae_slot1_Slot_ae_slot1_set,
34911   Field_ftsf30ae_slot1_Slot_ae_slot1_set,
34912   Field_ftsf31ae_slot1_Slot_ae_slot1_set,
34913   Field_ftsf32ae_slot1_Slot_ae_slot1_set,
34914   Field_ftsf33ae_slot1_Slot_ae_slot1_set,
34915   Field_ftsf34ae_slot1_Slot_ae_slot1_set,
34916   Field_ftsf35ae_slot1_Slot_ae_slot1_set,
34917   Field_ftsf36ae_slot1_Slot_ae_slot1_set,
34918   Field_ftsf37ae_slot1_Slot_ae_slot1_set,
34919   Field_ftsf38ae_slot1_Slot_ae_slot1_set,
34920   Field_ftsf39ae_slot1_Slot_ae_slot1_set,
34921   Field_ftsf40ae_slot1_Slot_ae_slot1_set,
34922   Field_ftsf41ae_slot1_Slot_ae_slot1_set,
34923   Field_ftsf42ae_slot1_Slot_ae_slot1_set,
34924   Field_ftsf43ae_slot1_Slot_ae_slot1_set,
34925   Field_ftsf44ae_slot1_Slot_ae_slot1_set,
34926   Field_ftsf45ae_slot1_Slot_ae_slot1_set,
34927   Field_ftsf46ae_slot1_Slot_ae_slot1_set,
34928   Field_ftsf47ae_slot1_Slot_ae_slot1_set,
34929   Field_ftsf48ae_slot1_Slot_ae_slot1_set,
34930   Field_ftsf49ae_slot1_Slot_ae_slot1_set,
34931   Field_ftsf50ae_slot1_Slot_ae_slot1_set,
34932   Field_ftsf51ae_slot1_Slot_ae_slot1_set,
34933   Field_ftsf52ae_slot1_Slot_ae_slot1_set,
34934   Field_ftsf53ae_slot1_Slot_ae_slot1_set,
34935   Field_ftsf54ae_slot1_Slot_ae_slot1_set,
34936   Field_ftsf55ae_slot1_Slot_ae_slot1_set,
34937   Field_ftsf56ae_slot1_Slot_ae_slot1_set,
34938   Field_ftsf57ae_slot1_Slot_ae_slot1_set,
34939   Field_ftsf58ae_slot1_Slot_ae_slot1_set,
34940   Field_ftsf59ae_slot1_Slot_ae_slot1_set,
34941   Field_ftsf60ae_slot1_Slot_ae_slot1_set,
34942   Field_ftsf61ae_slot1_Slot_ae_slot1_set,
34943   Field_ftsf63ae_slot1_Slot_ae_slot1_set,
34944   Field_ftsf64ae_slot1_Slot_ae_slot1_set,
34945   Field_ftsf66ae_slot1_Slot_ae_slot1_set,
34946   Field_ftsf67ae_slot1_Slot_ae_slot1_set,
34947   Field_ftsf69ae_slot1_Slot_ae_slot1_set,
34948   Field_ftsf71ae_slot1_Slot_ae_slot1_set,
34949   Field_ftsf72ae_slot1_Slot_ae_slot1_set,
34950   Field_ftsf73ae_slot1_Slot_ae_slot1_set,
34951   Field_ftsf75ae_slot1_Slot_ae_slot1_set,
34952   Field_ftsf76ae_slot1_Slot_ae_slot1_set,
34953   Field_ftsf77ae_slot1_Slot_ae_slot1_set,
34954   Field_ftsf78ae_slot1_Slot_ae_slot1_set,
34955   Field_ftsf79ae_slot1_Slot_ae_slot1_set,
34956   Field_ftsf80ae_slot1_Slot_ae_slot1_set,
34957   Field_ftsf81ae_slot1_Slot_ae_slot1_set,
34958   Field_ftsf82ae_slot1_Slot_ae_slot1_set,
34959   Field_ftsf84ae_slot1_Slot_ae_slot1_set,
34960   Field_ftsf86ae_slot1_Slot_ae_slot1_set,
34961   Field_ftsf87ae_slot1_Slot_ae_slot1_set,
34962   Field_ftsf88ae_slot1_Slot_ae_slot1_set,
34963   Field_ftsf89ae_slot1_Slot_ae_slot1_set,
34964   Field_ftsf90ae_slot1_Slot_ae_slot1_set,
34965   Field_ftsf91ae_slot1_Slot_ae_slot1_set,
34966   Field_ftsf92ae_slot1_Slot_ae_slot1_set,
34967   Field_ftsf94ae_slot1_Slot_ae_slot1_set,
34968   Field_ftsf96ae_slot1_Slot_ae_slot1_set,
34969   Field_ftsf97ae_slot1_Slot_ae_slot1_set,
34970   Field_ftsf98ae_slot1_Slot_ae_slot1_set,
34971   Field_ftsf99ae_slot1_Slot_ae_slot1_set,
34972   Field_ftsf100ae_slot1_Slot_ae_slot1_set,
34973   Field_ftsf101ae_slot1_Slot_ae_slot1_set,
34974   Field_ftsf103ae_slot1_Slot_ae_slot1_set,
34975   Field_ftsf104ae_slot1_Slot_ae_slot1_set,
34976   Field_ftsf105ae_slot1_Slot_ae_slot1_set,
34977   Field_ftsf106ae_slot1_Slot_ae_slot1_set,
34978   Field_ftsf107ae_slot1_Slot_ae_slot1_set,
34979   Field_ftsf108ae_slot1_Slot_ae_slot1_set,
34980   Field_ftsf109ae_slot1_Slot_ae_slot1_set,
34981   Field_ftsf110ae_slot1_Slot_ae_slot1_set,
34982   Field_ftsf111ae_slot1_Slot_ae_slot1_set,
34983   Field_ftsf112ae_slot1_Slot_ae_slot1_set,
34984   Field_ftsf113ae_slot1_Slot_ae_slot1_set,
34985   Field_ftsf114ae_slot1_Slot_ae_slot1_set,
34986   Field_ftsf115ae_slot1_Slot_ae_slot1_set,
34987   Field_ftsf116ae_slot1_Slot_ae_slot1_set,
34988   Field_ftsf118ae_slot1_Slot_ae_slot1_set,
34989   Field_ftsf119ae_slot1_Slot_ae_slot1_set,
34990   Field_ftsf120ae_slot1_Slot_ae_slot1_set,
34991   Field_ftsf122ae_slot1_Slot_ae_slot1_set,
34992   Field_ftsf124ae_slot1_Slot_ae_slot1_set,
34993   Field_ftsf125ae_slot1_Slot_ae_slot1_set,
34994   Field_ftsf126ae_slot1_Slot_ae_slot1_set,
34995   Field_ftsf127ae_slot1_Slot_ae_slot1_set,
34996   Field_ftsf128ae_slot1_Slot_ae_slot1_set,
34997   Field_ftsf129ae_slot1_Slot_ae_slot1_set,
34998   Field_ftsf130ae_slot1_Slot_ae_slot1_set,
34999   Field_ftsf131ae_slot1_Slot_ae_slot1_set,
35000   Field_ftsf132ae_slot1_Slot_ae_slot1_set,
35001   Field_ftsf133ae_slot1_Slot_ae_slot1_set,
35002   Field_ftsf134ae_slot1_Slot_ae_slot1_set,
35003   Field_ftsf135ae_slot1_Slot_ae_slot1_set,
35004   Field_ftsf136ae_slot1_Slot_ae_slot1_set,
35005   Field_ftsf137ae_slot1_Slot_ae_slot1_set,
35006   Field_ftsf138ae_slot1_Slot_ae_slot1_set,
35007   Field_ftsf139ae_slot1_Slot_ae_slot1_set,
35008   Field_ftsf140ae_slot1_Slot_ae_slot1_set,
35009   Field_ftsf141ae_slot1_Slot_ae_slot1_set,
35010   Field_ftsf142ae_slot1_Slot_ae_slot1_set,
35011   Field_ftsf143ae_slot1_Slot_ae_slot1_set,
35012   Field_ftsf144ae_slot1_Slot_ae_slot1_set,
35013   Field_ftsf145ae_slot1_Slot_ae_slot1_set,
35014   Field_ftsf146ae_slot1_Slot_ae_slot1_set,
35015   Field_ftsf147ae_slot1_Slot_ae_slot1_set,
35016   Field_ftsf148ae_slot1_Slot_ae_slot1_set,
35017   Field_ftsf149ae_slot1_Slot_ae_slot1_set,
35018   Field_ftsf150ae_slot1_Slot_ae_slot1_set,
35019   Field_ftsf151ae_slot1_Slot_ae_slot1_set,
35020   Field_ftsf152ae_slot1_Slot_ae_slot1_set,
35021   Field_ftsf153ae_slot1_Slot_ae_slot1_set,
35022   Field_ftsf154ae_slot1_Slot_ae_slot1_set,
35023   Field_ftsf155ae_slot1_Slot_ae_slot1_set,
35024   Field_ftsf156ae_slot1_Slot_ae_slot1_set,
35025   Field_ftsf157ae_slot1_Slot_ae_slot1_set,
35026   Field_ftsf158ae_slot1_Slot_ae_slot1_set,
35027   Field_ftsf159ae_slot1_Slot_ae_slot1_set,
35028   Field_ftsf160ae_slot1_Slot_ae_slot1_set,
35029   Field_ftsf161ae_slot1_Slot_ae_slot1_set,
35030   Field_ftsf162ae_slot1_Slot_ae_slot1_set,
35031   Field_ftsf163ae_slot1_Slot_ae_slot1_set,
35032   Field_ftsf164ae_slot1_Slot_ae_slot1_set,
35033   Field_ftsf165ae_slot1_Slot_ae_slot1_set,
35034   Field_ftsf166ae_slot1_Slot_ae_slot1_set,
35035   Field_ftsf167ae_slot1_Slot_ae_slot1_set,
35036   Field_ftsf168ae_slot1_Slot_ae_slot1_set,
35037   Field_ftsf169ae_slot1_Slot_ae_slot1_set,
35038   Field_ftsf170ae_slot1_Slot_ae_slot1_set,
35039   Field_ftsf171ae_slot1_Slot_ae_slot1_set,
35040   Field_ftsf172ae_slot1_Slot_ae_slot1_set,
35041   Field_ftsf173ae_slot1_Slot_ae_slot1_set,
35042   Field_ftsf174ae_slot1_Slot_ae_slot1_set,
35043   Field_ftsf175ae_slot1_Slot_ae_slot1_set,
35044   Field_ftsf176ae_slot1_Slot_ae_slot1_set,
35045   Field_ftsf177ae_slot1_Slot_ae_slot1_set,
35046   Field_ftsf178ae_slot1_Slot_ae_slot1_set,
35047   Field_ftsf179ae_slot1_Slot_ae_slot1_set,
35048   Field_ftsf180ae_slot1_Slot_ae_slot1_set,
35049   Field_ftsf181ae_slot1_Slot_ae_slot1_set,
35050   Field_ftsf182ae_slot1_Slot_ae_slot1_set,
35051   Field_ftsf183ae_slot1_Slot_ae_slot1_set,
35052   Field_ftsf184ae_slot1_Slot_ae_slot1_set,
35053   Field_ftsf185ae_slot1_Slot_ae_slot1_set,
35054   Field_ftsf186ae_slot1_Slot_ae_slot1_set,
35055   Field_ftsf187ae_slot1_Slot_ae_slot1_set,
35056   Field_ftsf188ae_slot1_Slot_ae_slot1_set,
35057   Field_ftsf189ae_slot1_Slot_ae_slot1_set,
35058   Field_ftsf190ae_slot1_Slot_ae_slot1_set,
35059   Field_ftsf191ae_slot1_Slot_ae_slot1_set,
35060   Field_ftsf192ae_slot1_Slot_ae_slot1_set,
35061   Field_ftsf193ae_slot1_Slot_ae_slot1_set,
35062   Field_ftsf194ae_slot1_Slot_ae_slot1_set,
35063   Field_ftsf195ae_slot1_Slot_ae_slot1_set,
35064   Field_ftsf196ae_slot1_Slot_ae_slot1_set,
35065   Field_ftsf197ae_slot1_Slot_ae_slot1_set,
35066   Field_ftsf198ae_slot1_Slot_ae_slot1_set,
35067   Field_ftsf199ae_slot1_Slot_ae_slot1_set,
35068   Field_ftsf200ae_slot1_Slot_ae_slot1_set,
35069   Field_ftsf201ae_slot1_Slot_ae_slot1_set,
35070   Field_ftsf202ae_slot1_Slot_ae_slot1_set,
35071   Field_ftsf203ae_slot1_Slot_ae_slot1_set,
35072   Field_ftsf204ae_slot1_Slot_ae_slot1_set,
35073   Field_ftsf205ae_slot1_Slot_ae_slot1_set,
35074   Field_ftsf206ae_slot1_Slot_ae_slot1_set,
35075   Field_ftsf207ae_slot1_Slot_ae_slot1_set,
35076   Field_ftsf208_Slot_ae_slot1_set,
35077   Field_ftsf209ae_slot1_Slot_ae_slot1_set,
35078   Field_ftsf210ae_slot1_Slot_ae_slot1_set,
35079   Field_ftsf211ae_slot1_Slot_ae_slot1_set,
35080   Field_ftsf330ae_slot1_Slot_ae_slot1_set,
35081   Field_ftsf332ae_slot1_Slot_ae_slot1_set,
35082   Field_ftsf334ae_slot1_Slot_ae_slot1_set,
35083   Field_ftsf336ae_slot1_Slot_ae_slot1_set,
35084   Field_ftsf337ae_slot1_Slot_ae_slot1_set,
35085   Field_ftsf338_Slot_ae_slot1_set,
35086   Field_ftsf339ae_slot1_Slot_ae_slot1_set,
35087   Field_ftsf340_Slot_ae_slot1_set,
35088   Field_ftsf341ae_slot1_Slot_ae_slot1_set,
35089   Field_ftsf342ae_slot1_Slot_ae_slot1_set,
35090   Field_ftsf343ae_slot1_Slot_ae_slot1_set,
35091   Field_ftsf344ae_slot1_Slot_ae_slot1_set,
35092   Field_ftsf346ae_slot1_Slot_ae_slot1_set,
35093   Field_ftsf347_Slot_ae_slot1_set,
35094   Field_ftsf348ae_slot1_Slot_ae_slot1_set,
35095   Field_ftsf349ae_slot1_Slot_ae_slot1_set,
35096   Field_ftsf350ae_slot1_Slot_ae_slot1_set,
35097   0,
35098   0,
35099   0,
35100   0,
35101   0,
35102   0,
35103   0,
35104   0,
35105   0,
35106   0,
35107   0,
35108   0,
35109   0,
35110   0,
35111   0,
35112   0,
35113   0,
35114   0,
35115   0,
35116   0,
35117   0,
35118   0,
35119   0,
35120   0,
35121   0,
35122   0,
35123   0,
35124   0,
35125   0,
35126   0,
35127   0,
35128   0,
35129   0,
35130   0,
35131   0,
35132   0,
35133   0,
35134   0,
35135   0,
35136   0,
35137   0,
35138   0,
35139   0,
35140   0,
35141   0,
35142   0,
35143   0,
35144   0,
35145   0,
35146   0,
35147   0,
35148   0,
35149   0,
35150   0,
35151   0,
35152   0,
35153   0,
35154   0,
35155   0,
35156   0,
35157   0,
35158   0,
35159   0,
35160   0,
35161   0,
35162   0,
35163   0,
35164   0,
35165   0,
35166   0,
35167   0,
35168   0,
35169   0,
35170   0,
35171   0,
35172   0,
35173   0,
35174   0,
35175   0,
35176   0,
35177   0,
35178   0,
35179   0,
35180   0,
35181   0,
35182   0,
35183   0,
35184   0,
35185   0,
35186   0,
35187   0,
35188   0,
35189   0,
35190   0,
35191   0,
35192   0,
35193   0,
35194   0,
35195   0,
35196   0,
35197   0,
35198   0,
35199   0,
35200   0,
35201   0,
35202   0,
35203   0,
35204   0,
35205   0,
35206   0,
35207   0,
35208   0,
35209   0,
35210   0,
35211   0,
35212   0,
35213   0,
35214   0,
35215   0,
35216   0,
35217   0,
35218   0,
35219   0,
35220   0,
35221   0,
35222   0,
35223   Implicit_Field_set,
35224   Implicit_Field_set,
35225   Implicit_Field_set,
35226   Implicit_Field_set,
35227   Implicit_Field_set,
35228   Implicit_Field_set,
35229   Implicit_Field_set,
35230   Implicit_Field_set
35231 };
35232
35233 static xtensa_get_field_fn
35234 Slot_ae_slot0_get_field_fns[] = {
35235   Field_t_Slot_ae_slot0_get,
35236   0,
35237   Field_bbi_Slot_ae_slot0_get,
35238   Field_imm12_Slot_ae_slot0_get,
35239   Field_imm8_Slot_ae_slot0_get,
35240   Field_s_Slot_ae_slot0_get,
35241   Field_imm12b_Slot_ae_slot0_get,
35242   Field_imm16_Slot_ae_slot0_get,
35243   0,
35244   0,
35245   Field_offset_Slot_ae_slot0_get,
35246   0,
35247   0,
35248   Field_op2_Slot_ae_slot0_get,
35249   Field_r_Slot_ae_slot0_get,
35250   0,
35251   0,
35252   Field_sae_Slot_ae_slot0_get,
35253   Field_sal_Slot_ae_slot0_get,
35254   Field_sargt_Slot_ae_slot0_get,
35255   0,
35256   Field_sas_Slot_ae_slot0_get,
35257   0,
35258   0,
35259   0,
35260   0,
35261   0,
35262   0,
35263   0,
35264   0,
35265   0,
35266   0,
35267   0,
35268   0,
35269   0,
35270   0,
35271   0,
35272   0,
35273   0,
35274   Field_s4_Slot_ae_slot0_get,
35275   0,
35276   0,
35277   Field_s8_Slot_ae_slot0_get,
35278   0,
35279   0,
35280   0,
35281   0,
35282   0,
35283   0,
35284   Field_ae_r32_Slot_ae_slot0_get,
35285   Field_ae_samt_s_t_Slot_ae_slot0_get,
35286   Field_ae_r20_Slot_ae_slot0_get,
35287   Field_ae_r10_Slot_ae_slot0_get,
35288   Field_ae_s20_Slot_ae_slot0_get,
35289   0,
35290   0,
35291   0,
35292   0,
35293   0,
35294   0,
35295   0,
35296   0,
35297   0,
35298   0,
35299   0,
35300   0,
35301   0,
35302   0,
35303   0,
35304   0,
35305   0,
35306   0,
35307   0,
35308   0,
35309   0,
35310   0,
35311   0,
35312   0,
35313   0,
35314   0,
35315   0,
35316   0,
35317   0,
35318   0,
35319   0,
35320   0,
35321   0,
35322   0,
35323   0,
35324   0,
35325   0,
35326   0,
35327   0,
35328   0,
35329   0,
35330   0,
35331   0,
35332   0,
35333   0,
35334   0,
35335   0,
35336   0,
35337   0,
35338   0,
35339   0,
35340   0,
35341   0,
35342   0,
35343   0,
35344   0,
35345   0,
35346   0,
35347   0,
35348   0,
35349   0,
35350   0,
35351   0,
35352   0,
35353   0,
35354   0,
35355   0,
35356   0,
35357   0,
35358   0,
35359   0,
35360   0,
35361   0,
35362   0,
35363   0,
35364   0,
35365   0,
35366   0,
35367   0,
35368   0,
35369   0,
35370   0,
35371   0,
35372   0,
35373   0,
35374   0,
35375   0,
35376   0,
35377   0,
35378   0,
35379   0,
35380   0,
35381   0,
35382   0,
35383   0,
35384   0,
35385   0,
35386   0,
35387   0,
35388   0,
35389   0,
35390   0,
35391   0,
35392   0,
35393   0,
35394   0,
35395   0,
35396   0,
35397   0,
35398   0,
35399   0,
35400   0,
35401   0,
35402   0,
35403   0,
35404   0,
35405   0,
35406   0,
35407   0,
35408   0,
35409   0,
35410   0,
35411   0,
35412   0,
35413   0,
35414   0,
35415   0,
35416   0,
35417   0,
35418   0,
35419   0,
35420   0,
35421   0,
35422   0,
35423   0,
35424   0,
35425   0,
35426   0,
35427   0,
35428   0,
35429   0,
35430   0,
35431   0,
35432   0,
35433   0,
35434   0,
35435   0,
35436   0,
35437   0,
35438   0,
35439   0,
35440   0,
35441   0,
35442   0,
35443   0,
35444   0,
35445   0,
35446   0,
35447   0,
35448   0,
35449   0,
35450   0,
35451   0,
35452   0,
35453   0,
35454   0,
35455   0,
35456   0,
35457   0,
35458   0,
35459   0,
35460   0,
35461   0,
35462   0,
35463   0,
35464   0,
35465   0,
35466   0,
35467   0,
35468   0,
35469   0,
35470   0,
35471   0,
35472   0,
35473   0,
35474   0,
35475   0,
35476   0,
35477   0,
35478   0,
35479   0,
35480   0,
35481   0,
35482   0,
35483   0,
35484   0,
35485   0,
35486   0,
35487   0,
35488   0,
35489   0,
35490   Field_op0_s4_Slot_ae_slot0_get,
35491   Field_ftsf212ae_slot0_Slot_ae_slot0_get,
35492   Field_ftsf213ae_slot0_Slot_ae_slot0_get,
35493   Field_ftsf214ae_slot0_Slot_ae_slot0_get,
35494   Field_ftsf215ae_slot0_Slot_ae_slot0_get,
35495   Field_ftsf216ae_slot0_Slot_ae_slot0_get,
35496   Field_ftsf217_Slot_ae_slot0_get,
35497   Field_ftsf218ae_slot0_Slot_ae_slot0_get,
35498   Field_ftsf219ae_slot0_Slot_ae_slot0_get,
35499   Field_ftsf220ae_slot0_Slot_ae_slot0_get,
35500   Field_ftsf221ae_slot0_Slot_ae_slot0_get,
35501   Field_ftsf222ae_slot0_Slot_ae_slot0_get,
35502   Field_ftsf223ae_slot0_Slot_ae_slot0_get,
35503   Field_ftsf224ae_slot0_Slot_ae_slot0_get,
35504   Field_ftsf225ae_slot0_Slot_ae_slot0_get,
35505   Field_ftsf226ae_slot0_Slot_ae_slot0_get,
35506   Field_ftsf227ae_slot0_Slot_ae_slot0_get,
35507   Field_ftsf228ae_slot0_Slot_ae_slot0_get,
35508   Field_ftsf229ae_slot0_Slot_ae_slot0_get,
35509   Field_ftsf230ae_slot0_Slot_ae_slot0_get,
35510   Field_ftsf231ae_slot0_Slot_ae_slot0_get,
35511   Field_ftsf232ae_slot0_Slot_ae_slot0_get,
35512   Field_ftsf233ae_slot0_Slot_ae_slot0_get,
35513   Field_ftsf234ae_slot0_Slot_ae_slot0_get,
35514   Field_ftsf235ae_slot0_Slot_ae_slot0_get,
35515   Field_ftsf236ae_slot0_Slot_ae_slot0_get,
35516   Field_ftsf237ae_slot0_Slot_ae_slot0_get,
35517   Field_ftsf238ae_slot0_Slot_ae_slot0_get,
35518   Field_ftsf239ae_slot0_Slot_ae_slot0_get,
35519   Field_ftsf240ae_slot0_Slot_ae_slot0_get,
35520   Field_ftsf241ae_slot0_Slot_ae_slot0_get,
35521   Field_ftsf242ae_slot0_Slot_ae_slot0_get,
35522   Field_ftsf243ae_slot0_Slot_ae_slot0_get,
35523   Field_ftsf244ae_slot0_Slot_ae_slot0_get,
35524   Field_ftsf245ae_slot0_Slot_ae_slot0_get,
35525   Field_ftsf246ae_slot0_Slot_ae_slot0_get,
35526   Field_ftsf247ae_slot0_Slot_ae_slot0_get,
35527   Field_ftsf248ae_slot0_Slot_ae_slot0_get,
35528   Field_ftsf249ae_slot0_Slot_ae_slot0_get,
35529   Field_ftsf250ae_slot0_Slot_ae_slot0_get,
35530   Field_ftsf251ae_slot0_Slot_ae_slot0_get,
35531   Field_ftsf252ae_slot0_Slot_ae_slot0_get,
35532   Field_ftsf253ae_slot0_Slot_ae_slot0_get,
35533   Field_ftsf254ae_slot0_Slot_ae_slot0_get,
35534   Field_ftsf255ae_slot0_Slot_ae_slot0_get,
35535   Field_ftsf256ae_slot0_Slot_ae_slot0_get,
35536   Field_ftsf257ae_slot0_Slot_ae_slot0_get,
35537   Field_ftsf258ae_slot0_Slot_ae_slot0_get,
35538   Field_ftsf259ae_slot0_Slot_ae_slot0_get,
35539   Field_ftsf260ae_slot0_Slot_ae_slot0_get,
35540   Field_ftsf261ae_slot0_Slot_ae_slot0_get,
35541   Field_ftsf262ae_slot0_Slot_ae_slot0_get,
35542   Field_ftsf263ae_slot0_Slot_ae_slot0_get,
35543   Field_ftsf264ae_slot0_Slot_ae_slot0_get,
35544   Field_ftsf265ae_slot0_Slot_ae_slot0_get,
35545   Field_ftsf266ae_slot0_Slot_ae_slot0_get,
35546   Field_ftsf267ae_slot0_Slot_ae_slot0_get,
35547   Field_ftsf268ae_slot0_Slot_ae_slot0_get,
35548   Field_ftsf269ae_slot0_Slot_ae_slot0_get,
35549   Field_ftsf270ae_slot0_Slot_ae_slot0_get,
35550   Field_ftsf271ae_slot0_Slot_ae_slot0_get,
35551   Field_ftsf272ae_slot0_Slot_ae_slot0_get,
35552   Field_ftsf273ae_slot0_Slot_ae_slot0_get,
35553   Field_ftsf274ae_slot0_Slot_ae_slot0_get,
35554   Field_ftsf275ae_slot0_Slot_ae_slot0_get,
35555   Field_ftsf276ae_slot0_Slot_ae_slot0_get,
35556   Field_ftsf277ae_slot0_Slot_ae_slot0_get,
35557   Field_ftsf278ae_slot0_Slot_ae_slot0_get,
35558   Field_ftsf279ae_slot0_Slot_ae_slot0_get,
35559   Field_ftsf281ae_slot0_Slot_ae_slot0_get,
35560   Field_ftsf282ae_slot0_Slot_ae_slot0_get,
35561   Field_ftsf283ae_slot0_Slot_ae_slot0_get,
35562   Field_ftsf284ae_slot0_Slot_ae_slot0_get,
35563   Field_ftsf286ae_slot0_Slot_ae_slot0_get,
35564   Field_ftsf288ae_slot0_Slot_ae_slot0_get,
35565   Field_ftsf290ae_slot0_Slot_ae_slot0_get,
35566   Field_ftsf292ae_slot0_Slot_ae_slot0_get,
35567   Field_ftsf293_Slot_ae_slot0_get,
35568   Field_ftsf294ae_slot0_Slot_ae_slot0_get,
35569   Field_ftsf295ae_slot0_Slot_ae_slot0_get,
35570   Field_ftsf296ae_slot0_Slot_ae_slot0_get,
35571   Field_ftsf297ae_slot0_Slot_ae_slot0_get,
35572   Field_ftsf298ae_slot0_Slot_ae_slot0_get,
35573   Field_ftsf299ae_slot0_Slot_ae_slot0_get,
35574   Field_ftsf300ae_slot0_Slot_ae_slot0_get,
35575   Field_ftsf301ae_slot0_Slot_ae_slot0_get,
35576   Field_ftsf302ae_slot0_Slot_ae_slot0_get,
35577   Field_ftsf303ae_slot0_Slot_ae_slot0_get,
35578   Field_ftsf304ae_slot0_Slot_ae_slot0_get,
35579   Field_ftsf306ae_slot0_Slot_ae_slot0_get,
35580   Field_ftsf308ae_slot0_Slot_ae_slot0_get,
35581   Field_ftsf309ae_slot0_Slot_ae_slot0_get,
35582   Field_ftsf310ae_slot0_Slot_ae_slot0_get,
35583   Field_ftsf311ae_slot0_Slot_ae_slot0_get,
35584   Field_ftsf312ae_slot0_Slot_ae_slot0_get,
35585   Field_ftsf313ae_slot0_Slot_ae_slot0_get,
35586   Field_ftsf314ae_slot0_Slot_ae_slot0_get,
35587   Field_ftsf315ae_slot0_Slot_ae_slot0_get,
35588   Field_ftsf316ae_slot0_Slot_ae_slot0_get,
35589   Field_ftsf317ae_slot0_Slot_ae_slot0_get,
35590   Field_ftsf318ae_slot0_Slot_ae_slot0_get,
35591   Field_ftsf319_Slot_ae_slot0_get,
35592   Field_ftsf320ae_slot0_Slot_ae_slot0_get,
35593   Field_ftsf321_Slot_ae_slot0_get,
35594   Field_ftsf322ae_slot0_Slot_ae_slot0_get,
35595   Field_ftsf323ae_slot0_Slot_ae_slot0_get,
35596   Field_ftsf324ae_slot0_Slot_ae_slot0_get,
35597   Field_ftsf325ae_slot0_Slot_ae_slot0_get,
35598   Field_ftsf326ae_slot0_Slot_ae_slot0_get,
35599   Field_ftsf328ae_slot0_Slot_ae_slot0_get,
35600   Field_ftsf329ae_slot0_Slot_ae_slot0_get,
35601   Field_ftsf352ae_slot0_Slot_ae_slot0_get,
35602   Field_ftsf353_Slot_ae_slot0_get,
35603   Field_ftsf354ae_slot0_Slot_ae_slot0_get,
35604   Field_ftsf356ae_slot0_Slot_ae_slot0_get,
35605   Field_ftsf357_Slot_ae_slot0_get,
35606   Field_ftsf358ae_slot0_Slot_ae_slot0_get,
35607   Field_ftsf359ae_slot0_Slot_ae_slot0_get,
35608   Field_ftsf360ae_slot0_Slot_ae_slot0_get,
35609   Field_ftsf361ae_slot0_Slot_ae_slot0_get,
35610   Field_ftsf362ae_slot0_Slot_ae_slot0_get,
35611   Field_ftsf364ae_slot0_Slot_ae_slot0_get,
35612   Field_ftsf365ae_slot0_Slot_ae_slot0_get,
35613   Field_ftsf366ae_slot0_Slot_ae_slot0_get,
35614   Field_ftsf368ae_slot0_Slot_ae_slot0_get,
35615   Field_ftsf369ae_slot0_Slot_ae_slot0_get,
35616   Implicit_Field_ar0_get,
35617   Implicit_Field_ar4_get,
35618   Implicit_Field_ar8_get,
35619   Implicit_Field_ar12_get,
35620   Implicit_Field_bt16_get,
35621   Implicit_Field_bs16_get,
35622   Implicit_Field_br16_get,
35623   Implicit_Field_brall_get
35624 };
35625
35626 static xtensa_set_field_fn
35627 Slot_ae_slot0_set_field_fns[] = {
35628   Field_t_Slot_ae_slot0_set,
35629   0,
35630   Field_bbi_Slot_ae_slot0_set,
35631   Field_imm12_Slot_ae_slot0_set,
35632   Field_imm8_Slot_ae_slot0_set,
35633   Field_s_Slot_ae_slot0_set,
35634   Field_imm12b_Slot_ae_slot0_set,
35635   Field_imm16_Slot_ae_slot0_set,
35636   0,
35637   0,
35638   Field_offset_Slot_ae_slot0_set,
35639   0,
35640   0,
35641   Field_op2_Slot_ae_slot0_set,
35642   Field_r_Slot_ae_slot0_set,
35643   0,
35644   0,
35645   Field_sae_Slot_ae_slot0_set,
35646   Field_sal_Slot_ae_slot0_set,
35647   Field_sargt_Slot_ae_slot0_set,
35648   0,
35649   Field_sas_Slot_ae_slot0_set,
35650   0,
35651   0,
35652   0,
35653   0,
35654   0,
35655   0,
35656   0,
35657   0,
35658   0,
35659   0,
35660   0,
35661   0,
35662   0,
35663   0,
35664   0,
35665   0,
35666   0,
35667   Field_s4_Slot_ae_slot0_set,
35668   0,
35669   0,
35670   Field_s8_Slot_ae_slot0_set,
35671   0,
35672   0,
35673   0,
35674   0,
35675   0,
35676   0,
35677   Field_ae_r32_Slot_ae_slot0_set,
35678   Field_ae_samt_s_t_Slot_ae_slot0_set,
35679   Field_ae_r20_Slot_ae_slot0_set,
35680   Field_ae_r10_Slot_ae_slot0_set,
35681   Field_ae_s20_Slot_ae_slot0_set,
35682   0,
35683   0,
35684   0,
35685   0,
35686   0,
35687   0,
35688   0,
35689   0,
35690   0,
35691   0,
35692   0,
35693   0,
35694   0,
35695   0,
35696   0,
35697   0,
35698   0,
35699   0,
35700   0,
35701   0,
35702   0,
35703   0,
35704   0,
35705   0,
35706   0,
35707   0,
35708   0,
35709   0,
35710   0,
35711   0,
35712   0,
35713   0,
35714   0,
35715   0,
35716   0,
35717   0,
35718   0,
35719   0,
35720   0,
35721   0,
35722   0,
35723   0,
35724   0,
35725   0,
35726   0,
35727   0,
35728   0,
35729   0,
35730   0,
35731   0,
35732   0,
35733   0,
35734   0,
35735   0,
35736   0,
35737   0,
35738   0,
35739   0,
35740   0,
35741   0,
35742   0,
35743   0,
35744   0,
35745   0,
35746   0,
35747   0,
35748   0,
35749   0,
35750   0,
35751   0,
35752   0,
35753   0,
35754   0,
35755   0,
35756   0,
35757   0,
35758   0,
35759   0,
35760   0,
35761   0,
35762   0,
35763   0,
35764   0,
35765   0,
35766   0,
35767   0,
35768   0,
35769   0,
35770   0,
35771   0,
35772   0,
35773   0,
35774   0,
35775   0,
35776   0,
35777   0,
35778   0,
35779   0,
35780   0,
35781   0,
35782   0,
35783   0,
35784   0,
35785   0,
35786   0,
35787   0,
35788   0,
35789   0,
35790   0,
35791   0,
35792   0,
35793   0,
35794   0,
35795   0,
35796   0,
35797   0,
35798   0,
35799   0,
35800   0,
35801   0,
35802   0,
35803   0,
35804   0,
35805   0,
35806   0,
35807   0,
35808   0,
35809   0,
35810   0,
35811   0,
35812   0,
35813   0,
35814   0,
35815   0,
35816   0,
35817   0,
35818   0,
35819   0,
35820   0,
35821   0,
35822   0,
35823   0,
35824   0,
35825   0,
35826   0,
35827   0,
35828   0,
35829   0,
35830   0,
35831   0,
35832   0,
35833   0,
35834   0,
35835   0,
35836   0,
35837   0,
35838   0,
35839   0,
35840   0,
35841   0,
35842   0,
35843   0,
35844   0,
35845   0,
35846   0,
35847   0,
35848   0,
35849   0,
35850   0,
35851   0,
35852   0,
35853   0,
35854   0,
35855   0,
35856   0,
35857   0,
35858   0,
35859   0,
35860   0,
35861   0,
35862   0,
35863   0,
35864   0,
35865   0,
35866   0,
35867   0,
35868   0,
35869   0,
35870   0,
35871   0,
35872   0,
35873   0,
35874   0,
35875   0,
35876   0,
35877   0,
35878   0,
35879   0,
35880   0,
35881   0,
35882   0,
35883   Field_op0_s4_Slot_ae_slot0_set,
35884   Field_ftsf212ae_slot0_Slot_ae_slot0_set,
35885   Field_ftsf213ae_slot0_Slot_ae_slot0_set,
35886   Field_ftsf214ae_slot0_Slot_ae_slot0_set,
35887   Field_ftsf215ae_slot0_Slot_ae_slot0_set,
35888   Field_ftsf216ae_slot0_Slot_ae_slot0_set,
35889   Field_ftsf217_Slot_ae_slot0_set,
35890   Field_ftsf218ae_slot0_Slot_ae_slot0_set,
35891   Field_ftsf219ae_slot0_Slot_ae_slot0_set,
35892   Field_ftsf220ae_slot0_Slot_ae_slot0_set,
35893   Field_ftsf221ae_slot0_Slot_ae_slot0_set,
35894   Field_ftsf222ae_slot0_Slot_ae_slot0_set,
35895   Field_ftsf223ae_slot0_Slot_ae_slot0_set,
35896   Field_ftsf224ae_slot0_Slot_ae_slot0_set,
35897   Field_ftsf225ae_slot0_Slot_ae_slot0_set,
35898   Field_ftsf226ae_slot0_Slot_ae_slot0_set,
35899   Field_ftsf227ae_slot0_Slot_ae_slot0_set,
35900   Field_ftsf228ae_slot0_Slot_ae_slot0_set,
35901   Field_ftsf229ae_slot0_Slot_ae_slot0_set,
35902   Field_ftsf230ae_slot0_Slot_ae_slot0_set,
35903   Field_ftsf231ae_slot0_Slot_ae_slot0_set,
35904   Field_ftsf232ae_slot0_Slot_ae_slot0_set,
35905   Field_ftsf233ae_slot0_Slot_ae_slot0_set,
35906   Field_ftsf234ae_slot0_Slot_ae_slot0_set,
35907   Field_ftsf235ae_slot0_Slot_ae_slot0_set,
35908   Field_ftsf236ae_slot0_Slot_ae_slot0_set,
35909   Field_ftsf237ae_slot0_Slot_ae_slot0_set,
35910   Field_ftsf238ae_slot0_Slot_ae_slot0_set,
35911   Field_ftsf239ae_slot0_Slot_ae_slot0_set,
35912   Field_ftsf240ae_slot0_Slot_ae_slot0_set,
35913   Field_ftsf241ae_slot0_Slot_ae_slot0_set,
35914   Field_ftsf242ae_slot0_Slot_ae_slot0_set,
35915   Field_ftsf243ae_slot0_Slot_ae_slot0_set,
35916   Field_ftsf244ae_slot0_Slot_ae_slot0_set,
35917   Field_ftsf245ae_slot0_Slot_ae_slot0_set,
35918   Field_ftsf246ae_slot0_Slot_ae_slot0_set,
35919   Field_ftsf247ae_slot0_Slot_ae_slot0_set,
35920   Field_ftsf248ae_slot0_Slot_ae_slot0_set,
35921   Field_ftsf249ae_slot0_Slot_ae_slot0_set,
35922   Field_ftsf250ae_slot0_Slot_ae_slot0_set,
35923   Field_ftsf251ae_slot0_Slot_ae_slot0_set,
35924   Field_ftsf252ae_slot0_Slot_ae_slot0_set,
35925   Field_ftsf253ae_slot0_Slot_ae_slot0_set,
35926   Field_ftsf254ae_slot0_Slot_ae_slot0_set,
35927   Field_ftsf255ae_slot0_Slot_ae_slot0_set,
35928   Field_ftsf256ae_slot0_Slot_ae_slot0_set,
35929   Field_ftsf257ae_slot0_Slot_ae_slot0_set,
35930   Field_ftsf258ae_slot0_Slot_ae_slot0_set,
35931   Field_ftsf259ae_slot0_Slot_ae_slot0_set,
35932   Field_ftsf260ae_slot0_Slot_ae_slot0_set,
35933   Field_ftsf261ae_slot0_Slot_ae_slot0_set,
35934   Field_ftsf262ae_slot0_Slot_ae_slot0_set,
35935   Field_ftsf263ae_slot0_Slot_ae_slot0_set,
35936   Field_ftsf264ae_slot0_Slot_ae_slot0_set,
35937   Field_ftsf265ae_slot0_Slot_ae_slot0_set,
35938   Field_ftsf266ae_slot0_Slot_ae_slot0_set,
35939   Field_ftsf267ae_slot0_Slot_ae_slot0_set,
35940   Field_ftsf268ae_slot0_Slot_ae_slot0_set,
35941   Field_ftsf269ae_slot0_Slot_ae_slot0_set,
35942   Field_ftsf270ae_slot0_Slot_ae_slot0_set,
35943   Field_ftsf271ae_slot0_Slot_ae_slot0_set,
35944   Field_ftsf272ae_slot0_Slot_ae_slot0_set,
35945   Field_ftsf273ae_slot0_Slot_ae_slot0_set,
35946   Field_ftsf274ae_slot0_Slot_ae_slot0_set,
35947   Field_ftsf275ae_slot0_Slot_ae_slot0_set,
35948   Field_ftsf276ae_slot0_Slot_ae_slot0_set,
35949   Field_ftsf277ae_slot0_Slot_ae_slot0_set,
35950   Field_ftsf278ae_slot0_Slot_ae_slot0_set,
35951   Field_ftsf279ae_slot0_Slot_ae_slot0_set,
35952   Field_ftsf281ae_slot0_Slot_ae_slot0_set,
35953   Field_ftsf282ae_slot0_Slot_ae_slot0_set,
35954   Field_ftsf283ae_slot0_Slot_ae_slot0_set,
35955   Field_ftsf284ae_slot0_Slot_ae_slot0_set,
35956   Field_ftsf286ae_slot0_Slot_ae_slot0_set,
35957   Field_ftsf288ae_slot0_Slot_ae_slot0_set,
35958   Field_ftsf290ae_slot0_Slot_ae_slot0_set,
35959   Field_ftsf292ae_slot0_Slot_ae_slot0_set,
35960   Field_ftsf293_Slot_ae_slot0_set,
35961   Field_ftsf294ae_slot0_Slot_ae_slot0_set,
35962   Field_ftsf295ae_slot0_Slot_ae_slot0_set,
35963   Field_ftsf296ae_slot0_Slot_ae_slot0_set,
35964   Field_ftsf297ae_slot0_Slot_ae_slot0_set,
35965   Field_ftsf298ae_slot0_Slot_ae_slot0_set,
35966   Field_ftsf299ae_slot0_Slot_ae_slot0_set,
35967   Field_ftsf300ae_slot0_Slot_ae_slot0_set,
35968   Field_ftsf301ae_slot0_Slot_ae_slot0_set,
35969   Field_ftsf302ae_slot0_Slot_ae_slot0_set,
35970   Field_ftsf303ae_slot0_Slot_ae_slot0_set,
35971   Field_ftsf304ae_slot0_Slot_ae_slot0_set,
35972   Field_ftsf306ae_slot0_Slot_ae_slot0_set,
35973   Field_ftsf308ae_slot0_Slot_ae_slot0_set,
35974   Field_ftsf309ae_slot0_Slot_ae_slot0_set,
35975   Field_ftsf310ae_slot0_Slot_ae_slot0_set,
35976   Field_ftsf311ae_slot0_Slot_ae_slot0_set,
35977   Field_ftsf312ae_slot0_Slot_ae_slot0_set,
35978   Field_ftsf313ae_slot0_Slot_ae_slot0_set,
35979   Field_ftsf314ae_slot0_Slot_ae_slot0_set,
35980   Field_ftsf315ae_slot0_Slot_ae_slot0_set,
35981   Field_ftsf316ae_slot0_Slot_ae_slot0_set,
35982   Field_ftsf317ae_slot0_Slot_ae_slot0_set,
35983   Field_ftsf318ae_slot0_Slot_ae_slot0_set,
35984   Field_ftsf319_Slot_ae_slot0_set,
35985   Field_ftsf320ae_slot0_Slot_ae_slot0_set,
35986   Field_ftsf321_Slot_ae_slot0_set,
35987   Field_ftsf322ae_slot0_Slot_ae_slot0_set,
35988   Field_ftsf323ae_slot0_Slot_ae_slot0_set,
35989   Field_ftsf324ae_slot0_Slot_ae_slot0_set,
35990   Field_ftsf325ae_slot0_Slot_ae_slot0_set,
35991   Field_ftsf326ae_slot0_Slot_ae_slot0_set,
35992   Field_ftsf328ae_slot0_Slot_ae_slot0_set,
35993   Field_ftsf329ae_slot0_Slot_ae_slot0_set,
35994   Field_ftsf352ae_slot0_Slot_ae_slot0_set,
35995   Field_ftsf353_Slot_ae_slot0_set,
35996   Field_ftsf354ae_slot0_Slot_ae_slot0_set,
35997   Field_ftsf356ae_slot0_Slot_ae_slot0_set,
35998   Field_ftsf357_Slot_ae_slot0_set,
35999   Field_ftsf358ae_slot0_Slot_ae_slot0_set,
36000   Field_ftsf359ae_slot0_Slot_ae_slot0_set,
36001   Field_ftsf360ae_slot0_Slot_ae_slot0_set,
36002   Field_ftsf361ae_slot0_Slot_ae_slot0_set,
36003   Field_ftsf362ae_slot0_Slot_ae_slot0_set,
36004   Field_ftsf364ae_slot0_Slot_ae_slot0_set,
36005   Field_ftsf365ae_slot0_Slot_ae_slot0_set,
36006   Field_ftsf366ae_slot0_Slot_ae_slot0_set,
36007   Field_ftsf368ae_slot0_Slot_ae_slot0_set,
36008   Field_ftsf369ae_slot0_Slot_ae_slot0_set,
36009   Implicit_Field_set,
36010   Implicit_Field_set,
36011   Implicit_Field_set,
36012   Implicit_Field_set,
36013   Implicit_Field_set,
36014   Implicit_Field_set,
36015   Implicit_Field_set,
36016   Implicit_Field_set
36017 };
36018
36019 static xtensa_slot_internal slots[] = {
36020   { "Inst", "x24", 0,
36021     Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
36022     Slot_inst_get_field_fns, Slot_inst_set_field_fns,
36023     Slot_inst_decode, "nop" },
36024   { "Inst16a", "x16a", 0,
36025     Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
36026     Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
36027     Slot_inst16a_decode, "" },
36028   { "Inst16b", "x16b", 0,
36029     Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
36030     Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
36031     Slot_inst16b_decode, "nop.n" },
36032   { "ae_slot1", "ae_format", 1,
36033     Slot_ae_format_Format_ae_slot1_31_get, Slot_ae_format_Format_ae_slot1_31_set,
36034     Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns,
36035     Slot_ae_slot1_decode, "nop" },
36036   { "ae_slot0", "ae_format", 0,
36037     Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set,
36038     Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns,
36039     Slot_ae_slot0_decode, "nop" }
36040 };
36041
36042 \f
36043 /* Instruction formats.  */
36044
36045 static void
36046 Format_x24_encode (xtensa_insnbuf insn)
36047 {
36048   insn[0] = 0;
36049   insn[1] = 0;
36050 }
36051
36052 static void
36053 Format_x16a_encode (xtensa_insnbuf insn)
36054 {
36055   insn[0] = 0x8;
36056   insn[1] = 0;
36057 }
36058
36059 static void
36060 Format_x16b_encode (xtensa_insnbuf insn)
36061 {
36062   insn[0] = 0xc;
36063   insn[1] = 0;
36064 }
36065
36066 static void
36067 Format_ae_format_encode (xtensa_insnbuf insn)
36068 {
36069   insn[0] = 0xf;
36070   insn[1] = 0;
36071 }
36072
36073 static int Format_x24_slots[] = { 0 };
36074
36075 static int Format_x16a_slots[] = { 1 };
36076
36077 static int Format_x16b_slots[] = { 2 };
36078
36079 static int Format_ae_format_slots[] = { 4, 3 };
36080
36081 static xtensa_format_internal formats[] = {
36082   { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
36083   { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
36084   { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
36085   { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots }
36086 };
36087
36088
36089 static int
36090 format_decoder (const xtensa_insnbuf insn)
36091 {
36092   if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0)
36093     return 0; /* x24 */
36094   if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0)
36095     return 1; /* x16a */
36096   if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0)
36097     return 2; /* x16b */
36098   if ((insn[0] & 0xf) == 0xf && (insn[1] & 0xffc00000) == 0)
36099     return 3; /* ae_format */
36100   return -1;
36101 }
36102
36103 static int length_table[256] = {
36104   3,
36105   3,
36106   3,
36107   3,
36108   3,
36109   3,
36110   3,
36111   3,
36112   2,
36113   2,
36114   2,
36115   2,
36116   2,
36117   2,
36118   -1,
36119   8,
36120   3,
36121   3,
36122   3,
36123   3,
36124   3,
36125   3,
36126   3,
36127   3,
36128   2,
36129   2,
36130   2,
36131   2,
36132   2,
36133   2,
36134   -1,
36135   8,
36136   3,
36137   3,
36138   3,
36139   3,
36140   3,
36141   3,
36142   3,
36143   3,
36144   2,
36145   2,
36146   2,
36147   2,
36148   2,
36149   2,
36150   -1,
36151   8,
36152   3,
36153   3,
36154   3,
36155   3,
36156   3,
36157   3,
36158   3,
36159   3,
36160   2,
36161   2,
36162   2,
36163   2,
36164   2,
36165   2,
36166   -1,
36167   8,
36168   3,
36169   3,
36170   3,
36171   3,
36172   3,
36173   3,
36174   3,
36175   3,
36176   2,
36177   2,
36178   2,
36179   2,
36180   2,
36181   2,
36182   -1,
36183   8,
36184   3,
36185   3,
36186   3,
36187   3,
36188   3,
36189   3,
36190   3,
36191   3,
36192   2,
36193   2,
36194   2,
36195   2,
36196   2,
36197   2,
36198   -1,
36199   8,
36200   3,
36201   3,
36202   3,
36203   3,
36204   3,
36205   3,
36206   3,
36207   3,
36208   2,
36209   2,
36210   2,
36211   2,
36212   2,
36213   2,
36214   -1,
36215   8,
36216   3,
36217   3,
36218   3,
36219   3,
36220   3,
36221   3,
36222   3,
36223   3,
36224   2,
36225   2,
36226   2,
36227   2,
36228   2,
36229   2,
36230   -1,
36231   8,
36232   3,
36233   3,
36234   3,
36235   3,
36236   3,
36237   3,
36238   3,
36239   3,
36240   2,
36241   2,
36242   2,
36243   2,
36244   2,
36245   2,
36246   -1,
36247   8,
36248   3,
36249   3,
36250   3,
36251   3,
36252   3,
36253   3,
36254   3,
36255   3,
36256   2,
36257   2,
36258   2,
36259   2,
36260   2,
36261   2,
36262   -1,
36263   8,
36264   3,
36265   3,
36266   3,
36267   3,
36268   3,
36269   3,
36270   3,
36271   3,
36272   2,
36273   2,
36274   2,
36275   2,
36276   2,
36277   2,
36278   -1,
36279   8,
36280   3,
36281   3,
36282   3,
36283   3,
36284   3,
36285   3,
36286   3,
36287   3,
36288   2,
36289   2,
36290   2,
36291   2,
36292   2,
36293   2,
36294   -1,
36295   8,
36296   3,
36297   3,
36298   3,
36299   3,
36300   3,
36301   3,
36302   3,
36303   3,
36304   2,
36305   2,
36306   2,
36307   2,
36308   2,
36309   2,
36310   -1,
36311   8,
36312   3,
36313   3,
36314   3,
36315   3,
36316   3,
36317   3,
36318   3,
36319   3,
36320   2,
36321   2,
36322   2,
36323   2,
36324   2,
36325   2,
36326   -1,
36327   8,
36328   3,
36329   3,
36330   3,
36331   3,
36332   3,
36333   3,
36334   3,
36335   3,
36336   2,
36337   2,
36338   2,
36339   2,
36340   2,
36341   2,
36342   -1,
36343   8,
36344   3,
36345   3,
36346   3,
36347   3,
36348   3,
36349   3,
36350   3,
36351   3,
36352   2,
36353   2,
36354   2,
36355   2,
36356   2,
36357   2,
36358   -1,
36359   8
36360 };
36361
36362 static int
36363 length_decoder (const unsigned char *insn)
36364 {
36365   int l = insn[0];
36366   return length_table[l];
36367 }
36368
36369 \f
36370 /* Top-level ISA structure.  */
36371
36372 xtensa_isa_internal xtensa_modules = {
36373   0 /* little-endian */,
36374   8 /* insn_size */, 0,
36375   4, formats, format_decoder, length_decoder,
36376   5, slots,
36377   389 /* num_fields */,
36378   454, operands,
36379   588, iclasses,
36380   656, opcodes, 0,
36381   8, regfiles,
36382   NUM_STATES, states, 0,
36383   NUM_SYSREGS, sysregs, 0,
36384   { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
36385   2, interfaces, 0,
36386   4, funcUnits, 0
36387 };