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target/ppc: Fix typo in comments
[qemu/ar7.git] / hw / net / e1000e_core.c
blob9b76f82db5b83ed611f5007da00964931de7692d
1 /*
2 * Core code for QEMU e1000e emulation
3 *
4 * Software developer's manuals:
5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
6 *
7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
8 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 *
10 * Authors:
11 * Dmitry Fleytman <dmitry@daynix.com>
12 * Leonid Bloch <leonid@daynix.com>
13 * Yan Vugenfirer <yan@daynix.com>
14 *
15 * Based on work done by:
16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
17 * Copyright (c) 2008 Qumranet
18 * Based on work done by:
19 * Copyright (c) 2007 Dan Aloni
20 * Copyright (c) 2004 Antony T Curtis
21 *
22 * This library is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU Lesser General Public
24 * License as published by the Free Software Foundation; either
25 * version 2 of the License, or (at your option) any later version.
26 *
27 * This library is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
30 * Lesser General Public License for more details.
31 *
32 * You should have received a copy of the GNU Lesser General Public
33 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
34 */
35
36 #include "qemu/osdep.h"
37 #include "net/net.h"
38 #include "net/tap.h"
39 #include "hw/hw.h"
40 #include "hw/pci/msi.h"
41 #include "hw/pci/msix.h"
42 #include "sysemu/runstate.h"
43
44 #include "net_tx_pkt.h"
45 #include "net_rx_pkt.h"
46
47 #include "e1000x_common.h"
48 #include "e1000e_core.h"
49
50 #include "trace.h"
51
52 #define E1000E_MIN_XITR (500) /* No more then 7813 interrupts per
53 second according to spec 10.2.4.2 */
54 #define E1000E_MAX_TX_FRAGS (64)
55
56 static inline void
57 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val);
58
59 static inline void
60 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp)
61 {
62 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) {
63 trace_e1000e_wrn_no_ts_support();
64 }
65 }
66
67 static inline void
68 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length)
69 {
70 if (cmd_and_length & E1000_TXD_CMD_SNAP) {
71 trace_e1000e_wrn_no_snap_support();
72 }
73 }
74
75 static inline void
76 e1000e_raise_legacy_irq(E1000ECore *core)
77 {
78 trace_e1000e_irq_legacy_notify(true);
79 e1000x_inc_reg_if_not_full(core->mac, IAC);
80 pci_set_irq(core->owner, 1);
81 }
82
83 static inline void
84 e1000e_lower_legacy_irq(E1000ECore *core)
85 {
86 trace_e1000e_irq_legacy_notify(false);
87 pci_set_irq(core->owner, 0);
88 }
89
90 static inline void
91 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer)
92 {
93 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] *
94 timer->delay_resolution_ns;
95
96 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
97
98 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
99
100 timer->running = true;
101 }
102
103 static void
104 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer)
105 {
106 if (timer->running) {
107 e1000e_intrmgr_rearm_timer(timer);
108 }
109 }
110
111 static void
112 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer)
113 {
114 if (timer->running) {
115 timer_del(timer->timer);
116 }
117 }
118
119 static inline void
120 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer)
121 {
122 if (timer->running) {
123 timer_del(timer->timer);
124 timer->running = false;
125 }
126 }
127
128 static inline void
129 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core)
130 {
131 trace_e1000e_irq_fire_delayed_interrupts();
132 e1000e_set_interrupt_cause(core, 0);
133 }
134
135 static void
136 e1000e_intrmgr_on_timer(void *opaque)
137 {
138 E1000IntrDelayTimer *timer = opaque;
139
140 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2);
141
142 timer->running = false;
143 e1000e_intrmgr_fire_delayed_interrupts(timer->core);
144 }
145
146 static void
147 e1000e_intrmgr_on_throttling_timer(void *opaque)
148 {
149 E1000IntrDelayTimer *timer = opaque;
150
151 assert(!msix_enabled(timer->core->owner));
152
153 timer->running = false;
154
155 if (!timer->core->itr_intr_pending) {
156 trace_e1000e_irq_throttling_no_pending_interrupts();
157 return;
158 }
159
160 if (msi_enabled(timer->core->owner)) {
161 trace_e1000e_irq_msi_notify_postponed();
162 e1000e_set_interrupt_cause(timer->core, 0);
163 } else {
164 trace_e1000e_irq_legacy_notify_postponed();
165 e1000e_set_interrupt_cause(timer->core, 0);
166 }
167 }
168
169 static void
170 e1000e_intrmgr_on_msix_throttling_timer(void *opaque)
171 {
172 E1000IntrDelayTimer *timer = opaque;
173 int idx = timer - &timer->core->eitr[0];
174
175 assert(msix_enabled(timer->core->owner));
176
177 timer->running = false;
178
179 if (!timer->core->eitr_intr_pending[idx]) {
180 trace_e1000e_irq_throttling_no_pending_vec(idx);
181 return;
182 }
183
184 trace_e1000e_irq_msix_notify_postponed_vec(idx);
185 msix_notify(timer->core->owner, idx);
186 }
187
188 static void
189 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create)
190 {
191 int i;
192
193 core->radv.delay_reg = RADV;
194 core->rdtr.delay_reg = RDTR;
195 core->raid.delay_reg = RAID;
196 core->tadv.delay_reg = TADV;
197 core->tidv.delay_reg = TIDV;
198
199 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
200 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
201 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
202 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
203 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
204
205 core->radv.core = core;
206 core->rdtr.core = core;
207 core->raid.core = core;
208 core->tadv.core = core;
209 core->tidv.core = core;
210
211 core->itr.core = core;
212 core->itr.delay_reg = ITR;
213 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
214
215 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
216 core->eitr[i].core = core;
217 core->eitr[i].delay_reg = EITR + i;
218 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
219 }
220
221 if (!create) {
222 return;
223 }
224
225 core->radv.timer =
226 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv);
227 core->rdtr.timer =
228 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr);
229 core->raid.timer =
230 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid);
231
232 core->tadv.timer =
233 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv);
234 core->tidv.timer =
235 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv);
236
237 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
238 e1000e_intrmgr_on_throttling_timer,
239 &core->itr);
240
241 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
242 core->eitr[i].timer =
243 timer_new_ns(QEMU_CLOCK_VIRTUAL,
244 e1000e_intrmgr_on_msix_throttling_timer,
245 &core->eitr[i]);
246 }
247 }
248
249 static inline void
250 e1000e_intrmgr_stop_delay_timers(E1000ECore *core)
251 {
252 e1000e_intrmgr_stop_timer(&core->radv);
253 e1000e_intrmgr_stop_timer(&core->rdtr);
254 e1000e_intrmgr_stop_timer(&core->raid);
255 e1000e_intrmgr_stop_timer(&core->tidv);
256 e1000e_intrmgr_stop_timer(&core->tadv);
257 }
258
259 static bool
260 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes)
261 {
262 uint32_t delayable_causes;
263 uint32_t rdtr = core->mac[RDTR];
264 uint32_t radv = core->mac[RADV];
265 uint32_t raid = core->mac[RAID];
266
267 if (msix_enabled(core->owner)) {
268 return false;
269 }
270
271 delayable_causes = E1000_ICR_RXQ0 |
272 E1000_ICR_RXQ1 |
273 E1000_ICR_RXT0;
274
275 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) {
276 delayable_causes |= E1000_ICR_ACK;
277 }
278
279 /* Clean up all causes that may be delayed */
280 core->delayed_causes |= *causes & delayable_causes;
281 *causes &= ~delayable_causes;
282
283 /* Check if delayed RX interrupts disabled by client
284 or if there are causes that cannot be delayed */
285 if ((rdtr == 0) || (*causes != 0)) {
286 return false;
287 }
288
289 /* Check if delayed RX ACK interrupts disabled by client
290 and there is an ACK packet received */
291 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) {
292 return false;
293 }
294
295 /* All causes delayed */
296 e1000e_intrmgr_rearm_timer(&core->rdtr);
297
298 if (!core->radv.running && (radv != 0)) {
299 e1000e_intrmgr_rearm_timer(&core->radv);
300 }
301
302 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) {
303 e1000e_intrmgr_rearm_timer(&core->raid);
304 }
305
306 return true;
307 }
308
309 static bool
310 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes)
311 {
312 static const uint32_t delayable_causes = E1000_ICR_TXQ0 |
313 E1000_ICR_TXQ1 |
314 E1000_ICR_TXQE |
315 E1000_ICR_TXDW;
316
317 if (msix_enabled(core->owner)) {
318 return false;
319 }
320
321 /* Clean up all causes that may be delayed */
322 core->delayed_causes |= *causes & delayable_causes;
323 *causes &= ~delayable_causes;
324
325 /* If there are causes that cannot be delayed */
326 if (*causes != 0) {
327 return false;
328 }
329
330 /* All causes delayed */
331 e1000e_intrmgr_rearm_timer(&core->tidv);
332
333 if (!core->tadv.running && (core->mac[TADV] != 0)) {
334 e1000e_intrmgr_rearm_timer(&core->tadv);
335 }
336
337 return true;
338 }
339
340 static uint32_t
341 e1000e_intmgr_collect_delayed_causes(E1000ECore *core)
342 {
343 uint32_t res;
344
345 if (msix_enabled(core->owner)) {
346 assert(core->delayed_causes == 0);
347 return 0;
348 }
349
350 res = core->delayed_causes;
351 core->delayed_causes = 0;
352
353 e1000e_intrmgr_stop_delay_timers(core);
354
355 return res;
356 }
357
358 static void
359 e1000e_intrmgr_fire_all_timers(E1000ECore *core)
360 {
361 int i;
362 uint32_t val = e1000e_intmgr_collect_delayed_causes(core);
363
364 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]);
365 core->mac[ICR] |= val;
366
367 if (core->itr.running) {
368 timer_del(core->itr.timer);
369 e1000e_intrmgr_on_throttling_timer(&core->itr);
370 }
371
372 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
373 if (core->eitr[i].running) {
374 timer_del(core->eitr[i].timer);
375 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]);
376 }
377 }
378 }
379
380 static void
381 e1000e_intrmgr_resume(E1000ECore *core)
382 {
383 int i;
384
385 e1000e_intmgr_timer_resume(&core->radv);
386 e1000e_intmgr_timer_resume(&core->rdtr);
387 e1000e_intmgr_timer_resume(&core->raid);
388 e1000e_intmgr_timer_resume(&core->tidv);
389 e1000e_intmgr_timer_resume(&core->tadv);
390
391 e1000e_intmgr_timer_resume(&core->itr);
392
393 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
394 e1000e_intmgr_timer_resume(&core->eitr[i]);
395 }
396 }
397
398 static void
399 e1000e_intrmgr_pause(E1000ECore *core)
400 {
401 int i;
402
403 e1000e_intmgr_timer_pause(&core->radv);
404 e1000e_intmgr_timer_pause(&core->rdtr);
405 e1000e_intmgr_timer_pause(&core->raid);
406 e1000e_intmgr_timer_pause(&core->tidv);
407 e1000e_intmgr_timer_pause(&core->tadv);
408
409 e1000e_intmgr_timer_pause(&core->itr);
410
411 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
412 e1000e_intmgr_timer_pause(&core->eitr[i]);
413 }
414 }
415
416 static void
417 e1000e_intrmgr_reset(E1000ECore *core)
418 {
419 int i;
420
421 core->delayed_causes = 0;
422
423 e1000e_intrmgr_stop_delay_timers(core);
424
425 e1000e_intrmgr_stop_timer(&core->itr);
426
427 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
428 e1000e_intrmgr_stop_timer(&core->eitr[i]);
429 }
430 }
431
432 static void
433 e1000e_intrmgr_pci_unint(E1000ECore *core)
434 {
435 int i;
436
437 timer_del(core->radv.timer);
438 timer_free(core->radv.timer);
439 timer_del(core->rdtr.timer);
440 timer_free(core->rdtr.timer);
441 timer_del(core->raid.timer);
442 timer_free(core->raid.timer);
443
444 timer_del(core->tadv.timer);
445 timer_free(core->tadv.timer);
446 timer_del(core->tidv.timer);
447 timer_free(core->tidv.timer);
448
449 timer_del(core->itr.timer);
450 timer_free(core->itr.timer);
451
452 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
453 timer_del(core->eitr[i].timer);
454 timer_free(core->eitr[i].timer);
455 }
456 }
457
458 static void
459 e1000e_intrmgr_pci_realize(E1000ECore *core)
460 {
461 e1000e_intrmgr_initialize_all_timers(core, true);
462 }
463
464 static inline bool
465 e1000e_rx_csum_enabled(E1000ECore *core)
466 {
467 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true;
468 }
469
470 static inline bool
471 e1000e_rx_use_legacy_descriptor(E1000ECore *core)
472 {
473 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true;
474 }
475
476 static inline bool
477 e1000e_rx_use_ps_descriptor(E1000ECore *core)
478 {
479 return !e1000e_rx_use_legacy_descriptor(core) &&
480 (core->mac[RCTL] & E1000_RCTL_DTYP_PS);
481 }
482
483 static inline bool
484 e1000e_rss_enabled(E1000ECore *core)
485 {
486 return E1000_MRQC_ENABLED(core->mac[MRQC]) &&
487 !e1000e_rx_csum_enabled(core) &&
488 !e1000e_rx_use_legacy_descriptor(core);
489 }
490
491 typedef struct E1000E_RSSInfo_st {
492 bool enabled;
493 uint32_t hash;
494 uint32_t queue;
495 uint32_t type;
496 } E1000E_RSSInfo;
497
498 static uint32_t
499 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt)
500 {
501 bool isip4, isip6, isudp, istcp;
502
503 assert(e1000e_rss_enabled(core));
504
505 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
506
507 if (isip4) {
508 bool fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
509
510 trace_e1000e_rx_rss_ip4(fragment, istcp, core->mac[MRQC],
511 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]),
512 E1000_MRQC_EN_IPV4(core->mac[MRQC]));
513
514 if (!fragment && istcp && E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) {
515 return E1000_MRQ_RSS_TYPE_IPV4TCP;
516 }
517
518 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
519 return E1000_MRQ_RSS_TYPE_IPV4;
520 }
521 } else if (isip6) {
522 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt);
523
524 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS;
525 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS;
526
527 /*
528 * Following two traces must not be combined because resulting
529 * event will have 11 arguments totally and some trace backends
530 * (at least "ust") have limitation of maximum 10 arguments per
531 * event. Events with more arguments fail to compile for
532 * backends like these.
533 */
534 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]);
535 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, istcp,
536 ip6info->has_ext_hdrs,
537 ip6info->rss_ex_dst_valid,
538 ip6info->rss_ex_src_valid,
539 core->mac[MRQC],
540 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]),
541 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
542 E1000_MRQC_EN_IPV6(core->mac[MRQC]));
543
544 if ((!ex_dis || !ip6info->has_ext_hdrs) &&
545 (!new_ex_dis || !(ip6info->rss_ex_dst_valid ||
546 ip6info->rss_ex_src_valid))) {
547
548 if (istcp && !ip6info->fragment &&
549 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) {
550 return E1000_MRQ_RSS_TYPE_IPV6TCP;
551 }
552
553 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
554 return E1000_MRQ_RSS_TYPE_IPV6EX;
555 }
556
557 }
558
559 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) {
560 return E1000_MRQ_RSS_TYPE_IPV6;
561 }
562
563 }
564
565 return E1000_MRQ_RSS_TYPE_NONE;
566 }
567
568 static uint32_t
569 e1000e_rss_calc_hash(E1000ECore *core,
570 struct NetRxPkt *pkt,
571 E1000E_RSSInfo *info)
572 {
573 NetRxPktRssType type;
574
575 assert(e1000e_rss_enabled(core));
576
577 switch (info->type) {
578 case E1000_MRQ_RSS_TYPE_IPV4:
579 type = NetPktRssIpV4;
580 break;
581 case E1000_MRQ_RSS_TYPE_IPV4TCP:
582 type = NetPktRssIpV4Tcp;
583 break;
584 case E1000_MRQ_RSS_TYPE_IPV6TCP:
585 type = NetPktRssIpV6Tcp;
586 break;
587 case E1000_MRQ_RSS_TYPE_IPV6:
588 type = NetPktRssIpV6;
589 break;
590 case E1000_MRQ_RSS_TYPE_IPV6EX:
591 type = NetPktRssIpV6Ex;
592 break;
593 default:
594 assert(false);
595 return 0;
596 }
597
598 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]);
599 }
600
601 static void
602 e1000e_rss_parse_packet(E1000ECore *core,
603 struct NetRxPkt *pkt,
604 E1000E_RSSInfo *info)
605 {
606 trace_e1000e_rx_rss_started();
607
608 if (!e1000e_rss_enabled(core)) {
609 info->enabled = false;
610 info->hash = 0;
611 info->queue = 0;
612 info->type = 0;
613 trace_e1000e_rx_rss_disabled();
614 return;
615 }
616
617 info->enabled = true;
618
619 info->type = e1000e_rss_get_hash_type(core, pkt);
620
621 trace_e1000e_rx_rss_type(info->type);
622
623 if (info->type == E1000_MRQ_RSS_TYPE_NONE) {
624 info->hash = 0;
625 info->queue = 0;
626 return;
627 }
628
629 info->hash = e1000e_rss_calc_hash(core, pkt, info);
630 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
631 }
632
633 static void
634 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx)
635 {
636 if (tx->props.tse && tx->cptse) {
637 net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss);
638 net_tx_pkt_update_ip_checksums(tx->tx_pkt);
639 e1000x_inc_reg_if_not_full(core->mac, TSCTC);
640 return;
641 }
642
643 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) {
644 net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0);
645 }
646
647 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) {
648 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
649 }
650 }
651
652 static bool
653 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index)
654 {
655 int target_queue = MIN(core->max_queue_num, queue_index);
656 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue);
657
658 e1000e_setup_tx_offloads(core, tx);
659
660 net_tx_pkt_dump(tx->tx_pkt);
661
662 if ((core->phy[0][PHY_CTRL] & MII_CR_LOOPBACK) ||
663 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) {
664 return net_tx_pkt_send_loopback(tx->tx_pkt, queue);
665 } else {
666 return net_tx_pkt_send(tx->tx_pkt, queue);
667 }
668 }
669
670 static void
671 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt)
672 {
673 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
674 PTC1023, PTC1522 };
675
676 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt);
677
678 e1000x_increase_size_stats(core->mac, PTCregs, tot_len);
679 e1000x_inc_reg_if_not_full(core->mac, TPT);
680 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len);
681
682 switch (net_tx_pkt_get_packet_type(tx_pkt)) {
683 case ETH_PKT_BCAST:
684 e1000x_inc_reg_if_not_full(core->mac, BPTC);
685 break;
686 case ETH_PKT_MCAST:
687 e1000x_inc_reg_if_not_full(core->mac, MPTC);
688 break;
689 case ETH_PKT_UCAST:
690 break;
691 default:
692 g_assert_not_reached();
693 }
694
695 core->mac[GPTC] = core->mac[TPT];
696 core->mac[GOTCL] = core->mac[TOTL];
697 core->mac[GOTCH] = core->mac[TOTH];
698 }
699
700 static void
701 e1000e_process_tx_desc(E1000ECore *core,
702 struct e1000e_tx *tx,
703 struct e1000_tx_desc *dp,
704 int queue_index)
705 {
706 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
707 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
708 unsigned int split_size = txd_lower & 0xffff;
709 uint64_t addr;
710 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
711 bool eop = txd_lower & E1000_TXD_CMD_EOP;
712
713 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
714 e1000x_read_tx_ctx_descr(xp, &tx->props);
715 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length));
716 return;
717 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
718 /* data descriptor */
719 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
720 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0;
721 e1000e_process_ts_option(core, dp);
722 } else {
723 /* legacy descriptor */
724 e1000e_process_ts_option(core, dp);
725 tx->cptse = 0;
726 }
727
728 addr = le64_to_cpu(dp->buffer_addr);
729
730 if (!tx->skip_cp) {
731 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, addr, split_size)) {
732 tx->skip_cp = true;
733 }
734 }
735
736 if (eop) {
737 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
738 if (e1000x_vlan_enabled(core->mac) &&
739 e1000x_is_vlan_txd(txd_lower)) {
740 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt,
741 le16_to_cpu(dp->upper.fields.special), core->vet);
742 }
743 if (e1000e_tx_pkt_send(core, tx, queue_index)) {
744 e1000e_on_tx_done_update_stats(core, tx->tx_pkt);
745 }
746 }
747
748 tx->skip_cp = false;
749 net_tx_pkt_reset(tx->tx_pkt);
750
751 tx->sum_needed = 0;
752 tx->cptse = 0;
753 }
754 }
755
756 static inline uint32_t
757 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx)
758 {
759 if (!msix_enabled(core->owner)) {
760 return E1000_ICR_TXDW;
761 }
762
763 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1;
764 }
765
766 static inline uint32_t
767 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx,
768 bool min_threshold_hit)
769 {
770 if (!msix_enabled(core->owner)) {
771 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0);
772 }
773
774 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1;
775 }
776
777 static uint32_t
778 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base,
779 struct e1000_tx_desc *dp, bool *ide, int queue_idx)
780 {
781 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
782
783 if (!(txd_lower & E1000_TXD_CMD_RS) &&
784 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) {
785 return 0;
786 }
787
788 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false;
789
790 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD;
791
792 dp->upper.data = cpu_to_le32(txd_upper);
793 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp),
794 &dp->upper, sizeof(dp->upper));
795 return e1000e_tx_wb_interrupt_cause(core, queue_idx);
796 }
797
798 typedef struct E1000E_RingInfo_st {
799 int dbah;
800 int dbal;
801 int dlen;
802 int dh;
803 int dt;
804 int idx;
805 } E1000E_RingInfo;
806
807 static inline bool
808 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r)
809 {
810 return core->mac[r->dh] == core->mac[r->dt] ||
811 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN;
812 }
813
814 static inline uint64_t
815 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r)
816 {
817 uint64_t bah = core->mac[r->dbah];
818 uint64_t bal = core->mac[r->dbal];
819
820 return (bah << 32) + bal;
821 }
822
823 static inline uint64_t
824 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r)
825 {
826 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh];
827 }
828
829 static inline void
830 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count)
831 {
832 core->mac[r->dh] += count;
833
834 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) {
835 core->mac[r->dh] = 0;
836 }
837 }
838
839 static inline uint32_t
840 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r)
841 {
842 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen],
843 core->mac[r->dh], core->mac[r->dt]);
844
845 if (core->mac[r->dh] <= core->mac[r->dt]) {
846 return core->mac[r->dt] - core->mac[r->dh];
847 }
848
849 if (core->mac[r->dh] > core->mac[r->dt]) {
850 return core->mac[r->dlen] / E1000_RING_DESC_LEN +
851 core->mac[r->dt] - core->mac[r->dh];
852 }
853
854 g_assert_not_reached();
855 return 0;
856 }
857
858 static inline bool
859 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r)
860 {
861 return core->mac[r->dlen] > 0;
862 }
863
864 static inline uint32_t
865 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r)
866 {
867 return core->mac[r->dlen];
868 }
869
870 typedef struct E1000E_TxRing_st {
871 const E1000E_RingInfo *i;
872 struct e1000e_tx *tx;
873 } E1000E_TxRing;
874
875 static inline int
876 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx)
877 {
878 return (reg_idx - base_reg_idx) / (0x100 >> 2);
879 }
880
881 static inline void
882 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx)
883 {
884 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
885 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 },
886 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 }
887 };
888
889 assert(idx < ARRAY_SIZE(i));
890
891 txr->i = &i[idx];
892 txr->tx = &core->tx[idx];
893 }
894
895 typedef struct E1000E_RxRing_st {
896 const E1000E_RingInfo *i;
897 } E1000E_RxRing;
898
899 static inline void
900 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx)
901 {
902 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
903 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 },
904 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 }
905 };
906
907 assert(idx < ARRAY_SIZE(i));
908
909 rxr->i = &i[idx];
910 }
911
912 static void
913 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr)
914 {
915 dma_addr_t base;
916 struct e1000_tx_desc desc;
917 bool ide = false;
918 const E1000E_RingInfo *txi = txr->i;
919 uint32_t cause = E1000_ICS_TXQE;
920
921 if (!(core->mac[TCTL] & E1000_TCTL_EN)) {
922 trace_e1000e_tx_disabled();
923 return;
924 }
925
926 while (!e1000e_ring_empty(core, txi)) {
927 base = e1000e_ring_head_descr(core, txi);
928
929 pci_dma_read(core->owner, base, &desc, sizeof(desc));
930
931 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr,
932 desc.lower.data, desc.upper.data);
933
934 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx);
935 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx);
936
937 e1000e_ring_advance(core, txi, 1);
938 }
939
940 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) {
941 e1000e_set_interrupt_cause(core, cause);
942 }
943 }
944
945 static bool
946 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r,
947 size_t total_size)
948 {
949 uint32_t bufs = e1000e_ring_free_descr_num(core, r);
950
951 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size,
952 core->rx_desc_buf_size);
953
954 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) *
955 core->rx_desc_buf_size;
956 }
957
958 void
959 e1000e_start_recv(E1000ECore *core)
960 {
961 int i;
962
963 trace_e1000e_rx_start_recv();
964
965 for (i = 0; i <= core->max_queue_num; i++) {
966 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i));
967 }
968 }
969
970 int
971 e1000e_can_receive(E1000ECore *core)
972 {
973 int i;
974
975 if (!e1000x_rx_ready(core->owner, core->mac)) {
976 return false;
977 }
978
979 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
980 E1000E_RxRing rxr;
981
982 e1000e_rx_ring_init(core, &rxr, i);
983 if (e1000e_ring_enabled(core, rxr.i) &&
984 e1000e_has_rxbufs(core, rxr.i, 1)) {
985 trace_e1000e_rx_can_recv();
986 return true;
987 }
988 }
989
990 trace_e1000e_rx_can_recv_rings_full();
991 return false;
992 }
993
994 ssize_t
995 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size)
996 {
997 const struct iovec iov = {
998 .iov_base = (uint8_t *)buf,
999 .iov_len = size
1000 };
1001
1002 return e1000e_receive_iov(core, &iov, 1);
1003 }
1004
1005 static inline bool
1006 e1000e_rx_l3_cso_enabled(E1000ECore *core)
1007 {
1008 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD);
1009 }
1010
1011 static inline bool
1012 e1000e_rx_l4_cso_enabled(E1000ECore *core)
1013 {
1014 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
1015 }
1016
1017 static bool
1018 e1000e_receive_filter(E1000ECore *core, const uint8_t *buf, int size)
1019 {
1020 uint32_t rctl = core->mac[RCTL];
1021
1022 if (e1000x_is_vlan_packet(buf, core->vet) &&
1023 e1000x_vlan_rx_filter_enabled(core->mac)) {
1024 uint16_t vid = lduw_be_p(buf + 14);
1025 uint32_t vfta = ldl_le_p((uint32_t *)(core->mac + VFTA) +
1026 ((vid >> 5) & 0x7f));
1027 if ((vfta & (1 << (vid & 0x1f))) == 0) {
1028 trace_e1000e_rx_flt_vlan_mismatch(vid);
1029 return false;
1030 } else {
1031 trace_e1000e_rx_flt_vlan_match(vid);
1032 }
1033 }
1034
1035 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1036 case ETH_PKT_UCAST:
1037 if (rctl & E1000_RCTL_UPE) {
1038 return true; /* promiscuous ucast */
1039 }
1040 break;
1041
1042 case ETH_PKT_BCAST:
1043 if (rctl & E1000_RCTL_BAM) {
1044 return true; /* broadcast enabled */
1045 }
1046 break;
1047
1048 case ETH_PKT_MCAST:
1049 if (rctl & E1000_RCTL_MPE) {
1050 return true; /* promiscuous mcast */
1051 }
1052 break;
1053
1054 default:
1055 g_assert_not_reached();
1056 }
1057
1058 return e1000x_rx_group_filter(core->mac, buf);
1059 }
1060
1061 static inline void
1062 e1000e_read_lgcy_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr)
1063 {
1064 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc;
1065 *buff_addr = le64_to_cpu(d->buffer_addr);
1066 }
1067
1068 static inline void
1069 e1000e_read_ext_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr)
1070 {
1071 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc;
1072 *buff_addr = le64_to_cpu(d->read.buffer_addr);
1073 }
1074
1075 static inline void
1076 e1000e_read_ps_rx_descr(E1000ECore *core, uint8_t *desc,
1077 hwaddr (*buff_addr)[MAX_PS_BUFFERS])
1078 {
1079 int i;
1080 union e1000_rx_desc_packet_split *d =
1081 (union e1000_rx_desc_packet_split *) desc;
1082
1083 for (i = 0; i < MAX_PS_BUFFERS; i++) {
1084 (*buff_addr)[i] = le64_to_cpu(d->read.buffer_addr[i]);
1085 }
1086
1087 trace_e1000e_rx_desc_ps_read((*buff_addr)[0], (*buff_addr)[1],
1088 (*buff_addr)[2], (*buff_addr)[3]);
1089 }
1090
1091 static inline void
1092 e1000e_read_rx_descr(E1000ECore *core, uint8_t *desc,
1093 hwaddr (*buff_addr)[MAX_PS_BUFFERS])
1094 {
1095 if (e1000e_rx_use_legacy_descriptor(core)) {
1096 e1000e_read_lgcy_rx_descr(core, desc, &(*buff_addr)[0]);
1097 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0;
1098 } else {
1099 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1100 e1000e_read_ps_rx_descr(core, desc, buff_addr);
1101 } else {
1102 e1000e_read_ext_rx_descr(core, desc, &(*buff_addr)[0]);
1103 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0;
1104 }
1105 }
1106 }
1107
1108 static void
1109 e1000e_verify_csum_in_sw(E1000ECore *core,
1110 struct NetRxPkt *pkt,
1111 uint32_t *status_flags,
1112 bool istcp, bool isudp)
1113 {
1114 bool csum_valid;
1115 uint32_t csum_error;
1116
1117 if (e1000e_rx_l3_cso_enabled(core)) {
1118 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) {
1119 trace_e1000e_rx_metadata_l3_csum_validation_failed();
1120 } else {
1121 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE;
1122 *status_flags |= E1000_RXD_STAT_IPCS | csum_error;
1123 }
1124 } else {
1125 trace_e1000e_rx_metadata_l3_cso_disabled();
1126 }
1127
1128 if (!e1000e_rx_l4_cso_enabled(core)) {
1129 trace_e1000e_rx_metadata_l4_cso_disabled();
1130 return;
1131 }
1132
1133 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1134 trace_e1000e_rx_metadata_l4_csum_validation_failed();
1135 return;
1136 }
1137
1138 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE;
1139
1140 if (istcp) {
1141 *status_flags |= E1000_RXD_STAT_TCPCS |
1142 csum_error;
1143 } else if (isudp) {
1144 *status_flags |= E1000_RXD_STAT_TCPCS |
1145 E1000_RXD_STAT_UDPCS |
1146 csum_error;
1147 }
1148 }
1149
1150 static inline bool
1151 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt)
1152 {
1153 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) {
1154 return false;
1155 }
1156
1157 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) {
1158 return !net_rx_pkt_has_tcp_data(rx_pkt);
1159 }
1160
1161 return true;
1162 }
1163
1164 static void
1165 e1000e_build_rx_metadata(E1000ECore *core,
1166 struct NetRxPkt *pkt,
1167 bool is_eop,
1168 const E1000E_RSSInfo *rss_info,
1169 uint32_t *rss, uint32_t *mrq,
1170 uint32_t *status_flags,
1171 uint16_t *ip_id,
1172 uint16_t *vlan_tag)
1173 {
1174 struct virtio_net_hdr *vhdr;
1175 bool isip4, isip6, istcp, isudp;
1176 uint32_t pkt_type;
1177
1178 *status_flags = E1000_RXD_STAT_DD;
1179
1180 /* No additional metadata needed for non-EOP descriptors */
1181 if (!is_eop) {
1182 goto func_exit;
1183 }
1184
1185 *status_flags |= E1000_RXD_STAT_EOP;
1186
1187 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
1188 trace_e1000e_rx_metadata_protocols(isip4, isip6, isudp, istcp);
1189
1190 /* VLAN state */
1191 if (net_rx_pkt_is_vlan_stripped(pkt)) {
1192 *status_flags |= E1000_RXD_STAT_VP;
1193 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
1194 trace_e1000e_rx_metadata_vlan(*vlan_tag);
1195 }
1196
1197 /* Packet parsing results */
1198 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) {
1199 if (rss_info->enabled) {
1200 *rss = cpu_to_le32(rss_info->hash);
1201 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8));
1202 trace_e1000e_rx_metadata_rss(*rss, *mrq);
1203 }
1204 } else if (isip4) {
1205 *status_flags |= E1000_RXD_STAT_IPIDV;
1206 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt));
1207 trace_e1000e_rx_metadata_ip_id(*ip_id);
1208 }
1209
1210 if (istcp && e1000e_is_tcp_ack(core, pkt)) {
1211 *status_flags |= E1000_RXD_STAT_ACK;
1212 trace_e1000e_rx_metadata_ack();
1213 }
1214
1215 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) {
1216 trace_e1000e_rx_metadata_ipv6_filtering_disabled();
1217 pkt_type = E1000_RXD_PKT_MAC;
1218 } else if (istcp || isudp) {
1219 pkt_type = isip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP;
1220 } else if (isip4 || isip6) {
1221 pkt_type = isip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6;
1222 } else {
1223 pkt_type = E1000_RXD_PKT_MAC;
1224 }
1225
1226 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type);
1227 trace_e1000e_rx_metadata_pkt_type(pkt_type);
1228
1229 /* RX CSO information */
1230 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
1231 trace_e1000e_rx_metadata_ipv6_sum_disabled();
1232 goto func_exit;
1233 }
1234
1235 if (!net_rx_pkt_has_virt_hdr(pkt)) {
1236 trace_e1000e_rx_metadata_no_virthdr();
1237 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp);
1238 goto func_exit;
1239 }
1240
1241 vhdr = net_rx_pkt_get_vhdr(pkt);
1242
1243 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
1244 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
1245 trace_e1000e_rx_metadata_virthdr_no_csum_info();
1246 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp);
1247 goto func_exit;
1248 }
1249
1250 if (e1000e_rx_l3_cso_enabled(core)) {
1251 *status_flags |= isip4 ? E1000_RXD_STAT_IPCS : 0;
1252 } else {
1253 trace_e1000e_rx_metadata_l3_cso_disabled();
1254 }
1255
1256 if (e1000e_rx_l4_cso_enabled(core)) {
1257 if (istcp) {
1258 *status_flags |= E1000_RXD_STAT_TCPCS;
1259 } else if (isudp) {
1260 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
1261 }
1262 } else {
1263 trace_e1000e_rx_metadata_l4_cso_disabled();
1264 }
1265
1266 trace_e1000e_rx_metadata_status_flags(*status_flags);
1267
1268 func_exit:
1269 *status_flags = cpu_to_le32(*status_flags);
1270 }
1271
1272 static inline void
1273 e1000e_write_lgcy_rx_descr(E1000ECore *core, uint8_t *desc,
1274 struct NetRxPkt *pkt,
1275 const E1000E_RSSInfo *rss_info,
1276 uint16_t length)
1277 {
1278 uint32_t status_flags, rss, mrq;
1279 uint16_t ip_id;
1280
1281 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc;
1282
1283 assert(!rss_info->enabled);
1284
1285 d->length = cpu_to_le16(length);
1286 d->csum = 0;
1287
1288 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1289 rss_info,
1290 &rss, &mrq,
1291 &status_flags, &ip_id,
1292 &d->special);
1293 d->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24);
1294 d->status = (uint8_t) le32_to_cpu(status_flags);
1295 d->special = 0;
1296 }
1297
1298 static inline void
1299 e1000e_write_ext_rx_descr(E1000ECore *core, uint8_t *desc,
1300 struct NetRxPkt *pkt,
1301 const E1000E_RSSInfo *rss_info,
1302 uint16_t length)
1303 {
1304 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc;
1305
1306 memset(&d->wb, 0, sizeof(d->wb));
1307
1308 d->wb.upper.length = cpu_to_le16(length);
1309
1310 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1311 rss_info,
1312 &d->wb.lower.hi_dword.rss,
1313 &d->wb.lower.mrq,
1314 &d->wb.upper.status_error,
1315 &d->wb.lower.hi_dword.csum_ip.ip_id,
1316 &d->wb.upper.vlan);
1317 }
1318
1319 static inline void
1320 e1000e_write_ps_rx_descr(E1000ECore *core, uint8_t *desc,
1321 struct NetRxPkt *pkt,
1322 const E1000E_RSSInfo *rss_info,
1323 size_t ps_hdr_len,
1324 uint16_t(*written)[MAX_PS_BUFFERS])
1325 {
1326 int i;
1327 union e1000_rx_desc_packet_split *d =
1328 (union e1000_rx_desc_packet_split *) desc;
1329
1330 memset(&d->wb, 0, sizeof(d->wb));
1331
1332 d->wb.middle.length0 = cpu_to_le16((*written)[0]);
1333
1334 for (i = 0; i < PS_PAGE_BUFFERS; i++) {
1335 d->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]);
1336 }
1337
1338 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1339 rss_info,
1340 &d->wb.lower.hi_dword.rss,
1341 &d->wb.lower.mrq,
1342 &d->wb.middle.status_error,
1343 &d->wb.lower.hi_dword.csum_ip.ip_id,
1344 &d->wb.middle.vlan);
1345
1346 d->wb.upper.header_status =
1347 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0));
1348
1349 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1],
1350 (*written)[2], (*written)[3]);
1351 }
1352
1353 static inline void
1354 e1000e_write_rx_descr(E1000ECore *core, uint8_t *desc,
1355 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info,
1356 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS])
1357 {
1358 if (e1000e_rx_use_legacy_descriptor(core)) {
1359 assert(ps_hdr_len == 0);
1360 e1000e_write_lgcy_rx_descr(core, desc, pkt, rss_info, (*written)[0]);
1361 } else {
1362 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1363 e1000e_write_ps_rx_descr(core, desc, pkt, rss_info,
1364 ps_hdr_len, written);
1365 } else {
1366 assert(ps_hdr_len == 0);
1367 e1000e_write_ext_rx_descr(core, desc, pkt, rss_info,
1368 (*written)[0]);
1369 }
1370 }
1371 }
1372
1373 typedef struct e1000e_ba_state_st {
1374 uint16_t written[MAX_PS_BUFFERS];
1375 uint8_t cur_idx;
1376 } e1000e_ba_state;
1377
1378 static inline void
1379 e1000e_write_hdr_to_rx_buffers(E1000ECore *core,
1380 hwaddr (*ba)[MAX_PS_BUFFERS],
1381 e1000e_ba_state *bastate,
1382 const char *data,
1383 dma_addr_t data_len)
1384 {
1385 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]);
1386
1387 pci_dma_write(core->owner, (*ba)[0] + bastate->written[0], data, data_len);
1388 bastate->written[0] += data_len;
1389
1390 bastate->cur_idx = 1;
1391 }
1392
1393 static void
1394 e1000e_write_to_rx_buffers(E1000ECore *core,
1395 hwaddr (*ba)[MAX_PS_BUFFERS],
1396 e1000e_ba_state *bastate,
1397 const char *data,
1398 dma_addr_t data_len)
1399 {
1400 while (data_len > 0) {
1401 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx];
1402 uint32_t cur_buf_bytes_left = cur_buf_len -
1403 bastate->written[bastate->cur_idx];
1404 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left);
1405
1406 trace_e1000e_rx_desc_buff_write(bastate->cur_idx,
1407 (*ba)[bastate->cur_idx],
1408 bastate->written[bastate->cur_idx],
1409 data,
1410 bytes_to_write);
1411
1412 pci_dma_write(core->owner,
1413 (*ba)[bastate->cur_idx] + bastate->written[bastate->cur_idx],
1414 data, bytes_to_write);
1415
1416 bastate->written[bastate->cur_idx] += bytes_to_write;
1417 data += bytes_to_write;
1418 data_len -= bytes_to_write;
1419
1420 if (bastate->written[bastate->cur_idx] == cur_buf_len) {
1421 bastate->cur_idx++;
1422 }
1423
1424 assert(bastate->cur_idx < MAX_PS_BUFFERS);
1425 }
1426 }
1427
1428 static void
1429 e1000e_update_rx_stats(E1000ECore *core,
1430 size_t data_size,
1431 size_t data_fcs_size)
1432 {
1433 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size);
1434
1435 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1436 case ETH_PKT_BCAST:
1437 e1000x_inc_reg_if_not_full(core->mac, BPRC);
1438 break;
1439
1440 case ETH_PKT_MCAST:
1441 e1000x_inc_reg_if_not_full(core->mac, MPRC);
1442 break;
1443
1444 default:
1445 break;
1446 }
1447 }
1448
1449 static inline bool
1450 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi)
1451 {
1452 return e1000e_ring_free_descr_num(core, rxi) ==
1453 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift;
1454 }
1455
1456 static bool
1457 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len)
1458 {
1459 bool isip4, isip6, isudp, istcp;
1460 bool fragment;
1461
1462 if (!e1000e_rx_use_ps_descriptor(core)) {
1463 return false;
1464 }
1465
1466 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
1467
1468 if (isip4) {
1469 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
1470 } else if (isip6) {
1471 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment;
1472 } else {
1473 return false;
1474 }
1475
1476 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) {
1477 return false;
1478 }
1479
1480 if (!fragment && (isudp || istcp)) {
1481 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt);
1482 } else {
1483 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt);
1484 }
1485
1486 if ((*hdr_len > core->rxbuf_sizes[0]) ||
1487 (*hdr_len > net_rx_pkt_get_total_len(pkt))) {
1488 return false;
1489 }
1490
1491 return true;
1492 }
1493
1494 static void
1495 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt,
1496 const E1000E_RxRing *rxr,
1497 const E1000E_RSSInfo *rss_info)
1498 {
1499 PCIDevice *d = core->owner;
1500 dma_addr_t base;
1501 uint8_t desc[E1000_MAX_RX_DESC_LEN];
1502 size_t desc_size;
1503 size_t desc_offset = 0;
1504 size_t iov_ofs = 0;
1505
1506 struct iovec *iov = net_rx_pkt_get_iovec(pkt);
1507 size_t size = net_rx_pkt_get_total_len(pkt);
1508 size_t total_size = size + e1000x_fcs_len(core->mac);
1509 const E1000E_RingInfo *rxi;
1510 size_t ps_hdr_len = 0;
1511 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len);
1512 bool is_first = true;
1513
1514 rxi = rxr->i;
1515
1516 do {
1517 hwaddr ba[MAX_PS_BUFFERS];
1518 e1000e_ba_state bastate = { { 0 } };
1519 bool is_last = false;
1520
1521 desc_size = total_size - desc_offset;
1522
1523 if (desc_size > core->rx_desc_buf_size) {
1524 desc_size = core->rx_desc_buf_size;
1525 }
1526
1527 if (e1000e_ring_empty(core, rxi)) {
1528 return;
1529 }
1530
1531 base = e1000e_ring_head_descr(core, rxi);
1532
1533 pci_dma_read(d, base, &desc, core->rx_desc_len);
1534
1535 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len);
1536
1537 e1000e_read_rx_descr(core, desc, &ba);
1538
1539 if (ba[0]) {
1540 if (desc_offset < size) {
1541 static const uint32_t fcs_pad;
1542 size_t iov_copy;
1543 size_t copy_size = size - desc_offset;
1544 if (copy_size > core->rx_desc_buf_size) {
1545 copy_size = core->rx_desc_buf_size;
1546 }
1547
1548 /* For PS mode copy the packet header first */
1549 if (do_ps) {
1550 if (is_first) {
1551 size_t ps_hdr_copied = 0;
1552 do {
1553 iov_copy = MIN(ps_hdr_len - ps_hdr_copied,
1554 iov->iov_len - iov_ofs);
1555
1556 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate,
1557 iov->iov_base, iov_copy);
1558
1559 copy_size -= iov_copy;
1560 ps_hdr_copied += iov_copy;
1561
1562 iov_ofs += iov_copy;
1563 if (iov_ofs == iov->iov_len) {
1564 iov++;
1565 iov_ofs = 0;
1566 }
1567 } while (ps_hdr_copied < ps_hdr_len);
1568
1569 is_first = false;
1570 } else {
1571 /* Leave buffer 0 of each descriptor except first */
1572 /* empty as per spec 7.1.5.1 */
1573 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate,
1574 NULL, 0);
1575 }
1576 }
1577
1578 /* Copy packet payload */
1579 while (copy_size) {
1580 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
1581
1582 e1000e_write_to_rx_buffers(core, &ba, &bastate,
1583 iov->iov_base + iov_ofs, iov_copy);
1584
1585 copy_size -= iov_copy;
1586 iov_ofs += iov_copy;
1587 if (iov_ofs == iov->iov_len) {
1588 iov++;
1589 iov_ofs = 0;
1590 }
1591 }
1592
1593 if (desc_offset + desc_size >= total_size) {
1594 /* Simulate FCS checksum presence in the last descriptor */
1595 e1000e_write_to_rx_buffers(core, &ba, &bastate,
1596 (const char *) &fcs_pad, e1000x_fcs_len(core->mac));
1597 }
1598 }
1599 desc_offset += desc_size;
1600 if (desc_offset >= total_size) {
1601 is_last = true;
1602 }
1603 } else { /* as per intel docs; skip descriptors with null buf addr */
1604 trace_e1000e_rx_null_descriptor();
1605 }
1606
1607 e1000e_write_rx_descr(core, desc, is_last ? core->rx_pkt : NULL,
1608 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written);
1609 pci_dma_write(d, base, &desc, core->rx_desc_len);
1610
1611 e1000e_ring_advance(core, rxi,
1612 core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
1613
1614 } while (desc_offset < total_size);
1615
1616 e1000e_update_rx_stats(core, size, total_size);
1617 }
1618
1619 static inline void
1620 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt)
1621 {
1622 if (net_rx_pkt_has_virt_hdr(pkt)) {
1623 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt);
1624
1625 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
1626 net_rx_pkt_fix_l4_csum(pkt);
1627 }
1628 }
1629 }
1630
1631 ssize_t
1632 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt)
1633 {
1634 static const int maximum_ethernet_hdr_len = (14 + 4);
1635 /* Min. octets in an ethernet frame sans FCS */
1636 static const int min_buf_size = 60;
1637
1638 uint32_t n = 0;
1639 uint8_t min_buf[min_buf_size];
1640 struct iovec min_iov;
1641 uint8_t *filter_buf;
1642 size_t size, orig_size;
1643 size_t iov_ofs = 0;
1644 E1000E_RxRing rxr;
1645 E1000E_RSSInfo rss_info;
1646 size_t total_size;
1647 ssize_t retval;
1648 bool rdmts_hit;
1649
1650 trace_e1000e_rx_receive_iov(iovcnt);
1651
1652 if (!e1000x_hw_rx_enabled(core->mac)) {
1653 return -1;
1654 }
1655
1656 /* Pull virtio header in */
1657 if (core->has_vnet) {
1658 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt);
1659 iov_ofs = sizeof(struct virtio_net_hdr);
1660 }
1661
1662 filter_buf = iov->iov_base + iov_ofs;
1663 orig_size = iov_size(iov, iovcnt);
1664 size = orig_size - iov_ofs;
1665
1666 /* Pad to minimum Ethernet frame length */
1667 if (size < sizeof(min_buf)) {
1668 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size);
1669 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1670 e1000x_inc_reg_if_not_full(core->mac, RUC);
1671 min_iov.iov_base = filter_buf = min_buf;
1672 min_iov.iov_len = size = sizeof(min_buf);
1673 iovcnt = 1;
1674 iov = &min_iov;
1675 iov_ofs = 0;
1676 } else if (iov->iov_len < maximum_ethernet_hdr_len) {
1677 /* This is very unlikely, but may happen. */
1678 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len);
1679 filter_buf = min_buf;
1680 }
1681
1682 /* Discard oversized packets if !LPE and !SBP. */
1683 if (e1000x_is_oversized(core->mac, size)) {
1684 return orig_size;
1685 }
1686
1687 net_rx_pkt_set_packet_type(core->rx_pkt,
1688 get_eth_packet_type(PKT_GET_ETH_HDR(filter_buf)));
1689
1690 if (!e1000e_receive_filter(core, filter_buf, size)) {
1691 trace_e1000e_rx_flt_dropped();
1692 return orig_size;
1693 }
1694
1695 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
1696 e1000x_vlan_enabled(core->mac), core->vet);
1697
1698 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info);
1699 e1000e_rx_ring_init(core, &rxr, rss_info.queue);
1700
1701 trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx);
1702
1703 total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
1704 e1000x_fcs_len(core->mac);
1705
1706 if (e1000e_has_rxbufs(core, rxr.i, total_size)) {
1707 e1000e_rx_fix_l4_csum(core, core->rx_pkt);
1708
1709 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
1710
1711 retval = orig_size;
1712
1713 /* Perform small receive detection (RSRPD) */
1714 if (total_size < core->mac[RSRPD]) {
1715 n |= E1000_ICS_SRPD;
1716 }
1717
1718 /* Perform ACK receive detection */
1719 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) &&
1720 (e1000e_is_tcp_ack(core, core->rx_pkt))) {
1721 n |= E1000_ICS_ACK;
1722 }
1723
1724 /* Check if receive descriptor minimum threshold hit */
1725 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i);
1726 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit);
1727
1728 trace_e1000e_rx_written_to_guest(n);
1729 } else {
1730 n |= E1000_ICS_RXO;
1731 retval = 0;
1732
1733 trace_e1000e_rx_not_written_to_guest(n);
1734 }
1735
1736 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) {
1737 trace_e1000e_rx_interrupt_set(n);
1738 e1000e_set_interrupt_cause(core, n);
1739 } else {
1740 trace_e1000e_rx_interrupt_delayed(n);
1741 }
1742
1743 return retval;
1744 }
1745
1746 static inline bool
1747 e1000e_have_autoneg(E1000ECore *core)
1748 {
1749 return core->phy[0][PHY_CTRL] & MII_CR_AUTO_NEG_EN;
1750 }
1751
1752 static void e1000e_update_flowctl_status(E1000ECore *core)
1753 {
1754 if (e1000e_have_autoneg(core) &&
1755 core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE) {
1756 trace_e1000e_link_autoneg_flowctl(true);
1757 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE;
1758 } else {
1759 trace_e1000e_link_autoneg_flowctl(false);
1760 }
1761 }
1762
1763 static inline void
1764 e1000e_link_down(E1000ECore *core)
1765 {
1766 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1767 e1000e_update_flowctl_status(core);
1768 }
1769
1770 static inline void
1771 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val)
1772 {
1773 /* bits 0-5 reserved; MII_CR_[RESTART_AUTO_NEG,RESET] are self clearing */
1774 core->phy[0][PHY_CTRL] = val & ~(0x3f |
1775 MII_CR_RESET |
1776 MII_CR_RESTART_AUTO_NEG);
1777
1778 if ((val & MII_CR_RESTART_AUTO_NEG) &&
1779 e1000e_have_autoneg(core)) {
1780 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1781 }
1782 }
1783
1784 static void
1785 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val)
1786 {
1787 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10);
1788
1789 if (val & BIT(10)) {
1790 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1791 }
1792 }
1793
1794 static void
1795 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val)
1796 {
1797 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK;
1798 }
1799
1800 void
1801 e1000e_core_set_link_status(E1000ECore *core)
1802 {
1803 NetClientState *nc = qemu_get_queue(core->owner_nic);
1804 uint32_t old_status = core->mac[STATUS];
1805
1806 trace_e1000e_link_status_changed(nc->link_down ? false : true);
1807
1808 if (nc->link_down) {
1809 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1810 } else {
1811 if (e1000e_have_autoneg(core) &&
1812 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
1813 e1000x_restart_autoneg(core->mac, core->phy[0],
1814 core->autoneg_timer);
1815 } else {
1816 e1000x_update_regs_on_link_up(core->mac, core->phy[0]);
1817 e1000e_start_recv(core);
1818 }
1819 }
1820
1821 if (core->mac[STATUS] != old_status) {
1822 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
1823 }
1824 }
1825
1826 static void
1827 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val)
1828 {
1829 trace_e1000e_core_ctrl_write(index, val);
1830
1831 /* RST is self clearing */
1832 core->mac[CTRL] = val & ~E1000_CTRL_RST;
1833 core->mac[CTRL_DUP] = core->mac[CTRL];
1834
1835 trace_e1000e_link_set_params(
1836 !!(val & E1000_CTRL_ASDE),
1837 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1838 !!(val & E1000_CTRL_FRCSPD),
1839 !!(val & E1000_CTRL_FRCDPX),
1840 !!(val & E1000_CTRL_RFCE),
1841 !!(val & E1000_CTRL_TFCE));
1842
1843 if (val & E1000_CTRL_RST) {
1844 trace_e1000e_core_ctrl_sw_reset();
1845 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
1846 }
1847
1848 if (val & E1000_CTRL_PHY_RST) {
1849 trace_e1000e_core_ctrl_phy_reset();
1850 core->mac[STATUS] |= E1000_STATUS_PHYRA;
1851 }
1852 }
1853
1854 static void
1855 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val)
1856 {
1857 trace_e1000e_rx_set_rfctl(val);
1858
1859 if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1860 trace_e1000e_wrn_iscsi_filtering_not_supported();
1861 }
1862
1863 if (!(val & E1000_RFCTL_NFSW_DIS)) {
1864 trace_e1000e_wrn_nfsw_filtering_not_supported();
1865 }
1866
1867 if (!(val & E1000_RFCTL_NFSR_DIS)) {
1868 trace_e1000e_wrn_nfsr_filtering_not_supported();
1869 }
1870
1871 core->mac[RFCTL] = val;
1872 }
1873
1874 static void
1875 e1000e_calc_per_desc_buf_size(E1000ECore *core)
1876 {
1877 int i;
1878 core->rx_desc_buf_size = 0;
1879
1880 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) {
1881 core->rx_desc_buf_size += core->rxbuf_sizes[i];
1882 }
1883 }
1884
1885 static void
1886 e1000e_parse_rxbufsize(E1000ECore *core)
1887 {
1888 uint32_t rctl = core->mac[RCTL];
1889
1890 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes));
1891
1892 if (rctl & E1000_RCTL_DTYP_MASK) {
1893 uint32_t bsize;
1894
1895 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK;
1896 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128;
1897
1898 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK;
1899 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024;
1900
1901 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK;
1902 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024;
1903
1904 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK;
1905 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024;
1906 } else if (rctl & E1000_RCTL_FLXBUF_MASK) {
1907 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK;
1908 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024;
1909 } else {
1910 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl);
1911 }
1912
1913 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1],
1914 core->rxbuf_sizes[2], core->rxbuf_sizes[3]);
1915
1916 e1000e_calc_per_desc_buf_size(core);
1917 }
1918
1919 static void
1920 e1000e_calc_rxdesclen(E1000ECore *core)
1921 {
1922 if (e1000e_rx_use_legacy_descriptor(core)) {
1923 core->rx_desc_len = sizeof(struct e1000_rx_desc);
1924 } else {
1925 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1926 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split);
1927 } else {
1928 core->rx_desc_len = sizeof(union e1000_rx_desc_extended);
1929 }
1930 }
1931 trace_e1000e_rx_desc_len(core->rx_desc_len);
1932 }
1933
1934 static void
1935 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val)
1936 {
1937 core->mac[RCTL] = val;
1938 trace_e1000e_rx_set_rctl(core->mac[RCTL]);
1939
1940 if (val & E1000_RCTL_EN) {
1941 e1000e_parse_rxbufsize(core);
1942 e1000e_calc_rxdesclen(core);
1943 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 +
1944 E1000_RING_DESC_LEN_SHIFT;
1945
1946 e1000e_start_recv(core);
1947 }
1948 }
1949
1950 static
1951 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE])
1952 (E1000ECore *, int, uint16_t) = {
1953 [0] = {
1954 [PHY_CTRL] = e1000e_set_phy_ctrl,
1955 [PHY_PAGE] = e1000e_set_phy_page,
1956 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits
1957 }
1958 };
1959
1960 static inline void
1961 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits)
1962 {
1963 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits);
1964 core->mac[IMS] &= ~bits;
1965 }
1966
1967 static inline bool
1968 e1000e_postpone_interrupt(bool *interrupt_pending,
1969 E1000IntrDelayTimer *timer)
1970 {
1971 if (timer->running) {
1972 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2);
1973
1974 *interrupt_pending = true;
1975 return true;
1976 }
1977
1978 if (timer->core->mac[timer->delay_reg] != 0) {
1979 e1000e_intrmgr_rearm_timer(timer);
1980 }
1981
1982 return false;
1983 }
1984
1985 static inline bool
1986 e1000e_itr_should_postpone(E1000ECore *core)
1987 {
1988 return e1000e_postpone_interrupt(&core->itr_intr_pending, &core->itr);
1989 }
1990
1991 static inline bool
1992 e1000e_eitr_should_postpone(E1000ECore *core, int idx)
1993 {
1994 return e1000e_postpone_interrupt(&core->eitr_intr_pending[idx],
1995 &core->eitr[idx]);
1996 }
1997
1998 static void
1999 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2000 {
2001 uint32_t effective_eiac;
2002
2003 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2004 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2005 if (vec < E1000E_MSIX_VEC_NUM) {
2006 if (!e1000e_eitr_should_postpone(core, vec)) {
2007 trace_e1000e_irq_msix_notify_vec(vec);
2008 msix_notify(core->owner, vec);
2009 }
2010 } else {
2011 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2012 }
2013 } else {
2014 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2015 }
2016
2017 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) {
2018 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause);
2019 core->mac[IAM] &= ~cause;
2020 }
2021
2022 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]);
2023
2024 effective_eiac = core->mac[EIAC] & cause;
2025
2026 core->mac[ICR] &= ~effective_eiac;
2027 core->msi_causes_pending &= ~effective_eiac;
2028
2029 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2030 core->mac[IMS] &= ~effective_eiac;
2031 }
2032 }
2033
2034 static void
2035 e1000e_msix_notify(E1000ECore *core, uint32_t causes)
2036 {
2037 if (causes & E1000_ICR_RXQ0) {
2038 e1000e_msix_notify_one(core, E1000_ICR_RXQ0,
2039 E1000_IVAR_RXQ0(core->mac[IVAR]));
2040 }
2041
2042 if (causes & E1000_ICR_RXQ1) {
2043 e1000e_msix_notify_one(core, E1000_ICR_RXQ1,
2044 E1000_IVAR_RXQ1(core->mac[IVAR]));
2045 }
2046
2047 if (causes & E1000_ICR_TXQ0) {
2048 e1000e_msix_notify_one(core, E1000_ICR_TXQ0,
2049 E1000_IVAR_TXQ0(core->mac[IVAR]));
2050 }
2051
2052 if (causes & E1000_ICR_TXQ1) {
2053 e1000e_msix_notify_one(core, E1000_ICR_TXQ1,
2054 E1000_IVAR_TXQ1(core->mac[IVAR]));
2055 }
2056
2057 if (causes & E1000_ICR_OTHER) {
2058 e1000e_msix_notify_one(core, E1000_ICR_OTHER,
2059 E1000_IVAR_OTHER(core->mac[IVAR]));
2060 }
2061 }
2062
2063 static void
2064 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2065 {
2066 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2067 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2068 if (vec < E1000E_MSIX_VEC_NUM) {
2069 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec);
2070 msix_clr_pending(core->owner, vec);
2071 } else {
2072 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2073 }
2074 } else {
2075 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2076 }
2077 }
2078
2079 static void
2080 e1000e_msix_clear(E1000ECore *core, uint32_t causes)
2081 {
2082 if (causes & E1000_ICR_RXQ0) {
2083 e1000e_msix_clear_one(core, E1000_ICR_RXQ0,
2084 E1000_IVAR_RXQ0(core->mac[IVAR]));
2085 }
2086
2087 if (causes & E1000_ICR_RXQ1) {
2088 e1000e_msix_clear_one(core, E1000_ICR_RXQ1,
2089 E1000_IVAR_RXQ1(core->mac[IVAR]));
2090 }
2091
2092 if (causes & E1000_ICR_TXQ0) {
2093 e1000e_msix_clear_one(core, E1000_ICR_TXQ0,
2094 E1000_IVAR_TXQ0(core->mac[IVAR]));
2095 }
2096
2097 if (causes & E1000_ICR_TXQ1) {
2098 e1000e_msix_clear_one(core, E1000_ICR_TXQ1,
2099 E1000_IVAR_TXQ1(core->mac[IVAR]));
2100 }
2101
2102 if (causes & E1000_ICR_OTHER) {
2103 e1000e_msix_clear_one(core, E1000_ICR_OTHER,
2104 E1000_IVAR_OTHER(core->mac[IVAR]));
2105 }
2106 }
2107
2108 static inline void
2109 e1000e_fix_icr_asserted(E1000ECore *core)
2110 {
2111 core->mac[ICR] &= ~E1000_ICR_ASSERTED;
2112 if (core->mac[ICR]) {
2113 core->mac[ICR] |= E1000_ICR_ASSERTED;
2114 }
2115
2116 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
2117 }
2118
2119 static void
2120 e1000e_send_msi(E1000ECore *core, bool msix)
2121 {
2122 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED;
2123
2124 core->msi_causes_pending &= causes;
2125 causes ^= core->msi_causes_pending;
2126 if (causes == 0) {
2127 return;
2128 }
2129 core->msi_causes_pending |= causes;
2130
2131 if (msix) {
2132 e1000e_msix_notify(core, causes);
2133 } else {
2134 if (!e1000e_itr_should_postpone(core)) {
2135 trace_e1000e_irq_msi_notify(causes);
2136 msi_notify(core->owner, 0);
2137 }
2138 }
2139 }
2140
2141 static void
2142 e1000e_update_interrupt_state(E1000ECore *core)
2143 {
2144 bool interrupts_pending;
2145 bool is_msix = msix_enabled(core->owner);
2146
2147 /* Set ICR[OTHER] for MSI-X */
2148 if (is_msix) {
2149 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) {
2150 core->mac[ICR] |= E1000_ICR_OTHER;
2151 trace_e1000e_irq_add_msi_other(core->mac[ICR]);
2152 }
2153 }
2154
2155 e1000e_fix_icr_asserted(core);
2156
2157 /*
2158 * Make sure ICR and ICS registers have the same value.
2159 * The spec says that the ICS register is write-only. However in practice,
2160 * on real hardware ICS is readable, and for reads it has the same value as
2161 * ICR (except that ICS does not have the clear on read behaviour of ICR).
2162 *
2163 * The VxWorks PRO/1000 driver uses this behaviour.
2164 */
2165 core->mac[ICS] = core->mac[ICR];
2166
2167 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false;
2168 if (!interrupts_pending) {
2169 core->msi_causes_pending = 0;
2170 }
2171
2172 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
2173 core->mac[ICR], core->mac[IMS]);
2174
2175 if (is_msix || msi_enabled(core->owner)) {
2176 if (interrupts_pending) {
2177 e1000e_send_msi(core, is_msix);
2178 }
2179 } else {
2180 if (interrupts_pending) {
2181 if (!e1000e_itr_should_postpone(core)) {
2182 e1000e_raise_legacy_irq(core);
2183 }
2184 } else {
2185 e1000e_lower_legacy_irq(core);
2186 }
2187 }
2188 }
2189
2190 static void
2191 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val)
2192 {
2193 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]);
2194
2195 val |= e1000e_intmgr_collect_delayed_causes(core);
2196 core->mac[ICR] |= val;
2197
2198 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]);
2199
2200 e1000e_update_interrupt_state(core);
2201 }
2202
2203 static inline void
2204 e1000e_autoneg_timer(void *opaque)
2205 {
2206 E1000ECore *core = opaque;
2207 if (!qemu_get_queue(core->owner_nic)->link_down) {
2208 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]);
2209 e1000e_start_recv(core);
2210
2211 e1000e_update_flowctl_status(core);
2212 /* signal link status change to the guest */
2213 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
2214 }
2215 }
2216
2217 static inline uint16_t
2218 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)
2219 {
2220 uint16_t index = (addr & 0x1ffff) >> 2;
2221 return index + (mac_reg_access[index] & 0xfffe);
2222 }
2223
2224 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = {
2225 [0] = {
2226 [PHY_CTRL] = PHY_ANYPAGE | PHY_RW,
2227 [PHY_STATUS] = PHY_ANYPAGE | PHY_R,
2228 [PHY_ID1] = PHY_ANYPAGE | PHY_R,
2229 [PHY_ID2] = PHY_ANYPAGE | PHY_R,
2230 [PHY_AUTONEG_ADV] = PHY_ANYPAGE | PHY_RW,
2231 [PHY_LP_ABILITY] = PHY_ANYPAGE | PHY_R,
2232 [PHY_AUTONEG_EXP] = PHY_ANYPAGE | PHY_R,
2233 [PHY_NEXT_PAGE_TX] = PHY_ANYPAGE | PHY_RW,
2234 [PHY_LP_NEXT_PAGE] = PHY_ANYPAGE | PHY_R,
2235 [PHY_1000T_CTRL] = PHY_ANYPAGE | PHY_RW,
2236 [PHY_1000T_STATUS] = PHY_ANYPAGE | PHY_R,
2237 [PHY_EXT_STATUS] = PHY_ANYPAGE | PHY_R,
2238 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW,
2239
2240 [PHY_COPPER_CTRL1] = PHY_RW,
2241 [PHY_COPPER_STAT1] = PHY_R,
2242 [PHY_COPPER_CTRL3] = PHY_RW,
2243 [PHY_RX_ERR_CNTR] = PHY_R,
2244 [PHY_OEM_BITS] = PHY_RW,
2245 [PHY_BIAS_1] = PHY_RW,
2246 [PHY_BIAS_2] = PHY_RW,
2247 [PHY_COPPER_INT_ENABLE] = PHY_RW,
2248 [PHY_COPPER_STAT2] = PHY_R,
2249 [PHY_COPPER_CTRL2] = PHY_RW
2250 },
2251 [2] = {
2252 [PHY_MAC_CTRL1] = PHY_RW,
2253 [PHY_MAC_INT_ENABLE] = PHY_RW,
2254 [PHY_MAC_STAT] = PHY_R,
2255 [PHY_MAC_CTRL2] = PHY_RW
2256 },
2257 [3] = {
2258 [PHY_LED_03_FUNC_CTRL1] = PHY_RW,
2259 [PHY_LED_03_POL_CTRL] = PHY_RW,
2260 [PHY_LED_TIMER_CTRL] = PHY_RW,
2261 [PHY_LED_45_CTRL] = PHY_RW
2262 },
2263 [5] = {
2264 [PHY_1000T_SKEW] = PHY_R,
2265 [PHY_1000T_SWAP] = PHY_R
2266 },
2267 [6] = {
2268 [PHY_CRC_COUNTERS] = PHY_R
2269 }
2270 };
2271
2272 static bool
2273 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr,
2274 char cap, uint8_t *page)
2275 {
2276 *page =
2277 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0
2278 : core->phy[0][PHY_PAGE];
2279
2280 if (*page >= E1000E_PHY_PAGES) {
2281 return false;
2282 }
2283
2284 return e1000e_phy_regcap[*page][addr] & cap;
2285 }
2286
2287 static void
2288 e1000e_phy_reg_write(E1000ECore *core, uint8_t page,
2289 uint32_t addr, uint16_t data)
2290 {
2291 assert(page < E1000E_PHY_PAGES);
2292 assert(addr < E1000E_PHY_PAGE_SIZE);
2293
2294 if (e1000e_phyreg_writeops[page][addr]) {
2295 e1000e_phyreg_writeops[page][addr](core, addr, data);
2296 } else {
2297 core->phy[page][addr] = data;
2298 }
2299 }
2300
2301 static void
2302 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val)
2303 {
2304 uint32_t data = val & E1000_MDIC_DATA_MASK;
2305 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2306 uint8_t page;
2307
2308 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2309 val = core->mac[MDIC] | E1000_MDIC_ERROR;
2310 } else if (val & E1000_MDIC_OP_READ) {
2311 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) {
2312 trace_e1000e_core_mdic_read_unhandled(page, addr);
2313 val |= E1000_MDIC_ERROR;
2314 } else {
2315 val = (val ^ data) | core->phy[page][addr];
2316 trace_e1000e_core_mdic_read(page, addr, val);
2317 }
2318 } else if (val & E1000_MDIC_OP_WRITE) {
2319 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) {
2320 trace_e1000e_core_mdic_write_unhandled(page, addr);
2321 val |= E1000_MDIC_ERROR;
2322 } else {
2323 trace_e1000e_core_mdic_write(page, addr, data);
2324 e1000e_phy_reg_write(core, page, addr, data);
2325 }
2326 }
2327 core->mac[MDIC] = val | E1000_MDIC_READY;
2328
2329 if (val & E1000_MDIC_INT_EN) {
2330 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC);
2331 }
2332 }
2333
2334 static void
2335 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val)
2336 {
2337 core->mac[index] = val & 0xffff;
2338 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val);
2339 e1000e_start_recv(core);
2340 }
2341
2342 static void
2343 e1000e_set_status(E1000ECore *core, int index, uint32_t val)
2344 {
2345 if ((val & E1000_STATUS_PHYRA) == 0) {
2346 core->mac[index] &= ~E1000_STATUS_PHYRA;
2347 }
2348 }
2349
2350 static void
2351 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val)
2352 {
2353 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2354 !!(val & E1000_CTRL_EXT_SPD_BYPS));
2355
2356 /* Zero self-clearing bits */
2357 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
2358 core->mac[CTRL_EXT] = val;
2359 }
2360
2361 static void
2362 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val)
2363 {
2364 int i;
2365
2366 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2367
2368 if (!msix_enabled(core->owner)) {
2369 return;
2370 }
2371
2372 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
2373 if (core->mac[PBACLR] & BIT(i)) {
2374 msix_clr_pending(core->owner, i);
2375 }
2376 }
2377 }
2378
2379 static void
2380 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val)
2381 {
2382 core->mac[FCRTH] = val & 0xFFF8;
2383 }
2384
2385 static void
2386 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val)
2387 {
2388 core->mac[FCRTL] = val & 0x8000FFF8;
2389 }
2390
2391 static inline void
2392 e1000e_set_16bit(E1000ECore *core, int index, uint32_t val)
2393 {
2394 core->mac[index] = val & 0xffff;
2395 }
2396
2397 static void
2398 e1000e_set_12bit(E1000ECore *core, int index, uint32_t val)
2399 {
2400 core->mac[index] = val & 0xfff;
2401 }
2402
2403 static void
2404 e1000e_set_vet(E1000ECore *core, int index, uint32_t val)
2405 {
2406 core->mac[VET] = val & 0xffff;
2407 core->vet = le16_to_cpu(core->mac[VET]);
2408 trace_e1000e_vlan_vet(core->vet);
2409 }
2410
2411 static void
2412 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val)
2413 {
2414 core->mac[index] = val & E1000_XDLEN_MASK;
2415 }
2416
2417 static void
2418 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val)
2419 {
2420 core->mac[index] = val & E1000_XDBAL_MASK;
2421 }
2422
2423 static void
2424 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val)
2425 {
2426 E1000E_TxRing txr;
2427 core->mac[index] = val;
2428
2429 if (core->mac[TARC0] & E1000_TARC_ENABLE) {
2430 e1000e_tx_ring_init(core, &txr, 0);
2431 e1000e_start_xmit(core, &txr);
2432 }
2433
2434 if (core->mac[TARC1] & E1000_TARC_ENABLE) {
2435 e1000e_tx_ring_init(core, &txr, 1);
2436 e1000e_start_xmit(core, &txr);
2437 }
2438 }
2439
2440 static void
2441 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val)
2442 {
2443 E1000E_TxRing txr;
2444 int qidx = e1000e_mq_queue_idx(TDT, index);
2445 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1;
2446
2447 core->mac[index] = val & 0xffff;
2448
2449 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) {
2450 e1000e_tx_ring_init(core, &txr, qidx);
2451 e1000e_start_xmit(core, &txr);
2452 }
2453 }
2454
2455 static void
2456 e1000e_set_ics(E1000ECore *core, int index, uint32_t val)
2457 {
2458 trace_e1000e_irq_write_ics(val);
2459 e1000e_set_interrupt_cause(core, val);
2460 }
2461
2462 static void
2463 e1000e_set_icr(E1000ECore *core, int index, uint32_t val)
2464 {
2465 uint32_t icr = 0;
2466 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2467 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2468 trace_e1000e_irq_icr_process_iame();
2469 e1000e_clear_ims_bits(core, core->mac[IAM]);
2470 }
2471
2472 icr = core->mac[ICR] & ~val;
2473 /* Windows driver expects that the "receive overrun" bit and other
2474 * ones to be cleared when the "Other" bit (#24) is cleared.
2475 */
2476 icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr;
2477 trace_e1000e_irq_icr_write(val, core->mac[ICR], icr);
2478 core->mac[ICR] = icr;
2479 e1000e_update_interrupt_state(core);
2480 }
2481
2482 static void
2483 e1000e_set_imc(E1000ECore *core, int index, uint32_t val)
2484 {
2485 trace_e1000e_irq_ims_clear_set_imc(val);
2486 e1000e_clear_ims_bits(core, val);
2487 e1000e_update_interrupt_state(core);
2488 }
2489
2490 static void
2491 e1000e_set_ims(E1000ECore *core, int index, uint32_t val)
2492 {
2493 static const uint32_t ims_ext_mask =
2494 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 |
2495 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2496 E1000_IMS_OTHER;
2497
2498 static const uint32_t ims_valid_mask =
2499 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC |
2500 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 |
2501 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD |
2502 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 |
2503 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2504 E1000_IMS_OTHER;
2505
2506 uint32_t valid_val = val & ims_valid_mask;
2507
2508 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val);
2509 core->mac[IMS] |= valid_val;
2510
2511 if ((valid_val & ims_ext_mask) &&
2512 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) &&
2513 msix_enabled(core->owner)) {
2514 e1000e_msix_clear(core, valid_val);
2515 }
2516
2517 if ((valid_val == ims_valid_mask) &&
2518 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) {
2519 trace_e1000e_irq_fire_all_timers(val);
2520 e1000e_intrmgr_fire_all_timers(core);
2521 }
2522
2523 e1000e_update_interrupt_state(core);
2524 }
2525
2526 static void
2527 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val)
2528 {
2529 e1000e_set_16bit(core, index, val);
2530
2531 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) {
2532 trace_e1000e_irq_rdtr_fpd_running();
2533 e1000e_intrmgr_fire_delayed_interrupts(core);
2534 } else {
2535 trace_e1000e_irq_rdtr_fpd_not_running();
2536 }
2537 }
2538
2539 static void
2540 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val)
2541 {
2542 e1000e_set_16bit(core, index, val);
2543
2544 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) {
2545 trace_e1000e_irq_tidv_fpd_running();
2546 e1000e_intrmgr_fire_delayed_interrupts(core);
2547 } else {
2548 trace_e1000e_irq_tidv_fpd_not_running();
2549 }
2550 }
2551
2552 static uint32_t
2553 e1000e_mac_readreg(E1000ECore *core, int index)
2554 {
2555 return core->mac[index];
2556 }
2557
2558 static uint32_t
2559 e1000e_mac_ics_read(E1000ECore *core, int index)
2560 {
2561 trace_e1000e_irq_read_ics(core->mac[ICS]);
2562 return core->mac[ICS];
2563 }
2564
2565 static uint32_t
2566 e1000e_mac_ims_read(E1000ECore *core, int index)
2567 {
2568 trace_e1000e_irq_read_ims(core->mac[IMS]);
2569 return core->mac[IMS];
2570 }
2571
2572 #define E1000E_LOW_BITS_READ_FUNC(num) \
2573 static uint32_t \
2574 e1000e_mac_low##num##_read(E1000ECore *core, int index) \
2575 { \
2576 return core->mac[index] & (BIT(num) - 1); \
2577 } \
2578
2579 #define E1000E_LOW_BITS_READ(num) \
2580 e1000e_mac_low##num##_read
2581
2582 E1000E_LOW_BITS_READ_FUNC(4);
2583 E1000E_LOW_BITS_READ_FUNC(6);
2584 E1000E_LOW_BITS_READ_FUNC(11);
2585 E1000E_LOW_BITS_READ_FUNC(13);
2586 E1000E_LOW_BITS_READ_FUNC(16);
2587
2588 static uint32_t
2589 e1000e_mac_swsm_read(E1000ECore *core, int index)
2590 {
2591 uint32_t val = core->mac[SWSM];
2592 core->mac[SWSM] = val | 1;
2593 return val;
2594 }
2595
2596 static uint32_t
2597 e1000e_mac_itr_read(E1000ECore *core, int index)
2598 {
2599 return core->itr_guest_value;
2600 }
2601
2602 static uint32_t
2603 e1000e_mac_eitr_read(E1000ECore *core, int index)
2604 {
2605 return core->eitr_guest_value[index - EITR];
2606 }
2607
2608 static uint32_t
2609 e1000e_mac_icr_read(E1000ECore *core, int index)
2610 {
2611 uint32_t ret = core->mac[ICR];
2612 trace_e1000e_irq_icr_read_entry(ret);
2613
2614 if (core->mac[IMS] == 0) {
2615 trace_e1000e_irq_icr_clear_zero_ims();
2616 core->mac[ICR] = 0;
2617 }
2618
2619 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2620 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2621 trace_e1000e_irq_icr_clear_iame();
2622 core->mac[ICR] = 0;
2623 trace_e1000e_irq_icr_process_iame();
2624 e1000e_clear_ims_bits(core, core->mac[IAM]);
2625 }
2626
2627 trace_e1000e_irq_icr_read_exit(core->mac[ICR]);
2628 e1000e_update_interrupt_state(core);
2629 return ret;
2630 }
2631
2632 static uint32_t
2633 e1000e_mac_read_clr4(E1000ECore *core, int index)
2634 {
2635 uint32_t ret = core->mac[index];
2636
2637 core->mac[index] = 0;
2638 return ret;
2639 }
2640
2641 static uint32_t
2642 e1000e_mac_read_clr8(E1000ECore *core, int index)
2643 {
2644 uint32_t ret = core->mac[index];
2645
2646 core->mac[index] = 0;
2647 core->mac[index - 1] = 0;
2648 return ret;
2649 }
2650
2651 static uint32_t
2652 e1000e_get_ctrl(E1000ECore *core, int index)
2653 {
2654 uint32_t val = core->mac[CTRL];
2655
2656 trace_e1000e_link_read_params(
2657 !!(val & E1000_CTRL_ASDE),
2658 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2659 !!(val & E1000_CTRL_FRCSPD),
2660 !!(val & E1000_CTRL_FRCDPX),
2661 !!(val & E1000_CTRL_RFCE),
2662 !!(val & E1000_CTRL_TFCE));
2663
2664 return val;
2665 }
2666
2667 static uint32_t
2668 e1000e_get_status(E1000ECore *core, int index)
2669 {
2670 uint32_t res = core->mac[STATUS];
2671
2672 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) {
2673 res |= E1000_STATUS_GIO_MASTER_ENABLE;
2674 }
2675
2676 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) {
2677 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0;
2678 } else {
2679 res |= E1000_STATUS_FD;
2680 }
2681
2682 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) ||
2683 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) {
2684 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) {
2685 case E1000_CTRL_SPD_10:
2686 res |= E1000_STATUS_SPEED_10;
2687 break;
2688 case E1000_CTRL_SPD_100:
2689 res |= E1000_STATUS_SPEED_100;
2690 break;
2691 case E1000_CTRL_SPD_1000:
2692 default:
2693 res |= E1000_STATUS_SPEED_1000;
2694 break;
2695 }
2696 } else {
2697 res |= E1000_STATUS_SPEED_1000;
2698 }
2699
2700 trace_e1000e_link_status(
2701 !!(res & E1000_STATUS_LU),
2702 !!(res & E1000_STATUS_FD),
2703 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT,
2704 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT);
2705
2706 return res;
2707 }
2708
2709 static uint32_t
2710 e1000e_get_tarc(E1000ECore *core, int index)
2711 {
2712 return core->mac[index] & ((BIT(11) - 1) |
2713 BIT(27) |
2714 BIT(28) |
2715 BIT(29) |
2716 BIT(30));
2717 }
2718
2719 static void
2720 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val)
2721 {
2722 core->mac[index] = val;
2723 }
2724
2725 static void
2726 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val)
2727 {
2728 uint32_t macaddr[2];
2729
2730 core->mac[index] = val;
2731
2732 macaddr[0] = cpu_to_le32(core->mac[RA]);
2733 macaddr[1] = cpu_to_le32(core->mac[RA + 1]);
2734 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic),
2735 (uint8_t *) macaddr);
2736
2737 trace_e1000e_mac_set_sw(MAC_ARG(macaddr));
2738 }
2739
2740 static void
2741 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val)
2742 {
2743 static const uint32_t ro_bits = E1000_EECD_PRES |
2744 E1000_EECD_AUTO_RD |
2745 E1000_EECD_SIZE_EX_MASK;
2746
2747 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);
2748 }
2749
2750 static void
2751 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val)
2752 {
2753 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2754 uint32_t flags = 0;
2755 uint32_t data = 0;
2756
2757 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2758 data = core->eeprom[addr];
2759 flags = E1000_EERW_DONE;
2760 }
2761
2762 core->mac[EERD] = flags |
2763 (addr << E1000_EERW_ADDR_SHIFT) |
2764 (data << E1000_EERW_DATA_SHIFT);
2765 }
2766
2767 static void
2768 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val)
2769 {
2770 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2771 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK;
2772 uint32_t flags = 0;
2773
2774 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2775 core->eeprom[addr] = data;
2776 flags = E1000_EERW_DONE;
2777 }
2778
2779 core->mac[EERD] = flags |
2780 (addr << E1000_EERW_ADDR_SHIFT) |
2781 (data << E1000_EERW_DATA_SHIFT);
2782 }
2783
2784 static void
2785 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val)
2786 {
2787 core->mac[RXDCTL] = core->mac[RXDCTL1] = val;
2788 }
2789
2790 static void
2791 e1000e_set_itr(E1000ECore *core, int index, uint32_t val)
2792 {
2793 uint32_t interval = val & 0xffff;
2794
2795 trace_e1000e_irq_itr_set(val);
2796
2797 core->itr_guest_value = interval;
2798 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2799 }
2800
2801 static void
2802 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val)
2803 {
2804 uint32_t interval = val & 0xffff;
2805 uint32_t eitr_num = index - EITR;
2806
2807 trace_e1000e_irq_eitr_set(eitr_num, val);
2808
2809 core->eitr_guest_value[eitr_num] = interval;
2810 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2811 }
2812
2813 static void
2814 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val)
2815 {
2816 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) {
2817 hw_error("e1000e: PSRCTL.BSIZE0 cannot be zero");
2818 }
2819
2820 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) {
2821 hw_error("e1000e: PSRCTL.BSIZE1 cannot be zero");
2822 }
2823
2824 core->mac[PSRCTL] = val;
2825 }
2826
2827 static void
2828 e1000e_update_rx_offloads(E1000ECore *core)
2829 {
2830 int cso_state = e1000e_rx_l4_cso_enabled(core);
2831
2832 trace_e1000e_rx_set_cso(cso_state);
2833
2834 if (core->has_vnet) {
2835 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer,
2836 cso_state, 0, 0, 0, 0);
2837 }
2838 }
2839
2840 static void
2841 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val)
2842 {
2843 core->mac[RXCSUM] = val;
2844 e1000e_update_rx_offloads(core);
2845 }
2846
2847 static void
2848 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val)
2849 {
2850 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS;
2851 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits;
2852 }
2853
2854 #define e1000e_getreg(x) [x] = e1000e_mac_readreg
2855 static uint32_t (*e1000e_macreg_readops[])(E1000ECore *, int) = {
2856 e1000e_getreg(PBA),
2857 e1000e_getreg(WUFC),
2858 e1000e_getreg(MANC),
2859 e1000e_getreg(TOTL),
2860 e1000e_getreg(RDT0),
2861 e1000e_getreg(RDBAH0),
2862 e1000e_getreg(TDBAL1),
2863 e1000e_getreg(RDLEN0),
2864 e1000e_getreg(RDH1),
2865 e1000e_getreg(LATECOL),
2866 e1000e_getreg(SEQEC),
2867 e1000e_getreg(XONTXC),
2868 e1000e_getreg(WUS),
2869 e1000e_getreg(GORCL),
2870 e1000e_getreg(MGTPRC),
2871 e1000e_getreg(EERD),
2872 e1000e_getreg(EIAC),
2873 e1000e_getreg(PSRCTL),
2874 e1000e_getreg(MANC2H),
2875 e1000e_getreg(RXCSUM),
2876 e1000e_getreg(GSCL_3),
2877 e1000e_getreg(GSCN_2),
2878 e1000e_getreg(RSRPD),
2879 e1000e_getreg(RDBAL1),
2880 e1000e_getreg(FCAH),
2881 e1000e_getreg(FCRTH),
2882 e1000e_getreg(FLOP),
2883 e1000e_getreg(FLASHT),
2884 e1000e_getreg(RXSTMPH),
2885 e1000e_getreg(TXSTMPL),
2886 e1000e_getreg(TIMADJL),
2887 e1000e_getreg(TXDCTL),
2888 e1000e_getreg(RDH0),
2889 e1000e_getreg(TDT1),
2890 e1000e_getreg(TNCRS),
2891 e1000e_getreg(RJC),
2892 e1000e_getreg(IAM),
2893 e1000e_getreg(GSCL_2),
2894 e1000e_getreg(RDBAH1),
2895 e1000e_getreg(FLSWDATA),
2896 e1000e_getreg(RXSATRH),
2897 e1000e_getreg(TIPG),
2898 e1000e_getreg(FLMNGCTL),
2899 e1000e_getreg(FLMNGCNT),
2900 e1000e_getreg(TSYNCTXCTL),
2901 e1000e_getreg(EXTCNF_SIZE),
2902 e1000e_getreg(EXTCNF_CTRL),
2903 e1000e_getreg(EEMNGDATA),
2904 e1000e_getreg(CTRL_EXT),
2905 e1000e_getreg(SYSTIMH),
2906 e1000e_getreg(EEMNGCTL),
2907 e1000e_getreg(FLMNGDATA),
2908 e1000e_getreg(TSYNCRXCTL),
2909 e1000e_getreg(TDH),
2910 e1000e_getreg(LEDCTL),
2911 e1000e_getreg(STATUS),
2912 e1000e_getreg(TCTL),
2913 e1000e_getreg(TDBAL),
2914 e1000e_getreg(TDLEN),
2915 e1000e_getreg(TDH1),
2916 e1000e_getreg(RADV),
2917 e1000e_getreg(ECOL),
2918 e1000e_getreg(DC),
2919 e1000e_getreg(RLEC),
2920 e1000e_getreg(XOFFTXC),
2921 e1000e_getreg(RFC),
2922 e1000e_getreg(RNBC),
2923 e1000e_getreg(MGTPTC),
2924 e1000e_getreg(TIMINCA),
2925 e1000e_getreg(RXCFGL),
2926 e1000e_getreg(MFUTP01),
2927 e1000e_getreg(FACTPS),
2928 e1000e_getreg(GSCL_1),
2929 e1000e_getreg(GSCN_0),
2930 e1000e_getreg(GCR2),
2931 e1000e_getreg(RDT1),
2932 e1000e_getreg(PBACLR),
2933 e1000e_getreg(FCTTV),
2934 e1000e_getreg(EEWR),
2935 e1000e_getreg(FLSWCTL),
2936 e1000e_getreg(RXDCTL1),
2937 e1000e_getreg(RXSATRL),
2938 e1000e_getreg(SYSTIML),
2939 e1000e_getreg(RXUDP),
2940 e1000e_getreg(TORL),
2941 e1000e_getreg(TDLEN1),
2942 e1000e_getreg(MCC),
2943 e1000e_getreg(WUC),
2944 e1000e_getreg(EECD),
2945 e1000e_getreg(MFUTP23),
2946 e1000e_getreg(RAID),
2947 e1000e_getreg(FCRTV),
2948 e1000e_getreg(TXDCTL1),
2949 e1000e_getreg(RCTL),
2950 e1000e_getreg(TDT),
2951 e1000e_getreg(MDIC),
2952 e1000e_getreg(FCRUC),
2953 e1000e_getreg(VET),
2954 e1000e_getreg(RDBAL0),
2955 e1000e_getreg(TDBAH1),
2956 e1000e_getreg(RDTR),
2957 e1000e_getreg(SCC),
2958 e1000e_getreg(COLC),
2959 e1000e_getreg(CEXTERR),
2960 e1000e_getreg(XOFFRXC),
2961 e1000e_getreg(IPAV),
2962 e1000e_getreg(GOTCL),
2963 e1000e_getreg(MGTPDC),
2964 e1000e_getreg(GCR),
2965 e1000e_getreg(IVAR),
2966 e1000e_getreg(POEMB),
2967 e1000e_getreg(MFVAL),
2968 e1000e_getreg(FUNCTAG),
2969 e1000e_getreg(GSCL_4),
2970 e1000e_getreg(GSCN_3),
2971 e1000e_getreg(MRQC),
2972 e1000e_getreg(RDLEN1),
2973 e1000e_getreg(FCT),
2974 e1000e_getreg(FLA),
2975 e1000e_getreg(FLOL),
2976 e1000e_getreg(RXDCTL),
2977 e1000e_getreg(RXSTMPL),
2978 e1000e_getreg(TXSTMPH),
2979 e1000e_getreg(TIMADJH),
2980 e1000e_getreg(FCRTL),
2981 e1000e_getreg(TDBAH),
2982 e1000e_getreg(TADV),
2983 e1000e_getreg(XONRXC),
2984 e1000e_getreg(TSCTFC),
2985 e1000e_getreg(RFCTL),
2986 e1000e_getreg(GSCN_1),
2987 e1000e_getreg(FCAL),
2988 e1000e_getreg(FLSWCNT),
2989
2990 [TOTH] = e1000e_mac_read_clr8,
2991 [GOTCH] = e1000e_mac_read_clr8,
2992 [PRC64] = e1000e_mac_read_clr4,
2993 [PRC255] = e1000e_mac_read_clr4,
2994 [PRC1023] = e1000e_mac_read_clr4,
2995 [PTC64] = e1000e_mac_read_clr4,
2996 [PTC255] = e1000e_mac_read_clr4,
2997 [PTC1023] = e1000e_mac_read_clr4,
2998 [GPRC] = e1000e_mac_read_clr4,
2999 [TPT] = e1000e_mac_read_clr4,
3000 [RUC] = e1000e_mac_read_clr4,
3001 [BPRC] = e1000e_mac_read_clr4,
3002 [MPTC] = e1000e_mac_read_clr4,
3003 [IAC] = e1000e_mac_read_clr4,
3004 [ICR] = e1000e_mac_icr_read,
3005 [RDFH] = E1000E_LOW_BITS_READ(13),
3006 [RDFHS] = E1000E_LOW_BITS_READ(13),
3007 [RDFPC] = E1000E_LOW_BITS_READ(13),
3008 [TDFH] = E1000E_LOW_BITS_READ(13),
3009 [TDFHS] = E1000E_LOW_BITS_READ(13),
3010 [STATUS] = e1000e_get_status,
3011 [TARC0] = e1000e_get_tarc,
3012 [PBS] = E1000E_LOW_BITS_READ(6),
3013 [ICS] = e1000e_mac_ics_read,
3014 [AIT] = E1000E_LOW_BITS_READ(16),
3015 [TORH] = e1000e_mac_read_clr8,
3016 [GORCH] = e1000e_mac_read_clr8,
3017 [PRC127] = e1000e_mac_read_clr4,
3018 [PRC511] = e1000e_mac_read_clr4,
3019 [PRC1522] = e1000e_mac_read_clr4,
3020 [PTC127] = e1000e_mac_read_clr4,
3021 [PTC511] = e1000e_mac_read_clr4,
3022 [PTC1522] = e1000e_mac_read_clr4,
3023 [GPTC] = e1000e_mac_read_clr4,
3024 [TPR] = e1000e_mac_read_clr4,
3025 [ROC] = e1000e_mac_read_clr4,
3026 [MPRC] = e1000e_mac_read_clr4,
3027 [BPTC] = e1000e_mac_read_clr4,
3028 [TSCTC] = e1000e_mac_read_clr4,
3029 [ITR] = e1000e_mac_itr_read,
3030 [RDFT] = E1000E_LOW_BITS_READ(13),
3031 [RDFTS] = E1000E_LOW_BITS_READ(13),
3032 [TDFPC] = E1000E_LOW_BITS_READ(13),
3033 [TDFT] = E1000E_LOW_BITS_READ(13),
3034 [TDFTS] = E1000E_LOW_BITS_READ(13),
3035 [CTRL] = e1000e_get_ctrl,
3036 [TARC1] = e1000e_get_tarc,
3037 [SWSM] = e1000e_mac_swsm_read,
3038 [IMS] = e1000e_mac_ims_read,
3039
3040 [CRCERRS ... MPC] = e1000e_mac_readreg,
3041 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg,
3042 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg,
3043 [RA ... RA + 31] = e1000e_mac_readreg,
3044 [WUPM ... WUPM + 31] = e1000e_mac_readreg,
3045 [MTA ... MTA + 127] = e1000e_mac_readreg,
3046 [VFTA ... VFTA + 127] = e1000e_mac_readreg,
3047 [FFMT ... FFMT + 254] = E1000E_LOW_BITS_READ(4),
3048 [FFVT ... FFVT + 254] = e1000e_mac_readreg,
3049 [MDEF ... MDEF + 7] = e1000e_mac_readreg,
3050 [FFLT ... FFLT + 10] = E1000E_LOW_BITS_READ(11),
3051 [FTFT ... FTFT + 254] = e1000e_mac_readreg,
3052 [PBM ... PBM + 10239] = e1000e_mac_readreg,
3053 [RETA ... RETA + 31] = e1000e_mac_readreg,
3054 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg,
3055 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg,
3056 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read
3057 };
3058 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) };
3059
3060 #define e1000e_putreg(x) [x] = e1000e_mac_writereg
3061 static void (*e1000e_macreg_writeops[])(E1000ECore *, int, uint32_t) = {
3062 e1000e_putreg(PBA),
3063 e1000e_putreg(SWSM),
3064 e1000e_putreg(WUFC),
3065 e1000e_putreg(RDBAH1),
3066 e1000e_putreg(TDBAH),
3067 e1000e_putreg(TXDCTL),
3068 e1000e_putreg(RDBAH0),
3069 e1000e_putreg(LEDCTL),
3070 e1000e_putreg(FCAL),
3071 e1000e_putreg(FCRUC),
3072 e1000e_putreg(AIT),
3073 e1000e_putreg(TDFH),
3074 e1000e_putreg(TDFT),
3075 e1000e_putreg(TDFHS),
3076 e1000e_putreg(TDFTS),
3077 e1000e_putreg(TDFPC),
3078 e1000e_putreg(WUC),
3079 e1000e_putreg(WUS),
3080 e1000e_putreg(RDFH),
3081 e1000e_putreg(RDFT),
3082 e1000e_putreg(RDFHS),
3083 e1000e_putreg(RDFTS),
3084 e1000e_putreg(RDFPC),
3085 e1000e_putreg(IPAV),
3086 e1000e_putreg(TDBAH1),
3087 e1000e_putreg(TIMINCA),
3088 e1000e_putreg(IAM),
3089 e1000e_putreg(EIAC),
3090 e1000e_putreg(IVAR),
3091 e1000e_putreg(TARC0),
3092 e1000e_putreg(TARC1),
3093 e1000e_putreg(FLSWDATA),
3094 e1000e_putreg(POEMB),
3095 e1000e_putreg(PBS),
3096 e1000e_putreg(MFUTP01),
3097 e1000e_putreg(MFUTP23),
3098 e1000e_putreg(MANC),
3099 e1000e_putreg(MANC2H),
3100 e1000e_putreg(MFVAL),
3101 e1000e_putreg(EXTCNF_CTRL),
3102 e1000e_putreg(FACTPS),
3103 e1000e_putreg(FUNCTAG),
3104 e1000e_putreg(GSCL_1),
3105 e1000e_putreg(GSCL_2),
3106 e1000e_putreg(GSCL_3),
3107 e1000e_putreg(GSCL_4),
3108 e1000e_putreg(GSCN_0),
3109 e1000e_putreg(GSCN_1),
3110 e1000e_putreg(GSCN_2),
3111 e1000e_putreg(GSCN_3),
3112 e1000e_putreg(GCR2),
3113 e1000e_putreg(MRQC),
3114 e1000e_putreg(FLOP),
3115 e1000e_putreg(FLOL),
3116 e1000e_putreg(FLSWCTL),
3117 e1000e_putreg(FLSWCNT),
3118 e1000e_putreg(FLA),
3119 e1000e_putreg(RXDCTL1),
3120 e1000e_putreg(TXDCTL1),
3121 e1000e_putreg(TIPG),
3122 e1000e_putreg(RXSTMPH),
3123 e1000e_putreg(RXSTMPL),
3124 e1000e_putreg(RXSATRL),
3125 e1000e_putreg(RXSATRH),
3126 e1000e_putreg(TXSTMPL),
3127 e1000e_putreg(TXSTMPH),
3128 e1000e_putreg(SYSTIML),
3129 e1000e_putreg(SYSTIMH),
3130 e1000e_putreg(TIMADJL),
3131 e1000e_putreg(TIMADJH),
3132 e1000e_putreg(RXUDP),
3133 e1000e_putreg(RXCFGL),
3134 e1000e_putreg(TSYNCRXCTL),
3135 e1000e_putreg(TSYNCTXCTL),
3136 e1000e_putreg(FLSWDATA),
3137 e1000e_putreg(EXTCNF_SIZE),
3138 e1000e_putreg(EEMNGCTL),
3139 e1000e_putreg(RA),
3140
3141 [TDH1] = e1000e_set_16bit,
3142 [TDT1] = e1000e_set_tdt,
3143 [TCTL] = e1000e_set_tctl,
3144 [TDT] = e1000e_set_tdt,
3145 [MDIC] = e1000e_set_mdic,
3146 [ICS] = e1000e_set_ics,
3147 [TDH] = e1000e_set_16bit,
3148 [RDH0] = e1000e_set_16bit,
3149 [RDT0] = e1000e_set_rdt,
3150 [IMC] = e1000e_set_imc,
3151 [IMS] = e1000e_set_ims,
3152 [ICR] = e1000e_set_icr,
3153 [EECD] = e1000e_set_eecd,
3154 [RCTL] = e1000e_set_rx_control,
3155 [CTRL] = e1000e_set_ctrl,
3156 [RDTR] = e1000e_set_rdtr,
3157 [RADV] = e1000e_set_16bit,
3158 [TADV] = e1000e_set_16bit,
3159 [ITR] = e1000e_set_itr,
3160 [EERD] = e1000e_set_eerd,
3161 [GCR] = e1000e_set_gcr,
3162 [PSRCTL] = e1000e_set_psrctl,
3163 [RXCSUM] = e1000e_set_rxcsum,
3164 [RAID] = e1000e_set_16bit,
3165 [RSRPD] = e1000e_set_12bit,
3166 [TIDV] = e1000e_set_tidv,
3167 [TDLEN1] = e1000e_set_dlen,
3168 [TDLEN] = e1000e_set_dlen,
3169 [RDLEN0] = e1000e_set_dlen,
3170 [RDLEN1] = e1000e_set_dlen,
3171 [TDBAL] = e1000e_set_dbal,
3172 [TDBAL1] = e1000e_set_dbal,
3173 [RDBAL0] = e1000e_set_dbal,
3174 [RDBAL1] = e1000e_set_dbal,
3175 [RDH1] = e1000e_set_16bit,
3176 [RDT1] = e1000e_set_rdt,
3177 [STATUS] = e1000e_set_status,
3178 [PBACLR] = e1000e_set_pbaclr,
3179 [CTRL_EXT] = e1000e_set_ctrlext,
3180 [FCAH] = e1000e_set_16bit,
3181 [FCT] = e1000e_set_16bit,
3182 [FCTTV] = e1000e_set_16bit,
3183 [FCRTV] = e1000e_set_16bit,
3184 [FCRTH] = e1000e_set_fcrth,
3185 [FCRTL] = e1000e_set_fcrtl,
3186 [VET] = e1000e_set_vet,
3187 [RXDCTL] = e1000e_set_rxdctl,
3188 [FLASHT] = e1000e_set_16bit,
3189 [EEWR] = e1000e_set_eewr,
3190 [CTRL_DUP] = e1000e_set_ctrl,
3191 [RFCTL] = e1000e_set_rfctl,
3192 [RA + 1] = e1000e_mac_setmacaddr,
3193
3194 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg,
3195 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg,
3196 [RA + 2 ... RA + 31] = e1000e_mac_writereg,
3197 [WUPM ... WUPM + 31] = e1000e_mac_writereg,
3198 [MTA ... MTA + 127] = e1000e_mac_writereg,
3199 [VFTA ... VFTA + 127] = e1000e_mac_writereg,
3200 [FFMT ... FFMT + 254] = e1000e_mac_writereg,
3201 [FFVT ... FFVT + 254] = e1000e_mac_writereg,
3202 [PBM ... PBM + 10239] = e1000e_mac_writereg,
3203 [MDEF ... MDEF + 7] = e1000e_mac_writereg,
3204 [FFLT ... FFLT + 10] = e1000e_mac_writereg,
3205 [FTFT ... FTFT + 254] = e1000e_mac_writereg,
3206 [RETA ... RETA + 31] = e1000e_mac_writereg,
3207 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg,
3208 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg,
3209 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr
3210 };
3211 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) };
3212
3213 enum { MAC_ACCESS_PARTIAL = 1 };
3214
3215 /* The array below combines alias offsets of the index values for the
3216 * MAC registers that have aliases, with the indication of not fully
3217 * implemented registers (lowest bit). This combination is possible
3218 * because all of the offsets are even. */
3219 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = {
3220 /* Alias index offsets */
3221 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802,
3222 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6,
3223 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904,
3224 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8,
3225 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00,
3226 [RA_A ... RA_A + 31] = 0x14f0,
3227 [VFTA_A ... VFTA_A + 127] = 0x1400,
3228 [RDBAL0_A ... RDLEN0_A] = 0x09bc,
3229 [TDBAL_A ... TDLEN_A] = 0x0cf8,
3230 /* Access options */
3231 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL,
3232 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL,
3233 [RDFPC] = MAC_ACCESS_PARTIAL,
3234 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL,
3235 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL,
3236 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL,
3237 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL,
3238 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL,
3239 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL,
3240 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL,
3241 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL,
3242 [TXDCTL1] = MAC_ACCESS_PARTIAL,
3243 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL
3244 };
3245
3246 void
3247 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size)
3248 {
3249 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3250
3251 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) {
3252 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3253 trace_e1000e_wrn_regs_write_trivial(index << 2);
3254 }
3255 trace_e1000e_core_write(index << 2, size, val);
3256 e1000e_macreg_writeops[index](core, index, val);
3257 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3258 trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3259 } else {
3260 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3261 }
3262 }
3263
3264 uint64_t
3265 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size)
3266 {
3267 uint64_t val;
3268 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3269
3270 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3271 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3272 trace_e1000e_wrn_regs_read_trivial(index << 2);
3273 }
3274 val = e1000e_macreg_readops[index](core, index);
3275 trace_e1000e_core_read(index << 2, size, val);
3276 return val;
3277 } else {
3278 trace_e1000e_wrn_regs_read_unknown(index << 2, size);
3279 }
3280 return 0;
3281 }
3282
3283 static inline void
3284 e1000e_autoneg_pause(E1000ECore *core)
3285 {
3286 timer_del(core->autoneg_timer);
3287 }
3288
3289 static void
3290 e1000e_autoneg_resume(E1000ECore *core)
3291 {
3292 if (e1000e_have_autoneg(core) &&
3293 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
3294 qemu_get_queue(core->owner_nic)->link_down = false;
3295 timer_mod(core->autoneg_timer,
3296 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
3297 }
3298 }
3299
3300 static void
3301 e1000e_vm_state_change(void *opaque, int running, RunState state)
3302 {
3303 E1000ECore *core = opaque;
3304
3305 if (running) {
3306 trace_e1000e_vm_state_running();
3307 e1000e_intrmgr_resume(core);
3308 e1000e_autoneg_resume(core);
3309 } else {
3310 trace_e1000e_vm_state_stopped();
3311 e1000e_autoneg_pause(core);
3312 e1000e_intrmgr_pause(core);
3313 }
3314 }
3315
3316 void
3317 e1000e_core_pci_realize(E1000ECore *core,
3318 const uint16_t *eeprom_templ,
3319 uint32_t eeprom_size,
3320 const uint8_t *macaddr)
3321 {
3322 int i;
3323
3324 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3325 e1000e_autoneg_timer, core);
3326 e1000e_intrmgr_pci_realize(core);
3327
3328 core->vmstate =
3329 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core);
3330
3331 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3332 net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner,
3333 E1000E_MAX_TX_FRAGS, core->has_vnet);
3334 }
3335
3336 net_rx_pkt_init(&core->rx_pkt, core->has_vnet);
3337
3338 e1000x_core_prepare_eeprom(core->eeprom,
3339 eeprom_templ,
3340 eeprom_size,
3341 PCI_DEVICE_GET_CLASS(core->owner)->device_id,
3342 macaddr);
3343 e1000e_update_rx_offloads(core);
3344 }
3345
3346 void
3347 e1000e_core_pci_uninit(E1000ECore *core)
3348 {
3349 int i;
3350
3351 timer_del(core->autoneg_timer);
3352 timer_free(core->autoneg_timer);
3353
3354 e1000e_intrmgr_pci_unint(core);
3355
3356 qemu_del_vm_change_state_handler(core->vmstate);
3357
3358 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3359 net_tx_pkt_reset(core->tx[i].tx_pkt);
3360 net_tx_pkt_uninit(core->tx[i].tx_pkt);
3361 }
3362
3363 net_rx_pkt_uninit(core->rx_pkt);
3364 }
3365
3366 static const uint16_t
3367 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {
3368 [0] = {
3369 [PHY_CTRL] = MII_CR_SPEED_SELECT_MSB |
3370 MII_CR_FULL_DUPLEX |
3371 MII_CR_AUTO_NEG_EN,
3372
3373 [PHY_STATUS] = MII_SR_EXTENDED_CAPS |
3374 MII_SR_LINK_STATUS |
3375 MII_SR_AUTONEG_CAPS |
3376 MII_SR_PREAMBLE_SUPPRESS |
3377 MII_SR_EXTENDED_STATUS |
3378 MII_SR_10T_HD_CAPS |
3379 MII_SR_10T_FD_CAPS |
3380 MII_SR_100X_HD_CAPS |
3381 MII_SR_100X_FD_CAPS,
3382
3383 [PHY_ID1] = 0x141,
3384 [PHY_ID2] = E1000_PHY_ID2_82574x,
3385 [PHY_AUTONEG_ADV] = 0xde1,
3386 [PHY_LP_ABILITY] = 0x7e0,
3387 [PHY_AUTONEG_EXP] = BIT(2),
3388 [PHY_NEXT_PAGE_TX] = BIT(0) | BIT(13),
3389 [PHY_1000T_CTRL] = BIT(8) | BIT(9) | BIT(10) | BIT(11),
3390 [PHY_1000T_STATUS] = 0x3c00,
3391 [PHY_EXT_STATUS] = BIT(12) | BIT(13),
3392
3393 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) |
3394 BIT(12) | BIT(13),
3395 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15)
3396 },
3397 [2] = {
3398 [PHY_MAC_CTRL1] = BIT(3) | BIT(7),
3399 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12)
3400 },
3401 [3] = {
3402 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14)
3403 }
3404 };
3405
3406 static const uint32_t e1000e_mac_reg_init[] = {
3407 [PBA] = 0x00140014,
3408 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18),
3409 [EXTCNF_CTRL] = BIT(3),
3410 [EEMNGCTL] = BIT(31),
3411 [FLASHT] = 0x2,
3412 [FLSWCTL] = BIT(30) | BIT(31),
3413 [FLOL] = BIT(0),
3414 [RXDCTL] = BIT(16),
3415 [RXDCTL1] = BIT(16),
3416 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20),
3417 [RXCFGL] = 0x88F7,
3418 [RXUDP] = 0x319,
3419 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
3420 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU |
3421 E1000_CTRL_ADVD3WUC,
3422 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU,
3423 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) |
3424 (4 << E1000_PSRCTL_BSIZE1_SHIFT) |
3425 (4 << E1000_PSRCTL_BSIZE2_SHIFT),
3426 [TARC0] = 0x3 | E1000_TARC_ENABLE,
3427 [TARC1] = 0x3 | E1000_TARC_ENABLE,
3428 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES,
3429 [EERD] = E1000_EERW_DONE,
3430 [EEWR] = E1000_EERW_DONE,
3431 [GCR] = E1000_L0S_ADJUST |
3432 E1000_L1_ENTRY_LATENCY_MSB |
3433 E1000_L1_ENTRY_LATENCY_LSB,
3434 [TDFH] = 0x600,
3435 [TDFT] = 0x600,
3436 [TDFHS] = 0x600,
3437 [TDFTS] = 0x600,
3438 [POEMB] = 0x30D,
3439 [PBS] = 0x028,
3440 [MANC] = E1000_MANC_DIS_IP_CHK_ARP,
3441 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000,
3442 [SWSM] = 1,
3443 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD,
3444 [ITR] = E1000E_MIN_XITR,
3445 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR,
3446 };
3447
3448 void
3449 e1000e_core_reset(E1000ECore *core)
3450 {
3451 int i;
3452
3453 timer_del(core->autoneg_timer);
3454
3455 e1000e_intrmgr_reset(core);
3456
3457 memset(core->phy, 0, sizeof core->phy);
3458 memmove(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init);
3459 memset(core->mac, 0, sizeof core->mac);
3460 memmove(core->mac, e1000e_mac_reg_init, sizeof e1000e_mac_reg_init);
3461
3462 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT;
3463
3464 if (qemu_get_queue(core->owner_nic)->link_down) {
3465 e1000e_link_down(core);
3466 }
3467
3468 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
3469
3470 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3471 net_tx_pkt_reset(core->tx[i].tx_pkt);
3472 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props));
3473 core->tx[i].skip_cp = false;
3474 }
3475 }
3476
3477 void e1000e_core_pre_save(E1000ECore *core)
3478 {
3479 int i;
3480 NetClientState *nc = qemu_get_queue(core->owner_nic);
3481
3482 /*
3483 * If link is down and auto-negotiation is supported and ongoing,
3484 * complete auto-negotiation immediately. This allows us to look
3485 * at MII_SR_AUTONEG_COMPLETE to infer link status on load.
3486 */
3487 if (nc->link_down && e1000e_have_autoneg(core)) {
3488 core->phy[0][PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE;
3489 e1000e_update_flowctl_status(core);
3490 }
3491
3492 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3493 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) {
3494 core->tx[i].skip_cp = true;
3495 }
3496 }
3497 }
3498
3499 int
3500 e1000e_core_post_load(E1000ECore *core)
3501 {
3502 NetClientState *nc = qemu_get_queue(core->owner_nic);
3503
3504 /* nc.link_down can't be migrated, so infer link_down according
3505 * to link status bit in core.mac[STATUS].
3506 */
3507 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
3508
3509 return 0;
3510 }
AR7 emulation for QEMU