hw/net/smc91c111.c

   1 /*
   2  * SMSC 91C111 Ethernet interface emulation
   3  *
   4  * Copyright (c) 2005 CodeSourcery, LLC.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "net/net.h"
  12 #include "hw/devices.h"
  13 /* For crc32 */
  14 #include <zlib.h>
  15
  16 /* Number of 2k memory pages available.  */
  17 #define NUM_PACKETS 4
  18
  19 #define TYPE_SMC91C111 "smc91c111"
  20 #define SMC91C111(obj) OBJECT_CHECK(smc91c111_state, (obj), TYPE_SMC91C111)
  21
  22 typedef struct {
  23     SysBusDevice parent_obj;
  24
  25     NICState *nic;
  26     NICConf conf;
  27     uint16_t tcr;
  28     uint16_t rcr;
  29     uint16_t cr;
  30     uint16_t ctr;
  31     uint16_t gpr;
  32     uint16_t ptr;
  33     uint16_t ercv;
  34     qemu_irq irq;
  35     int bank;
  36     int packet_num;
  37     int tx_alloc;
  38     /* Bitmask of allocated packets.  */
  39     int allocated;
  40     int tx_fifo_len;
  41     int tx_fifo[NUM_PACKETS];
  42     int rx_fifo_len;
  43     int rx_fifo[NUM_PACKETS];
  44     int tx_fifo_done_len;
  45     int tx_fifo_done[NUM_PACKETS];
  46     /* Packet buffer memory.  */
  47     uint8_t data[NUM_PACKETS][2048];
  48     uint8_t int_level;
  49     uint8_t int_mask;
  50     MemoryRegion mmio;
  51 } smc91c111_state;
  52
  53 static const VMStateDescription vmstate_smc91c111 = {
  54     .name = "smc91c111",
  55     .version_id = 1,
  56     .minimum_version_id = 1,
  57     .fields      = (VMStateField []) {
  58         VMSTATE_UINT16(tcr, smc91c111_state),
  59         VMSTATE_UINT16(rcr, smc91c111_state),
  60         VMSTATE_UINT16(cr, smc91c111_state),
  61         VMSTATE_UINT16(ctr, smc91c111_state),
  62         VMSTATE_UINT16(gpr, smc91c111_state),
  63         VMSTATE_UINT16(ptr, smc91c111_state),
  64         VMSTATE_UINT16(ercv, smc91c111_state),
  65         VMSTATE_INT32(bank, smc91c111_state),
  66         VMSTATE_INT32(packet_num, smc91c111_state),
  67         VMSTATE_INT32(tx_alloc, smc91c111_state),
  68         VMSTATE_INT32(allocated, smc91c111_state),
  69         VMSTATE_INT32(tx_fifo_len, smc91c111_state),
  70         VMSTATE_INT32_ARRAY(tx_fifo, smc91c111_state, NUM_PACKETS),
  71         VMSTATE_INT32(rx_fifo_len, smc91c111_state),
  72         VMSTATE_INT32_ARRAY(rx_fifo, smc91c111_state, NUM_PACKETS),
  73         VMSTATE_INT32(tx_fifo_done_len, smc91c111_state),
  74         VMSTATE_INT32_ARRAY(tx_fifo_done, smc91c111_state, NUM_PACKETS),
  75         VMSTATE_BUFFER_UNSAFE(data, smc91c111_state, 0, NUM_PACKETS * 2048),
  76         VMSTATE_UINT8(int_level, smc91c111_state),
  77         VMSTATE_UINT8(int_mask, smc91c111_state),
  78         VMSTATE_END_OF_LIST()
  79     }
  80 };
  81
  82 #define RCR_SOFT_RST  0x8000
  83 #define RCR_STRIP_CRC 0x0200
  84 #define RCR_RXEN      0x0100
  85
  86 #define TCR_EPH_LOOP  0x2000
  87 #define TCR_NOCRC     0x0100
  88 #define TCR_PAD_EN    0x0080
  89 #define TCR_FORCOL    0x0004
  90 #define TCR_LOOP      0x0002
  91 #define TCR_TXEN      0x0001
  92
  93 #define INT_MD        0x80
  94 #define INT_ERCV      0x40
  95 #define INT_EPH       0x20
  96 #define INT_RX_OVRN   0x10
  97 #define INT_ALLOC     0x08
  98 #define INT_TX_EMPTY  0x04
  99 #define INT_TX        0x02
 100 #define INT_RCV       0x01
 101
 102 #define CTR_AUTO_RELEASE  0x0800
 103 #define CTR_RELOAD        0x0002
 104 #define CTR_STORE         0x0001
 105
 106 #define RS_ALGNERR      0x8000
 107 #define RS_BRODCAST     0x4000
 108 #define RS_BADCRC       0x2000
 109 #define RS_ODDFRAME     0x1000
 110 #define RS_TOOLONG      0x0800
 111 #define RS_TOOSHORT     0x0400
 112 #define RS_MULTICAST    0x0001
 113
 114 /* Update interrupt status.  */
 115 static void smc91c111_update(smc91c111_state *s)
 116 {
 117     int level;
 118
 119     if (s->tx_fifo_len == 0)
 120         s->int_level |= INT_TX_EMPTY;
 121     if (s->tx_fifo_done_len != 0)
 122         s->int_level |= INT_TX;
 123     level = (s->int_level & s->int_mask) != 0;
 124     qemu_set_irq(s->irq, level);
 125 }
 126
 127 /* Try to allocate a packet.  Returns 0x80 on failure.  */
 128 static int smc91c111_allocate_packet(smc91c111_state *s)
 129 {
 130     int i;
 131     if (s->allocated == (1 << NUM_PACKETS) - 1) {
 132         return 0x80;
 133     }
 134
 135     for (i = 0; i < NUM_PACKETS; i++) {
 136         if ((s->allocated & (1 << i)) == 0)
 137             break;
 138     }
 139     s->allocated |= 1 << i;
 140     return i;
 141 }
 142
 143
 144 /* Process a pending TX allocate.  */
 145 static void smc91c111_tx_alloc(smc91c111_state *s)
 146 {
 147     s->tx_alloc = smc91c111_allocate_packet(s);
 148     if (s->tx_alloc == 0x80)
 149         return;
 150     s->int_level |= INT_ALLOC;
 151     smc91c111_update(s);
 152 }
 153
 154 /* Remove and item from the RX FIFO.  */
 155 static void smc91c111_pop_rx_fifo(smc91c111_state *s)
 156 {
 157     int i;
 158
 159     s->rx_fifo_len--;
 160     if (s->rx_fifo_len) {
 161         for (i = 0; i < s->rx_fifo_len; i++)
 162             s->rx_fifo[i] = s->rx_fifo[i + 1];
 163         s->int_level |= INT_RCV;
 164     } else {
 165         s->int_level &= ~INT_RCV;
 166     }
 167     smc91c111_update(s);
 168 }
 169
 170 /* Remove an item from the TX completion FIFO.  */
 171 static void smc91c111_pop_tx_fifo_done(smc91c111_state *s)
 172 {
 173     int i;
 174
 175     if (s->tx_fifo_done_len == 0)
 176         return;
 177     s->tx_fifo_done_len--;
 178     for (i = 0; i < s->tx_fifo_done_len; i++)
 179         s->tx_fifo_done[i] = s->tx_fifo_done[i + 1];
 180 }
 181
 182 /* Release the memory allocated to a packet.  */
 183 static void smc91c111_release_packet(smc91c111_state *s, int packet)
 184 {
 185     s->allocated &= ~(1 << packet);
 186     if (s->tx_alloc == 0x80)
 187         smc91c111_tx_alloc(s);
 188 }
 189
 190 /* Flush the TX FIFO.  */
 191 static void smc91c111_do_tx(smc91c111_state *s)
 192 {
 193     int i;
 194     int len;
 195     int control;
 196     int packetnum;
 197     uint8_t *p;
 198
 199     if ((s->tcr & TCR_TXEN) == 0)
 200         return;
 201     if (s->tx_fifo_len == 0)
 202         return;
 203     for (i = 0; i < s->tx_fifo_len; i++) {
 204         packetnum = s->tx_fifo[i];
 205         p = &s->data[packetnum][0];
 206         /* Set status word.  */
 207         *(p++) = 0x01;
 208         *(p++) = 0x40;
 209         len = *(p++);
 210         len |= ((int)*(p++)) << 8;
 211         len -= 6;
 212         control = p[len + 1];
 213         if (control & 0x20)
 214             len++;
 215         /* ??? This overwrites the data following the buffer.
 216            Don't know what real hardware does.  */
 217         if (len < 64 && (s->tcr & TCR_PAD_EN)) {
 218             memset(p + len, 0, 64 - len);
 219             len = 64;
 220         }
 221 #if 0
 222         {
 223             int add_crc;
 224
 225             /* The card is supposed to append the CRC to the frame.
 226                However none of the other network traffic has the CRC
 227                appended.  Suspect this is low level ethernet detail we
 228                don't need to worry about.  */
 229             add_crc = (control & 0x10) || (s->tcr & TCR_NOCRC) == 0;
 230             if (add_crc) {
 231                 uint32_t crc;
 232
 233                 crc = crc32(~0, p, len);
 234                 memcpy(p + len, &crc, 4);
 235                 len += 4;
 236             }
 237         }
 238 #endif
 239         if (s->ctr & CTR_AUTO_RELEASE)
 240             /* Race?  */
 241             smc91c111_release_packet(s, packetnum);
 242         else if (s->tx_fifo_done_len < NUM_PACKETS)
 243             s->tx_fifo_done[s->tx_fifo_done_len++] = packetnum;
 244         qemu_send_packet(qemu_get_queue(s->nic), p, len);
 245     }
 246     s->tx_fifo_len = 0;
 247     smc91c111_update(s);
 248 }
 249
 250 /* Add a packet to the TX FIFO.  */
 251 static void smc91c111_queue_tx(smc91c111_state *s, int packet)
 252 {
 253     if (s->tx_fifo_len == NUM_PACKETS)
 254         return;
 255     s->tx_fifo[s->tx_fifo_len++] = packet;
 256     smc91c111_do_tx(s);
 257 }
 258
 259 static void smc91c111_reset(DeviceState *dev)
 260 {
 261     smc91c111_state *s = SMC91C111(dev);
 262
 263     s->bank = 0;
 264     s->tx_fifo_len = 0;
 265     s->tx_fifo_done_len = 0;
 266     s->rx_fifo_len = 0;
 267     s->allocated = 0;
 268     s->packet_num = 0;
 269     s->tx_alloc = 0;
 270     s->tcr = 0;
 271     s->rcr = 0;
 272     s->cr = 0xa0b1;
 273     s->ctr = 0x1210;
 274     s->ptr = 0;
 275     s->ercv = 0x1f;
 276     s->int_level = INT_TX_EMPTY;
 277     s->int_mask = 0;
 278     smc91c111_update(s);
 279 }
 280
 281 #define SET_LOW(name, val) s->name = (s->name & 0xff00) | val
 282 #define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8)
 283
 284 static void smc91c111_writeb(void *opaque, hwaddr offset,
 285                              uint32_t value)
 286 {
 287     smc91c111_state *s = (smc91c111_state *)opaque;
 288
 289     offset = offset & 0xf;
 290     if (offset == 14) {
 291         s->bank = value;
 292         return;
 293     }
 294     if (offset == 15)
 295         return;
 296     switch (s->bank) {
 297     case 0:
 298         switch (offset) {
 299         case 0: /* TCR */
 300             SET_LOW(tcr, value);
 301             return;
 302         case 1:
 303             SET_HIGH(tcr, value);
 304             return;
 305         case 4: /* RCR */
 306             SET_LOW(rcr, value);
 307             return;
 308         case 5:
 309             SET_HIGH(rcr, value);
 310             if (s->rcr & RCR_SOFT_RST) {
 311                 smc91c111_reset(DEVICE(s));
 312             }
 313             return;
 314         case 10: case 11: /* RPCR */
 315             /* Ignored */
 316             return;
 317         case 12: case 13: /* Reserved */
 318             return;
 319         }
 320         break;
 321
 322     case 1:
 323         switch (offset) {
 324         case 0: /* CONFIG */
 325             SET_LOW(cr, value);
 326             return;
 327         case 1:
 328             SET_HIGH(cr,value);
 329             return;
 330         case 2: case 3: /* BASE */
 331         case 4: case 5: case 6: case 7: case 8: case 9: /* IA */
 332             /* Not implemented.  */
 333             return;
 334         case 10: /* Genral Purpose */
 335             SET_LOW(gpr, value);
 336             return;
 337         case 11:
 338             SET_HIGH(gpr, value);
 339             return;
 340         case 12: /* Control */
 341             if (value & 1)
 342                 fprintf(stderr, "smc91c111:EEPROM store not implemented\n");
 343             if (value & 2)
 344                 fprintf(stderr, "smc91c111:EEPROM reload not implemented\n");
 345             value &= ~3;
 346             SET_LOW(ctr, value);
 347             return;
 348         case 13:
 349             SET_HIGH(ctr, value);
 350             return;
 351         }
 352         break;
 353
 354     case 2:
 355         switch (offset) {
 356         case 0: /* MMU Command */
 357             switch (value >> 5) {
 358             case 0: /* no-op */
 359                 break;
 360             case 1: /* Allocate for TX.  */
 361                 s->tx_alloc = 0x80;
 362                 s->int_level &= ~INT_ALLOC;
 363                 smc91c111_update(s);
 364                 smc91c111_tx_alloc(s);
 365                 break;
 366             case 2: /* Reset MMU.  */
 367                 s->allocated = 0;
 368                 s->tx_fifo_len = 0;
 369                 s->tx_fifo_done_len = 0;
 370                 s->rx_fifo_len = 0;
 371                 s->tx_alloc = 0;
 372                 break;
 373             case 3: /* Remove from RX FIFO.  */
 374                 smc91c111_pop_rx_fifo(s);
 375                 break;
 376             case 4: /* Remove from RX FIFO and release.  */
 377                 if (s->rx_fifo_len > 0) {
 378                     smc91c111_release_packet(s, s->rx_fifo[0]);
 379                 }
 380                 smc91c111_pop_rx_fifo(s);
 381                 break;
 382             case 5: /* Release.  */
 383                 smc91c111_release_packet(s, s->packet_num);
 384                 break;
 385             case 6: /* Add to TX FIFO.  */
 386                 smc91c111_queue_tx(s, s->packet_num);
 387                 break;
 388             case 7: /* Reset TX FIFO.  */
 389                 s->tx_fifo_len = 0;
 390                 s->tx_fifo_done_len = 0;
 391                 break;
 392             }
 393             return;
 394         case 1:
 395             /* Ignore.  */
 396             return;
 397         case 2: /* Packet Number Register */
 398             s->packet_num = value;
 399             return;
 400         case 3: case 4: case 5:
 401             /* Should be readonly, but linux writes to them anyway. Ignore.  */
 402             return;
 403         case 6: /* Pointer */
 404             SET_LOW(ptr, value);
 405             return;
 406         case 7:
 407             SET_HIGH(ptr, value);
 408             return;
 409         case 8: case 9: case 10: case 11: /* Data */
 410             {
 411                 int p;
 412                 int n;
 413
 414                 if (s->ptr & 0x8000)
 415                     n = s->rx_fifo[0];
 416                 else
 417                     n = s->packet_num;
 418                 p = s->ptr & 0x07ff;
 419                 if (s->ptr & 0x4000) {
 420                     s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x7ff);
 421                 } else {
 422                     p += (offset & 3);
 423                 }
 424                 s->data[n][p] = value;
 425             }
 426             return;
 427         case 12: /* Interrupt ACK.  */
 428             s->int_level &= ~(value & 0xd6);
 429             if (value & INT_TX)
 430                 smc91c111_pop_tx_fifo_done(s);
 431             smc91c111_update(s);
 432             return;
 433         case 13: /* Interrupt mask.  */
 434             s->int_mask = value;
 435             smc91c111_update(s);
 436             return;
 437         }
 438         break;
 439
 440     case 3:
 441         switch (offset) {
 442         case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
 443             /* Multicast table.  */
 444             /* Not implemented.  */
 445             return;
 446         case 8: case 9: /* Management Interface.  */
 447             /* Not implemented.  */
 448             return;
 449         case 12: /* Early receive.  */
 450             s->ercv = value & 0x1f;
 451             return;
 452         case 13:
 453             /* Ignore.  */
 454             return;
 455         }
 456         break;
 457     }
 458     hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset);
 459 }
 460
 461 static uint32_t smc91c111_readb(void *opaque, hwaddr offset)
 462 {
 463     smc91c111_state *s = (smc91c111_state *)opaque;
 464
 465     offset = offset & 0xf;
 466     if (offset == 14) {
 467         return s->bank;
 468     }
 469     if (offset == 15)
 470         return 0x33;
 471     switch (s->bank) {
 472     case 0:
 473         switch (offset) {
 474         case 0: /* TCR */
 475             return s->tcr & 0xff;
 476         case 1:
 477             return s->tcr >> 8;
 478         case 2: /* EPH Status */
 479             return 0;
 480         case 3:
 481             return 0x40;
 482         case 4: /* RCR */
 483             return s->rcr & 0xff;
 484         case 5:
 485             return s->rcr >> 8;
 486         case 6: /* Counter */
 487         case 7:
 488             /* Not implemented.  */
 489             return 0;
 490         case 8: /* Memory size.  */
 491             return NUM_PACKETS;
 492         case 9: /* Free memory available.  */
 493             {
 494                 int i;
 495                 int n;
 496                 n = 0;
 497                 for (i = 0; i < NUM_PACKETS; i++) {
 498                     if (s->allocated & (1 << i))
 499                         n++;
 500                 }
 501                 return n;
 502             }
 503         case 10: case 11: /* RPCR */
 504             /* Not implemented.  */
 505             return 0;
 506         case 12: case 13: /* Reserved */
 507             return 0;
 508         }
 509         break;
 510
 511     case 1:
 512         switch (offset) {
 513         case 0: /* CONFIG */
 514             return s->cr & 0xff;
 515         case 1:
 516             return s->cr >> 8;
 517         case 2: case 3: /* BASE */
 518             /* Not implemented.  */
 519             return 0;
 520         case 4: case 5: case 6: case 7: case 8: case 9: /* IA */
 521             return s->conf.macaddr.a[offset - 4];
 522         case 10: /* General Purpose */
 523             return s->gpr & 0xff;
 524         case 11:
 525             return s->gpr >> 8;
 526         case 12: /* Control */
 527             return s->ctr & 0xff;
 528         case 13:
 529             return s->ctr >> 8;
 530         }
 531         break;
 532
 533     case 2:
 534         switch (offset) {
 535         case 0: case 1: /* MMUCR Busy bit.  */
 536             return 0;
 537         case 2: /* Packet Number.  */
 538             return s->packet_num;
 539         case 3: /* Allocation Result.  */
 540             return s->tx_alloc;
 541         case 4: /* TX FIFO */
 542             if (s->tx_fifo_done_len == 0)
 543                 return 0x80;
 544             else
 545                 return s->tx_fifo_done[0];
 546         case 5: /* RX FIFO */
 547             if (s->rx_fifo_len == 0)
 548                 return 0x80;
 549             else
 550                 return s->rx_fifo[0];
 551         case 6: /* Pointer */
 552             return s->ptr & 0xff;
 553         case 7:
 554             return (s->ptr >> 8) & 0xf7;
 555         case 8: case 9: case 10: case 11: /* Data */
 556             {
 557                 int p;
 558                 int n;
 559
 560                 if (s->ptr & 0x8000)
 561                     n = s->rx_fifo[0];
 562                 else
 563                     n = s->packet_num;
 564                 p = s->ptr & 0x07ff;
 565                 if (s->ptr & 0x4000) {
 566                     s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x07ff);
 567                 } else {
 568                     p += (offset & 3);
 569                 }
 570                 return s->data[n][p];
 571             }
 572         case 12: /* Interrupt status.  */
 573             return s->int_level;
 574         case 13: /* Interrupt mask.  */
 575             return s->int_mask;
 576         }
 577         break;
 578
 579     case 3:
 580         switch (offset) {
 581         case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
 582             /* Multicast table.  */
 583             /* Not implemented.  */
 584             return 0;
 585         case 8: /* Management Interface.  */
 586             /* Not implemented.  */
 587             return 0x30;
 588         case 9:
 589             return 0x33;
 590         case 10: /* Revision.  */
 591             return 0x91;
 592         case 11:
 593             return 0x33;
 594         case 12:
 595             return s->ercv;
 596         case 13:
 597             return 0;
 598         }
 599         break;
 600     }
 601     hw_error("smc91c111_read: Bad reg %d:%x\n", s->bank, (int)offset);
 602     return 0;
 603 }
 604
 605 static void smc91c111_writew(void *opaque, hwaddr offset,
 606                              uint32_t value)
 607 {
 608     smc91c111_writeb(opaque, offset, value & 0xff);
 609     smc91c111_writeb(opaque, offset + 1, value >> 8);
 610 }
 611
 612 static void smc91c111_writel(void *opaque, hwaddr offset,
 613                              uint32_t value)
 614 {
 615     /* 32-bit writes to offset 0xc only actually write to the bank select
 616        register (offset 0xe)  */
 617     if (offset != 0xc)
 618         smc91c111_writew(opaque, offset, value & 0xffff);
 619     smc91c111_writew(opaque, offset + 2, value >> 16);
 620 }
 621
 622 static uint32_t smc91c111_readw(void *opaque, hwaddr offset)
 623 {
 624     uint32_t val;
 625     val = smc91c111_readb(opaque, offset);
 626     val |= smc91c111_readb(opaque, offset + 1) << 8;
 627     return val;
 628 }
 629
 630 static uint32_t smc91c111_readl(void *opaque, hwaddr offset)
 631 {
 632     uint32_t val;
 633     val = smc91c111_readw(opaque, offset);
 634     val |= smc91c111_readw(opaque, offset + 2) << 16;
 635     return val;
 636 }
 637
 638 static int smc91c111_can_receive(NetClientState *nc)
 639 {
 640     smc91c111_state *s = qemu_get_nic_opaque(nc);
 641
 642     if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST))
 643         return 1;
 644     if (s->allocated == (1 << NUM_PACKETS) - 1)
 645         return 0;
 646     return 1;
 647 }
 648
 649 static ssize_t smc91c111_receive(NetClientState *nc, const uint8_t *buf, size_t size)
 650 {
 651     smc91c111_state *s = qemu_get_nic_opaque(nc);
 652     int status;
 653     int packetsize;
 654     uint32_t crc;
 655     int packetnum;
 656     uint8_t *p;
 657
 658     if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST))
 659         return -1;
 660     /* Short packets are padded with zeros.  Receiving a packet
 661        < 64 bytes long is considered an error condition.  */
 662     if (size < 64)
 663         packetsize = 64;
 664     else
 665         packetsize = (size & ~1);
 666     packetsize += 6;
 667     crc = (s->rcr & RCR_STRIP_CRC) == 0;
 668     if (crc)
 669         packetsize += 4;
 670     /* TODO: Flag overrun and receive errors.  */
 671     if (packetsize > 2048)
 672         return -1;
 673     packetnum = smc91c111_allocate_packet(s);
 674     if (packetnum == 0x80)
 675         return -1;
 676     s->rx_fifo[s->rx_fifo_len++] = packetnum;
 677
 678     p = &s->data[packetnum][0];
 679     /* ??? Multicast packets?  */
 680     status = 0;
 681     if (size > 1518)
 682         status |= RS_TOOLONG;
 683     if (size & 1)
 684         status |= RS_ODDFRAME;
 685     *(p++) = status & 0xff;
 686     *(p++) = status >> 8;
 687     *(p++) = packetsize & 0xff;
 688     *(p++) = packetsize >> 8;
 689     memcpy(p, buf, size & ~1);
 690     p += (size & ~1);
 691     /* Pad short packets.  */
 692     if (size < 64) {
 693         int pad;
 694
 695         if (size & 1)
 696             *(p++) = buf[size - 1];
 697         pad = 64 - size;
 698         memset(p, 0, pad);
 699         p += pad;
 700         size = 64;
 701     }
 702     /* It's not clear if the CRC should go before or after the last byte in
 703        odd sized packets.  Linux disables the CRC, so that's no help.
 704        The pictures in the documentation show the CRC aligned on a 16-bit
 705        boundary before the last odd byte, so that's what we do.  */
 706     if (crc) {
 707         crc = crc32(~0, buf, size);
 708         *(p++) = crc & 0xff; crc >>= 8;
 709         *(p++) = crc & 0xff; crc >>= 8;
 710         *(p++) = crc & 0xff; crc >>= 8;
 711         *(p++) = crc & 0xff;
 712     }
 713     if (size & 1) {
 714         *(p++) = buf[size - 1];
 715         *p = 0x60;
 716     } else {
 717         *(p++) = 0;
 718         *p = 0x40;
 719     }
 720     /* TODO: Raise early RX interrupt?  */
 721     s->int_level |= INT_RCV;
 722     smc91c111_update(s);
 723
 724     return size;
 725 }
 726
 727 static const MemoryRegionOps smc91c111_mem_ops = {
 728     /* The special case for 32 bit writes to 0xc means we can't just
 729      * set .impl.min/max_access_size to 1, unfortunately
 730      */
 731     .old_mmio = {
 732         .read = { smc91c111_readb, smc91c111_readw, smc91c111_readl, },
 733         .write = { smc91c111_writeb, smc91c111_writew, smc91c111_writel, },
 734     },
 735     .endianness = DEVICE_NATIVE_ENDIAN,
 736 };
 737
 738 static void smc91c111_cleanup(NetClientState *nc)
 739 {
 740     smc91c111_state *s = qemu_get_nic_opaque(nc);
 741
 742     s->nic = NULL;
 743 }
 744
 745 static NetClientInfo net_smc91c111_info = {
 746     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 747     .size = sizeof(NICState),
 748     .can_receive = smc91c111_can_receive,
 749     .receive = smc91c111_receive,
 750     .cleanup = smc91c111_cleanup,
 751 };
 752
 753 static int smc91c111_init1(SysBusDevice *sbd)
 754 {
 755     DeviceState *dev = DEVICE(sbd);
 756     smc91c111_state *s = SMC91C111(dev);
 757
 758     memory_region_init_io(&s->mmio, OBJECT(s), &smc91c111_mem_ops, s,
 759                           "smc91c111-mmio", 16);
 760     sysbus_init_mmio(sbd, &s->mmio);
 761     sysbus_init_irq(sbd, &s->irq);
 762     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 763     s->nic = qemu_new_nic(&net_smc91c111_info, &s->conf,
 764                           object_get_typename(OBJECT(dev)), dev->id, s);
 765     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 766     /* ??? Save/restore.  */
 767     return 0;
 768 }
 769
 770 static Property smc91c111_properties[] = {
 771     DEFINE_NIC_PROPERTIES(smc91c111_state, conf),
 772     DEFINE_PROP_END_OF_LIST(),
 773 };
 774
 775 static void smc91c111_class_init(ObjectClass *klass, void *data)
 776 {
 777     DeviceClass *dc = DEVICE_CLASS(klass);
 778     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 779
 780     k->init = smc91c111_init1;
 781     dc->reset = smc91c111_reset;
 782     dc->vmsd = &vmstate_smc91c111;
 783     dc->props = smc91c111_properties;
 784 }
 785
 786 static const TypeInfo smc91c111_info = {
 787     .name          = TYPE_SMC91C111,
 788     .parent        = TYPE_SYS_BUS_DEVICE,
 789     .instance_size = sizeof(smc91c111_state),
 790     .class_init    = smc91c111_class_init,
 791 };
 792
 793 static void smc91c111_register_types(void)
 794 {
 795     type_register_static(&smc91c111_info);
 796 }
 797
 798 /* Legacy helper function.  Should go away when machine config files are
 799    implemented.  */
 800 void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq)
 801 {
 802     DeviceState *dev;
 803     SysBusDevice *s;
 804
 805     qemu_check_nic_model(nd, "smc91c111");
 806     dev = qdev_create(NULL, TYPE_SMC91C111);
 807     qdev_set_nic_properties(dev, nd);
 808     qdev_init_nofail(dev);
 809     s = SYS_BUS_DEVICE(dev);
 810     sysbus_mmio_map(s, 0, base);
 811     sysbus_connect_irq(s, 0, irq);
 812 }
 813
 814 type_init(smc91c111_register_types)