target-ppc/cpu.h

   1 /*
   2  *  PowerPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #if !defined (__CPU_PPC_H__)
  20 #define __CPU_PPC_H__
  21
  22 #include "config.h"
  23 #include "qemu-common.h"
  24
  25 //#define PPC_EMULATE_32BITS_HYPV
  26
  27 #if defined (TARGET_PPC64)
  28 /* PowerPC 64 definitions */
  29 #define TARGET_LONG_BITS 64
  30 #define TARGET_PAGE_BITS 12
  31
  32 #define TARGET_IS_BIENDIAN 1
  33
  34 /* Note that the official physical address space bits is 62-M where M
  35    is implementation dependent.  I've not looked up M for the set of
  36    cpus we emulate at the system level.  */
  37 #define TARGET_PHYS_ADDR_SPACE_BITS 62
  38
  39 /* Note that the PPC environment architecture talks about 80 bit virtual
  40    addresses, with segmentation.  Obviously that's not all visible to a
  41    single process, which is all we're concerned with here.  */
  42 #ifdef TARGET_ABI32
  43 # define TARGET_VIRT_ADDR_SPACE_BITS 32
  44 #else
  45 # define TARGET_VIRT_ADDR_SPACE_BITS 64
  46 #endif
  47
  48 #define TARGET_PAGE_BITS_16M 24
  49
  50 #else /* defined (TARGET_PPC64) */
  51 /* PowerPC 32 definitions */
  52 #define TARGET_LONG_BITS 32
  53
  54 #if defined(TARGET_PPCEMB)
  55 /* Specific definitions for PowerPC embedded */
  56 /* BookE have 36 bits physical address space */
  57 #if defined(CONFIG_USER_ONLY)
  58 /* It looks like a lot of Linux programs assume page size
  59  * is 4kB long. This is evil, but we have to deal with it...
  60  */
  61 #define TARGET_PAGE_BITS 12
  62 #else /* defined(CONFIG_USER_ONLY) */
  63 /* Pages can be 1 kB small */
  64 #define TARGET_PAGE_BITS 10
  65 #endif /* defined(CONFIG_USER_ONLY) */
  66 #else /* defined(TARGET_PPCEMB) */
  67 /* "standard" PowerPC 32 definitions */
  68 #define TARGET_PAGE_BITS 12
  69 #endif /* defined(TARGET_PPCEMB) */
  70
  71 #define TARGET_PHYS_ADDR_SPACE_BITS 36
  72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  73
  74 #endif /* defined (TARGET_PPC64) */
  75
  76 #define CPUArchState struct CPUPPCState
  77
  78 #include "exec/cpu-defs.h"
  79
  80 #include "fpu/softfloat.h"
  81
  82 #define TARGET_HAS_ICE 1
  83
  84 #if defined (TARGET_PPC64)
  85 #define ELF_MACHINE     EM_PPC64
  86 #else
  87 #define ELF_MACHINE     EM_PPC
  88 #endif
  89
  90 /*****************************************************************************/
  91 /* MMU model                                                                 */
  92 typedef enum powerpc_mmu_t powerpc_mmu_t;
  93 enum powerpc_mmu_t {
  94     POWERPC_MMU_UNKNOWN    = 0x00000000,
  95     /* Standard 32 bits PowerPC MMU                            */
  96     POWERPC_MMU_32B        = 0x00000001,
  97     /* PowerPC 6xx MMU with software TLB                       */
  98     POWERPC_MMU_SOFT_6xx   = 0x00000002,
  99     /* PowerPC 74xx MMU with software TLB                      */
 100     POWERPC_MMU_SOFT_74xx  = 0x00000003,
 101     /* PowerPC 4xx MMU with software TLB                       */
 102     POWERPC_MMU_SOFT_4xx   = 0x00000004,
 103     /* PowerPC 4xx MMU with software TLB and zones protections */
 104     POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
 105     /* PowerPC MMU in real mode only                           */
 106     POWERPC_MMU_REAL       = 0x00000006,
 107     /* Freescale MPC8xx MMU model                              */
 108     POWERPC_MMU_MPC8xx     = 0x00000007,
 109     /* BookE MMU model                                         */
 110     POWERPC_MMU_BOOKE      = 0x00000008,
 111     /* BookE 2.06 MMU model                                    */
 112     POWERPC_MMU_BOOKE206   = 0x00000009,
 113     /* PowerPC 601 MMU model (specific BATs format)            */
 114     POWERPC_MMU_601        = 0x0000000A,
 115 #if defined(TARGET_PPC64)
 116 #define POWERPC_MMU_64       0x00010000
 117 #define POWERPC_MMU_1TSEG    0x00020000
 118 #define POWERPC_MMU_AMR      0x00040000
 119     /* 64 bits PowerPC MMU                                     */
 120     POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
 121     /* Architecture 2.06 variant                               */
 122     POWERPC_MMU_2_06       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
 123                              | POWERPC_MMU_AMR | 0x00000003,
 124     /* Architecture 2.06 "degraded" (no 1T segments)           */
 125     POWERPC_MMU_2_06a      = POWERPC_MMU_64 | POWERPC_MMU_AMR
 126                              | 0x00000003,
 127     /* Architecture 2.06 "degraded" (no 1T segments or AMR)    */
 128     POWERPC_MMU_2_06d      = POWERPC_MMU_64 | 0x00000003,
 129 #endif /* defined(TARGET_PPC64) */
 130 };
 131
 132 /*****************************************************************************/
 133 /* Exception model                                                           */
 134 typedef enum powerpc_excp_t powerpc_excp_t;
 135 enum powerpc_excp_t {
 136     POWERPC_EXCP_UNKNOWN   = 0,
 137     /* Standard PowerPC exception model */
 138     POWERPC_EXCP_STD,
 139     /* PowerPC 40x exception model      */
 140     POWERPC_EXCP_40x,
 141     /* PowerPC 601 exception model      */
 142     POWERPC_EXCP_601,
 143     /* PowerPC 602 exception model      */
 144     POWERPC_EXCP_602,
 145     /* PowerPC 603 exception model      */
 146     POWERPC_EXCP_603,
 147     /* PowerPC 603e exception model     */
 148     POWERPC_EXCP_603E,
 149     /* PowerPC G2 exception model       */
 150     POWERPC_EXCP_G2,
 151     /* PowerPC 604 exception model      */
 152     POWERPC_EXCP_604,
 153     /* PowerPC 7x0 exception model      */
 154     POWERPC_EXCP_7x0,
 155     /* PowerPC 7x5 exception model      */
 156     POWERPC_EXCP_7x5,
 157     /* PowerPC 74xx exception model     */
 158     POWERPC_EXCP_74xx,
 159     /* BookE exception model            */
 160     POWERPC_EXCP_BOOKE,
 161 #if defined(TARGET_PPC64)
 162     /* PowerPC 970 exception model      */
 163     POWERPC_EXCP_970,
 164     /* POWER7 exception model           */
 165     POWERPC_EXCP_POWER7,
 166 #endif /* defined(TARGET_PPC64) */
 167 };
 168
 169 /*****************************************************************************/
 170 /* Exception vectors definitions                                             */
 171 enum {
 172     POWERPC_EXCP_NONE    = -1,
 173     /* The 64 first entries are used by the PowerPC embedded specification   */
 174     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
 175     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
 176     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
 177     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
 178     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
 179     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
 180     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
 181     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
 182     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
 183     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
 184     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
 185     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
 186     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
 187     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
 188     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
 189     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
 190     /* Vectors 16 to 31 are reserved                                         */
 191     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
 192     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
 193     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
 194     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
 195     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
 196     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
 197     POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
 198     POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
 199     POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
 200     /* Vectors 42 to 63 are reserved                                         */
 201     /* Exceptions defined in the PowerPC server specification                */
 202     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
 203     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
 204     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
 205     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
 206     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
 207     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
 208     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
 209     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
 210     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
 211     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
 212     /* 40x specific exceptions                                               */
 213     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
 214     /* 601 specific exceptions                                               */
 215     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
 216     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
 217     /* 602 specific exceptions                                               */
 218     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
 219     /* 602/603 specific exceptions                                           */
 220     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
 221     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 222     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 223     /* Exceptions available on most PowerPC                                  */
 224     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 225     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
 226     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
 227     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
 228     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
 229     /* 7xx/74xx specific exceptions                                          */
 230     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
 231     /* 74xx specific exceptions                                              */
 232     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
 233     /* 970FX specific exceptions                                             */
 234     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
 235     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
 236     /* Freescale embedded cores specific exceptions                          */
 237     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
 238     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
 239     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
 240     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
 241     /* VSX Unavailable (Power ISA 2.06 and later)                            */
 242     POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
 243     POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
 244     /* EOL                                                                   */
 245     POWERPC_EXCP_NB       = 96,
 246     /* QEMU exceptions: used internally during code translation              */
 247     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
 248     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
 249     /* QEMU exceptions: special cases we want to stop translation            */
 250     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
 251     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 252     POWERPC_EXCP_STCX         = 0x204 /* Conditional stores in user mode     */
 253 };
 254
 255 /* Exceptions error codes                                                    */
 256 enum {
 257     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 258     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 259     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 260     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 261     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 262     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 263     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 264     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 265     /* FP exceptions                                                         */
 266     POWERPC_EXCP_FP            = 0x10,
 267     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 268     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 269     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 270     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 271     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
 272     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 273     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 274     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 275     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 276     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 277     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 278     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 279     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 280     /* Invalid instruction                                                   */
 281     POWERPC_EXCP_INVAL         = 0x20,
 282     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 283     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 284     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 285     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 286     /* Privileged instruction                                                */
 287     POWERPC_EXCP_PRIV          = 0x30,
 288     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 289     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 290     /* Trap                                                                  */
 291     POWERPC_EXCP_TRAP          = 0x40,
 292 };
 293
 294 /*****************************************************************************/
 295 /* Input pins model                                                          */
 296 typedef enum powerpc_input_t powerpc_input_t;
 297 enum powerpc_input_t {
 298     PPC_FLAGS_INPUT_UNKNOWN = 0,
 299     /* PowerPC 6xx bus                  */
 300     PPC_FLAGS_INPUT_6xx,
 301     /* BookE bus                        */
 302     PPC_FLAGS_INPUT_BookE,
 303     /* PowerPC 405 bus                  */
 304     PPC_FLAGS_INPUT_405,
 305     /* PowerPC 970 bus                  */
 306     PPC_FLAGS_INPUT_970,
 307     /* PowerPC POWER7 bus               */
 308     PPC_FLAGS_INPUT_POWER7,
 309     /* PowerPC 401 bus                  */
 310     PPC_FLAGS_INPUT_401,
 311     /* Freescale RCPU bus               */
 312     PPC_FLAGS_INPUT_RCPU,
 313 };
 314
 315 #define PPC_INPUT(env) (env->bus_model)
 316
 317 /*****************************************************************************/
 318 typedef struct opc_handler_t opc_handler_t;
 319
 320 /*****************************************************************************/
 321 /* Types used to describe some PowerPC registers */
 322 typedef struct CPUPPCState CPUPPCState;
 323 typedef struct ppc_tb_t ppc_tb_t;
 324 typedef struct ppc_spr_t ppc_spr_t;
 325 typedef struct ppc_dcr_t ppc_dcr_t;
 326 typedef union ppc_avr_t ppc_avr_t;
 327 typedef union ppc_tlb_t ppc_tlb_t;
 328
 329 /* SPR access micro-ops generations callbacks */
 330 struct ppc_spr_t {
 331     void (*uea_read)(void *opaque, int gpr_num, int spr_num);
 332     void (*uea_write)(void *opaque, int spr_num, int gpr_num);
 333 #if !defined(CONFIG_USER_ONLY)
 334     void (*oea_read)(void *opaque, int gpr_num, int spr_num);
 335     void (*oea_write)(void *opaque, int spr_num, int gpr_num);
 336     void (*hea_read)(void *opaque, int gpr_num, int spr_num);
 337     void (*hea_write)(void *opaque, int spr_num, int gpr_num);
 338 #endif
 339     const char *name;
 340     target_ulong default_value;
 341 #ifdef CONFIG_KVM
 342     /* We (ab)use the fact that all the SPRs will have ids for the
 343      * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
 344      * don't sync this */
 345     uint64_t one_reg_id;
 346 #endif
 347 };
 348
 349 /* Altivec registers (128 bits) */
 350 union ppc_avr_t {
 351     float32 f[4];
 352     uint8_t u8[16];
 353     uint16_t u16[8];
 354     uint32_t u32[4];
 355     int8_t s8[16];
 356     int16_t s16[8];
 357     int32_t s32[4];
 358     uint64_t u64[2];
 359     int64_t s64[2];
 360 #ifdef CONFIG_INT128
 361     __uint128_t u128;
 362 #endif
 363 };
 364
 365 #if !defined(CONFIG_USER_ONLY)
 366 /* Software TLB cache */
 367 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 368 struct ppc6xx_tlb_t {
 369     target_ulong pte0;
 370     target_ulong pte1;
 371     target_ulong EPN;
 372 };
 373
 374 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 375 struct ppcemb_tlb_t {
 376     uint64_t RPN;
 377     target_ulong EPN;
 378     target_ulong PID;
 379     target_ulong size;
 380     uint32_t prot;
 381     uint32_t attr; /* Storage attributes */
 382 };
 383
 384 typedef struct ppcmas_tlb_t {
 385      uint32_t mas8;
 386      uint32_t mas1;
 387      uint64_t mas2;
 388      uint64_t mas7_3;
 389 } ppcmas_tlb_t;
 390
 391 union ppc_tlb_t {
 392     ppc6xx_tlb_t *tlb6;
 393     ppcemb_tlb_t *tlbe;
 394     ppcmas_tlb_t *tlbm;
 395 };
 396
 397 /* possible TLB variants */
 398 #define TLB_NONE               0
 399 #define TLB_6XX                1
 400 #define TLB_EMB                2
 401 #define TLB_MAS                3
 402 #endif
 403
 404 #define SDR_32_HTABORG         0xFFFF0000UL
 405 #define SDR_32_HTABMASK        0x000001FFUL
 406
 407 #if defined(TARGET_PPC64)
 408 #define SDR_64_HTABORG         0xFFFFFFFFFFFC0000ULL
 409 #define SDR_64_HTABSIZE        0x000000000000001FULL
 410 #endif /* defined(TARGET_PPC64 */
 411
 412 typedef struct ppc_slb_t ppc_slb_t;
 413 struct ppc_slb_t {
 414     uint64_t esid;
 415     uint64_t vsid;
 416 };
 417
 418 #define MAX_SLB_ENTRIES         64
 419 #define SEGMENT_SHIFT_256M      28
 420 #define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
 421
 422 #define SEGMENT_SHIFT_1T        40
 423 #define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
 424
 425
 426 /*****************************************************************************/
 427 /* Machine state register bits definition                                    */
 428 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 429 #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
 430 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 431 #define MSR_SHV  60 /* hypervisor state                               hflags */
 432 #define MSR_TS0  34 /* Transactional state, 2 bits (Book3s)                  */
 433 #define MSR_TS1  33
 434 #define MSR_TM   32 /* Transactional Memory Available (Book3s)               */
 435 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
 436 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 437 #define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
 438 #define MSR_GS   28 /* guest state for BookE                                 */
 439 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 440 #define MSR_VR   25 /* altivec available                            x hflags */
 441 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
 442 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
 443 #define MSR_VSX  23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
 444 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 445 #define MSR_KEY  19 /* key bit on 603e                                       */
 446 #define MSR_POW  18 /* Power management                                      */
 447 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 448 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 449 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
 450 #define MSR_EE   15 /* External interrupt enable                             */
 451 #define MSR_PR   14 /* Problem state                                  hflags */
 452 #define MSR_FP   13 /* Floating point available                       hflags */
 453 #define MSR_ME   12 /* Machine check interrupt enable                        */
 454 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 455 #define MSR_SE   10 /* Single-step trace enable                     x hflags */
 456 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
 457 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
 458 #define MSR_BE   9  /* Branch trace enable                          x hflags */
 459 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 460 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 461 #define MSR_AL   7  /* AL bit on POWER                                       */
 462 #define MSR_EP   6  /* Exception prefix on 601                               */
 463 #define MSR_IR   5  /* Instruction relocate                                  */
 464 #define MSR_DR   4  /* Data relocate                                         */
 465 #define MSR_PE   3  /* Protection enable on 403                              */
 466 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
 467 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 468 #define MSR_RI   1  /* Recoverable interrupt                        1        */
 469 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 470
 471 #define LPCR_ILE (1 << (63-38))
 472 #define LPCR_AIL_SHIFT (63-40)      /* Alternate interrupt location */
 473 #define LPCR_AIL (3 << LPCR_AIL_SHIFT)
 474
 475 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
 476 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
 477 #define msr_shv  ((env->msr >> MSR_SHV)  & 1)
 478 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
 479 #define msr_icm  ((env->msr >> MSR_ICM)  & 1)
 480 #define msr_thv  ((env->msr >> MSR_THV)  & 1)
 481 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
 482 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
 483 #define msr_vr   ((env->msr >> MSR_VR)   & 1)
 484 #define msr_spe  ((env->msr >> MSR_SPE)  & 1)
 485 #define msr_ap   ((env->msr >> MSR_AP)   & 1)
 486 #define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
 487 #define msr_sa   ((env->msr >> MSR_SA)   & 1)
 488 #define msr_key  ((env->msr >> MSR_KEY)  & 1)
 489 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
 490 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
 491 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
 492 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 493 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
 494 #define msr_pr   ((env->msr >> MSR_PR)   & 1)
 495 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 496 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 497 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 498 #define msr_se   ((env->msr >> MSR_SE)   & 1)
 499 #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
 500 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
 501 #define msr_be   ((env->msr >> MSR_BE)   & 1)
 502 #define msr_de   ((env->msr >> MSR_DE)   & 1)
 503 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 504 #define msr_al   ((env->msr >> MSR_AL)   & 1)
 505 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
 506 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
 507 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
 508 #define msr_pe   ((env->msr >> MSR_PE)   & 1)
 509 #define msr_px   ((env->msr >> MSR_PX)   & 1)
 510 #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
 511 #define msr_ri   ((env->msr >> MSR_RI)   & 1)
 512 #define msr_le   ((env->msr >> MSR_LE)   & 1)
 513 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 514 #define msr_tm   ((env->msr >> MSR_TM)   & 1)
 515
 516 /* Hypervisor bit is more specific */
 517 #if defined(TARGET_PPC64)
 518 #define MSR_HVB (1ULL << MSR_SHV)
 519 #define msr_hv  msr_shv
 520 #else
 521 #if defined(PPC_EMULATE_32BITS_HYPV)
 522 #define MSR_HVB (1ULL << MSR_THV)
 523 #define msr_hv  msr_thv
 524 #else
 525 #define MSR_HVB (0ULL)
 526 #define msr_hv  (0)
 527 #endif
 528 #endif
 529
 530 /* Facility Status and Control (FSCR) bits */
 531 #define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
 532 #define FSCR_TAR        (63 - 55) /* Target Address Register */
 533 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
 534 #define FSCR_IC_MASK    (0xFFULL)
 535 #define FSCR_IC_POS     (63 - 7)
 536 #define FSCR_IC_DSCR_SPR3   2
 537 #define FSCR_IC_PMU         3
 538 #define FSCR_IC_BHRB        4
 539 #define FSCR_IC_TM          5
 540 #define FSCR_IC_EBB         7
 541 #define FSCR_IC_TAR         8
 542
 543 /* Exception state register bits definition                                  */
 544 #define ESR_PIL   (1 << (63 - 36)) /* Illegal Instruction                    */
 545 #define ESR_PPR   (1 << (63 - 37)) /* Privileged Instruction                 */
 546 #define ESR_PTR   (1 << (63 - 38)) /* Trap                                   */
 547 #define ESR_FP    (1 << (63 - 39)) /* Floating-Point Operation               */
 548 #define ESR_ST    (1 << (63 - 40)) /* Store Operation                        */
 549 #define ESR_AP    (1 << (63 - 44)) /* Auxiliary Processor Operation          */
 550 #define ESR_PUO   (1 << (63 - 45)) /* Unimplemented Operation                */
 551 #define ESR_BO    (1 << (63 - 46)) /* Byte Ordering                          */
 552 #define ESR_PIE   (1 << (63 - 47)) /* Imprecise exception                    */
 553 #define ESR_DATA  (1 << (63 - 53)) /* Data Access (Embedded page table)      */
 554 #define ESR_TLBI  (1 << (63 - 54)) /* TLB Ineligible (Embedded page table)   */
 555 #define ESR_PT    (1 << (63 - 55)) /* Page Table (Embedded page table)       */
 556 #define ESR_SPV   (1 << (63 - 56)) /* SPE/VMX operation                      */
 557 #define ESR_EPID  (1 << (63 - 57)) /* External Process ID operation          */
 558 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation                          */
 559 #define ESR_MIF   (1 << (63 - 62)) /* Misaligned instruction (VLE)           */
 560
 561 enum {
 562     POWERPC_FLAG_NONE     = 0x00000000,
 563     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 564     POWERPC_FLAG_SPE      = 0x00000001,
 565     POWERPC_FLAG_VRE      = 0x00000002,
 566     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 567     POWERPC_FLAG_TGPR     = 0x00000004,
 568     POWERPC_FLAG_CE       = 0x00000008,
 569     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 570     POWERPC_FLAG_SE       = 0x00000010,
 571     POWERPC_FLAG_DWE      = 0x00000020,
 572     POWERPC_FLAG_UBLE     = 0x00000040,
 573     /* Flag for MSR bit 9 signification (BE/DE)                              */
 574     POWERPC_FLAG_BE       = 0x00000080,
 575     POWERPC_FLAG_DE       = 0x00000100,
 576     /* Flag for MSR bit 2 signification (PX/PMM)                             */
 577     POWERPC_FLAG_PX       = 0x00000200,
 578     POWERPC_FLAG_PMM      = 0x00000400,
 579     /* Flag for special features                                             */
 580     /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
 581     POWERPC_FLAG_RTC_CLK  = 0x00010000,
 582     POWERPC_FLAG_BUS_CLK  = 0x00020000,
 583     /* Has CFAR                                                              */
 584     POWERPC_FLAG_CFAR     = 0x00040000,
 585     /* Has VSX                                                               */
 586     POWERPC_FLAG_VSX      = 0x00080000,
 587 };
 588
 589 /*****************************************************************************/
 590 /* Floating point status and control register                                */
 591 #define FPSCR_FX     31 /* Floating-point exception summary                  */
 592 #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
 593 #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
 594 #define FPSCR_OX     28 /* Floating-point overflow exception                 */
 595 #define FPSCR_UX     27 /* Floating-point underflow exception                */
 596 #define FPSCR_ZX     26 /* Floating-point zero divide exception              */
 597 #define FPSCR_XX     25 /* Floating-point inexact exception                  */
 598 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
 599 #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
 600 #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
 601 #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
 602 #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
 603 #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
 604 #define FPSCR_FR     18 /* Floating-point fraction rounded                   */
 605 #define FPSCR_FI     17 /* Floating-point fraction inexact                   */
 606 #define FPSCR_C      16 /* Floating-point result class descriptor            */
 607 #define FPSCR_FL     15 /* Floating-point less than or negative              */
 608 #define FPSCR_FG     14 /* Floating-point greater than or negative           */
 609 #define FPSCR_FE     13 /* Floating-point equal or zero                      */
 610 #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
 611 #define FPSCR_FPCC   12 /* Floating-point condition code                     */
 612 #define FPSCR_FPRF   12 /* Floating-point result flags                       */
 613 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
 614 #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
 615 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
 616 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
 617 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
 618 #define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
 619 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
 620 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
 621 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
 622 #define FPSCR_RN1    1
 623 #define FPSCR_RN     0  /* Floating-point rounding control                   */
 624 #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
 625 #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
 626 #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
 627 #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
 628 #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
 629 #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
 630 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
 631 #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
 632 #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
 633 #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
 634 #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
 635 #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
 636 #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
 637 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
 638 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
 639 #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
 640 #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
 641 #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
 642 #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
 643 #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
 644 #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
 645 #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
 646 #define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
 647 /* Invalid operation exception summary */
 648 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
 649                                   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
 650                                   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
 651                                   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
 652                                   (1 << FPSCR_VXCVI)))
 653 /* exception summary */
 654 #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
 655 /* enabled exception summary */
 656 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
 657                    0x1F)
 658
 659 /*****************************************************************************/
 660 /* Vector status and control register */
 661 #define VSCR_NJ         16 /* Vector non-java */
 662 #define VSCR_SAT        0 /* Vector saturation */
 663 #define vscr_nj         (((env->vscr) >> VSCR_NJ)       & 0x1)
 664 #define vscr_sat        (((env->vscr) >> VSCR_SAT)      & 0x1)
 665
 666 /*****************************************************************************/
 667 /* BookE e500 MMU registers */
 668
 669 #define MAS0_NV_SHIFT      0
 670 #define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
 671
 672 #define MAS0_WQ_SHIFT      12
 673 #define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
 674 /* Write TLB entry regardless of reservation */
 675 #define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
 676 /* Write TLB entry only already in use */
 677 #define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
 678 /* Clear TLB entry */
 679 #define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
 680
 681 #define MAS0_HES_SHIFT     14
 682 #define MAS0_HES           (1 << MAS0_HES_SHIFT)
 683
 684 #define MAS0_ESEL_SHIFT    16
 685 #define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
 686
 687 #define MAS0_TLBSEL_SHIFT  28
 688 #define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
 689 #define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
 690 #define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
 691 #define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
 692 #define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
 693
 694 #define MAS0_ATSEL_SHIFT   31
 695 #define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
 696 #define MAS0_ATSEL_TLB     0
 697 #define MAS0_ATSEL_LRAT    MAS0_ATSEL
 698
 699 #define MAS1_TSIZE_SHIFT   7
 700 #define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
 701
 702 #define MAS1_TS_SHIFT      12
 703 #define MAS1_TS            (1 << MAS1_TS_SHIFT)
 704
 705 #define MAS1_IND_SHIFT     13
 706 #define MAS1_IND           (1 << MAS1_IND_SHIFT)
 707
 708 #define MAS1_TID_SHIFT     16
 709 #define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
 710
 711 #define MAS1_IPROT_SHIFT   30
 712 #define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
 713
 714 #define MAS1_VALID_SHIFT   31
 715 #define MAS1_VALID         0x80000000
 716
 717 #define MAS2_EPN_SHIFT     12
 718 #define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
 719
 720 #define MAS2_ACM_SHIFT     6
 721 #define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
 722
 723 #define MAS2_VLE_SHIFT     5
 724 #define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
 725
 726 #define MAS2_W_SHIFT       4
 727 #define MAS2_W             (1 << MAS2_W_SHIFT)
 728
 729 #define MAS2_I_SHIFT       3
 730 #define MAS2_I             (1 << MAS2_I_SHIFT)
 731
 732 #define MAS2_M_SHIFT       2
 733 #define MAS2_M             (1 << MAS2_M_SHIFT)
 734
 735 #define MAS2_G_SHIFT       1
 736 #define MAS2_G             (1 << MAS2_G_SHIFT)
 737
 738 #define MAS2_E_SHIFT       0
 739 #define MAS2_E             (1 << MAS2_E_SHIFT)
 740
 741 #define MAS3_RPN_SHIFT     12
 742 #define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
 743
 744 #define MAS3_U0                 0x00000200
 745 #define MAS3_U1                 0x00000100
 746 #define MAS3_U2                 0x00000080
 747 #define MAS3_U3                 0x00000040
 748 #define MAS3_UX                 0x00000020
 749 #define MAS3_SX                 0x00000010
 750 #define MAS3_UW                 0x00000008
 751 #define MAS3_SW                 0x00000004
 752 #define MAS3_UR                 0x00000002
 753 #define MAS3_SR                 0x00000001
 754 #define MAS3_SPSIZE_SHIFT       1
 755 #define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
 756
 757 #define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
 758 #define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
 759 #define MAS4_TIDSELD_MASK       0x00030000
 760 #define MAS4_TIDSELD_PID0       0x00000000
 761 #define MAS4_TIDSELD_PID1       0x00010000
 762 #define MAS4_TIDSELD_PID2       0x00020000
 763 #define MAS4_TIDSELD_PIDZ       0x00030000
 764 #define MAS4_INDD               0x00008000      /* Default IND */
 765 #define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
 766 #define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
 767 #define MAS4_ACMD               0x00000040
 768 #define MAS4_VLED               0x00000020
 769 #define MAS4_WD                 0x00000010
 770 #define MAS4_ID                 0x00000008
 771 #define MAS4_MD                 0x00000004
 772 #define MAS4_GD                 0x00000002
 773 #define MAS4_ED                 0x00000001
 774 #define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
 775 #define MAS4_WIMGED_SHIFT       0
 776
 777 #define MAS5_SGS                0x80000000
 778 #define MAS5_SLPID_MASK         0x00000fff
 779
 780 #define MAS6_SPID0              0x3fff0000
 781 #define MAS6_SPID1              0x00007ffe
 782 #define MAS6_ISIZE(x)           MAS1_TSIZE(x)
 783 #define MAS6_SAS                0x00000001
 784 #define MAS6_SPID               MAS6_SPID0
 785 #define MAS6_SIND               0x00000002      /* Indirect page */
 786 #define MAS6_SIND_SHIFT         1
 787 #define MAS6_SPID_MASK          0x3fff0000
 788 #define MAS6_SPID_SHIFT         16
 789 #define MAS6_ISIZE_MASK         0x00000f80
 790 #define MAS6_ISIZE_SHIFT        7
 791
 792 #define MAS7_RPN                0xffffffff
 793
 794 #define MAS8_TGS                0x80000000
 795 #define MAS8_VF                 0x40000000
 796 #define MAS8_TLBPID             0x00000fff
 797
 798 /* Bit definitions for MMUCFG */
 799 #define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
 800 #define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
 801 #define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
 802 #define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
 803 #define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
 804 #define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
 805 #define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
 806 #define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
 807 #define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
 808
 809 /* Bit definitions for MMUCSR0 */
 810 #define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
 811 #define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
 812 #define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
 813 #define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
 814 #define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
 815                          MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
 816 #define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
 817 #define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
 818 #define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
 819 #define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
 820
 821 /* TLBnCFG encoding */
 822 #define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
 823 #define TLBnCFG_HES             0x00002000      /* HW select supported */
 824 #define TLBnCFG_AVAIL           0x00004000      /* variable page size */
 825 #define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
 826 #define TLBnCFG_GTWE            0x00010000      /* Guest can write */
 827 #define TLBnCFG_IND             0x00020000      /* IND entries supported */
 828 #define TLBnCFG_PT              0x00040000      /* Can load from page table */
 829 #define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
 830 #define TLBnCFG_MINSIZE_SHIFT   20
 831 #define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
 832 #define TLBnCFG_MAXSIZE_SHIFT   16
 833 #define TLBnCFG_ASSOC           0xff000000      /* Associativity */
 834 #define TLBnCFG_ASSOC_SHIFT     24
 835
 836 /* TLBnPS encoding */
 837 #define TLBnPS_4K               0x00000004
 838 #define TLBnPS_8K               0x00000008
 839 #define TLBnPS_16K              0x00000010
 840 #define TLBnPS_32K              0x00000020
 841 #define TLBnPS_64K              0x00000040
 842 #define TLBnPS_128K             0x00000080
 843 #define TLBnPS_256K             0x00000100
 844 #define TLBnPS_512K             0x00000200
 845 #define TLBnPS_1M               0x00000400
 846 #define TLBnPS_2M               0x00000800
 847 #define TLBnPS_4M               0x00001000
 848 #define TLBnPS_8M               0x00002000
 849 #define TLBnPS_16M              0x00004000
 850 #define TLBnPS_32M              0x00008000
 851 #define TLBnPS_64M              0x00010000
 852 #define TLBnPS_128M             0x00020000
 853 #define TLBnPS_256M             0x00040000
 854 #define TLBnPS_512M             0x00080000
 855 #define TLBnPS_1G               0x00100000
 856 #define TLBnPS_2G               0x00200000
 857 #define TLBnPS_4G               0x00400000
 858 #define TLBnPS_8G               0x00800000
 859 #define TLBnPS_16G              0x01000000
 860 #define TLBnPS_32G              0x02000000
 861 #define TLBnPS_64G              0x04000000
 862 #define TLBnPS_128G             0x08000000
 863 #define TLBnPS_256G             0x10000000
 864
 865 /* tlbilx action encoding */
 866 #define TLBILX_T_ALL                    0
 867 #define TLBILX_T_TID                    1
 868 #define TLBILX_T_FULLMATCH              3
 869 #define TLBILX_T_CLASS0                 4
 870 #define TLBILX_T_CLASS1                 5
 871 #define TLBILX_T_CLASS2                 6
 872 #define TLBILX_T_CLASS3                 7
 873
 874 /* BookE 2.06 helper defines */
 875
 876 #define BOOKE206_FLUSH_TLB0    (1 << 0)
 877 #define BOOKE206_FLUSH_TLB1    (1 << 1)
 878 #define BOOKE206_FLUSH_TLB2    (1 << 2)
 879 #define BOOKE206_FLUSH_TLB3    (1 << 3)
 880
 881 /* number of possible TLBs */
 882 #define BOOKE206_MAX_TLBN      4
 883
 884 /*****************************************************************************/
 885 /* Embedded.Processor Control */
 886
 887 #define DBELL_TYPE_SHIFT               27
 888 #define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
 889 #define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
 890 #define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
 891 #define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
 892 #define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
 893 #define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
 894
 895 #define DBELL_BRDCAST                  (1 << 26)
 896 #define DBELL_LPIDTAG_SHIFT            14
 897 #define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
 898 #define DBELL_PIRTAG_MASK              0x3fff
 899
 900 /*****************************************************************************/
 901 /* Segment page size information, used by recent hash MMUs
 902  * The format of this structure mirrors kvm_ppc_smmu_info
 903  */
 904
 905 #define PPC_PAGE_SIZES_MAX_SZ   8
 906
 907 struct ppc_one_page_size {
 908     uint32_t page_shift;  /* Page shift (or 0) */
 909     uint32_t pte_enc;     /* Encoding in the HPTE (>>12) */
 910 };
 911
 912 struct ppc_one_seg_page_size {
 913     uint32_t page_shift;  /* Base page shift of segment (or 0) */
 914     uint32_t slb_enc;     /* SLB encoding for BookS */
 915     struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
 916 };
 917
 918 struct ppc_segment_page_sizes {
 919     struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
 920 };
 921
 922
 923 /*****************************************************************************/
 924 /* The whole PowerPC CPU context */
 925 #define NB_MMU_MODES 3
 926
 927 #define PPC_CPU_OPCODES_LEN          0x40
 928 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
 929
 930 struct CPUPPCState {
 931     /* First are the most commonly used resources
 932      * during translated code execution
 933      */
 934     /* general purpose registers */
 935     target_ulong gpr[32];
 936     /* Storage for GPR MSB, used by the SPE extension */
 937     target_ulong gprh[32];
 938     /* LR */
 939     target_ulong lr;
 940     /* CTR */
 941     target_ulong ctr;
 942     /* condition register */
 943     uint32_t crf[8];
 944 #if defined(TARGET_PPC64)
 945     /* CFAR */
 946     target_ulong cfar;
 947 #endif
 948     /* XER (with SO, OV, CA split out) */
 949     target_ulong xer;
 950     target_ulong so;
 951     target_ulong ov;
 952     target_ulong ca;
 953     /* Reservation address */
 954     target_ulong reserve_addr;
 955     /* Reservation value */
 956     target_ulong reserve_val;
 957     target_ulong reserve_val2;
 958     /* Reservation store address */
 959     target_ulong reserve_ea;
 960     /* Reserved store source register and size */
 961     target_ulong reserve_info;
 962
 963     /* Those ones are used in supervisor mode only */
 964     /* machine state register */
 965     target_ulong msr;
 966     /* temporary general purpose registers */
 967     target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
 968
 969     /* Floating point execution context */
 970     float_status fp_status;
 971     /* floating point registers */
 972     float64 fpr[32];
 973     /* floating point status and control register */
 974     target_ulong fpscr;
 975
 976     /* Next instruction pointer */
 977     target_ulong nip;
 978
 979     int access_type; /* when a memory exception occurs, the access
 980                         type is stored here */
 981
 982     CPU_COMMON
 983
 984     /* MMU context - only relevant for full system emulation */
 985 #if !defined(CONFIG_USER_ONLY)
 986 #if defined(TARGET_PPC64)
 987     /* PowerPC 64 SLB area */
 988     ppc_slb_t slb[MAX_SLB_ENTRIES];
 989     int32_t slb_nr;
 990 #endif
 991     /* segment registers */
 992     hwaddr htab_base;
 993     /* mask used to normalize hash value to PTEG index */
 994     hwaddr htab_mask;
 995     target_ulong sr[32];
 996     /* externally stored hash table */
 997     uint8_t *external_htab;
 998     /* BATs */
 999     uint32_t nb_BATs;
1000     target_ulong DBAT[2][8];
1001     target_ulong IBAT[2][8];
1002     /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1003     int32_t nb_tlb;      /* Total number of TLB                              */
1004     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1005     int nb_ways;     /* Number of ways in the TLB set                        */
1006     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
1007     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1008     int nb_pids;     /* Number of available PID registers                    */
1009     int tlb_type;    /* Type of TLB we're dealing with                       */
1010     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
1011     /* 403 dedicated access protection registers */
1012     target_ulong pb[4];
1013     bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
1014     bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
1015 #endif
1016
1017     /* Other registers */
1018     /* Special purpose registers */
1019     target_ulong spr[1024];
1020     ppc_spr_t spr_cb[1024];
1021     /* Altivec registers */
1022     ppc_avr_t avr[32];
1023     uint32_t vscr;
1024     /* VSX registers */
1025     uint64_t vsr[32];
1026     /* SPE registers */
1027     uint64_t spe_acc;
1028     uint32_t spe_fscr;
1029     /* SPE and Altivec can share a status since they will never be used
1030      * simultaneously */
1031     float_status vec_status;
1032
1033     /* Internal devices resources */
1034     /* Time base and decrementer */
1035     ppc_tb_t *tb_env;
1036     /* Device control registers */
1037     ppc_dcr_t *dcr_env;
1038
1039     int dcache_line_size;
1040     int icache_line_size;
1041
1042     /* Those resources are used during exception processing */
1043     /* CPU model definition */
1044     target_ulong msr_mask;
1045     powerpc_mmu_t mmu_model;
1046     powerpc_excp_t excp_model;
1047     powerpc_input_t bus_model;
1048     int bfd_mach;
1049     uint32_t flags;
1050     uint64_t insns_flags;
1051     uint64_t insns_flags2;
1052 #if defined(TARGET_PPC64)
1053     struct ppc_segment_page_sizes sps;
1054 #endif
1055
1056 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1057     uint64_t vpa_addr;
1058     uint64_t slb_shadow_addr, slb_shadow_size;
1059     uint64_t dtl_addr, dtl_size;
1060 #endif /* TARGET_PPC64 */
1061
1062     int error_code;
1063     uint32_t pending_interrupts;
1064 #if !defined(CONFIG_USER_ONLY)
1065     /* This is the IRQ controller, which is implementation dependent
1066      * and only relevant when emulating a complete machine.
1067      */
1068     uint32_t irq_input_state;
1069     void **irq_inputs;
1070     /* Exception vectors */
1071     target_ulong excp_vectors[POWERPC_EXCP_NB];
1072     target_ulong excp_prefix;
1073     target_ulong ivor_mask;
1074     target_ulong ivpr_mask;
1075     target_ulong hreset_vector;
1076     hwaddr mpic_iack;
1077     /* true when the external proxy facility mode is enabled */
1078     bool mpic_proxy;
1079 #endif
1080
1081     /* Those resources are used only during code translation */
1082     /* opcode handlers */
1083     opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1084
1085     /* Those resources are used only in QEMU core */
1086     target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
1087     target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1088     int mmu_idx;         /* precomputed MMU index to speed up mem accesses */
1089
1090     /* Power management */
1091     int (*check_pow)(CPUPPCState *env);
1092
1093 #if !defined(CONFIG_USER_ONLY)
1094     void *load_info;    /* Holds boot loading state.  */
1095 #endif
1096
1097     /* booke timers */
1098
1099     /* Specifies bit locations of the Time Base used to signal a fixed timer
1100      * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1101      *
1102      * 0 selects the least significant bit.
1103      * 63 selects the most significant bit.
1104      */
1105     uint8_t fit_period[4];
1106     uint8_t wdt_period[4];
1107
1108     /* Transactional memory state */
1109     target_ulong tm_gpr[32];
1110     ppc_avr_t tm_vsr[64];
1111     uint64_t tm_cr;
1112     uint64_t tm_lr;
1113     uint64_t tm_ctr;
1114     uint64_t tm_fpscr;
1115     uint64_t tm_amr;
1116     uint64_t tm_ppr;
1117     uint64_t tm_vrsave;
1118     uint32_t tm_vscr;
1119     uint64_t tm_dscr;
1120     uint64_t tm_tar;
1121 };
1122
1123 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1124 do {                                            \
1125     env->fit_period[0] = (a_);                  \
1126     env->fit_period[1] = (b_);                  \
1127     env->fit_period[2] = (c_);                  \
1128     env->fit_period[3] = (d_);                  \
1129  } while (0)
1130
1131 #define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1132 do {                                            \
1133     env->wdt_period[0] = (a_);                  \
1134     env->wdt_period[1] = (b_);                  \
1135     env->wdt_period[2] = (c_);                  \
1136     env->wdt_period[3] = (d_);                  \
1137  } while (0)
1138
1139 #include "cpu-qom.h"
1140
1141 /*****************************************************************************/
1142 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1143 void ppc_translate_init(void);
1144 void gen_update_current_nip(void *opaque);
1145 int cpu_ppc_exec (CPUPPCState *s);
1146 /* you can call this signal handler from your SIGBUS and SIGSEGV
1147    signal handlers to inform the virtual CPU of exceptions. non zero
1148    is returned if the signal was handled by the virtual CPU.  */
1149 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1150                             void *puc);
1151 #if defined(CONFIG_USER_ONLY)
1152 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1153                              int mmu_idx);
1154 #endif
1155
1156 #if !defined(CONFIG_USER_ONLY)
1157 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1158 #endif /* !defined(CONFIG_USER_ONLY) */
1159 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1160
1161 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1162 int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
1163 int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version);
1164
1165 /* Time-base and decrementer management */
1166 #ifndef NO_CPU_IO_DEFS
1167 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1168 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1169 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1170 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1171 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1172 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1173 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1174 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1175 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1176 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1177 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1178 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1179 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1180 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1181 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1182 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1183 #if !defined(CONFIG_USER_ONLY)
1184 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1185 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1186 target_ulong load_40x_pit (CPUPPCState *env);
1187 void store_40x_pit (CPUPPCState *env, target_ulong val);
1188 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1189 void store_40x_sler (CPUPPCState *env, uint32_t val);
1190 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1191 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1192 void ppc_tlb_invalidate_all (CPUPPCState *env);
1193 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1194 #endif
1195 #endif
1196
1197 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1198
1199 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1200 {
1201     uint64_t gprv;
1202
1203     gprv = env->gpr[gprn];
1204     if (env->flags & POWERPC_FLAG_SPE) {
1205         /* If the CPU implements the SPE extension, we have to get the
1206          * high bits of the GPR from the gprh storage area
1207          */
1208         gprv &= 0xFFFFFFFFULL;
1209         gprv |= (uint64_t)env->gprh[gprn] << 32;
1210     }
1211
1212     return gprv;
1213 }
1214
1215 /* Device control registers */
1216 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1217 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1218
1219 static inline CPUPPCState *cpu_init(const char *cpu_model)
1220 {
1221     PowerPCCPU *cpu = cpu_ppc_init(cpu_model);
1222     if (cpu == NULL) {
1223         return NULL;
1224     }
1225     return &cpu->env;
1226 }
1227
1228 #define cpu_exec cpu_ppc_exec
1229 #define cpu_gen_code cpu_ppc_gen_code
1230 #define cpu_signal_handler cpu_ppc_signal_handler
1231 #define cpu_list ppc_cpu_list
1232
1233 /* MMU modes definitions */
1234 #define MMU_MODE0_SUFFIX _user
1235 #define MMU_MODE1_SUFFIX _kernel
1236 #define MMU_MODE2_SUFFIX _hypv
1237 #define MMU_USER_IDX 0
1238 static inline int cpu_mmu_index (CPUPPCState *env)
1239 {
1240     return env->mmu_idx;
1241 }
1242
1243 #include "exec/cpu-all.h"
1244
1245 /*****************************************************************************/
1246 /* CRF definitions */
1247 #define CRF_LT        3
1248 #define CRF_GT        2
1249 #define CRF_EQ        1
1250 #define CRF_SO        0
1251 #define CRF_CH        (1 << CRF_LT)
1252 #define CRF_CL        (1 << CRF_GT)
1253 #define CRF_CH_OR_CL  (1 << CRF_EQ)
1254 #define CRF_CH_AND_CL (1 << CRF_SO)
1255
1256 /* XER definitions */
1257 #define XER_SO  31
1258 #define XER_OV  30
1259 #define XER_CA  29
1260 #define XER_CMP  8
1261 #define XER_BC   0
1262 #define xer_so  (env->so)
1263 #define xer_ov  (env->ov)
1264 #define xer_ca  (env->ca)
1265 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1266 #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1267
1268 /* SPR definitions */
1269 #define SPR_MQ                (0x000)
1270 #define SPR_XER               (0x001)
1271 #define SPR_601_VRTCU         (0x004)
1272 #define SPR_601_VRTCL         (0x005)
1273 #define SPR_601_UDECR         (0x006)
1274 #define SPR_LR                (0x008)
1275 #define SPR_CTR               (0x009)
1276 #define SPR_UAMR              (0x00C)
1277 #define SPR_DSCR              (0x011)
1278 #define SPR_DSISR             (0x012)
1279 #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
1280 #define SPR_601_RTCU          (0x014)
1281 #define SPR_601_RTCL          (0x015)
1282 #define SPR_DECR              (0x016)
1283 #define SPR_SDR1              (0x019)
1284 #define SPR_SRR0              (0x01A)
1285 #define SPR_SRR1              (0x01B)
1286 #define SPR_CFAR              (0x01C)
1287 #define SPR_AMR               (0x01D)
1288 #define SPR_BOOKE_PID         (0x030)
1289 #define SPR_BOOKE_DECAR       (0x036)
1290 #define SPR_BOOKE_CSRR0       (0x03A)
1291 #define SPR_BOOKE_CSRR1       (0x03B)
1292 #define SPR_BOOKE_DEAR        (0x03D)
1293 #define SPR_BOOKE_ESR         (0x03E)
1294 #define SPR_BOOKE_IVPR        (0x03F)
1295 #define SPR_MPC_EIE           (0x050)
1296 #define SPR_MPC_EID           (0x051)
1297 #define SPR_MPC_NRI           (0x052)
1298 #define SPR_TFHAR             (0x080)
1299 #define SPR_TFIAR             (0x081)
1300 #define SPR_TEXASR            (0x082)
1301 #define SPR_TEXASRU           (0x083)
1302 #define SPR_UCTRL             (0x088)
1303 #define SPR_MPC_CMPA          (0x090)
1304 #define SPR_MPC_CMPB          (0x091)
1305 #define SPR_MPC_CMPC          (0x092)
1306 #define SPR_MPC_CMPD          (0x093)
1307 #define SPR_MPC_ECR           (0x094)
1308 #define SPR_MPC_DER           (0x095)
1309 #define SPR_MPC_COUNTA        (0x096)
1310 #define SPR_MPC_COUNTB        (0x097)
1311 #define SPR_CTRL              (0x098)
1312 #define SPR_MPC_CMPE          (0x098)
1313 #define SPR_MPC_CMPF          (0x099)
1314 #define SPR_FSCR              (0x099)
1315 #define SPR_MPC_CMPG          (0x09A)
1316 #define SPR_MPC_CMPH          (0x09B)
1317 #define SPR_MPC_LCTRL1        (0x09C)
1318 #define SPR_MPC_LCTRL2        (0x09D)
1319 #define SPR_UAMOR             (0x09D)
1320 #define SPR_MPC_ICTRL         (0x09E)
1321 #define SPR_MPC_BAR           (0x09F)
1322 #define SPR_VRSAVE            (0x100)
1323 #define SPR_USPRG0            (0x100)
1324 #define SPR_USPRG1            (0x101)
1325 #define SPR_USPRG2            (0x102)
1326 #define SPR_USPRG3            (0x103)
1327 #define SPR_USPRG4            (0x104)
1328 #define SPR_USPRG5            (0x105)
1329 #define SPR_USPRG6            (0x106)
1330 #define SPR_USPRG7            (0x107)
1331 #define SPR_VTBL              (0x10C)
1332 #define SPR_VTBU              (0x10D)
1333 #define SPR_SPRG0             (0x110)
1334 #define SPR_SPRG1             (0x111)
1335 #define SPR_SPRG2             (0x112)
1336 #define SPR_SPRG3             (0x113)
1337 #define SPR_SPRG4             (0x114)
1338 #define SPR_SCOMC             (0x114)
1339 #define SPR_SPRG5             (0x115)
1340 #define SPR_SCOMD             (0x115)
1341 #define SPR_SPRG6             (0x116)
1342 #define SPR_SPRG7             (0x117)
1343 #define SPR_ASR               (0x118)
1344 #define SPR_EAR               (0x11A)
1345 #define SPR_TBL               (0x11C)
1346 #define SPR_TBU               (0x11D)
1347 #define SPR_TBU40             (0x11E)
1348 #define SPR_SVR               (0x11E)
1349 #define SPR_BOOKE_PIR         (0x11E)
1350 #define SPR_PVR               (0x11F)
1351 #define SPR_HSPRG0            (0x130)
1352 #define SPR_BOOKE_DBSR        (0x130)
1353 #define SPR_HSPRG1            (0x131)
1354 #define SPR_HDSISR            (0x132)
1355 #define SPR_HDAR              (0x133)
1356 #define SPR_BOOKE_EPCR        (0x133)
1357 #define SPR_SPURR             (0x134)
1358 #define SPR_BOOKE_DBCR0       (0x134)
1359 #define SPR_IBCR              (0x135)
1360 #define SPR_PURR              (0x135)
1361 #define SPR_BOOKE_DBCR1       (0x135)
1362 #define SPR_DBCR              (0x136)
1363 #define SPR_HDEC              (0x136)
1364 #define SPR_BOOKE_DBCR2       (0x136)
1365 #define SPR_HIOR              (0x137)
1366 #define SPR_MBAR              (0x137)
1367 #define SPR_RMOR              (0x138)
1368 #define SPR_BOOKE_IAC1        (0x138)
1369 #define SPR_HRMOR             (0x139)
1370 #define SPR_BOOKE_IAC2        (0x139)
1371 #define SPR_HSRR0             (0x13A)
1372 #define SPR_BOOKE_IAC3        (0x13A)
1373 #define SPR_HSRR1             (0x13B)
1374 #define SPR_BOOKE_IAC4        (0x13B)
1375 #define SPR_BOOKE_DAC1        (0x13C)
1376 #define SPR_LPIDR             (0x13D)
1377 #define SPR_DABR2             (0x13D)
1378 #define SPR_BOOKE_DAC2        (0x13D)
1379 #define SPR_BOOKE_DVC1        (0x13E)
1380 #define SPR_LPCR              (0x13E)
1381 #define SPR_BOOKE_DVC2        (0x13F)
1382 #define SPR_BOOKE_TSR         (0x150)
1383 #define SPR_PCR               (0x152)
1384 #define SPR_BOOKE_TCR         (0x154)
1385 #define SPR_BOOKE_TLB0PS      (0x158)
1386 #define SPR_BOOKE_TLB1PS      (0x159)
1387 #define SPR_BOOKE_TLB2PS      (0x15A)
1388 #define SPR_BOOKE_TLB3PS      (0x15B)
1389 #define SPR_BOOKE_MAS7_MAS3   (0x174)
1390 #define SPR_BOOKE_IVOR0       (0x190)
1391 #define SPR_BOOKE_IVOR1       (0x191)
1392 #define SPR_BOOKE_IVOR2       (0x192)
1393 #define SPR_BOOKE_IVOR3       (0x193)
1394 #define SPR_BOOKE_IVOR4       (0x194)
1395 #define SPR_BOOKE_IVOR5       (0x195)
1396 #define SPR_BOOKE_IVOR6       (0x196)
1397 #define SPR_BOOKE_IVOR7       (0x197)
1398 #define SPR_BOOKE_IVOR8       (0x198)
1399 #define SPR_BOOKE_IVOR9       (0x199)
1400 #define SPR_BOOKE_IVOR10      (0x19A)
1401 #define SPR_BOOKE_IVOR11      (0x19B)
1402 #define SPR_BOOKE_IVOR12      (0x19C)
1403 #define SPR_BOOKE_IVOR13      (0x19D)
1404 #define SPR_BOOKE_IVOR14      (0x19E)
1405 #define SPR_BOOKE_IVOR15      (0x19F)
1406 #define SPR_BOOKE_IVOR38      (0x1B0)
1407 #define SPR_BOOKE_IVOR39      (0x1B1)
1408 #define SPR_BOOKE_IVOR40      (0x1B2)
1409 #define SPR_BOOKE_IVOR41      (0x1B3)
1410 #define SPR_BOOKE_IVOR42      (0x1B4)
1411 #define SPR_BOOKE_GIVOR2      (0x1B8)
1412 #define SPR_BOOKE_GIVOR3      (0x1B9)
1413 #define SPR_BOOKE_GIVOR4      (0x1BA)
1414 #define SPR_BOOKE_GIVOR8      (0x1BB)
1415 #define SPR_BOOKE_GIVOR13     (0x1BC)
1416 #define SPR_BOOKE_GIVOR14     (0x1BD)
1417 #define SPR_TIR               (0x1BE)
1418 #define SPR_BOOKE_SPEFSCR     (0x200)
1419 #define SPR_Exxx_BBEAR        (0x201)
1420 #define SPR_Exxx_BBTAR        (0x202)
1421 #define SPR_Exxx_L1CFG0       (0x203)
1422 #define SPR_Exxx_L1CFG1       (0x204)
1423 #define SPR_Exxx_NPIDR        (0x205)
1424 #define SPR_ATBL              (0x20E)
1425 #define SPR_ATBU              (0x20F)
1426 #define SPR_IBAT0U            (0x210)
1427 #define SPR_BOOKE_IVOR32      (0x210)
1428 #define SPR_RCPU_MI_GRA       (0x210)
1429 #define SPR_IBAT0L            (0x211)
1430 #define SPR_BOOKE_IVOR33      (0x211)
1431 #define SPR_IBAT1U            (0x212)
1432 #define SPR_BOOKE_IVOR34      (0x212)
1433 #define SPR_IBAT1L            (0x213)
1434 #define SPR_BOOKE_IVOR35      (0x213)
1435 #define SPR_IBAT2U            (0x214)
1436 #define SPR_BOOKE_IVOR36      (0x214)
1437 #define SPR_IBAT2L            (0x215)
1438 #define SPR_BOOKE_IVOR37      (0x215)
1439 #define SPR_IBAT3U            (0x216)
1440 #define SPR_IBAT3L            (0x217)
1441 #define SPR_DBAT0U            (0x218)
1442 #define SPR_RCPU_L2U_GRA      (0x218)
1443 #define SPR_DBAT0L            (0x219)
1444 #define SPR_DBAT1U            (0x21A)
1445 #define SPR_DBAT1L            (0x21B)
1446 #define SPR_DBAT2U            (0x21C)
1447 #define SPR_DBAT2L            (0x21D)
1448 #define SPR_DBAT3U            (0x21E)
1449 #define SPR_DBAT3L            (0x21F)
1450 #define SPR_IBAT4U            (0x230)
1451 #define SPR_RPCU_BBCMCR       (0x230)
1452 #define SPR_MPC_IC_CST        (0x230)
1453 #define SPR_Exxx_CTXCR        (0x230)
1454 #define SPR_IBAT4L            (0x231)
1455 #define SPR_MPC_IC_ADR        (0x231)
1456 #define SPR_Exxx_DBCR3        (0x231)
1457 #define SPR_IBAT5U            (0x232)
1458 #define SPR_MPC_IC_DAT        (0x232)
1459 #define SPR_Exxx_DBCNT        (0x232)
1460 #define SPR_IBAT5L            (0x233)
1461 #define SPR_IBAT6U            (0x234)
1462 #define SPR_IBAT6L            (0x235)
1463 #define SPR_IBAT7U            (0x236)
1464 #define SPR_IBAT7L            (0x237)
1465 #define SPR_DBAT4U            (0x238)
1466 #define SPR_RCPU_L2U_MCR      (0x238)
1467 #define SPR_MPC_DC_CST        (0x238)
1468 #define SPR_Exxx_ALTCTXCR     (0x238)
1469 #define SPR_DBAT4L            (0x239)
1470 #define SPR_MPC_DC_ADR        (0x239)
1471 #define SPR_DBAT5U            (0x23A)
1472 #define SPR_BOOKE_MCSRR0      (0x23A)
1473 #define SPR_MPC_DC_DAT        (0x23A)
1474 #define SPR_DBAT5L            (0x23B)
1475 #define SPR_BOOKE_MCSRR1      (0x23B)
1476 #define SPR_DBAT6U            (0x23C)
1477 #define SPR_BOOKE_MCSR        (0x23C)
1478 #define SPR_DBAT6L            (0x23D)
1479 #define SPR_Exxx_MCAR         (0x23D)
1480 #define SPR_DBAT7U            (0x23E)
1481 #define SPR_BOOKE_DSRR0       (0x23E)
1482 #define SPR_DBAT7L            (0x23F)
1483 #define SPR_BOOKE_DSRR1       (0x23F)
1484 #define SPR_BOOKE_SPRG8       (0x25C)
1485 #define SPR_BOOKE_SPRG9       (0x25D)
1486 #define SPR_BOOKE_MAS0        (0x270)
1487 #define SPR_BOOKE_MAS1        (0x271)
1488 #define SPR_BOOKE_MAS2        (0x272)
1489 #define SPR_BOOKE_MAS3        (0x273)
1490 #define SPR_BOOKE_MAS4        (0x274)
1491 #define SPR_BOOKE_MAS5        (0x275)
1492 #define SPR_BOOKE_MAS6        (0x276)
1493 #define SPR_BOOKE_PID1        (0x279)
1494 #define SPR_BOOKE_PID2        (0x27A)
1495 #define SPR_MPC_DPDR          (0x280)
1496 #define SPR_MPC_IMMR          (0x288)
1497 #define SPR_BOOKE_TLB0CFG     (0x2B0)
1498 #define SPR_BOOKE_TLB1CFG     (0x2B1)
1499 #define SPR_BOOKE_TLB2CFG     (0x2B2)
1500 #define SPR_BOOKE_TLB3CFG     (0x2B3)
1501 #define SPR_BOOKE_EPR         (0x2BE)
1502 #define SPR_PERF0             (0x300)
1503 #define SPR_RCPU_MI_RBA0      (0x300)
1504 #define SPR_MPC_MI_CTR        (0x300)
1505 #define SPR_PERF1             (0x301)
1506 #define SPR_RCPU_MI_RBA1      (0x301)
1507 #define SPR_POWER_UMMCR2      (0x301)
1508 #define SPR_PERF2             (0x302)
1509 #define SPR_RCPU_MI_RBA2      (0x302)
1510 #define SPR_MPC_MI_AP         (0x302)
1511 #define SPR_POWER_UMMCRA      (0x302)
1512 #define SPR_PERF3             (0x303)
1513 #define SPR_RCPU_MI_RBA3      (0x303)
1514 #define SPR_MPC_MI_EPN        (0x303)
1515 #define SPR_POWER_UPMC1       (0x303)
1516 #define SPR_PERF4             (0x304)
1517 #define SPR_POWER_UPMC2       (0x304)
1518 #define SPR_PERF5             (0x305)
1519 #define SPR_MPC_MI_TWC        (0x305)
1520 #define SPR_POWER_UPMC3       (0x305)
1521 #define SPR_PERF6             (0x306)
1522 #define SPR_MPC_MI_RPN        (0x306)
1523 #define SPR_POWER_UPMC4       (0x306)
1524 #define SPR_PERF7             (0x307)
1525 #define SPR_POWER_UPMC5       (0x307)
1526 #define SPR_PERF8             (0x308)
1527 #define SPR_RCPU_L2U_RBA0     (0x308)
1528 #define SPR_MPC_MD_CTR        (0x308)
1529 #define SPR_POWER_UPMC6       (0x308)
1530 #define SPR_PERF9             (0x309)
1531 #define SPR_RCPU_L2U_RBA1     (0x309)
1532 #define SPR_MPC_MD_CASID      (0x309)
1533 #define SPR_970_UPMC7         (0X309)
1534 #define SPR_PERFA             (0x30A)
1535 #define SPR_RCPU_L2U_RBA2     (0x30A)
1536 #define SPR_MPC_MD_AP         (0x30A)
1537 #define SPR_970_UPMC8         (0X30A)
1538 #define SPR_PERFB             (0x30B)
1539 #define SPR_RCPU_L2U_RBA3     (0x30B)
1540 #define SPR_MPC_MD_EPN        (0x30B)
1541 #define SPR_POWER_UMMCR0      (0X30B)
1542 #define SPR_PERFC             (0x30C)
1543 #define SPR_MPC_MD_TWB        (0x30C)
1544 #define SPR_POWER_USIAR       (0X30C)
1545 #define SPR_PERFD             (0x30D)
1546 #define SPR_MPC_MD_TWC        (0x30D)
1547 #define SPR_POWER_USDAR       (0X30D)
1548 #define SPR_PERFE             (0x30E)
1549 #define SPR_MPC_MD_RPN        (0x30E)
1550 #define SPR_POWER_UMMCR1      (0X30E)
1551 #define SPR_PERFF             (0x30F)
1552 #define SPR_MPC_MD_TW         (0x30F)
1553 #define SPR_UPERF0            (0x310)
1554 #define SPR_UPERF1            (0x311)
1555 #define SPR_POWER_MMCR2       (0x311)
1556 #define SPR_UPERF2            (0x312)
1557 #define SPR_POWER_MMCRA       (0X312)
1558 #define SPR_UPERF3            (0x313)
1559 #define SPR_POWER_PMC1        (0X313)
1560 #define SPR_UPERF4            (0x314)
1561 #define SPR_POWER_PMC2        (0X314)
1562 #define SPR_UPERF5            (0x315)
1563 #define SPR_POWER_PMC3        (0X315)
1564 #define SPR_UPERF6            (0x316)
1565 #define SPR_POWER_PMC4        (0X316)
1566 #define SPR_UPERF7            (0x317)
1567 #define SPR_POWER_PMC5        (0X317)
1568 #define SPR_UPERF8            (0x318)
1569 #define SPR_POWER_PMC6        (0X318)
1570 #define SPR_UPERF9            (0x319)
1571 #define SPR_970_PMC7          (0X319)
1572 #define SPR_UPERFA            (0x31A)
1573 #define SPR_970_PMC8          (0X31A)
1574 #define SPR_UPERFB            (0x31B)
1575 #define SPR_POWER_MMCR0       (0X31B)
1576 #define SPR_UPERFC            (0x31C)
1577 #define SPR_POWER_SIAR        (0X31C)
1578 #define SPR_UPERFD            (0x31D)
1579 #define SPR_POWER_SDAR        (0X31D)
1580 #define SPR_UPERFE            (0x31E)
1581 #define SPR_POWER_MMCR1       (0X31E)
1582 #define SPR_UPERFF            (0x31F)
1583 #define SPR_RCPU_MI_RA0       (0x320)
1584 #define SPR_MPC_MI_DBCAM      (0x320)
1585 #define SPR_BESCRS            (0x320)
1586 #define SPR_RCPU_MI_RA1       (0x321)
1587 #define SPR_MPC_MI_DBRAM0     (0x321)
1588 #define SPR_BESCRSU           (0x321)
1589 #define SPR_RCPU_MI_RA2       (0x322)
1590 #define SPR_MPC_MI_DBRAM1     (0x322)
1591 #define SPR_BESCRR            (0x322)
1592 #define SPR_RCPU_MI_RA3       (0x323)
1593 #define SPR_BESCRRU           (0x323)
1594 #define SPR_EBBHR             (0x324)
1595 #define SPR_EBBRR             (0x325)
1596 #define SPR_BESCR             (0x326)
1597 #define SPR_RCPU_L2U_RA0      (0x328)
1598 #define SPR_MPC_MD_DBCAM      (0x328)
1599 #define SPR_RCPU_L2U_RA1      (0x329)
1600 #define SPR_MPC_MD_DBRAM0     (0x329)
1601 #define SPR_RCPU_L2U_RA2      (0x32A)
1602 #define SPR_MPC_MD_DBRAM1     (0x32A)
1603 #define SPR_RCPU_L2U_RA3      (0x32B)
1604 #define SPR_TAR               (0x32F)
1605 #define SPR_440_INV0          (0x370)
1606 #define SPR_440_INV1          (0x371)
1607 #define SPR_440_INV2          (0x372)
1608 #define SPR_440_INV3          (0x373)
1609 #define SPR_440_ITV0          (0x374)
1610 #define SPR_440_ITV1          (0x375)
1611 #define SPR_440_ITV2          (0x376)
1612 #define SPR_440_ITV3          (0x377)
1613 #define SPR_440_CCR1          (0x378)
1614 #define SPR_DCRIPR            (0x37B)
1615 #define SPR_POWER_MMCRS       (0x37E)
1616 #define SPR_PPR               (0x380)
1617 #define SPR_750_GQR0          (0x390)
1618 #define SPR_440_DNV0          (0x390)
1619 #define SPR_750_GQR1          (0x391)
1620 #define SPR_440_DNV1          (0x391)
1621 #define SPR_750_GQR2          (0x392)
1622 #define SPR_440_DNV2          (0x392)
1623 #define SPR_750_GQR3          (0x393)
1624 #define SPR_440_DNV3          (0x393)
1625 #define SPR_750_GQR4          (0x394)
1626 #define SPR_440_DTV0          (0x394)
1627 #define SPR_750_GQR5          (0x395)
1628 #define SPR_440_DTV1          (0x395)
1629 #define SPR_750_GQR6          (0x396)
1630 #define SPR_440_DTV2          (0x396)
1631 #define SPR_750_GQR7          (0x397)
1632 #define SPR_440_DTV3          (0x397)
1633 #define SPR_750_THRM4         (0x398)
1634 #define SPR_750CL_HID2        (0x398)
1635 #define SPR_440_DVLIM         (0x398)
1636 #define SPR_750_WPAR          (0x399)
1637 #define SPR_440_IVLIM         (0x399)
1638 #define SPR_750_DMAU          (0x39A)
1639 #define SPR_750_DMAL          (0x39B)
1640 #define SPR_440_RSTCFG        (0x39B)
1641 #define SPR_BOOKE_DCDBTRL     (0x39C)
1642 #define SPR_BOOKE_DCDBTRH     (0x39D)
1643 #define SPR_BOOKE_ICDBTRL     (0x39E)
1644 #define SPR_BOOKE_ICDBTRH     (0x39F)
1645 #define SPR_74XX_UMMCR2       (0x3A0)
1646 #define SPR_7XX_UPMC5         (0x3A1)
1647 #define SPR_7XX_UPMC6         (0x3A2)
1648 #define SPR_UBAMR             (0x3A7)
1649 #define SPR_7XX_UMMCR0        (0x3A8)
1650 #define SPR_7XX_UPMC1         (0x3A9)
1651 #define SPR_7XX_UPMC2         (0x3AA)
1652 #define SPR_7XX_USIAR         (0x3AB)
1653 #define SPR_7XX_UMMCR1        (0x3AC)
1654 #define SPR_7XX_UPMC3         (0x3AD)
1655 #define SPR_7XX_UPMC4         (0x3AE)
1656 #define SPR_USDA              (0x3AF)
1657 #define SPR_40x_ZPR           (0x3B0)
1658 #define SPR_BOOKE_MAS7        (0x3B0)
1659 #define SPR_74XX_MMCR2        (0x3B0)
1660 #define SPR_7XX_PMC5          (0x3B1)
1661 #define SPR_40x_PID           (0x3B1)
1662 #define SPR_7XX_PMC6          (0x3B2)
1663 #define SPR_440_MMUCR         (0x3B2)
1664 #define SPR_4xx_CCR0          (0x3B3)
1665 #define SPR_BOOKE_EPLC        (0x3B3)
1666 #define SPR_405_IAC3          (0x3B4)
1667 #define SPR_BOOKE_EPSC        (0x3B4)
1668 #define SPR_405_IAC4          (0x3B5)
1669 #define SPR_405_DVC1          (0x3B6)
1670 #define SPR_405_DVC2          (0x3B7)
1671 #define SPR_BAMR              (0x3B7)
1672 #define SPR_7XX_MMCR0         (0x3B8)
1673 #define SPR_7XX_PMC1          (0x3B9)
1674 #define SPR_40x_SGR           (0x3B9)
1675 #define SPR_7XX_PMC2          (0x3BA)
1676 #define SPR_40x_DCWR          (0x3BA)
1677 #define SPR_7XX_SIAR          (0x3BB)
1678 #define SPR_405_SLER          (0x3BB)
1679 #define SPR_7XX_MMCR1         (0x3BC)
1680 #define SPR_405_SU0R          (0x3BC)
1681 #define SPR_401_SKR           (0x3BC)
1682 #define SPR_7XX_PMC3          (0x3BD)
1683 #define SPR_405_DBCR1         (0x3BD)
1684 #define SPR_7XX_PMC4          (0x3BE)
1685 #define SPR_SDA               (0x3BF)
1686 #define SPR_403_VTBL          (0x3CC)
1687 #define SPR_403_VTBU          (0x3CD)
1688 #define SPR_DMISS             (0x3D0)
1689 #define SPR_DCMP              (0x3D1)
1690 #define SPR_HASH1             (0x3D2)
1691 #define SPR_HASH2             (0x3D3)
1692 #define SPR_BOOKE_ICDBDR      (0x3D3)
1693 #define SPR_TLBMISS           (0x3D4)
1694 #define SPR_IMISS             (0x3D4)
1695 #define SPR_40x_ESR           (0x3D4)
1696 #define SPR_PTEHI             (0x3D5)
1697 #define SPR_ICMP              (0x3D5)
1698 #define SPR_40x_DEAR          (0x3D5)
1699 #define SPR_PTELO             (0x3D6)
1700 #define SPR_RPA               (0x3D6)
1701 #define SPR_40x_EVPR          (0x3D6)
1702 #define SPR_L3PM              (0x3D7)
1703 #define SPR_403_CDBCR         (0x3D7)
1704 #define SPR_L3ITCR0           (0x3D8)
1705 #define SPR_TCR               (0x3D8)
1706 #define SPR_40x_TSR           (0x3D8)
1707 #define SPR_IBR               (0x3DA)
1708 #define SPR_40x_TCR           (0x3DA)
1709 #define SPR_ESASRR            (0x3DB)
1710 #define SPR_40x_PIT           (0x3DB)
1711 #define SPR_403_TBL           (0x3DC)
1712 #define SPR_403_TBU           (0x3DD)
1713 #define SPR_SEBR              (0x3DE)
1714 #define SPR_40x_SRR2          (0x3DE)
1715 #define SPR_SER               (0x3DF)
1716 #define SPR_40x_SRR3          (0x3DF)
1717 #define SPR_L3OHCR            (0x3E8)
1718 #define SPR_L3ITCR1           (0x3E9)
1719 #define SPR_L3ITCR2           (0x3EA)
1720 #define SPR_L3ITCR3           (0x3EB)
1721 #define SPR_HID0              (0x3F0)
1722 #define SPR_40x_DBSR          (0x3F0)
1723 #define SPR_HID1              (0x3F1)
1724 #define SPR_IABR              (0x3F2)
1725 #define SPR_40x_DBCR0         (0x3F2)
1726 #define SPR_601_HID2          (0x3F2)
1727 #define SPR_Exxx_L1CSR0       (0x3F2)
1728 #define SPR_ICTRL             (0x3F3)
1729 #define SPR_HID2              (0x3F3)
1730 #define SPR_750CL_HID4        (0x3F3)
1731 #define SPR_Exxx_L1CSR1       (0x3F3)
1732 #define SPR_440_DBDR          (0x3F3)
1733 #define SPR_LDSTDB            (0x3F4)
1734 #define SPR_750_TDCL          (0x3F4)
1735 #define SPR_40x_IAC1          (0x3F4)
1736 #define SPR_MMUCSR0           (0x3F4)
1737 #define SPR_970_HID4          (0x3F4)
1738 #define SPR_DABR              (0x3F5)
1739 #define DABR_MASK (~(target_ulong)0x7)
1740 #define SPR_Exxx_BUCSR        (0x3F5)
1741 #define SPR_40x_IAC2          (0x3F5)
1742 #define SPR_601_HID5          (0x3F5)
1743 #define SPR_40x_DAC1          (0x3F6)
1744 #define SPR_MSSCR0            (0x3F6)
1745 #define SPR_970_HID5          (0x3F6)
1746 #define SPR_MSSSR0            (0x3F7)
1747 #define SPR_MSSCR1            (0x3F7)
1748 #define SPR_DABRX             (0x3F7)
1749 #define SPR_40x_DAC2          (0x3F7)
1750 #define SPR_MMUCFG            (0x3F7)
1751 #define SPR_LDSTCR            (0x3F8)
1752 #define SPR_L2PMCR            (0x3F8)
1753 #define SPR_750FX_HID2        (0x3F8)
1754 #define SPR_Exxx_L1FINV0      (0x3F8)
1755 #define SPR_L2CR              (0x3F9)
1756 #define SPR_L3CR              (0x3FA)
1757 #define SPR_750_TDCH          (0x3FA)
1758 #define SPR_IABR2             (0x3FA)
1759 #define SPR_40x_DCCR          (0x3FA)
1760 #define SPR_ICTC              (0x3FB)
1761 #define SPR_40x_ICCR          (0x3FB)
1762 #define SPR_THRM1             (0x3FC)
1763 #define SPR_403_PBL1          (0x3FC)
1764 #define SPR_SP                (0x3FD)
1765 #define SPR_THRM2             (0x3FD)
1766 #define SPR_403_PBU1          (0x3FD)
1767 #define SPR_604_HID13         (0x3FD)
1768 #define SPR_LT                (0x3FE)
1769 #define SPR_THRM3             (0x3FE)
1770 #define SPR_RCPU_FPECR        (0x3FE)
1771 #define SPR_403_PBL2          (0x3FE)
1772 #define SPR_PIR               (0x3FF)
1773 #define SPR_403_PBU2          (0x3FF)
1774 #define SPR_601_HID15         (0x3FF)
1775 #define SPR_604_HID15         (0x3FF)
1776 #define SPR_E500_SVR          (0x3FF)
1777
1778 /* Disable MAS Interrupt Updates for Hypervisor */
1779 #define EPCR_DMIUH            (1 << 22)
1780 /* Disable Guest TLB Management Instructions */
1781 #define EPCR_DGTMI            (1 << 23)
1782 /* Guest Interrupt Computation Mode */
1783 #define EPCR_GICM             (1 << 24)
1784 /* Interrupt Computation Mode */
1785 #define EPCR_ICM              (1 << 25)
1786 /* Disable Embedded Hypervisor Debug */
1787 #define EPCR_DUVD             (1 << 26)
1788 /* Instruction Storage Interrupt Directed to Guest State */
1789 #define EPCR_ISIGS            (1 << 27)
1790 /* Data Storage Interrupt Directed to Guest State */
1791 #define EPCR_DSIGS            (1 << 28)
1792 /* Instruction TLB Error Interrupt Directed to Guest State */
1793 #define EPCR_ITLBGS           (1 << 29)
1794 /* Data TLB Error Interrupt Directed to Guest State */
1795 #define EPCR_DTLBGS           (1 << 30)
1796 /* External Input Interrupt Directed to Guest State */
1797 #define EPCR_EXTGS            (1 << 31)
1798
1799 #define   L1CSR0_CPE            0x00010000      /* Data Cache Parity Enable */
1800 #define   L1CSR0_CUL            0x00000400      /* (D-)Cache Unable to Lock */
1801 #define   L1CSR0_DCLFR          0x00000100      /* D-Cache Lock Flash Reset */
1802 #define   L1CSR0_DCFI           0x00000002      /* Data Cache Flash Invalidate */
1803 #define   L1CSR0_DCE            0x00000001      /* Data Cache Enable */
1804
1805 #define   L1CSR1_CPE            0x00010000      /* Instruction Cache Parity Enable */
1806 #define   L1CSR1_ICUL           0x00000400      /* I-Cache Unable to Lock */
1807 #define   L1CSR1_ICLFR          0x00000100      /* I-Cache Lock Flash Reset */
1808 #define   L1CSR1_ICFI           0x00000002      /* Instruction Cache Flash Invalidate */
1809 #define   L1CSR1_ICE            0x00000001      /* Instruction Cache Enable */
1810
1811 /* HID0 bits */
1812 #define HID0_DEEPNAP        (1 << 24)
1813 #define HID0_DOZE           (1 << 23)
1814 #define HID0_NAP            (1 << 22)
1815
1816 /*****************************************************************************/
1817 /* PowerPC Instructions types definitions                                    */
1818 enum {
1819     PPC_NONE           = 0x0000000000000000ULL,
1820     /* PowerPC base instructions set                                         */
1821     PPC_INSNS_BASE     = 0x0000000000000001ULL,
1822     /*   integer operations instructions                                     */
1823 #define PPC_INTEGER PPC_INSNS_BASE
1824     /*   flow control instructions                                           */
1825 #define PPC_FLOW    PPC_INSNS_BASE
1826     /*   virtual memory instructions                                         */
1827 #define PPC_MEM     PPC_INSNS_BASE
1828     /*   ld/st with reservation instructions                                 */
1829 #define PPC_RES     PPC_INSNS_BASE
1830     /*   spr/msr access instructions                                         */
1831 #define PPC_MISC    PPC_INSNS_BASE
1832     /* Deprecated instruction sets                                           */
1833     /*   Original POWER instruction set                                      */
1834     PPC_POWER          = 0x0000000000000002ULL,
1835     /*   POWER2 instruction set extension                                    */
1836     PPC_POWER2         = 0x0000000000000004ULL,
1837     /*   Power RTC support                                                   */
1838     PPC_POWER_RTC      = 0x0000000000000008ULL,
1839     /*   Power-to-PowerPC bridge (601)                                       */
1840     PPC_POWER_BR       = 0x0000000000000010ULL,
1841     /* 64 bits PowerPC instruction set                                       */
1842     PPC_64B            = 0x0000000000000020ULL,
1843     /*   New 64 bits extensions (PowerPC 2.0x)                               */
1844     PPC_64BX           = 0x0000000000000040ULL,
1845     /*   64 bits hypervisor extensions                                       */
1846     PPC_64H            = 0x0000000000000080ULL,
1847     /*   New wait instruction (PowerPC 2.0x)                                 */
1848     PPC_WAIT           = 0x0000000000000100ULL,
1849     /*   Time base mftb instruction                                          */
1850     PPC_MFTB           = 0x0000000000000200ULL,
1851
1852     /* Fixed-point unit extensions                                           */
1853     /*   PowerPC 602 specific                                                */
1854     PPC_602_SPEC       = 0x0000000000000400ULL,
1855     /*   isel instruction                                                    */
1856     PPC_ISEL           = 0x0000000000000800ULL,
1857     /*   popcntb instruction                                                 */
1858     PPC_POPCNTB        = 0x0000000000001000ULL,
1859     /*   string load / store                                                 */
1860     PPC_STRING         = 0x0000000000002000ULL,
1861
1862     /* Floating-point unit extensions                                        */
1863     /*   Optional floating point instructions                                */
1864     PPC_FLOAT          = 0x0000000000010000ULL,
1865     /* New floating-point extensions (PowerPC 2.0x)                          */
1866     PPC_FLOAT_EXT      = 0x0000000000020000ULL,
1867     PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
1868     PPC_FLOAT_FRES     = 0x0000000000080000ULL,
1869     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
1870     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1871     PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
1872     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
1873
1874     /* Vector/SIMD extensions                                                */
1875     /*   Altivec support                                                     */
1876     PPC_ALTIVEC        = 0x0000000001000000ULL,
1877     /*   PowerPC 2.03 SPE extension                                          */
1878     PPC_SPE            = 0x0000000002000000ULL,
1879     /*   PowerPC 2.03 SPE single-precision floating-point extension          */
1880     PPC_SPE_SINGLE     = 0x0000000004000000ULL,
1881     /*   PowerPC 2.03 SPE double-precision floating-point extension          */
1882     PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
1883
1884     /* Optional memory control instructions                                  */
1885     PPC_MEM_TLBIA      = 0x0000000010000000ULL,
1886     PPC_MEM_TLBIE      = 0x0000000020000000ULL,
1887     PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
1888     /*   sync instruction                                                    */
1889     PPC_MEM_SYNC       = 0x0000000080000000ULL,
1890     /*   eieio instruction                                                   */
1891     PPC_MEM_EIEIO      = 0x0000000100000000ULL,
1892
1893     /* Cache control instructions                                            */
1894     PPC_CACHE          = 0x0000000200000000ULL,
1895     /*   icbi instruction                                                    */
1896     PPC_CACHE_ICBI     = 0x0000000400000000ULL,
1897     /*   dcbz instruction                                                    */
1898     PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
1899     /*   dcba instruction                                                    */
1900     PPC_CACHE_DCBA     = 0x0000002000000000ULL,
1901     /*   Freescale cache locking instructions                                */
1902     PPC_CACHE_LOCK     = 0x0000004000000000ULL,
1903
1904     /* MMU related extensions                                                */
1905     /*   external control instructions                                       */
1906     PPC_EXTERN         = 0x0000010000000000ULL,
1907     /*   segment register access instructions                                */
1908     PPC_SEGMENT        = 0x0000020000000000ULL,
1909     /*   PowerPC 6xx TLB management instructions                             */
1910     PPC_6xx_TLB        = 0x0000040000000000ULL,
1911     /* PowerPC 74xx TLB management instructions                              */
1912     PPC_74xx_TLB       = 0x0000080000000000ULL,
1913     /*   PowerPC 40x TLB management instructions                             */
1914     PPC_40x_TLB        = 0x0000100000000000ULL,
1915     /*   segment register access instructions for PowerPC 64 "bridge"        */
1916     PPC_SEGMENT_64B    = 0x0000200000000000ULL,
1917     /*   SLB management                                                      */
1918     PPC_SLBI           = 0x0000400000000000ULL,
1919
1920     /* Embedded PowerPC dedicated instructions                               */
1921     PPC_WRTEE          = 0x0001000000000000ULL,
1922     /* PowerPC 40x exception model                                           */
1923     PPC_40x_EXCP       = 0x0002000000000000ULL,
1924     /* PowerPC 405 Mac instructions                                          */
1925     PPC_405_MAC        = 0x0004000000000000ULL,
1926     /* PowerPC 440 specific instructions                                     */
1927     PPC_440_SPEC       = 0x0008000000000000ULL,
1928     /* BookE (embedded) PowerPC specification                                */
1929     PPC_BOOKE          = 0x0010000000000000ULL,
1930     /* mfapidi instruction                                                   */
1931     PPC_MFAPIDI        = 0x0020000000000000ULL,
1932     /* tlbiva instruction                                                    */
1933     PPC_TLBIVA         = 0x0040000000000000ULL,
1934     /* tlbivax instruction                                                   */
1935     PPC_TLBIVAX        = 0x0080000000000000ULL,
1936     /* PowerPC 4xx dedicated instructions                                    */
1937     PPC_4xx_COMMON     = 0x0100000000000000ULL,
1938     /* PowerPC 40x ibct instructions                                         */
1939     PPC_40x_ICBT       = 0x0200000000000000ULL,
1940     /* rfmci is not implemented in all BookE PowerPC                         */
1941     PPC_RFMCI          = 0x0400000000000000ULL,
1942     /* rfdi instruction                                                      */
1943     PPC_RFDI           = 0x0800000000000000ULL,
1944     /* DCR accesses                                                          */
1945     PPC_DCR            = 0x1000000000000000ULL,
1946     /* DCR extended accesse                                                  */
1947     PPC_DCRX           = 0x2000000000000000ULL,
1948     /* user-mode DCR access, implemented in PowerPC 460                      */
1949     PPC_DCRUX          = 0x4000000000000000ULL,
1950     /* popcntw and popcntd instructions                                      */
1951     PPC_POPCNTWD       = 0x8000000000000000ULL,
1952
1953 #define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1954                         | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1955                         | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1956                         | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1957                         | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1958                         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1959                         | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1960                         | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1961                         | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1962                         | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1963                         | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1964                         | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1965                         | PPC_CACHE | PPC_CACHE_ICBI \
1966                         | PPC_CACHE_DCBZ \
1967                         | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1968                         | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1969                         | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1970                         | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1971                         | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1972                         | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1973                         | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1974                         | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1975                         | PPC_POPCNTWD)
1976
1977     /* extended type values */
1978
1979     /* BookE 2.06 PowerPC specification                                      */
1980     PPC2_BOOKE206      = 0x0000000000000001ULL,
1981     /* VSX (extensions to Altivec / VMX)                                     */
1982     PPC2_VSX           = 0x0000000000000002ULL,
1983     /* Decimal Floating Point (DFP)                                          */
1984     PPC2_DFP           = 0x0000000000000004ULL,
1985     /* Embedded.Processor Control                                            */
1986     PPC2_PRCNTL        = 0x0000000000000008ULL,
1987     /* Byte-reversed, indexed, double-word load and store                    */
1988     PPC2_DBRX          = 0x0000000000000010ULL,
1989     /* Book I 2.05 PowerPC specification                                     */
1990     PPC2_ISA205        = 0x0000000000000020ULL,
1991     /* VSX additions in ISA 2.07                                             */
1992     PPC2_VSX207        = 0x0000000000000040ULL,
1993     /* ISA 2.06B bpermd                                                      */
1994     PPC2_PERM_ISA206   = 0x0000000000000080ULL,
1995     /* ISA 2.06B divide extended variants                                    */
1996     PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
1997     /* ISA 2.06B larx/stcx. instructions                                     */
1998     PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
1999     /* ISA 2.06B floating point integer conversion                           */
2000     PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2001     /* ISA 2.06B floating point test instructions                            */
2002     PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2003     /* ISA 2.07 bctar instruction                                            */
2004     PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
2005     /* ISA 2.07 load/store quadword                                          */
2006     PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
2007     /* ISA 2.07 Altivec                                                      */
2008     PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
2009     /* PowerISA 2.07 Book3s specification                                    */
2010     PPC2_ISA207S       = 0x0000000000008000ULL,
2011     /* Double precision floating point conversion for signed integer 64      */
2012     PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
2013
2014 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2015                         PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2016                         PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2017                         PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2018                         PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2019                         PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2020                         PPC2_FP_CVT_S64)
2021 };
2022
2023 /*****************************************************************************/
2024 /* Memory access type :
2025  * may be needed for precise access rights control and precise exceptions.
2026  */
2027 enum {
2028     /* 1 bit to define user level / supervisor access */
2029     ACCESS_USER  = 0x00,
2030     ACCESS_SUPER = 0x01,
2031     /* Type of instruction that generated the access */
2032     ACCESS_CODE  = 0x10, /* Code fetch access                */
2033     ACCESS_INT   = 0x20, /* Integer load/store access        */
2034     ACCESS_FLOAT = 0x30, /* floating point load/store access */
2035     ACCESS_RES   = 0x40, /* load/store with reservation      */
2036     ACCESS_EXT   = 0x50, /* external access                  */
2037     ACCESS_CACHE = 0x60, /* Cache manipulation               */
2038 };
2039
2040 /* Hardware interruption sources:
2041  * all those exception can be raised simulteaneously
2042  */
2043 /* Input pins definitions */
2044 enum {
2045     /* 6xx bus input pins */
2046     PPC6xx_INPUT_HRESET     = 0,
2047     PPC6xx_INPUT_SRESET     = 1,
2048     PPC6xx_INPUT_CKSTP_IN   = 2,
2049     PPC6xx_INPUT_MCP        = 3,
2050     PPC6xx_INPUT_SMI        = 4,
2051     PPC6xx_INPUT_INT        = 5,
2052     PPC6xx_INPUT_TBEN       = 6,
2053     PPC6xx_INPUT_WAKEUP     = 7,
2054     PPC6xx_INPUT_NB,
2055 };
2056
2057 enum {
2058     /* Embedded PowerPC input pins */
2059     PPCBookE_INPUT_HRESET     = 0,
2060     PPCBookE_INPUT_SRESET     = 1,
2061     PPCBookE_INPUT_CKSTP_IN   = 2,
2062     PPCBookE_INPUT_MCP        = 3,
2063     PPCBookE_INPUT_SMI        = 4,
2064     PPCBookE_INPUT_INT        = 5,
2065     PPCBookE_INPUT_CINT       = 6,
2066     PPCBookE_INPUT_NB,
2067 };
2068
2069 enum {
2070     /* PowerPC E500 input pins */
2071     PPCE500_INPUT_RESET_CORE = 0,
2072     PPCE500_INPUT_MCK        = 1,
2073     PPCE500_INPUT_CINT       = 3,
2074     PPCE500_INPUT_INT        = 4,
2075     PPCE500_INPUT_DEBUG      = 6,
2076     PPCE500_INPUT_NB,
2077 };
2078
2079 enum {
2080     /* PowerPC 40x input pins */
2081     PPC40x_INPUT_RESET_CORE = 0,
2082     PPC40x_INPUT_RESET_CHIP = 1,
2083     PPC40x_INPUT_RESET_SYS  = 2,
2084     PPC40x_INPUT_CINT       = 3,
2085     PPC40x_INPUT_INT        = 4,
2086     PPC40x_INPUT_HALT       = 5,
2087     PPC40x_INPUT_DEBUG      = 6,
2088     PPC40x_INPUT_NB,
2089 };
2090
2091 enum {
2092     /* RCPU input pins */
2093     PPCRCPU_INPUT_PORESET   = 0,
2094     PPCRCPU_INPUT_HRESET    = 1,
2095     PPCRCPU_INPUT_SRESET    = 2,
2096     PPCRCPU_INPUT_IRQ0      = 3,
2097     PPCRCPU_INPUT_IRQ1      = 4,
2098     PPCRCPU_INPUT_IRQ2      = 5,
2099     PPCRCPU_INPUT_IRQ3      = 6,
2100     PPCRCPU_INPUT_IRQ4      = 7,
2101     PPCRCPU_INPUT_IRQ5      = 8,
2102     PPCRCPU_INPUT_IRQ6      = 9,
2103     PPCRCPU_INPUT_IRQ7      = 10,
2104     PPCRCPU_INPUT_NB,
2105 };
2106
2107 #if defined(TARGET_PPC64)
2108 enum {
2109     /* PowerPC 970 input pins */
2110     PPC970_INPUT_HRESET     = 0,
2111     PPC970_INPUT_SRESET     = 1,
2112     PPC970_INPUT_CKSTP      = 2,
2113     PPC970_INPUT_TBEN       = 3,
2114     PPC970_INPUT_MCP        = 4,
2115     PPC970_INPUT_INT        = 5,
2116     PPC970_INPUT_THINT      = 6,
2117     PPC970_INPUT_NB,
2118 };
2119
2120 enum {
2121     /* POWER7 input pins */
2122     POWER7_INPUT_INT        = 0,
2123     /* POWER7 probably has other inputs, but we don't care about them
2124      * for any existing machine.  We can wire these up when we need
2125      * them */
2126     POWER7_INPUT_NB,
2127 };
2128 #endif
2129
2130 /* Hardware exceptions definitions */
2131 enum {
2132     /* External hardware exception sources */
2133     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
2134     PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
2135     PPC_INTERRUPT_MCK,            /* Machine check exception              */
2136     PPC_INTERRUPT_EXT,            /* External interrupt                   */
2137     PPC_INTERRUPT_SMI,            /* System management interrupt          */
2138     PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
2139     PPC_INTERRUPT_DEBUG,          /* External debug exception             */
2140     PPC_INTERRUPT_THERM,          /* Thermal exception                    */
2141     /* Internal hardware exception sources */
2142     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
2143     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
2144     PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
2145     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
2146     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
2147     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
2148     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
2149     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
2150 };
2151
2152 /* Processor Compatibility mask (PCR) */
2153 enum {
2154     PCR_COMPAT_2_05     = 1ull << (63-62),
2155     PCR_COMPAT_2_06     = 1ull << (63-61),
2156     PCR_VEC_DIS         = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2157     PCR_VSX_DIS         = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2158     PCR_TM_DIS          = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2159 };
2160
2161 /*****************************************************************************/
2162
2163 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2164 {
2165     return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2166 }
2167
2168 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2169 {
2170     env->so = (xer >> XER_SO) & 1;
2171     env->ov = (xer >> XER_OV) & 1;
2172     env->ca = (xer >> XER_CA) & 1;
2173     env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2174 }
2175
2176 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2177                                         target_ulong *cs_base, int *flags)
2178 {
2179     *pc = env->nip;
2180     *cs_base = 0;
2181     *flags = env->hflags;
2182 }
2183
2184 #if !defined(CONFIG_USER_ONLY)
2185 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2186 {
2187     uintptr_t tlbml = (uintptr_t)tlbm;
2188     uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2189
2190     return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2191 }
2192
2193 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2194 {
2195     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2196     int r = tlbncfg & TLBnCFG_N_ENTRY;
2197     return r;
2198 }
2199
2200 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2201 {
2202     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2203     int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2204     return r;
2205 }
2206
2207 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2208 {
2209     int id = booke206_tlbm_id(env, tlbm);
2210     int end = 0;
2211     int i;
2212
2213     for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2214         end += booke206_tlb_size(env, i);
2215         if (id < end) {
2216             return i;
2217         }
2218     }
2219
2220     cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2221     return 0;
2222 }
2223
2224 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2225 {
2226     int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2227     int tlbid = booke206_tlbm_id(env, tlb);
2228     return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2229 }
2230
2231 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2232                                               target_ulong ea, int way)
2233 {
2234     int r;
2235     uint32_t ways = booke206_tlb_ways(env, tlbn);
2236     int ways_bits = ffs(ways) - 1;
2237     int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2238     int i;
2239
2240     way &= ways - 1;
2241     ea >>= MAS2_EPN_SHIFT;
2242     ea &= (1 << (tlb_bits - ways_bits)) - 1;
2243     r = (ea << ways_bits) | way;
2244
2245     if (r >= booke206_tlb_size(env, tlbn)) {
2246         return NULL;
2247     }
2248
2249     /* bump up to tlbn index */
2250     for (i = 0; i < tlbn; i++) {
2251         r += booke206_tlb_size(env, i);
2252     }
2253
2254     return &env->tlb.tlbm[r];
2255 }
2256
2257 /* returns bitmap of supported page sizes for a given TLB */
2258 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2259 {
2260     bool mav2 = false;
2261     uint32_t ret = 0;
2262
2263     if (mav2) {
2264         ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2265     } else {
2266         uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2267         uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2268         uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2269         int i;
2270         for (i = min; i <= max; i++) {
2271             ret |= (1 << (i << 1));
2272         }
2273     }
2274
2275     return ret;
2276 }
2277
2278 #endif
2279
2280 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2281 {
2282     if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2283         return msr & (1ULL << MSR_CM);
2284     }
2285
2286     return msr & (1ULL << MSR_SF);
2287 }
2288
2289 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2290
2291 #include "exec/exec-all.h"
2292
2293 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2294
2295 /**
2296  * ppc_get_vcpu_dt_id:
2297  * @cs: a PowerPCCPU struct.
2298  *
2299  * Returns a device-tree ID for a CPU.
2300  */
2301 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2302
2303 /**
2304  * ppc_get_vcpu_by_dt_id:
2305  * @cpu_dt_id: a device tree id
2306  *
2307  * Searches for a CPU by @cpu_dt_id.
2308  *
2309  * Returns: a PowerPCCPU struct
2310  */
2311 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2312
2313 #endif /* !defined (__CPU_PPC_H__) */