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block/rbd: fix memory leak
[qemu/ar7.git] / target-arm / helper.c
blob96abbed93599e2094bc36b32fbe87559656e55e8
1 #include "cpu.h"
2 #include "internals.h"
3 #include "exec/gdbstub.h"
4 #include "exec/helper-proto.h"
5 #include "qemu/host-utils.h"
6 #include "sysemu/arch_init.h"
7 #include "sysemu/sysemu.h"
8 #include "qemu/bitops.h"
9 #include "qemu/crc32c.h"
10 #include "exec/cpu_ldst.h"
11 #include "arm_ldst.h"
12 #include <zlib.h> /* For crc32 */
13
14 #ifndef CONFIG_USER_ONLY
15 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
16 int access_type, int is_user,
17 hwaddr *phys_ptr, int *prot,
18 target_ulong *page_size);
19
20 /* Definitions for the PMCCNTR and PMCR registers */
21 #define PMCRD 0x8
22 #define PMCRC 0x4
23 #define PMCRE 0x1
24 #endif
25
26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
27 {
28 int nregs;
29
30 /* VFP data registers are always little-endian. */
31 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
32 if (reg < nregs) {
33 stfq_le_p(buf, env->vfp.regs[reg]);
34 return 8;
35 }
36 if (arm_feature(env, ARM_FEATURE_NEON)) {
37 /* Aliases for Q regs. */
38 nregs += 16;
39 if (reg < nregs) {
40 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
41 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
42 return 16;
43 }
44 }
45 switch (reg - nregs) {
46 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
47 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
48 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
49 }
50 return 0;
51 }
52
53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
54 {
55 int nregs;
56
57 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
58 if (reg < nregs) {
59 env->vfp.regs[reg] = ldfq_le_p(buf);
60 return 8;
61 }
62 if (arm_feature(env, ARM_FEATURE_NEON)) {
63 nregs += 16;
64 if (reg < nregs) {
65 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
66 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
67 return 16;
68 }
69 }
70 switch (reg - nregs) {
71 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
72 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
73 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
74 }
75 return 0;
76 }
77
78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
79 {
80 switch (reg) {
81 case 0 ... 31:
82 /* 128 bit FP register */
83 stfq_le_p(buf, env->vfp.regs[reg * 2]);
84 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
85 return 16;
86 case 32:
87 /* FPSR */
88 stl_p(buf, vfp_get_fpsr(env));
89 return 4;
90 case 33:
91 /* FPCR */
92 stl_p(buf, vfp_get_fpcr(env));
93 return 4;
94 default:
95 return 0;
96 }
97 }
98
99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
100 {
101 switch (reg) {
102 case 0 ... 31:
103 /* 128 bit FP register */
104 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
105 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
106 return 16;
107 case 32:
108 /* FPSR */
109 vfp_set_fpsr(env, ldl_p(buf));
110 return 4;
111 case 33:
112 /* FPCR */
113 vfp_set_fpcr(env, ldl_p(buf));
114 return 4;
115 default:
116 return 0;
117 }
118 }
119
120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
121 {
122 if (cpreg_field_is_64bit(ri)) {
123 return CPREG_FIELD64(env, ri);
124 } else {
125 return CPREG_FIELD32(env, ri);
126 }
127 }
128
129 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
130 uint64_t value)
131 {
132 if (cpreg_field_is_64bit(ri)) {
133 CPREG_FIELD64(env, ri) = value;
134 } else {
135 CPREG_FIELD32(env, ri) = value;
136 }
137 }
138
139 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
140 {
141 return (char *)env + ri->fieldoffset;
142 }
143
144 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
145 {
146 /* Raw read of a coprocessor register (as needed for migration, etc). */
147 if (ri->type & ARM_CP_CONST) {
148 return ri->resetvalue;
149 } else if (ri->raw_readfn) {
150 return ri->raw_readfn(env, ri);
151 } else if (ri->readfn) {
152 return ri->readfn(env, ri);
153 } else {
154 return raw_read(env, ri);
155 }
156 }
157
158 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
159 uint64_t v)
160 {
161 /* Raw write of a coprocessor register (as needed for migration, etc).
162 * Note that constant registers are treated as write-ignored; the
163 * caller should check for success by whether a readback gives the
164 * value written.
165 */
166 if (ri->type & ARM_CP_CONST) {
167 return;
168 } else if (ri->raw_writefn) {
169 ri->raw_writefn(env, ri, v);
170 } else if (ri->writefn) {
171 ri->writefn(env, ri, v);
172 } else {
173 raw_write(env, ri, v);
174 }
175 }
176
177 bool write_cpustate_to_list(ARMCPU *cpu)
178 {
179 /* Write the coprocessor state from cpu->env to the (index,value) list. */
180 int i;
181 bool ok = true;
182
183 for (i = 0; i < cpu->cpreg_array_len; i++) {
184 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
185 const ARMCPRegInfo *ri;
186
187 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
188 if (!ri) {
189 ok = false;
190 continue;
191 }
192 if (ri->type & ARM_CP_NO_MIGRATE) {
193 continue;
194 }
195 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
196 }
197 return ok;
198 }
199
200 bool write_list_to_cpustate(ARMCPU *cpu)
201 {
202 int i;
203 bool ok = true;
204
205 for (i = 0; i < cpu->cpreg_array_len; i++) {
206 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
207 uint64_t v = cpu->cpreg_values[i];
208 const ARMCPRegInfo *ri;
209
210 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
211 if (!ri) {
212 ok = false;
213 continue;
214 }
215 if (ri->type & ARM_CP_NO_MIGRATE) {
216 continue;
217 }
218 /* Write value and confirm it reads back as written
219 * (to catch read-only registers and partially read-only
220 * registers where the incoming migration value doesn't match)
221 */
222 write_raw_cp_reg(&cpu->env, ri, v);
223 if (read_raw_cp_reg(&cpu->env, ri) != v) {
224 ok = false;
225 }
226 }
227 return ok;
228 }
229
230 static void add_cpreg_to_list(gpointer key, gpointer opaque)
231 {
232 ARMCPU *cpu = opaque;
233 uint64_t regidx;
234 const ARMCPRegInfo *ri;
235
236 regidx = *(uint32_t *)key;
237 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
238
239 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
240 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
241 /* The value array need not be initialized at this point */
242 cpu->cpreg_array_len++;
243 }
244 }
245
246 static void count_cpreg(gpointer key, gpointer opaque)
247 {
248 ARMCPU *cpu = opaque;
249 uint64_t regidx;
250 const ARMCPRegInfo *ri;
251
252 regidx = *(uint32_t *)key;
253 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
254
255 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
256 cpu->cpreg_array_len++;
257 }
258 }
259
260 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
261 {
262 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
263 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
264
265 if (aidx > bidx) {
266 return 1;
267 }
268 if (aidx < bidx) {
269 return -1;
270 }
271 return 0;
272 }
273
274 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
275 {
276 GList **plist = udata;
277
278 *plist = g_list_prepend(*plist, key);
279 }
280
281 void init_cpreg_list(ARMCPU *cpu)
282 {
283 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
284 * Note that we require cpreg_tuples[] to be sorted by key ID.
285 */
286 GList *keys = NULL;
287 int arraylen;
288
289 g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
290
291 keys = g_list_sort(keys, cpreg_key_compare);
292
293 cpu->cpreg_array_len = 0;
294
295 g_list_foreach(keys, count_cpreg, cpu);
296
297 arraylen = cpu->cpreg_array_len;
298 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
299 cpu->cpreg_values = g_new(uint64_t, arraylen);
300 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
301 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
302 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
303 cpu->cpreg_array_len = 0;
304
305 g_list_foreach(keys, add_cpreg_to_list, cpu);
306
307 assert(cpu->cpreg_array_len == arraylen);
308
309 g_list_free(keys);
310 }
311
312 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
313 {
314 ARMCPU *cpu = arm_env_get_cpu(env);
315
316 raw_write(env, ri, value);
317 tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
318 }
319
320 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
321 {
322 ARMCPU *cpu = arm_env_get_cpu(env);
323
324 if (raw_read(env, ri) != value) {
325 /* Unlike real hardware the qemu TLB uses virtual addresses,
326 * not modified virtual addresses, so this causes a TLB flush.
327 */
328 tlb_flush(CPU(cpu), 1);
329 raw_write(env, ri, value);
330 }
331 }
332
333 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
334 uint64_t value)
335 {
336 ARMCPU *cpu = arm_env_get_cpu(env);
337
338 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
339 && !extended_addresses_enabled(env)) {
340 /* For VMSA (when not using the LPAE long descriptor page table
341 * format) this register includes the ASID, so do a TLB flush.
342 * For PMSA it is purely a process ID and no action is needed.
343 */
344 tlb_flush(CPU(cpu), 1);
345 }
346 raw_write(env, ri, value);
347 }
348
349 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
350 uint64_t value)
351 {
352 /* Invalidate all (TLBIALL) */
353 ARMCPU *cpu = arm_env_get_cpu(env);
354
355 tlb_flush(CPU(cpu), 1);
356 }
357
358 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
359 uint64_t value)
360 {
361 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
362 ARMCPU *cpu = arm_env_get_cpu(env);
363
364 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
365 }
366
367 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
368 uint64_t value)
369 {
370 /* Invalidate by ASID (TLBIASID) */
371 ARMCPU *cpu = arm_env_get_cpu(env);
372
373 tlb_flush(CPU(cpu), value == 0);
374 }
375
376 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
377 uint64_t value)
378 {
379 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
380 ARMCPU *cpu = arm_env_get_cpu(env);
381
382 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
383 }
384
385 /* IS variants of TLB operations must affect all cores */
386 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
387 uint64_t value)
388 {
389 CPUState *other_cs;
390
391 CPU_FOREACH(other_cs) {
392 tlb_flush(other_cs, 1);
393 }
394 }
395
396 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
397 uint64_t value)
398 {
399 CPUState *other_cs;
400
401 CPU_FOREACH(other_cs) {
402 tlb_flush(other_cs, value == 0);
403 }
404 }
405
406 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
407 uint64_t value)
408 {
409 CPUState *other_cs;
410
411 CPU_FOREACH(other_cs) {
412 tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
413 }
414 }
415
416 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
417 uint64_t value)
418 {
419 CPUState *other_cs;
420
421 CPU_FOREACH(other_cs) {
422 tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
423 }
424 }
425
426 static const ARMCPRegInfo cp_reginfo[] = {
427 /* Define the secure and non-secure FCSE identifier CP registers
428 * separately because there is no secure bank in V8 (no _EL3). This allows
429 * the secure register to be properly reset and migrated. There is also no
430 * v8 EL1 version of the register so the non-secure instance stands alone.
431 */
432 { .name = "FCSEIDR(NS)",
433 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
434 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
435 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
436 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
437 { .name = "FCSEIDR(S)",
438 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
439 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
440 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
441 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
442 /* Define the secure and non-secure context identifier CP registers
443 * separately because there is no secure bank in V8 (no _EL3). This allows
444 * the secure register to be properly reset and migrated. In the
445 * non-secure case, the 32-bit register will have reset and migration
446 * disabled during registration as it is handled by the 64-bit instance.
447 */
448 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
449 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
450 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
451 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
452 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
453 { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
454 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
455 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
456 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
457 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
458 REGINFO_SENTINEL
459 };
460
461 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
462 /* NB: Some of these registers exist in v8 but with more precise
463 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
464 */
465 /* MMU Domain access control / MPU write buffer control */
466 { .name = "DACR",
467 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
468 .access = PL1_RW, .resetvalue = 0,
469 .writefn = dacr_write, .raw_writefn = raw_write,
470 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
471 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
472 /* ??? This covers not just the impdef TLB lockdown registers but also
473 * some v7VMSA registers relating to TEX remap, so it is overly broad.
474 */
475 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
476 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
477 /* Cache maintenance ops; some of this space may be overridden later. */
478 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
479 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
480 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
481 REGINFO_SENTINEL
482 };
483
484 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
485 /* Not all pre-v6 cores implemented this WFI, so this is slightly
486 * over-broad.
487 */
488 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
489 .access = PL1_W, .type = ARM_CP_WFI },
490 REGINFO_SENTINEL
491 };
492
493 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
494 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
495 * is UNPREDICTABLE; we choose to NOP as most implementations do).
496 */
497 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
498 .access = PL1_W, .type = ARM_CP_WFI },
499 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
500 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
501 * OMAPCP will override this space.
502 */
503 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
504 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
505 .resetvalue = 0 },
506 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
507 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
508 .resetvalue = 0 },
509 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
510 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
511 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
512 .resetvalue = 0 },
513 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
514 * implementing it as RAZ means the "debug architecture version" bits
515 * will read as a reserved value, which should cause Linux to not try
516 * to use the debug hardware.
517 */
518 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
519 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
520 /* MMU TLB control. Note that the wildcarding means we cover not just
521 * the unified TLB ops but also the dside/iside/inner-shareable variants.
522 */
523 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
524 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
525 .type = ARM_CP_NO_MIGRATE },
526 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
527 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
528 .type = ARM_CP_NO_MIGRATE },
529 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
530 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
531 .type = ARM_CP_NO_MIGRATE },
532 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
533 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
534 .type = ARM_CP_NO_MIGRATE },
535 REGINFO_SENTINEL
536 };
537
538 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
539 uint64_t value)
540 {
541 uint32_t mask = 0;
542
543 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
544 if (!arm_feature(env, ARM_FEATURE_V8)) {
545 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
546 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
547 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
548 */
549 if (arm_feature(env, ARM_FEATURE_VFP)) {
550 /* VFP coprocessor: cp10 & cp11 [23:20] */
551 mask |= (1 << 31) | (1 << 30) | (0xf << 20);
552
553 if (!arm_feature(env, ARM_FEATURE_NEON)) {
554 /* ASEDIS [31] bit is RAO/WI */
555 value |= (1 << 31);
556 }
557
558 /* VFPv3 and upwards with NEON implement 32 double precision
559 * registers (D0-D31).
560 */
561 if (!arm_feature(env, ARM_FEATURE_NEON) ||
562 !arm_feature(env, ARM_FEATURE_VFP3)) {
563 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
564 value |= (1 << 30);
565 }
566 }
567 value &= mask;
568 }
569 env->cp15.c1_coproc = value;
570 }
571
572 static const ARMCPRegInfo v6_cp_reginfo[] = {
573 /* prefetch by MVA in v6, NOP in v7 */
574 { .name = "MVA_prefetch",
575 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
576 .access = PL1_W, .type = ARM_CP_NOP },
577 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
578 .access = PL0_W, .type = ARM_CP_NOP },
579 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
580 .access = PL0_W, .type = ARM_CP_NOP },
581 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
582 .access = PL0_W, .type = ARM_CP_NOP },
583 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
584 .access = PL1_RW,
585 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
586 offsetof(CPUARMState, cp15.ifar_ns) },
587 .resetvalue = 0, },
588 /* Watchpoint Fault Address Register : should actually only be present
589 * for 1136, 1176, 11MPCore.
590 */
591 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
592 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
593 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
594 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
595 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
596 .resetvalue = 0, .writefn = cpacr_write },
597 REGINFO_SENTINEL
598 };
599
600 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
601 {
602 /* Performance monitor registers user accessibility is controlled
603 * by PMUSERENR.
604 */
605 if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) {
606 return CP_ACCESS_TRAP;
607 }
608 return CP_ACCESS_OK;
609 }
610
611 #ifndef CONFIG_USER_ONLY
612
613 static inline bool arm_ccnt_enabled(CPUARMState *env)
614 {
615 /* This does not support checking PMCCFILTR_EL0 register */
616
617 if (!(env->cp15.c9_pmcr & PMCRE)) {
618 return false;
619 }
620
621 return true;
622 }
623
624 void pmccntr_sync(CPUARMState *env)
625 {
626 uint64_t temp_ticks;
627
628 temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
629 get_ticks_per_sec(), 1000000);
630
631 if (env->cp15.c9_pmcr & PMCRD) {
632 /* Increment once every 64 processor clock cycles */
633 temp_ticks /= 64;
634 }
635
636 if (arm_ccnt_enabled(env)) {
637 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
638 }
639 }
640
641 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
642 uint64_t value)
643 {
644 pmccntr_sync(env);
645
646 if (value & PMCRC) {
647 /* The counter has been reset */
648 env->cp15.c15_ccnt = 0;
649 }
650
651 /* only the DP, X, D and E bits are writable */
652 env->cp15.c9_pmcr &= ~0x39;
653 env->cp15.c9_pmcr |= (value & 0x39);
654
655 pmccntr_sync(env);
656 }
657
658 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
659 {
660 uint64_t total_ticks;
661
662 if (!arm_ccnt_enabled(env)) {
663 /* Counter is disabled, do not change value */
664 return env->cp15.c15_ccnt;
665 }
666
667 total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
668 get_ticks_per_sec(), 1000000);
669
670 if (env->cp15.c9_pmcr & PMCRD) {
671 /* Increment once every 64 processor clock cycles */
672 total_ticks /= 64;
673 }
674 return total_ticks - env->cp15.c15_ccnt;
675 }
676
677 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
678 uint64_t value)
679 {
680 uint64_t total_ticks;
681
682 if (!arm_ccnt_enabled(env)) {
683 /* Counter is disabled, set the absolute value */
684 env->cp15.c15_ccnt = value;
685 return;
686 }
687
688 total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
689 get_ticks_per_sec(), 1000000);
690
691 if (env->cp15.c9_pmcr & PMCRD) {
692 /* Increment once every 64 processor clock cycles */
693 total_ticks /= 64;
694 }
695 env->cp15.c15_ccnt = total_ticks - value;
696 }
697
698 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
699 uint64_t value)
700 {
701 uint64_t cur_val = pmccntr_read(env, NULL);
702
703 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
704 }
705
706 #else /* CONFIG_USER_ONLY */
707
708 void pmccntr_sync(CPUARMState *env)
709 {
710 }
711
712 #endif
713
714 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
715 uint64_t value)
716 {
717 pmccntr_sync(env);
718 env->cp15.pmccfiltr_el0 = value & 0x7E000000;
719 pmccntr_sync(env);
720 }
721
722 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
723 uint64_t value)
724 {
725 value &= (1 << 31);
726 env->cp15.c9_pmcnten |= value;
727 }
728
729 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
730 uint64_t value)
731 {
732 value &= (1 << 31);
733 env->cp15.c9_pmcnten &= ~value;
734 }
735
736 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
737 uint64_t value)
738 {
739 env->cp15.c9_pmovsr &= ~value;
740 }
741
742 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
743 uint64_t value)
744 {
745 env->cp15.c9_pmxevtyper = value & 0xff;
746 }
747
748 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
749 uint64_t value)
750 {
751 env->cp15.c9_pmuserenr = value & 1;
752 }
753
754 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
755 uint64_t value)
756 {
757 /* We have no event counters so only the C bit can be changed */
758 value &= (1 << 31);
759 env->cp15.c9_pminten |= value;
760 }
761
762 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
763 uint64_t value)
764 {
765 value &= (1 << 31);
766 env->cp15.c9_pminten &= ~value;
767 }
768
769 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
770 uint64_t value)
771 {
772 /* Note that even though the AArch64 view of this register has bits
773 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
774 * architectural requirements for bits which are RES0 only in some
775 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
776 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
777 */
778 raw_write(env, ri, value & ~0x1FULL);
779 }
780
781 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
782 {
783 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
784 * For bits that vary between AArch32/64, code needs to check the
785 * current execution mode before directly using the feature bit.
786 */
787 uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
788
789 if (!arm_feature(env, ARM_FEATURE_EL2)) {
790 valid_mask &= ~SCR_HCE;
791
792 /* On ARMv7, SMD (or SCD as it is called in v7) is only
793 * supported if EL2 exists. The bit is UNK/SBZP when
794 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
795 * when EL2 is unavailable.
796 */
797 if (arm_feature(env, ARM_FEATURE_V7)) {
798 valid_mask &= ~SCR_SMD;
799 }
800 }
801
802 /* Clear all-context RES0 bits. */
803 value &= valid_mask;
804 raw_write(env, ri, value);
805 }
806
807 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
808 {
809 ARMCPU *cpu = arm_env_get_cpu(env);
810
811 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
812 * bank
813 */
814 uint32_t index = A32_BANKED_REG_GET(env, csselr,
815 ri->secure & ARM_CP_SECSTATE_S);
816
817 return cpu->ccsidr[index];
818 }
819
820 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
821 uint64_t value)
822 {
823 raw_write(env, ri, value & 0xf);
824 }
825
826 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
827 {
828 CPUState *cs = ENV_GET_CPU(env);
829 uint64_t ret = 0;
830
831 if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
832 ret |= CPSR_I;
833 }
834 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
835 ret |= CPSR_F;
836 }
837 /* External aborts are not possible in QEMU so A bit is always clear */
838 return ret;
839 }
840
841 static const ARMCPRegInfo v7_cp_reginfo[] = {
842 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
843 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
844 .access = PL1_W, .type = ARM_CP_NOP },
845 /* Performance monitors are implementation defined in v7,
846 * but with an ARM recommended set of registers, which we
847 * follow (although we don't actually implement any counters)
848 *
849 * Performance registers fall into three categories:
850 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
851 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
852 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
853 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
854 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
855 */
856 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
857 .access = PL0_RW, .type = ARM_CP_NO_MIGRATE,
858 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
859 .writefn = pmcntenset_write,
860 .accessfn = pmreg_access,
861 .raw_writefn = raw_write },
862 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
863 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
864 .access = PL0_RW, .accessfn = pmreg_access,
865 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
866 .writefn = pmcntenset_write, .raw_writefn = raw_write },
867 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
868 .access = PL0_RW,
869 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
870 .accessfn = pmreg_access,
871 .writefn = pmcntenclr_write,
872 .type = ARM_CP_NO_MIGRATE },
873 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
874 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
875 .access = PL0_RW, .accessfn = pmreg_access,
876 .type = ARM_CP_NO_MIGRATE,
877 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
878 .writefn = pmcntenclr_write },
879 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
880 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
881 .accessfn = pmreg_access,
882 .writefn = pmovsr_write,
883 .raw_writefn = raw_write },
884 /* Unimplemented so WI. */
885 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
886 .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
887 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
888 * We choose to RAZ/WI.
889 */
890 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
891 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
892 .accessfn = pmreg_access },
893 #ifndef CONFIG_USER_ONLY
894 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
895 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
896 .readfn = pmccntr_read, .writefn = pmccntr_write32,
897 .accessfn = pmreg_access },
898 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
899 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
900 .access = PL0_RW, .accessfn = pmreg_access,
901 .type = ARM_CP_IO,
902 .readfn = pmccntr_read, .writefn = pmccntr_write, },
903 #endif
904 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
905 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
906 .writefn = pmccfiltr_write,
907 .access = PL0_RW, .accessfn = pmreg_access,
908 .type = ARM_CP_IO,
909 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
910 .resetvalue = 0, },
911 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
912 .access = PL0_RW,
913 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
914 .accessfn = pmreg_access, .writefn = pmxevtyper_write,
915 .raw_writefn = raw_write },
916 /* Unimplemented, RAZ/WI. */
917 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
918 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
919 .accessfn = pmreg_access },
920 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
921 .access = PL0_R | PL1_RW,
922 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
923 .resetvalue = 0,
924 .writefn = pmuserenr_write, .raw_writefn = raw_write },
925 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
926 .access = PL1_RW,
927 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
928 .resetvalue = 0,
929 .writefn = pmintenset_write, .raw_writefn = raw_write },
930 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
931 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
932 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
933 .resetvalue = 0, .writefn = pmintenclr_write, },
934 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
935 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
936 .access = PL1_RW, .writefn = vbar_write,
937 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
938 offsetof(CPUARMState, cp15.vbar_ns) },
939 .resetvalue = 0 },
940 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
941 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
942 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
943 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
944 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
945 .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
946 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
947 offsetof(CPUARMState, cp15.csselr_ns) } },
948 /* Auxiliary ID register: this actually has an IMPDEF value but for now
949 * just RAZ for all cores:
950 */
951 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
952 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
953 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
954 /* Auxiliary fault status registers: these also are IMPDEF, and we
955 * choose to RAZ/WI for all cores.
956 */
957 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
958 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
959 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
960 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
961 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
962 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
963 /* MAIR can just read-as-written because we don't implement caches
964 * and so don't need to care about memory attributes.
965 */
966 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
967 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
968 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
969 .resetvalue = 0 },
970 /* For non-long-descriptor page tables these are PRRR and NMRR;
971 * regardless they still act as reads-as-written for QEMU.
972 * The override is necessary because of the overly-broad TLB_LOCKDOWN
973 * definition.
974 */
975 /* MAIR0/1 are defined seperately from their 64-bit counterpart which
976 * allows them to assign the correct fieldoffset based on the endianness
977 * handled in the field definitions.
978 */
979 { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
980 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
981 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
982 offsetof(CPUARMState, cp15.mair0_ns) },
983 .resetfn = arm_cp_reset_ignore },
984 { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
985 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
986 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
987 offsetof(CPUARMState, cp15.mair1_ns) },
988 .resetfn = arm_cp_reset_ignore },
989 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
990 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
991 .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
992 /* 32 bit ITLB invalidates */
993 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
994 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
995 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
996 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
997 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
998 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
999 /* 32 bit DTLB invalidates */
1000 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1001 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
1002 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1003 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
1004 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1005 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
1006 /* 32 bit TLB invalidates */
1007 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1008 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
1009 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1010 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
1011 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1012 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
1013 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1014 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
1015 REGINFO_SENTINEL
1016 };
1017
1018 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1019 /* 32 bit TLB invalidates, Inner Shareable */
1020 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1021 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_is_write },
1022 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1023 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_is_write },
1024 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1025 .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
1026 .writefn = tlbiasid_is_write },
1027 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1028 .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
1029 .writefn = tlbimvaa_is_write },
1030 REGINFO_SENTINEL
1031 };
1032
1033 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1034 uint64_t value)
1035 {
1036 value &= 1;
1037 env->teecr = value;
1038 }
1039
1040 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
1041 {
1042 if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1043 return CP_ACCESS_TRAP;
1044 }
1045 return CP_ACCESS_OK;
1046 }
1047
1048 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1049 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1050 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1051 .resetvalue = 0,
1052 .writefn = teecr_write },
1053 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1054 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1055 .accessfn = teehbr_access, .resetvalue = 0 },
1056 REGINFO_SENTINEL
1057 };
1058
1059 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1060 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1061 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1062 .access = PL0_RW,
1063 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1064 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1065 .access = PL0_RW,
1066 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1067 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1068 .resetfn = arm_cp_reset_ignore },
1069 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1070 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1071 .access = PL0_R|PL1_W,
1072 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1073 .resetvalue = 0},
1074 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1075 .access = PL0_R|PL1_W,
1076 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1077 offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1078 .resetfn = arm_cp_reset_ignore },
1079 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1080 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1081 .access = PL1_RW,
1082 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1083 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1084 .access = PL1_RW,
1085 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1086 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1087 .resetvalue = 0 },
1088 REGINFO_SENTINEL
1089 };
1090
1091 #ifndef CONFIG_USER_ONLY
1092
1093 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
1094 {
1095 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1096 if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
1097 return CP_ACCESS_TRAP;
1098 }
1099 return CP_ACCESS_OK;
1100 }
1101
1102 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
1103 {
1104 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1105 if (arm_current_el(env) == 0 &&
1106 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1107 return CP_ACCESS_TRAP;
1108 }
1109 return CP_ACCESS_OK;
1110 }
1111
1112 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
1113 {
1114 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1115 * EL0[PV]TEN is zero.
1116 */
1117 if (arm_current_el(env) == 0 &&
1118 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1119 return CP_ACCESS_TRAP;
1120 }
1121 return CP_ACCESS_OK;
1122 }
1123
1124 static CPAccessResult gt_pct_access(CPUARMState *env,
1125 const ARMCPRegInfo *ri)
1126 {
1127 return gt_counter_access(env, GTIMER_PHYS);
1128 }
1129
1130 static CPAccessResult gt_vct_access(CPUARMState *env,
1131 const ARMCPRegInfo *ri)
1132 {
1133 return gt_counter_access(env, GTIMER_VIRT);
1134 }
1135
1136 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1137 {
1138 return gt_timer_access(env, GTIMER_PHYS);
1139 }
1140
1141 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1142 {
1143 return gt_timer_access(env, GTIMER_VIRT);
1144 }
1145
1146 static uint64_t gt_get_countervalue(CPUARMState *env)
1147 {
1148 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1149 }
1150
1151 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1152 {
1153 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1154
1155 if (gt->ctl & 1) {
1156 /* Timer enabled: calculate and set current ISTATUS, irq, and
1157 * reset timer to when ISTATUS next has to change
1158 */
1159 uint64_t count = gt_get_countervalue(&cpu->env);
1160 /* Note that this must be unsigned 64 bit arithmetic: */
1161 int istatus = count >= gt->cval;
1162 uint64_t nexttick;
1163
1164 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1165 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1166 (istatus && !(gt->ctl & 2)));
1167 if (istatus) {
1168 /* Next transition is when count rolls back over to zero */
1169 nexttick = UINT64_MAX;
1170 } else {
1171 /* Next transition is when we hit cval */
1172 nexttick = gt->cval;
1173 }
1174 /* Note that the desired next expiry time might be beyond the
1175 * signed-64-bit range of a QEMUTimer -- in this case we just
1176 * set the timer for as far in the future as possible. When the
1177 * timer expires we will reset the timer for any remaining period.
1178 */
1179 if (nexttick > INT64_MAX / GTIMER_SCALE) {
1180 nexttick = INT64_MAX / GTIMER_SCALE;
1181 }
1182 timer_mod(cpu->gt_timer[timeridx], nexttick);
1183 } else {
1184 /* Timer disabled: ISTATUS and timer output always clear */
1185 gt->ctl &= ~4;
1186 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1187 timer_del(cpu->gt_timer[timeridx]);
1188 }
1189 }
1190
1191 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1192 {
1193 ARMCPU *cpu = arm_env_get_cpu(env);
1194 int timeridx = ri->opc1 & 1;
1195
1196 timer_del(cpu->gt_timer[timeridx]);
1197 }
1198
1199 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1200 {
1201 return gt_get_countervalue(env);
1202 }
1203
1204 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1205 uint64_t value)
1206 {
1207 int timeridx = ri->opc1 & 1;
1208
1209 env->cp15.c14_timer[timeridx].cval = value;
1210 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1211 }
1212
1213 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1214 {
1215 int timeridx = ri->crm & 1;
1216
1217 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1218 gt_get_countervalue(env));
1219 }
1220
1221 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1222 uint64_t value)
1223 {
1224 int timeridx = ri->crm & 1;
1225
1226 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
1227 + sextract64(value, 0, 32);
1228 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1229 }
1230
1231 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1232 uint64_t value)
1233 {
1234 ARMCPU *cpu = arm_env_get_cpu(env);
1235 int timeridx = ri->crm & 1;
1236 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1237
1238 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1239 if ((oldval ^ value) & 1) {
1240 /* Enable toggled */
1241 gt_recalc_timer(cpu, timeridx);
1242 } else if ((oldval ^ value) & 2) {
1243 /* IMASK toggled: don't need to recalculate,
1244 * just set the interrupt line based on ISTATUS
1245 */
1246 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1247 (oldval & 4) && !(value & 2));
1248 }
1249 }
1250
1251 void arm_gt_ptimer_cb(void *opaque)
1252 {
1253 ARMCPU *cpu = opaque;
1254
1255 gt_recalc_timer(cpu, GTIMER_PHYS);
1256 }
1257
1258 void arm_gt_vtimer_cb(void *opaque)
1259 {
1260 ARMCPU *cpu = opaque;
1261
1262 gt_recalc_timer(cpu, GTIMER_VIRT);
1263 }
1264
1265 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1266 /* Note that CNTFRQ is purely reads-as-written for the benefit
1267 * of software; writing it doesn't actually change the timer frequency.
1268 * Our reset value matches the fixed frequency we implement the timer at.
1269 */
1270 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1271 .type = ARM_CP_NO_MIGRATE,
1272 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1273 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1274 .resetfn = arm_cp_reset_ignore,
1275 },
1276 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1277 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1278 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1279 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1280 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1281 },
1282 /* overall control: mostly access permissions */
1283 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1284 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1285 .access = PL1_RW,
1286 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1287 .resetvalue = 0,
1288 },
1289 /* per-timer control */
1290 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1291 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1292 .accessfn = gt_ptimer_access,
1293 .fieldoffset = offsetoflow32(CPUARMState,
1294 cp15.c14_timer[GTIMER_PHYS].ctl),
1295 .resetfn = arm_cp_reset_ignore,
1296 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1297 },
1298 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1299 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1300 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1301 .accessfn = gt_ptimer_access,
1302 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1303 .resetvalue = 0,
1304 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1305 },
1306 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1307 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1308 .accessfn = gt_vtimer_access,
1309 .fieldoffset = offsetoflow32(CPUARMState,
1310 cp15.c14_timer[GTIMER_VIRT].ctl),
1311 .resetfn = arm_cp_reset_ignore,
1312 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1313 },
1314 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1315 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1316 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1317 .accessfn = gt_vtimer_access,
1318 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1319 .resetvalue = 0,
1320 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1321 },
1322 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1323 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1324 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1325 .accessfn = gt_ptimer_access,
1326 .readfn = gt_tval_read, .writefn = gt_tval_write,
1327 },
1328 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1329 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1330 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1331 .readfn = gt_tval_read, .writefn = gt_tval_write,
1332 },
1333 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1334 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1335 .accessfn = gt_vtimer_access,
1336 .readfn = gt_tval_read, .writefn = gt_tval_write,
1337 },
1338 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1339 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1340 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1341 .readfn = gt_tval_read, .writefn = gt_tval_write,
1342 },
1343 /* The counter itself */
1344 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1345 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1346 .accessfn = gt_pct_access,
1347 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1348 },
1349 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1350 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1351 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1352 .accessfn = gt_pct_access,
1353 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1354 },
1355 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1356 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1357 .accessfn = gt_vct_access,
1358 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1359 },
1360 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1361 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1362 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1363 .accessfn = gt_vct_access,
1364 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1365 },
1366 /* Comparison value, indicating when the timer goes off */
1367 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1368 .access = PL1_RW | PL0_R,
1369 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1370 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1371 .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1372 .writefn = gt_cval_write, .raw_writefn = raw_write,
1373 },
1374 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1375 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1376 .access = PL1_RW | PL0_R,
1377 .type = ARM_CP_IO,
1378 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1379 .resetvalue = 0, .accessfn = gt_vtimer_access,
1380 .writefn = gt_cval_write, .raw_writefn = raw_write,
1381 },
1382 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1383 .access = PL1_RW | PL0_R,
1384 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1385 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1386 .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1387 .writefn = gt_cval_write, .raw_writefn = raw_write,
1388 },
1389 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1390 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1391 .access = PL1_RW | PL0_R,
1392 .type = ARM_CP_IO,
1393 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1394 .resetvalue = 0, .accessfn = gt_vtimer_access,
1395 .writefn = gt_cval_write, .raw_writefn = raw_write,
1396 },
1397 REGINFO_SENTINEL
1398 };
1399
1400 #else
1401 /* In user-mode none of the generic timer registers are accessible,
1402 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1403 * so instead just don't register any of them.
1404 */
1405 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1406 REGINFO_SENTINEL
1407 };
1408
1409 #endif
1410
1411 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1412 {
1413 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1414 raw_write(env, ri, value);
1415 } else if (arm_feature(env, ARM_FEATURE_V7)) {
1416 raw_write(env, ri, value & 0xfffff6ff);
1417 } else {
1418 raw_write(env, ri, value & 0xfffff1ff);
1419 }
1420 }
1421
1422 #ifndef CONFIG_USER_ONLY
1423 /* get_phys_addr() isn't present for user-mode-only targets */
1424
1425 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1426 {
1427 if (ri->opc2 & 4) {
1428 /* Other states are only available with TrustZone; in
1429 * a non-TZ implementation these registers don't exist
1430 * at all, which is an Uncategorized trap. This underdecoding
1431 * is safe because the reginfo is NO_MIGRATE.
1432 */
1433 return CP_ACCESS_TRAP_UNCATEGORIZED;
1434 }
1435 return CP_ACCESS_OK;
1436 }
1437
1438 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1439 {
1440 hwaddr phys_addr;
1441 target_ulong page_size;
1442 int prot;
1443 int ret, is_user = ri->opc2 & 2;
1444 int access_type = ri->opc2 & 1;
1445 uint64_t par64;
1446
1447 ret = get_phys_addr(env, value, access_type, is_user,
1448 &phys_addr, &prot, &page_size);
1449 if (extended_addresses_enabled(env)) {
1450 /* ret is a DFSR/IFSR value for the long descriptor
1451 * translation table format, but with WnR always clear.
1452 * Convert it to a 64-bit PAR.
1453 */
1454 par64 = (1 << 11); /* LPAE bit always set */
1455 if (ret == 0) {
1456 par64 |= phys_addr & ~0xfffULL;
1457 /* We don't set the ATTR or SH fields in the PAR. */
1458 } else {
1459 par64 |= 1; /* F */
1460 par64 |= (ret & 0x3f) << 1; /* FS */
1461 /* Note that S2WLK and FSTAGE are always zero, because we don't
1462 * implement virtualization and therefore there can't be a stage 2
1463 * fault.
1464 */
1465 }
1466 } else {
1467 /* ret is a DFSR/IFSR value for the short descriptor
1468 * translation table format (with WnR always clear).
1469 * Convert it to a 32-bit PAR.
1470 */
1471 if (ret == 0) {
1472 /* We do not set any attribute bits in the PAR */
1473 if (page_size == (1 << 24)
1474 && arm_feature(env, ARM_FEATURE_V7)) {
1475 par64 = (phys_addr & 0xff000000) | (1 << 1);
1476 } else {
1477 par64 = phys_addr & 0xfffff000;
1478 }
1479 } else {
1480 par64 = ((ret & (1 << 10)) >> 5) | ((ret & (1 << 12)) >> 6) |
1481 ((ret & 0xf) << 1) | 1;
1482 }
1483 }
1484
1485 A32_BANKED_CURRENT_REG_SET(env, par, par64);
1486 }
1487 #endif
1488
1489 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1490 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1491 .access = PL1_RW, .resetvalue = 0,
1492 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
1493 offsetoflow32(CPUARMState, cp15.par_ns) },
1494 .writefn = par_write },
1495 #ifndef CONFIG_USER_ONLY
1496 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1497 .access = PL1_W, .accessfn = ats_access,
1498 .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1499 #endif
1500 REGINFO_SENTINEL
1501 };
1502
1503 /* Return basic MPU access permission bits. */
1504 static uint32_t simple_mpu_ap_bits(uint32_t val)
1505 {
1506 uint32_t ret;
1507 uint32_t mask;
1508 int i;
1509 ret = 0;
1510 mask = 3;
1511 for (i = 0; i < 16; i += 2) {
1512 ret |= (val >> i) & mask;
1513 mask <<= 2;
1514 }
1515 return ret;
1516 }
1517
1518 /* Pad basic MPU access permission bits to extended format. */
1519 static uint32_t extended_mpu_ap_bits(uint32_t val)
1520 {
1521 uint32_t ret;
1522 uint32_t mask;
1523 int i;
1524 ret = 0;
1525 mask = 3;
1526 for (i = 0; i < 16; i += 2) {
1527 ret |= (val & mask) << i;
1528 mask <<= 2;
1529 }
1530 return ret;
1531 }
1532
1533 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1534 uint64_t value)
1535 {
1536 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1537 }
1538
1539 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1540 {
1541 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1542 }
1543
1544 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1545 uint64_t value)
1546 {
1547 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1548 }
1549
1550 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1551 {
1552 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1553 }
1554
1555 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1556 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1557 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1558 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1559 .resetvalue = 0,
1560 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1561 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1562 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1563 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1564 .resetvalue = 0,
1565 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1566 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1567 .access = PL1_RW,
1568 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1569 .resetvalue = 0, },
1570 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1571 .access = PL1_RW,
1572 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1573 .resetvalue = 0, },
1574 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1575 .access = PL1_RW,
1576 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1577 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1578 .access = PL1_RW,
1579 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1580 /* Protection region base and size registers */
1581 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1582 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1583 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1584 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1585 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1586 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1587 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1588 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1589 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1590 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1591 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1592 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1593 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1594 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1595 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1596 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1597 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1598 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1599 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1600 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1601 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1602 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1603 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1604 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1605 REGINFO_SENTINEL
1606 };
1607
1608 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1609 uint64_t value)
1610 {
1611 TCR *tcr = raw_ptr(env, ri);
1612 int maskshift = extract32(value, 0, 3);
1613
1614 if (!arm_feature(env, ARM_FEATURE_V8)) {
1615 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
1616 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1617 * using Long-desciptor translation table format */
1618 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1619 } else if (arm_feature(env, ARM_FEATURE_EL3)) {
1620 /* In an implementation that includes the Security Extensions
1621 * TTBCR has additional fields PD0 [4] and PD1 [5] for
1622 * Short-descriptor translation table format.
1623 */
1624 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
1625 } else {
1626 value &= TTBCR_N;
1627 }
1628 }
1629
1630 /* Update the masks corresponding to the the TCR bank being written
1631 * Note that we always calculate mask and base_mask, but
1632 * they are only used for short-descriptor tables (ie if EAE is 0);
1633 * for long-descriptor tables the TCR fields are used differently
1634 * and the mask and base_mask values are meaningless.
1635 */
1636 tcr->raw_tcr = value;
1637 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1638 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
1639 }
1640
1641 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1642 uint64_t value)
1643 {
1644 ARMCPU *cpu = arm_env_get_cpu(env);
1645
1646 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1647 /* With LPAE the TTBCR could result in a change of ASID
1648 * via the TTBCR.A1 bit, so do a TLB flush.
1649 */
1650 tlb_flush(CPU(cpu), 1);
1651 }
1652 vmsa_ttbcr_raw_write(env, ri, value);
1653 }
1654
1655 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1656 {
1657 TCR *tcr = raw_ptr(env, ri);
1658
1659 /* Reset both the TCR as well as the masks corresponding to the bank of
1660 * the TCR being reset.
1661 */
1662 tcr->raw_tcr = 0;
1663 tcr->mask = 0;
1664 tcr->base_mask = 0xffffc000u;
1665 }
1666
1667 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1668 uint64_t value)
1669 {
1670 ARMCPU *cpu = arm_env_get_cpu(env);
1671 TCR *tcr = raw_ptr(env, ri);
1672
1673 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1674 tlb_flush(CPU(cpu), 1);
1675 tcr->raw_tcr = value;
1676 }
1677
1678 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1679 uint64_t value)
1680 {
1681 /* 64 bit accesses to the TTBRs can change the ASID and so we
1682 * must flush the TLB.
1683 */
1684 if (cpreg_field_is_64bit(ri)) {
1685 ARMCPU *cpu = arm_env_get_cpu(env);
1686
1687 tlb_flush(CPU(cpu), 1);
1688 }
1689 raw_write(env, ri, value);
1690 }
1691
1692 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1693 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1694 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1695 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
1696 offsetoflow32(CPUARMState, cp15.dfsr_ns) },
1697 .resetfn = arm_cp_reset_ignore, },
1698 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1699 .access = PL1_RW, .resetvalue = 0,
1700 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
1701 offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
1702 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1703 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1704 .access = PL1_RW,
1705 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
1706 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1707 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
1708 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
1709 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
1710 offsetof(CPUARMState, cp15.ttbr0_ns) } },
1711 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1712 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
1713 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
1714 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
1715 offsetof(CPUARMState, cp15.ttbr1_ns) } },
1716 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1717 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1718 .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1719 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1720 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
1721 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1722 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1723 .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1724 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
1725 offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
1726 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
1727 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1728 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
1729 .resetvalue = 0, },
1730 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
1731 .access = PL1_RW, .resetvalue = 0,
1732 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
1733 offsetof(CPUARMState, cp15.dfar_ns) } },
1734 REGINFO_SENTINEL
1735 };
1736
1737 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1738 uint64_t value)
1739 {
1740 env->cp15.c15_ticonfig = value & 0xe7;
1741 /* The OS_TYPE bit in this register changes the reported CPUID! */
1742 env->cp15.c0_cpuid = (value & (1 << 5)) ?
1743 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1744 }
1745
1746 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1747 uint64_t value)
1748 {
1749 env->cp15.c15_threadid = value & 0xffff;
1750 }
1751
1752 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1753 uint64_t value)
1754 {
1755 /* Wait-for-interrupt (deprecated) */
1756 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1757 }
1758
1759 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1760 uint64_t value)
1761 {
1762 /* On OMAP there are registers indicating the max/min index of dcache lines
1763 * containing a dirty line; cache flush operations have to reset these.
1764 */
1765 env->cp15.c15_i_max = 0x000;
1766 env->cp15.c15_i_min = 0xff0;
1767 }
1768
1769 static const ARMCPRegInfo omap_cp_reginfo[] = {
1770 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1771 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1772 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1773 .resetvalue = 0, },
1774 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1775 .access = PL1_RW, .type = ARM_CP_NOP },
1776 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1777 .access = PL1_RW,
1778 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1779 .writefn = omap_ticonfig_write },
1780 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1781 .access = PL1_RW,
1782 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1783 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1784 .access = PL1_RW, .resetvalue = 0xff0,
1785 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1786 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1787 .access = PL1_RW,
1788 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1789 .writefn = omap_threadid_write },
1790 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1791 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1792 .type = ARM_CP_NO_MIGRATE,
1793 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1794 /* TODO: Peripheral port remap register:
1795 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1796 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1797 * when MMU is off.
1798 */
1799 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1800 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1801 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1802 .writefn = omap_cachemaint_write },
1803 { .name = "C9", .cp = 15, .crn = 9,
1804 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1805 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1806 REGINFO_SENTINEL
1807 };
1808
1809 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1810 uint64_t value)
1811 {
1812 env->cp15.c15_cpar = value & 0x3fff;
1813 }
1814
1815 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1816 { .name = "XSCALE_CPAR",
1817 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1818 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1819 .writefn = xscale_cpar_write, },
1820 { .name = "XSCALE_AUXCR",
1821 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1822 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1823 .resetvalue = 0, },
1824 /* XScale specific cache-lockdown: since we have no cache we NOP these
1825 * and hope the guest does not really rely on cache behaviour.
1826 */
1827 { .name = "XSCALE_LOCK_ICACHE_LINE",
1828 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1829 .access = PL1_W, .type = ARM_CP_NOP },
1830 { .name = "XSCALE_UNLOCK_ICACHE",
1831 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1832 .access = PL1_W, .type = ARM_CP_NOP },
1833 { .name = "XSCALE_DCACHE_LOCK",
1834 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
1835 .access = PL1_RW, .type = ARM_CP_NOP },
1836 { .name = "XSCALE_UNLOCK_DCACHE",
1837 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
1838 .access = PL1_W, .type = ARM_CP_NOP },
1839 REGINFO_SENTINEL
1840 };
1841
1842 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1843 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1844 * implementation of this implementation-defined space.
1845 * Ideally this should eventually disappear in favour of actually
1846 * implementing the correct behaviour for all cores.
1847 */
1848 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1849 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1850 .access = PL1_RW,
1851 .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1852 .resetvalue = 0 },
1853 REGINFO_SENTINEL
1854 };
1855
1856 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1857 /* Cache status: RAZ because we have no cache so it's always clean */
1858 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1859 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1860 .resetvalue = 0 },
1861 REGINFO_SENTINEL
1862 };
1863
1864 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1865 /* We never have a a block transfer operation in progress */
1866 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1867 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1868 .resetvalue = 0 },
1869 /* The cache ops themselves: these all NOP for QEMU */
1870 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1871 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1872 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1873 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1874 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1875 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1876 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1877 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1878 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1879 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1880 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1881 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1882 REGINFO_SENTINEL
1883 };
1884
1885 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1886 /* The cache test-and-clean instructions always return (1 << 30)
1887 * to indicate that there are no dirty cache lines.
1888 */
1889 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1890 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1891 .resetvalue = (1 << 30) },
1892 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1893 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1894 .resetvalue = (1 << 30) },
1895 REGINFO_SENTINEL
1896 };
1897
1898 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1899 /* Ignore ReadBuffer accesses */
1900 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1901 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1902 .access = PL1_RW, .resetvalue = 0,
1903 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1904 REGINFO_SENTINEL
1905 };
1906
1907 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1908 {
1909 CPUState *cs = CPU(arm_env_get_cpu(env));
1910 uint32_t mpidr = cs->cpu_index;
1911 /* We don't support setting cluster ID ([8..11]) (known as Aff1
1912 * in later ARM ARM versions), or any of the higher affinity level fields,
1913 * so these bits always RAZ.
1914 */
1915 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1916 mpidr |= (1U << 31);
1917 /* Cores which are uniprocessor (non-coherent)
1918 * but still implement the MP extensions set
1919 * bit 30. (For instance, A9UP.) However we do
1920 * not currently model any of those cores.
1921 */
1922 }
1923 return mpidr;
1924 }
1925
1926 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1927 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1928 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1929 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1930 REGINFO_SENTINEL
1931 };
1932
1933 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1934 /* NOP AMAIR0/1: the override is because these clash with the rather
1935 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1936 */
1937 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1938 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1939 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1940 .resetvalue = 0 },
1941 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1942 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1943 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1944 .resetvalue = 0 },
1945 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1946 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
1947 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
1948 offsetof(CPUARMState, cp15.par_ns)} },
1949 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1950 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1951 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
1952 offsetof(CPUARMState, cp15.ttbr0_ns) },
1953 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1954 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1955 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1956 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
1957 offsetof(CPUARMState, cp15.ttbr1_ns) },
1958 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1959 REGINFO_SENTINEL
1960 };
1961
1962 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1963 {
1964 return vfp_get_fpcr(env);
1965 }
1966
1967 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1968 uint64_t value)
1969 {
1970 vfp_set_fpcr(env, value);
1971 }
1972
1973 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1974 {
1975 return vfp_get_fpsr(env);
1976 }
1977
1978 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1979 uint64_t value)
1980 {
1981 vfp_set_fpsr(env, value);
1982 }
1983
1984 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
1985 {
1986 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
1987 return CP_ACCESS_TRAP;
1988 }
1989 return CP_ACCESS_OK;
1990 }
1991
1992 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
1993 uint64_t value)
1994 {
1995 env->daif = value & PSTATE_DAIF;
1996 }
1997
1998 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1999 const ARMCPRegInfo *ri)
2000 {
2001 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2002 * SCTLR_EL1.UCI is set.
2003 */
2004 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2005 return CP_ACCESS_TRAP;
2006 }
2007 return CP_ACCESS_OK;
2008 }
2009
2010 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2011 * Page D4-1736 (DDI0487A.b)
2012 */
2013
2014 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
2015 uint64_t value)
2016 {
2017 /* Invalidate by VA (AArch64 version) */
2018 ARMCPU *cpu = arm_env_get_cpu(env);
2019 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2020
2021 tlb_flush_page(CPU(cpu), pageaddr);
2022 }
2023
2024 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
2025 uint64_t value)
2026 {
2027 /* Invalidate by VA, all ASIDs (AArch64 version) */
2028 ARMCPU *cpu = arm_env_get_cpu(env);
2029 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2030
2031 tlb_flush_page(CPU(cpu), pageaddr);
2032 }
2033
2034 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2035 uint64_t value)
2036 {
2037 /* Invalidate by ASID (AArch64 version) */
2038 ARMCPU *cpu = arm_env_get_cpu(env);
2039 int asid = extract64(value, 48, 16);
2040 tlb_flush(CPU(cpu), asid == 0);
2041 }
2042
2043 static void tlbi_aa64_va_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2044 uint64_t value)
2045 {
2046 CPUState *other_cs;
2047 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2048
2049 CPU_FOREACH(other_cs) {
2050 tlb_flush_page(other_cs, pageaddr);
2051 }
2052 }
2053
2054 static void tlbi_aa64_vaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2055 uint64_t value)
2056 {
2057 CPUState *other_cs;
2058 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2059
2060 CPU_FOREACH(other_cs) {
2061 tlb_flush_page(other_cs, pageaddr);
2062 }
2063 }
2064
2065 static void tlbi_aa64_asid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2066 uint64_t value)
2067 {
2068 CPUState *other_cs;
2069 int asid = extract64(value, 48, 16);
2070
2071 CPU_FOREACH(other_cs) {
2072 tlb_flush(other_cs, asid == 0);
2073 }
2074 }
2075
2076 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
2077 {
2078 /* We don't implement EL2, so the only control on DC ZVA is the
2079 * bit in the SCTLR which can prohibit access for EL0.
2080 */
2081 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
2082 return CP_ACCESS_TRAP;
2083 }
2084 return CP_ACCESS_OK;
2085 }
2086
2087 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
2088 {
2089 ARMCPU *cpu = arm_env_get_cpu(env);
2090 int dzp_bit = 1 << 4;
2091
2092 /* DZP indicates whether DC ZVA access is allowed */
2093 if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
2094 dzp_bit = 0;
2095 }
2096 return cpu->dcz_blocksize | dzp_bit;
2097 }
2098
2099 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2100 {
2101 if (!(env->pstate & PSTATE_SP)) {
2102 /* Access to SP_EL0 is undefined if it's being used as
2103 * the stack pointer.
2104 */
2105 return CP_ACCESS_TRAP_UNCATEGORIZED;
2106 }
2107 return CP_ACCESS_OK;
2108 }
2109
2110 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
2111 {
2112 return env->pstate & PSTATE_SP;
2113 }
2114
2115 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
2116 {
2117 update_spsel(env, val);
2118 }
2119
2120 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2121 uint64_t value)
2122 {
2123 ARMCPU *cpu = arm_env_get_cpu(env);
2124
2125 if (raw_read(env, ri) == value) {
2126 /* Skip the TLB flush if nothing actually changed; Linux likes
2127 * to do a lot of pointless SCTLR writes.
2128 */
2129 return;
2130 }
2131
2132 raw_write(env, ri, value);
2133 /* ??? Lots of these bits are not implemented. */
2134 /* This may enable/disable the MMU, so do a TLB flush. */
2135 tlb_flush(CPU(cpu), 1);
2136 }
2137
2138 static const ARMCPRegInfo v8_cp_reginfo[] = {
2139 /* Minimal set of EL0-visible registers. This will need to be expanded
2140 * significantly for system emulation of AArch64 CPUs.
2141 */
2142 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
2143 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
2144 .access = PL0_RW, .type = ARM_CP_NZCV },
2145 { .name = "DAIF", .state = ARM_CP_STATE_AA64,
2146 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
2147 .type = ARM_CP_NO_MIGRATE,
2148 .access = PL0_RW, .accessfn = aa64_daif_access,
2149 .fieldoffset = offsetof(CPUARMState, daif),
2150 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
2151 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
2152 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
2153 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
2154 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
2155 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
2156 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
2157 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
2158 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
2159 .access = PL0_R, .type = ARM_CP_NO_MIGRATE,
2160 .readfn = aa64_dczid_read },
2161 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
2162 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
2163 .access = PL0_W, .type = ARM_CP_DC_ZVA,
2164 #ifndef CONFIG_USER_ONLY
2165 /* Avoid overhead of an access check that always passes in user-mode */
2166 .accessfn = aa64_zva_access,
2167 #endif
2168 },
2169 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
2170 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
2171 .access = PL1_R, .type = ARM_CP_CURRENTEL },
2172 /* Cache ops: all NOPs since we don't emulate caches */
2173 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
2174 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2175 .access = PL1_W, .type = ARM_CP_NOP },
2176 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
2177 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2178 .access = PL1_W, .type = ARM_CP_NOP },
2179 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
2180 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
2181 .access = PL0_W, .type = ARM_CP_NOP,
2182 .accessfn = aa64_cacheop_access },
2183 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
2184 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2185 .access = PL1_W, .type = ARM_CP_NOP },
2186 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
2187 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2188 .access = PL1_W, .type = ARM_CP_NOP },
2189 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
2190 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
2191 .access = PL0_W, .type = ARM_CP_NOP,
2192 .accessfn = aa64_cacheop_access },
2193 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
2194 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2195 .access = PL1_W, .type = ARM_CP_NOP },
2196 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
2197 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
2198 .access = PL0_W, .type = ARM_CP_NOP,
2199 .accessfn = aa64_cacheop_access },
2200 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
2201 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
2202 .access = PL0_W, .type = ARM_CP_NOP,
2203 .accessfn = aa64_cacheop_access },
2204 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
2205 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2206 .access = PL1_W, .type = ARM_CP_NOP },
2207 /* TLBI operations */
2208 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
2209 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2210 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2211 .writefn = tlbiall_is_write },
2212 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2213 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2214 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2215 .writefn = tlbi_aa64_va_is_write },
2216 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2217 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2218 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2219 .writefn = tlbi_aa64_asid_is_write },
2220 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2221 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2222 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2223 .writefn = tlbi_aa64_vaa_is_write },
2224 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2225 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2226 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2227 .writefn = tlbi_aa64_va_is_write },
2228 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2229 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2230 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2231 .writefn = tlbi_aa64_vaa_is_write },
2232 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2233 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2234 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2235 .writefn = tlbiall_write },
2236 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2237 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2238 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2239 .writefn = tlbi_aa64_va_write },
2240 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2241 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2242 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2243 .writefn = tlbi_aa64_asid_write },
2244 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
2245 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2246 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2247 .writefn = tlbi_aa64_vaa_write },
2248 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
2249 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2250 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2251 .writefn = tlbi_aa64_va_write },
2252 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
2253 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2254 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2255 .writefn = tlbi_aa64_vaa_write },
2256 #ifndef CONFIG_USER_ONLY
2257 /* 64 bit address translation operations */
2258 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
2259 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
2260 .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2261 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
2262 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
2263 .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2264 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
2265 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
2266 .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2267 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
2268 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
2269 .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2270 #endif
2271 /* TLB invalidate last level of translation table walk */
2272 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2273 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_is_write },
2274 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2275 .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
2276 .writefn = tlbimvaa_is_write },
2277 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2278 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2279 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2280 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2281 /* 32 bit cache operations */
2282 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2283 .type = ARM_CP_NOP, .access = PL1_W },
2284 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
2285 .type = ARM_CP_NOP, .access = PL1_W },
2286 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2287 .type = ARM_CP_NOP, .access = PL1_W },
2288 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
2289 .type = ARM_CP_NOP, .access = PL1_W },
2290 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
2291 .type = ARM_CP_NOP, .access = PL1_W },
2292 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
2293 .type = ARM_CP_NOP, .access = PL1_W },
2294 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2295 .type = ARM_CP_NOP, .access = PL1_W },
2296 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2297 .type = ARM_CP_NOP, .access = PL1_W },
2298 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
2299 .type = ARM_CP_NOP, .access = PL1_W },
2300 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2301 .type = ARM_CP_NOP, .access = PL1_W },
2302 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
2303 .type = ARM_CP_NOP, .access = PL1_W },
2304 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
2305 .type = ARM_CP_NOP, .access = PL1_W },
2306 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2307 .type = ARM_CP_NOP, .access = PL1_W },
2308 /* MMU Domain access control / MPU write buffer control */
2309 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
2310 .access = PL1_RW, .resetvalue = 0,
2311 .writefn = dacr_write, .raw_writefn = raw_write,
2312 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
2313 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
2314 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
2315 .type = ARM_CP_NO_MIGRATE,
2316 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
2317 .access = PL1_RW,
2318 .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
2319 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
2320 .type = ARM_CP_NO_MIGRATE,
2321 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
2322 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
2323 /* We rely on the access checks not allowing the guest to write to the
2324 * state field when SPSel indicates that it's being used as the stack
2325 * pointer.
2326 */
2327 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
2328 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
2329 .access = PL1_RW, .accessfn = sp_el0_access,
2330 .type = ARM_CP_NO_MIGRATE,
2331 .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
2332 { .name = "SPSel", .state = ARM_CP_STATE_AA64,
2333 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
2334 .type = ARM_CP_NO_MIGRATE,
2335 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
2336 REGINFO_SENTINEL
2337 };
2338
2339 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
2340 static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
2341 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2342 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2343 .access = PL2_RW,
2344 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2345 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
2346 .type = ARM_CP_NO_MIGRATE,
2347 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
2348 .access = PL2_RW,
2349 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2350 REGINFO_SENTINEL
2351 };
2352
2353 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2354 {
2355 ARMCPU *cpu = arm_env_get_cpu(env);
2356 uint64_t valid_mask = HCR_MASK;
2357
2358 if (arm_feature(env, ARM_FEATURE_EL3)) {
2359 valid_mask &= ~HCR_HCD;
2360 } else {
2361 valid_mask &= ~HCR_TSC;
2362 }
2363
2364 /* Clear RES0 bits. */
2365 value &= valid_mask;
2366
2367 /* These bits change the MMU setup:
2368 * HCR_VM enables stage 2 translation
2369 * HCR_PTW forbids certain page-table setups
2370 * HCR_DC Disables stage1 and enables stage2 translation
2371 */
2372 if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
2373 tlb_flush(CPU(cpu), 1);
2374 }
2375 raw_write(env, ri, value);
2376 }
2377
2378 static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
2379 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
2380 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
2381 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
2382 .writefn = hcr_write },
2383 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
2384 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
2385 .access = PL2_RW, .resetvalue = 0,
2386 .writefn = dacr_write, .raw_writefn = raw_write,
2387 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
2388 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
2389 .type = ARM_CP_NO_MIGRATE,
2390 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
2391 .access = PL2_RW,
2392 .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
2393 { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
2394 .type = ARM_CP_NO_MIGRATE,
2395 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
2396 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
2397 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
2398 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
2399 .access = PL2_RW, .resetvalue = 0,
2400 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
2401 { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
2402 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
2403 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
2404 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
2405 .type = ARM_CP_NO_MIGRATE,
2406 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
2407 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
2408 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2409 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2410 .access = PL2_RW, .writefn = vbar_write,
2411 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
2412 .resetvalue = 0 },
2413 REGINFO_SENTINEL
2414 };
2415
2416 static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
2417 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
2418 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
2419 .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
2420 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
2421 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
2422 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
2423 .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2424 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
2425 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
2426 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
2427 .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
2428 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2429 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
2430 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
2431 .type = ARM_CP_NO_MIGRATE,
2432 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
2433 .access = PL3_RW,
2434 .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
2435 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
2436 .type = ARM_CP_NO_MIGRATE,
2437 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
2438 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
2439 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
2440 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
2441 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
2442 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
2443 .type = ARM_CP_NO_MIGRATE,
2444 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
2445 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
2446 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
2447 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
2448 .access = PL3_RW, .writefn = vbar_write,
2449 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
2450 .resetvalue = 0 },
2451 REGINFO_SENTINEL
2452 };
2453
2454 static const ARMCPRegInfo el3_cp_reginfo[] = {
2455 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
2456 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
2457 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
2458 .resetvalue = 0, .writefn = scr_write },
2459 { .name = "SCR", .type = ARM_CP_NO_MIGRATE,
2460 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
2461 .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
2462 .resetfn = arm_cp_reset_ignore, .writefn = scr_write },
2463 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
2464 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
2465 .access = PL3_RW, .resetvalue = 0,
2466 .fieldoffset = offsetof(CPUARMState, cp15.sder) },
2467 { .name = "SDER",
2468 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
2469 .access = PL3_RW, .resetvalue = 0,
2470 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
2471 /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
2472 { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
2473 .access = PL3_W | PL1_R, .resetvalue = 0,
2474 .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
2475 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
2476 .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
2477 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
2478 REGINFO_SENTINEL
2479 };
2480
2481 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2482 {
2483 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2484 * but the AArch32 CTR has its own reginfo struct)
2485 */
2486 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
2487 return CP_ACCESS_TRAP;
2488 }
2489 return CP_ACCESS_OK;
2490 }
2491
2492 static const ARMCPRegInfo debug_cp_reginfo[] = {
2493 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
2494 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
2495 * unlike DBGDRAR it is never accessible from EL0.
2496 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
2497 * accessor.
2498 */
2499 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2500 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2501 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
2502 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
2503 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2504 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2505 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2506 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
2507 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
2508 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2509 .access = PL1_RW,
2510 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2511 .resetvalue = 0 },
2512 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
2513 * We don't implement the configurable EL0 access.
2514 */
2515 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
2516 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2517 .type = ARM_CP_NO_MIGRATE,
2518 .access = PL1_R,
2519 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2520 .resetfn = arm_cp_reset_ignore },
2521 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2522 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
2523 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
2524 .access = PL1_W, .type = ARM_CP_NOP },
2525 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
2526 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
2527 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
2528 .access = PL1_RW, .type = ARM_CP_NOP },
2529 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
2530 * implement vector catch debug events yet.
2531 */
2532 { .name = "DBGVCR",
2533 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2534 .access = PL1_RW, .type = ARM_CP_NOP },
2535 REGINFO_SENTINEL
2536 };
2537
2538 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
2539 /* 64 bit access versions of the (dummy) debug registers */
2540 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
2541 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2542 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
2543 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2544 REGINFO_SENTINEL
2545 };
2546
2547 void hw_watchpoint_update(ARMCPU *cpu, int n)
2548 {
2549 CPUARMState *env = &cpu->env;
2550 vaddr len = 0;
2551 vaddr wvr = env->cp15.dbgwvr[n];
2552 uint64_t wcr = env->cp15.dbgwcr[n];
2553 int mask;
2554 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
2555
2556 if (env->cpu_watchpoint[n]) {
2557 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
2558 env->cpu_watchpoint[n] = NULL;
2559 }
2560
2561 if (!extract64(wcr, 0, 1)) {
2562 /* E bit clear : watchpoint disabled */
2563 return;
2564 }
2565
2566 switch (extract64(wcr, 3, 2)) {
2567 case 0:
2568 /* LSC 00 is reserved and must behave as if the wp is disabled */
2569 return;
2570 case 1:
2571 flags |= BP_MEM_READ;
2572 break;
2573 case 2:
2574 flags |= BP_MEM_WRITE;
2575 break;
2576 case 3:
2577 flags |= BP_MEM_ACCESS;
2578 break;
2579 }
2580
2581 /* Attempts to use both MASK and BAS fields simultaneously are
2582 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
2583 * thus generating a watchpoint for every byte in the masked region.
2584 */
2585 mask = extract64(wcr, 24, 4);
2586 if (mask == 1 || mask == 2) {
2587 /* Reserved values of MASK; we must act as if the mask value was
2588 * some non-reserved value, or as if the watchpoint were disabled.
2589 * We choose the latter.
2590 */
2591 return;
2592 } else if (mask) {
2593 /* Watchpoint covers an aligned area up to 2GB in size */
2594 len = 1ULL << mask;
2595 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
2596 * whether the watchpoint fires when the unmasked bits match; we opt
2597 * to generate the exceptions.
2598 */
2599 wvr &= ~(len - 1);
2600 } else {
2601 /* Watchpoint covers bytes defined by the byte address select bits */
2602 int bas = extract64(wcr, 5, 8);
2603 int basstart;
2604
2605 if (bas == 0) {
2606 /* This must act as if the watchpoint is disabled */
2607 return;
2608 }
2609
2610 if (extract64(wvr, 2, 1)) {
2611 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
2612 * ignored, and BAS[3:0] define which bytes to watch.
2613 */
2614 bas &= 0xf;
2615 }
2616 /* The BAS bits are supposed to be programmed to indicate a contiguous
2617 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
2618 * we fire for each byte in the word/doubleword addressed by the WVR.
2619 * We choose to ignore any non-zero bits after the first range of 1s.
2620 */
2621 basstart = ctz32(bas);
2622 len = cto32(bas >> basstart);
2623 wvr += basstart;
2624 }
2625
2626 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
2627 &env->cpu_watchpoint[n]);
2628 }
2629
2630 void hw_watchpoint_update_all(ARMCPU *cpu)
2631 {
2632 int i;
2633 CPUARMState *env = &cpu->env;
2634
2635 /* Completely clear out existing QEMU watchpoints and our array, to
2636 * avoid possible stale entries following migration load.
2637 */
2638 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
2639 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
2640
2641 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
2642 hw_watchpoint_update(cpu, i);
2643 }
2644 }
2645
2646 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2647 uint64_t value)
2648 {
2649 ARMCPU *cpu = arm_env_get_cpu(env);
2650 int i = ri->crm;
2651
2652 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
2653 * register reads and behaves as if values written are sign extended.
2654 * Bits [1:0] are RES0.
2655 */
2656 value = sextract64(value, 0, 49) & ~3ULL;
2657
2658 raw_write(env, ri, value);
2659 hw_watchpoint_update(cpu, i);
2660 }
2661
2662 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2663 uint64_t value)
2664 {
2665 ARMCPU *cpu = arm_env_get_cpu(env);
2666 int i = ri->crm;
2667
2668 raw_write(env, ri, value);
2669 hw_watchpoint_update(cpu, i);
2670 }
2671
2672 void hw_breakpoint_update(ARMCPU *cpu, int n)
2673 {
2674 CPUARMState *env = &cpu->env;
2675 uint64_t bvr = env->cp15.dbgbvr[n];
2676 uint64_t bcr = env->cp15.dbgbcr[n];
2677 vaddr addr;
2678 int bt;
2679 int flags = BP_CPU;
2680
2681 if (env->cpu_breakpoint[n]) {
2682 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
2683 env->cpu_breakpoint[n] = NULL;
2684 }
2685
2686 if (!extract64(bcr, 0, 1)) {
2687 /* E bit clear : watchpoint disabled */
2688 return;
2689 }
2690
2691 bt = extract64(bcr, 20, 4);
2692
2693 switch (bt) {
2694 case 4: /* unlinked address mismatch (reserved if AArch64) */
2695 case 5: /* linked address mismatch (reserved if AArch64) */
2696 qemu_log_mask(LOG_UNIMP,
2697 "arm: address mismatch breakpoint types not implemented");
2698 return;
2699 case 0: /* unlinked address match */
2700 case 1: /* linked address match */
2701 {
2702 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
2703 * we behave as if the register was sign extended. Bits [1:0] are
2704 * RES0. The BAS field is used to allow setting breakpoints on 16
2705 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
2706 * a bp will fire if the addresses covered by the bp and the addresses
2707 * covered by the insn overlap but the insn doesn't start at the
2708 * start of the bp address range. We choose to require the insn and
2709 * the bp to have the same address. The constraints on writing to
2710 * BAS enforced in dbgbcr_write mean we have only four cases:
2711 * 0b0000 => no breakpoint
2712 * 0b0011 => breakpoint on addr
2713 * 0b1100 => breakpoint on addr + 2
2714 * 0b1111 => breakpoint on addr
2715 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
2716 */
2717 int bas = extract64(bcr, 5, 4);
2718 addr = sextract64(bvr, 0, 49) & ~3ULL;
2719 if (bas == 0) {
2720 return;
2721 }
2722 if (bas == 0xc) {
2723 addr += 2;
2724 }
2725 break;
2726 }
2727 case 2: /* unlinked context ID match */
2728 case 8: /* unlinked VMID match (reserved if no EL2) */
2729 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
2730 qemu_log_mask(LOG_UNIMP,
2731 "arm: unlinked context breakpoint types not implemented");
2732 return;
2733 case 9: /* linked VMID match (reserved if no EL2) */
2734 case 11: /* linked context ID and VMID match (reserved if no EL2) */
2735 case 3: /* linked context ID match */
2736 default:
2737 /* We must generate no events for Linked context matches (unless
2738 * they are linked to by some other bp/wp, which is handled in
2739 * updates for the linking bp/wp). We choose to also generate no events
2740 * for reserved values.
2741 */
2742 return;
2743 }
2744
2745 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
2746 }
2747
2748 void hw_breakpoint_update_all(ARMCPU *cpu)
2749 {
2750 int i;
2751 CPUARMState *env = &cpu->env;
2752
2753 /* Completely clear out existing QEMU breakpoints and our array, to
2754 * avoid possible stale entries following migration load.
2755 */
2756 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
2757 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
2758
2759 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
2760 hw_breakpoint_update(cpu, i);
2761 }
2762 }
2763
2764 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2765 uint64_t value)
2766 {
2767 ARMCPU *cpu = arm_env_get_cpu(env);
2768 int i = ri->crm;
2769
2770 raw_write(env, ri, value);
2771 hw_breakpoint_update(cpu, i);
2772 }
2773
2774 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2775 uint64_t value)
2776 {
2777 ARMCPU *cpu = arm_env_get_cpu(env);
2778 int i = ri->crm;
2779
2780 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
2781 * copy of BAS[0].
2782 */
2783 value = deposit64(value, 6, 1, extract64(value, 5, 1));
2784 value = deposit64(value, 8, 1, extract64(value, 7, 1));
2785
2786 raw_write(env, ri, value);
2787 hw_breakpoint_update(cpu, i);
2788 }
2789
2790 static void define_debug_regs(ARMCPU *cpu)
2791 {
2792 /* Define v7 and v8 architectural debug registers.
2793 * These are just dummy implementations for now.
2794 */
2795 int i;
2796 int wrps, brps, ctx_cmps;
2797 ARMCPRegInfo dbgdidr = {
2798 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
2799 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
2800 };
2801
2802 /* Note that all these register fields hold "number of Xs minus 1". */
2803 brps = extract32(cpu->dbgdidr, 24, 4);
2804 wrps = extract32(cpu->dbgdidr, 28, 4);
2805 ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
2806
2807 assert(ctx_cmps <= brps);
2808
2809 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
2810 * of the debug registers such as number of breakpoints;
2811 * check that if they both exist then they agree.
2812 */
2813 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
2814 assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
2815 assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
2816 assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
2817 }
2818
2819 define_one_arm_cp_reg(cpu, &dbgdidr);
2820 define_arm_cp_regs(cpu, debug_cp_reginfo);
2821
2822 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
2823 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
2824 }
2825
2826 for (i = 0; i < brps + 1; i++) {
2827 ARMCPRegInfo dbgregs[] = {
2828 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
2829 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
2830 .access = PL1_RW,
2831 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
2832 .writefn = dbgbvr_write, .raw_writefn = raw_write
2833 },
2834 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
2835 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
2836 .access = PL1_RW,
2837 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
2838 .writefn = dbgbcr_write, .raw_writefn = raw_write
2839 },
2840 REGINFO_SENTINEL
2841 };
2842 define_arm_cp_regs(cpu, dbgregs);
2843 }
2844
2845 for (i = 0; i < wrps + 1; i++) {
2846 ARMCPRegInfo dbgregs[] = {
2847 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
2848 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
2849 .access = PL1_RW,
2850 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
2851 .writefn = dbgwvr_write, .raw_writefn = raw_write
2852 },
2853 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
2854 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
2855 .access = PL1_RW,
2856 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
2857 .writefn = dbgwcr_write, .raw_writefn = raw_write
2858 },
2859 REGINFO_SENTINEL
2860 };
2861 define_arm_cp_regs(cpu, dbgregs);
2862 }
2863 }
2864
2865 void register_cp_regs_for_features(ARMCPU *cpu)
2866 {
2867 /* Register all the coprocessor registers based on feature bits */
2868 CPUARMState *env = &cpu->env;
2869 if (arm_feature(env, ARM_FEATURE_M)) {
2870 /* M profile has no coprocessor registers */
2871 return;
2872 }
2873
2874 define_arm_cp_regs(cpu, cp_reginfo);
2875 if (!arm_feature(env, ARM_FEATURE_V8)) {
2876 /* Must go early as it is full of wildcards that may be
2877 * overridden by later definitions.
2878 */
2879 define_arm_cp_regs(cpu, not_v8_cp_reginfo);
2880 }
2881
2882 if (arm_feature(env, ARM_FEATURE_V6)) {
2883 /* The ID registers all have impdef reset values */
2884 ARMCPRegInfo v6_idregs[] = {
2885 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
2886 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2887 .access = PL1_R, .type = ARM_CP_CONST,
2888 .resetvalue = cpu->id_pfr0 },
2889 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
2890 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
2891 .access = PL1_R, .type = ARM_CP_CONST,
2892 .resetvalue = cpu->id_pfr1 },
2893 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
2894 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
2895 .access = PL1_R, .type = ARM_CP_CONST,
2896 .resetvalue = cpu->id_dfr0 },
2897 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
2898 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
2899 .access = PL1_R, .type = ARM_CP_CONST,
2900 .resetvalue = cpu->id_afr0 },
2901 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
2902 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
2903 .access = PL1_R, .type = ARM_CP_CONST,
2904 .resetvalue = cpu->id_mmfr0 },
2905 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
2906 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
2907 .access = PL1_R, .type = ARM_CP_CONST,
2908 .resetvalue = cpu->id_mmfr1 },
2909 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
2910 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
2911 .access = PL1_R, .type = ARM_CP_CONST,
2912 .resetvalue = cpu->id_mmfr2 },
2913 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
2914 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
2915 .access = PL1_R, .type = ARM_CP_CONST,
2916 .resetvalue = cpu->id_mmfr3 },
2917 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
2918 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
2919 .access = PL1_R, .type = ARM_CP_CONST,
2920 .resetvalue = cpu->id_isar0 },
2921 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
2922 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
2923 .access = PL1_R, .type = ARM_CP_CONST,
2924 .resetvalue = cpu->id_isar1 },
2925 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
2926 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2927 .access = PL1_R, .type = ARM_CP_CONST,
2928 .resetvalue = cpu->id_isar2 },
2929 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
2930 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
2931 .access = PL1_R, .type = ARM_CP_CONST,
2932 .resetvalue = cpu->id_isar3 },
2933 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
2934 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
2935 .access = PL1_R, .type = ARM_CP_CONST,
2936 .resetvalue = cpu->id_isar4 },
2937 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
2938 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
2939 .access = PL1_R, .type = ARM_CP_CONST,
2940 .resetvalue = cpu->id_isar5 },
2941 /* 6..7 are as yet unallocated and must RAZ */
2942 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
2943 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
2944 .resetvalue = 0 },
2945 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
2946 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
2947 .resetvalue = 0 },
2948 REGINFO_SENTINEL
2949 };
2950 define_arm_cp_regs(cpu, v6_idregs);
2951 define_arm_cp_regs(cpu, v6_cp_reginfo);
2952 } else {
2953 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
2954 }
2955 if (arm_feature(env, ARM_FEATURE_V6K)) {
2956 define_arm_cp_regs(cpu, v6k_cp_reginfo);
2957 }
2958 if (arm_feature(env, ARM_FEATURE_V7MP)) {
2959 define_arm_cp_regs(cpu, v7mp_cp_reginfo);
2960 }
2961 if (arm_feature(env, ARM_FEATURE_V7)) {
2962 /* v7 performance monitor control register: same implementor
2963 * field as main ID register, and we implement only the cycle
2964 * count register.
2965 */
2966 #ifndef CONFIG_USER_ONLY
2967 ARMCPRegInfo pmcr = {
2968 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
2969 .access = PL0_RW,
2970 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE,
2971 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
2972 .accessfn = pmreg_access, .writefn = pmcr_write,
2973 .raw_writefn = raw_write,
2974 };
2975 ARMCPRegInfo pmcr64 = {
2976 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
2977 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
2978 .access = PL0_RW, .accessfn = pmreg_access,
2979 .type = ARM_CP_IO,
2980 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
2981 .resetvalue = cpu->midr & 0xff000000,
2982 .writefn = pmcr_write, .raw_writefn = raw_write,
2983 };
2984 define_one_arm_cp_reg(cpu, &pmcr);
2985 define_one_arm_cp_reg(cpu, &pmcr64);
2986 #endif
2987 ARMCPRegInfo clidr = {
2988 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
2989 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
2990 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
2991 };
2992 define_one_arm_cp_reg(cpu, &clidr);
2993 define_arm_cp_regs(cpu, v7_cp_reginfo);
2994 define_debug_regs(cpu);
2995 } else {
2996 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
2997 }
2998 if (arm_feature(env, ARM_FEATURE_V8)) {
2999 /* AArch64 ID registers, which all have impdef reset values */
3000 ARMCPRegInfo v8_idregs[] = {
3001 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
3002 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
3003 .access = PL1_R, .type = ARM_CP_CONST,
3004 .resetvalue = cpu->id_aa64pfr0 },
3005 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
3006 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
3007 .access = PL1_R, .type = ARM_CP_CONST,
3008 .resetvalue = cpu->id_aa64pfr1},
3009 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
3010 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
3011 .access = PL1_R, .type = ARM_CP_CONST,
3012 /* We mask out the PMUVer field, because we don't currently
3013 * implement the PMU. Not advertising it prevents the guest
3014 * from trying to use it and getting UNDEFs on registers we
3015 * don't implement.
3016 */
3017 .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
3018 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
3019 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
3020 .access = PL1_R, .type = ARM_CP_CONST,
3021 .resetvalue = cpu->id_aa64dfr1 },
3022 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
3023 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
3024 .access = PL1_R, .type = ARM_CP_CONST,
3025 .resetvalue = cpu->id_aa64afr0 },
3026 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
3027 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
3028 .access = PL1_R, .type = ARM_CP_CONST,
3029 .resetvalue = cpu->id_aa64afr1 },
3030 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
3031 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
3032 .access = PL1_R, .type = ARM_CP_CONST,
3033 .resetvalue = cpu->id_aa64isar0 },
3034 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
3035 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
3036 .access = PL1_R, .type = ARM_CP_CONST,
3037 .resetvalue = cpu->id_aa64isar1 },
3038 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
3039 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3040 .access = PL1_R, .type = ARM_CP_CONST,
3041 .resetvalue = cpu->id_aa64mmfr0 },
3042 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
3043 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
3044 .access = PL1_R, .type = ARM_CP_CONST,
3045 .resetvalue = cpu->id_aa64mmfr1 },
3046 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
3047 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
3048 .access = PL1_R, .type = ARM_CP_CONST,
3049 .resetvalue = cpu->mvfr0 },
3050 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
3051 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
3052 .access = PL1_R, .type = ARM_CP_CONST,
3053 .resetvalue = cpu->mvfr1 },
3054 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
3055 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
3056 .access = PL1_R, .type = ARM_CP_CONST,
3057 .resetvalue = cpu->mvfr2 },
3058 REGINFO_SENTINEL
3059 };
3060 ARMCPRegInfo rvbar = {
3061 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
3062 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
3063 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
3064 };
3065 define_one_arm_cp_reg(cpu, &rvbar);
3066 define_arm_cp_regs(cpu, v8_idregs);
3067 define_arm_cp_regs(cpu, v8_cp_reginfo);
3068 }
3069 if (arm_feature(env, ARM_FEATURE_EL2)) {
3070 define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
3071 } else {
3072 /* If EL2 is missing but higher ELs are enabled, we need to
3073 * register the no_el2 reginfos.
3074 */
3075 if (arm_feature(env, ARM_FEATURE_EL3)) {
3076 define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo);
3077 }
3078 }
3079 if (arm_feature(env, ARM_FEATURE_EL3)) {
3080 if (arm_feature(env, ARM_FEATURE_V8)) {
3081 define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
3082 }
3083 define_arm_cp_regs(cpu, el3_cp_reginfo);
3084 }
3085 if (arm_feature(env, ARM_FEATURE_MPU)) {
3086 /* These are the MPU registers prior to PMSAv6. Any new
3087 * PMSA core later than the ARM946 will require that we
3088 * implement the PMSAv6 or PMSAv7 registers, which are
3089 * completely different.
3090 */
3091 assert(!arm_feature(env, ARM_FEATURE_V6));
3092 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
3093 } else {
3094 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
3095 }
3096 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
3097 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
3098 }
3099 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
3100 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
3101 }
3102 if (arm_feature(env, ARM_FEATURE_VAPA)) {
3103 define_arm_cp_regs(cpu, vapa_cp_reginfo);
3104 }
3105 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
3106 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
3107 }
3108 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
3109 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
3110 }
3111 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
3112 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
3113 }
3114 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
3115 define_arm_cp_regs(cpu, omap_cp_reginfo);
3116 }
3117 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
3118 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
3119 }
3120 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3121 define_arm_cp_regs(cpu, xscale_cp_reginfo);
3122 }
3123 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
3124 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
3125 }
3126 if (arm_feature(env, ARM_FEATURE_LPAE)) {
3127 define_arm_cp_regs(cpu, lpae_cp_reginfo);
3128 }
3129 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
3130 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
3131 * be read-only (ie write causes UNDEF exception).
3132 */
3133 {
3134 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
3135 /* Pre-v8 MIDR space.
3136 * Note that the MIDR isn't a simple constant register because
3137 * of the TI925 behaviour where writes to another register can
3138 * cause the MIDR value to change.
3139 *
3140 * Unimplemented registers in the c15 0 0 0 space default to
3141 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
3142 * and friends override accordingly.
3143 */
3144 { .name = "MIDR",
3145 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
3146 .access = PL1_R, .resetvalue = cpu->midr,
3147 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
3148 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
3149 .type = ARM_CP_OVERRIDE },
3150 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
3151 { .name = "DUMMY",
3152 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
3153 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3154 { .name = "DUMMY",
3155 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
3156 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3157 { .name = "DUMMY",
3158 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
3159 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3160 { .name = "DUMMY",
3161 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
3162 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3163 { .name = "DUMMY",
3164 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
3165 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3166 REGINFO_SENTINEL
3167 };
3168 ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
3169 /* v8 MIDR -- the wildcard isn't necessary, and nor is the
3170 * variable-MIDR TI925 behaviour. Instead we have a single
3171 * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
3172 */
3173 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
3174 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
3175 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
3176 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
3177 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
3178 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
3179 REGINFO_SENTINEL
3180 };
3181 ARMCPRegInfo id_cp_reginfo[] = {
3182 /* These are common to v8 and pre-v8 */
3183 { .name = "CTR",
3184 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
3185 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
3186 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
3187 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
3188 .access = PL0_R, .accessfn = ctr_el0_access,
3189 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
3190 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
3191 { .name = "TCMTR",
3192 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
3193 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3194 { .name = "TLBTR",
3195 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
3196 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3197 REGINFO_SENTINEL
3198 };
3199 ARMCPRegInfo crn0_wi_reginfo = {
3200 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
3201 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
3202 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
3203 };
3204 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
3205 arm_feature(env, ARM_FEATURE_STRONGARM)) {
3206 ARMCPRegInfo *r;
3207 /* Register the blanket "writes ignored" value first to cover the
3208 * whole space. Then update the specific ID registers to allow write
3209 * access, so that they ignore writes rather than causing them to
3210 * UNDEF.
3211 */
3212 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
3213 for (r = id_pre_v8_midr_cp_reginfo;
3214 r->type != ARM_CP_SENTINEL; r++) {
3215 r->access = PL1_RW;
3216 }
3217 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
3218 r->access = PL1_RW;
3219 }
3220 }
3221 if (arm_feature(env, ARM_FEATURE_V8)) {
3222 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
3223 } else {
3224 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
3225 }
3226 define_arm_cp_regs(cpu, id_cp_reginfo);
3227 }
3228
3229 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
3230 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
3231 }
3232
3233 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
3234 ARMCPRegInfo auxcr = {
3235 .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
3236 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
3237 .access = PL1_RW, .type = ARM_CP_CONST,
3238 .resetvalue = cpu->reset_auxcr
3239 };
3240 define_one_arm_cp_reg(cpu, &auxcr);
3241 }
3242
3243 if (arm_feature(env, ARM_FEATURE_CBAR)) {
3244 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
3245 /* 32 bit view is [31:18] 0...0 [43:32]. */
3246 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
3247 | extract64(cpu->reset_cbar, 32, 12);
3248 ARMCPRegInfo cbar_reginfo[] = {
3249 { .name = "CBAR",
3250 .type = ARM_CP_CONST,
3251 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
3252 .access = PL1_R, .resetvalue = cpu->reset_cbar },
3253 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
3254 .type = ARM_CP_CONST,
3255 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
3256 .access = PL1_R, .resetvalue = cbar32 },
3257 REGINFO_SENTINEL
3258 };
3259 /* We don't implement a r/w 64 bit CBAR currently */
3260 assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
3261 define_arm_cp_regs(cpu, cbar_reginfo);
3262 } else {
3263 ARMCPRegInfo cbar = {
3264 .name = "CBAR",
3265 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
3266 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
3267 .fieldoffset = offsetof(CPUARMState,
3268 cp15.c15_config_base_address)
3269 };
3270 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
3271 cbar.access = PL1_R;
3272 cbar.fieldoffset = 0;
3273 cbar.type = ARM_CP_CONST;
3274 }
3275 define_one_arm_cp_reg(cpu, &cbar);
3276 }
3277 }
3278
3279 /* Generic registers whose values depend on the implementation */
3280 {
3281 ARMCPRegInfo sctlr = {
3282 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
3283 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3284 .access = PL1_RW,
3285 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
3286 offsetof(CPUARMState, cp15.sctlr_ns) },
3287 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
3288 .raw_writefn = raw_write,
3289 };
3290 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3291 /* Normally we would always end the TB on an SCTLR write, but Linux
3292 * arch/arm/mach-pxa/sleep.S expects two instructions following
3293 * an MMU enable to execute from cache. Imitate this behaviour.
3294 */
3295 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
3296 }
3297 define_one_arm_cp_reg(cpu, &sctlr);
3298 }
3299 }
3300
3301 ARMCPU *cpu_arm_init(const char *cpu_model)
3302 {
3303 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
3304 }
3305
3306 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
3307 {
3308 CPUState *cs = CPU(cpu);
3309 CPUARMState *env = &cpu->env;
3310
3311 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
3312 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
3313 aarch64_fpu_gdb_set_reg,
3314 34, "aarch64-fpu.xml", 0);
3315 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
3316 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3317 51, "arm-neon.xml", 0);
3318 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
3319 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3320 35, "arm-vfp3.xml", 0);
3321 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
3322 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3323 19, "arm-vfp.xml", 0);
3324 }
3325 }
3326
3327 /* Sort alphabetically by type name, except for "any". */
3328 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
3329 {
3330 ObjectClass *class_a = (ObjectClass *)a;
3331 ObjectClass *class_b = (ObjectClass *)b;
3332 const char *name_a, *name_b;
3333
3334 name_a = object_class_get_name(class_a);
3335 name_b = object_class_get_name(class_b);
3336 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
3337 return 1;
3338 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
3339 return -1;
3340 } else {
3341 return strcmp(name_a, name_b);
3342 }
3343 }
3344
3345 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
3346 {
3347 ObjectClass *oc = data;
3348 CPUListState *s = user_data;
3349 const char *typename;
3350 char *name;
3351
3352 typename = object_class_get_name(oc);
3353 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
3354 (*s->cpu_fprintf)(s->file, " %s\n",
3355 name);
3356 g_free(name);
3357 }
3358
3359 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
3360 {
3361 CPUListState s = {
3362 .file = f,
3363 .cpu_fprintf = cpu_fprintf,
3364 };
3365 GSList *list;
3366
3367 list = object_class_get_list(TYPE_ARM_CPU, false);
3368 list = g_slist_sort(list, arm_cpu_list_compare);
3369 (*cpu_fprintf)(f, "Available CPUs:\n");
3370 g_slist_foreach(list, arm_cpu_list_entry, &s);
3371 g_slist_free(list);
3372 #ifdef CONFIG_KVM
3373 /* The 'host' CPU type is dynamically registered only if KVM is
3374 * enabled, so we have to special-case it here:
3375 */
3376 (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
3377 #endif
3378 }
3379
3380 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
3381 {
3382 ObjectClass *oc = data;
3383 CpuDefinitionInfoList **cpu_list = user_data;
3384 CpuDefinitionInfoList *entry;
3385 CpuDefinitionInfo *info;
3386 const char *typename;
3387
3388 typename = object_class_get_name(oc);
3389 info = g_malloc0(sizeof(*info));
3390 info->name = g_strndup(typename,
3391 strlen(typename) - strlen("-" TYPE_ARM_CPU));
3392
3393 entry = g_malloc0(sizeof(*entry));
3394 entry->value = info;
3395 entry->next = *cpu_list;
3396 *cpu_list = entry;
3397 }
3398
3399 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
3400 {
3401 CpuDefinitionInfoList *cpu_list = NULL;
3402 GSList *list;
3403
3404 list = object_class_get_list(TYPE_ARM_CPU, false);
3405 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
3406 g_slist_free(list);
3407
3408 return cpu_list;
3409 }
3410
3411 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
3412 void *opaque, int state, int secstate,
3413 int crm, int opc1, int opc2)
3414 {
3415 /* Private utility function for define_one_arm_cp_reg_with_opaque():
3416 * add a single reginfo struct to the hash table.
3417 */
3418 uint32_t *key = g_new(uint32_t, 1);
3419 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
3420 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
3421 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
3422
3423 /* Reset the secure state to the specific incoming state. This is
3424 * necessary as the register may have been defined with both states.
3425 */
3426 r2->secure = secstate;
3427
3428 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
3429 /* Register is banked (using both entries in array).
3430 * Overwriting fieldoffset as the array is only used to define
3431 * banked registers but later only fieldoffset is used.
3432 */
3433 r2->fieldoffset = r->bank_fieldoffsets[ns];
3434 }
3435
3436 if (state == ARM_CP_STATE_AA32) {
3437 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
3438 /* If the register is banked then we don't need to migrate or
3439 * reset the 32-bit instance in certain cases:
3440 *
3441 * 1) If the register has both 32-bit and 64-bit instances then we
3442 * can count on the 64-bit instance taking care of the
3443 * non-secure bank.
3444 * 2) If ARMv8 is enabled then we can count on a 64-bit version
3445 * taking care of the secure bank. This requires that separate
3446 * 32 and 64-bit definitions are provided.
3447 */
3448 if ((r->state == ARM_CP_STATE_BOTH && ns) ||
3449 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
3450 r2->type |= ARM_CP_NO_MIGRATE;
3451 r2->resetfn = arm_cp_reset_ignore;
3452 }
3453 } else if ((secstate != r->secure) && !ns) {
3454 /* The register is not banked so we only want to allow migration of
3455 * the non-secure instance.
3456 */
3457 r2->type |= ARM_CP_NO_MIGRATE;
3458 r2->resetfn = arm_cp_reset_ignore;
3459 }
3460
3461 if (r->state == ARM_CP_STATE_BOTH) {
3462 /* We assume it is a cp15 register if the .cp field is left unset.
3463 */
3464 if (r2->cp == 0) {
3465 r2->cp = 15;
3466 }
3467
3468 #ifdef HOST_WORDS_BIGENDIAN
3469 if (r2->fieldoffset) {
3470 r2->fieldoffset += sizeof(uint32_t);
3471 }
3472 #endif
3473 }
3474 }
3475 if (state == ARM_CP_STATE_AA64) {
3476 /* To allow abbreviation of ARMCPRegInfo
3477 * definitions, we treat cp == 0 as equivalent to
3478 * the value for "standard guest-visible sysreg".
3479 * STATE_BOTH definitions are also always "standard
3480 * sysreg" in their AArch64 view (the .cp value may
3481 * be non-zero for the benefit of the AArch32 view).
3482 */
3483 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
3484 r2->cp = CP_REG_ARM64_SYSREG_CP;
3485 }
3486 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
3487 r2->opc0, opc1, opc2);
3488 } else {
3489 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
3490 }
3491 if (opaque) {
3492 r2->opaque = opaque;
3493 }
3494 /* reginfo passed to helpers is correct for the actual access,
3495 * and is never ARM_CP_STATE_BOTH:
3496 */
3497 r2->state = state;
3498 /* Make sure reginfo passed to helpers for wildcarded regs
3499 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
3500 */
3501 r2->crm = crm;
3502 r2->opc1 = opc1;
3503 r2->opc2 = opc2;
3504 /* By convention, for wildcarded registers only the first
3505 * entry is used for migration; the others are marked as
3506 * NO_MIGRATE so we don't try to transfer the register
3507 * multiple times. Special registers (ie NOP/WFI) are
3508 * never migratable.
3509 */
3510 if ((r->type & ARM_CP_SPECIAL) ||
3511 ((r->crm == CP_ANY) && crm != 0) ||
3512 ((r->opc1 == CP_ANY) && opc1 != 0) ||
3513 ((r->opc2 == CP_ANY) && opc2 != 0)) {
3514 r2->type |= ARM_CP_NO_MIGRATE;
3515 }
3516
3517 /* Overriding of an existing definition must be explicitly
3518 * requested.
3519 */
3520 if (!(r->type & ARM_CP_OVERRIDE)) {
3521 ARMCPRegInfo *oldreg;
3522 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
3523 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
3524 fprintf(stderr, "Register redefined: cp=%d %d bit "
3525 "crn=%d crm=%d opc1=%d opc2=%d, "
3526 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
3527 r2->crn, r2->crm, r2->opc1, r2->opc2,
3528 oldreg->name, r2->name);
3529 g_assert_not_reached();
3530 }
3531 }
3532 g_hash_table_insert(cpu->cp_regs, key, r2);
3533 }
3534
3535
3536 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
3537 const ARMCPRegInfo *r, void *opaque)
3538 {
3539 /* Define implementations of coprocessor registers.
3540 * We store these in a hashtable because typically
3541 * there are less than 150 registers in a space which
3542 * is 16*16*16*8*8 = 262144 in size.
3543 * Wildcarding is supported for the crm, opc1 and opc2 fields.
3544 * If a register is defined twice then the second definition is
3545 * used, so this can be used to define some generic registers and
3546 * then override them with implementation specific variations.
3547 * At least one of the original and the second definition should
3548 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
3549 * against accidental use.
3550 *
3551 * The state field defines whether the register is to be
3552 * visible in the AArch32 or AArch64 execution state. If the
3553 * state is set to ARM_CP_STATE_BOTH then we synthesise a
3554 * reginfo structure for the AArch32 view, which sees the lower
3555 * 32 bits of the 64 bit register.
3556 *
3557 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
3558 * be wildcarded. AArch64 registers are always considered to be 64
3559 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
3560 * the register, if any.
3561 */
3562 int crm, opc1, opc2, state;
3563 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
3564 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
3565 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
3566 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
3567 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
3568 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
3569 /* 64 bit registers have only CRm and Opc1 fields */
3570 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
3571 /* op0 only exists in the AArch64 encodings */
3572 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
3573 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
3574 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
3575 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
3576 * encodes a minimum access level for the register. We roll this
3577 * runtime check into our general permission check code, so check
3578 * here that the reginfo's specified permissions are strict enough
3579 * to encompass the generic architectural permission check.
3580 */
3581 if (r->state != ARM_CP_STATE_AA32) {
3582 int mask = 0;
3583 switch (r->opc1) {
3584 case 0: case 1: case 2:
3585 /* min_EL EL1 */
3586 mask = PL1_RW;
3587 break;
3588 case 3:
3589 /* min_EL EL0 */
3590 mask = PL0_RW;
3591 break;
3592 case 4:
3593 /* min_EL EL2 */
3594 mask = PL2_RW;
3595 break;
3596 case 5:
3597 /* unallocated encoding, so not possible */
3598 assert(false);
3599 break;
3600 case 6:
3601 /* min_EL EL3 */
3602 mask = PL3_RW;
3603 break;
3604 case 7:
3605 /* min_EL EL1, secure mode only (we don't check the latter) */
3606 mask = PL1_RW;
3607 break;
3608 default:
3609 /* broken reginfo with out-of-range opc1 */
3610 assert(false);
3611 break;
3612 }
3613 /* assert our permissions are not too lax (stricter is fine) */
3614 assert((r->access & ~mask) == 0);
3615 }
3616
3617 /* Check that the register definition has enough info to handle
3618 * reads and writes if they are permitted.
3619 */
3620 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
3621 if (r->access & PL3_R) {
3622 assert((r->fieldoffset ||
3623 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
3624 r->readfn);
3625 }
3626 if (r->access & PL3_W) {
3627 assert((r->fieldoffset ||
3628 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
3629 r->writefn);
3630 }
3631 }
3632 /* Bad type field probably means missing sentinel at end of reg list */
3633 assert(cptype_valid(r->type));
3634 for (crm = crmmin; crm <= crmmax; crm++) {
3635 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
3636 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
3637 for (state = ARM_CP_STATE_AA32;
3638 state <= ARM_CP_STATE_AA64; state++) {
3639 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
3640 continue;
3641 }
3642 if (state == ARM_CP_STATE_AA32) {
3643 /* Under AArch32 CP registers can be common
3644 * (same for secure and non-secure world) or banked.
3645 */
3646 switch (r->secure) {
3647 case ARM_CP_SECSTATE_S:
3648 case ARM_CP_SECSTATE_NS:
3649 add_cpreg_to_hashtable(cpu, r, opaque, state,
3650 r->secure, crm, opc1, opc2);
3651 break;
3652 default:
3653 add_cpreg_to_hashtable(cpu, r, opaque, state,
3654 ARM_CP_SECSTATE_S,
3655 crm, opc1, opc2);
3656 add_cpreg_to_hashtable(cpu, r, opaque, state,
3657 ARM_CP_SECSTATE_NS,
3658 crm, opc1, opc2);
3659 break;
3660 }
3661 } else {
3662 /* AArch64 registers get mapped to non-secure instance
3663 * of AArch32 */
3664 add_cpreg_to_hashtable(cpu, r, opaque, state,
3665 ARM_CP_SECSTATE_NS,
3666 crm, opc1, opc2);
3667 }
3668 }
3669 }
3670 }
3671 }
3672 }
3673
3674 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
3675 const ARMCPRegInfo *regs, void *opaque)
3676 {
3677 /* Define a whole list of registers */
3678 const ARMCPRegInfo *r;
3679 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
3680 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
3681 }
3682 }
3683
3684 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
3685 {
3686 return g_hash_table_lookup(cpregs, &encoded_cp);
3687 }
3688
3689 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
3690 uint64_t value)
3691 {
3692 /* Helper coprocessor write function for write-ignore registers */
3693 }
3694
3695 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
3696 {
3697 /* Helper coprocessor write function for read-as-zero registers */
3698 return 0;
3699 }
3700
3701 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
3702 {
3703 /* Helper coprocessor reset function for do-nothing-on-reset registers */
3704 }
3705
3706 static int bad_mode_switch(CPUARMState *env, int mode)
3707 {
3708 /* Return true if it is not valid for us to switch to
3709 * this CPU mode (ie all the UNPREDICTABLE cases in
3710 * the ARM ARM CPSRWriteByInstr pseudocode).
3711 */
3712 switch (mode) {
3713 case ARM_CPU_MODE_USR:
3714 case ARM_CPU_MODE_SYS:
3715 case ARM_CPU_MODE_SVC:
3716 case ARM_CPU_MODE_ABT:
3717 case ARM_CPU_MODE_UND:
3718 case ARM_CPU_MODE_IRQ:
3719 case ARM_CPU_MODE_FIQ:
3720 return 0;
3721 case ARM_CPU_MODE_MON:
3722 return !arm_is_secure(env);
3723 default:
3724 return 1;
3725 }
3726 }
3727
3728 uint32_t cpsr_read(CPUARMState *env)
3729 {
3730 int ZF;
3731 ZF = (env->ZF == 0);
3732 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
3733 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
3734 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
3735 | ((env->condexec_bits & 0xfc) << 8)
3736 | (env->GE << 16) | (env->daif & CPSR_AIF);
3737 }
3738
3739 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
3740 {
3741 uint32_t changed_daif;
3742
3743 if (mask & CPSR_NZCV) {
3744 env->ZF = (~val) & CPSR_Z;
3745 env->NF = val;
3746 env->CF = (val >> 29) & 1;
3747 env->VF = (val << 3) & 0x80000000;
3748 }
3749 if (mask & CPSR_Q)
3750 env->QF = ((val & CPSR_Q) != 0);
3751 if (mask & CPSR_T)
3752 env->thumb = ((val & CPSR_T) != 0);
3753 if (mask & CPSR_IT_0_1) {
3754 env->condexec_bits &= ~3;
3755 env->condexec_bits |= (val >> 25) & 3;
3756 }
3757 if (mask & CPSR_IT_2_7) {
3758 env->condexec_bits &= 3;
3759 env->condexec_bits |= (val >> 8) & 0xfc;
3760 }
3761 if (mask & CPSR_GE) {
3762 env->GE = (val >> 16) & 0xf;
3763 }
3764
3765 /* In a V7 implementation that includes the security extensions but does
3766 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
3767 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
3768 * bits respectively.
3769 *
3770 * In a V8 implementation, it is permitted for privileged software to
3771 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
3772 */
3773 if (!arm_feature(env, ARM_FEATURE_V8) &&
3774 arm_feature(env, ARM_FEATURE_EL3) &&
3775 !arm_feature(env, ARM_FEATURE_EL2) &&
3776 !arm_is_secure(env)) {
3777
3778 changed_daif = (env->daif ^ val) & mask;
3779
3780 if (changed_daif & CPSR_A) {
3781 /* Check to see if we are allowed to change the masking of async
3782 * abort exceptions from a non-secure state.
3783 */
3784 if (!(env->cp15.scr_el3 & SCR_AW)) {
3785 qemu_log_mask(LOG_GUEST_ERROR,
3786 "Ignoring attempt to switch CPSR_A flag from "
3787 "non-secure world with SCR.AW bit clear\n");
3788 mask &= ~CPSR_A;
3789 }
3790 }
3791
3792 if (changed_daif & CPSR_F) {
3793 /* Check to see if we are allowed to change the masking of FIQ
3794 * exceptions from a non-secure state.
3795 */
3796 if (!(env->cp15.scr_el3 & SCR_FW)) {
3797 qemu_log_mask(LOG_GUEST_ERROR,
3798 "Ignoring attempt to switch CPSR_F flag from "
3799 "non-secure world with SCR.FW bit clear\n");
3800 mask &= ~CPSR_F;
3801 }
3802
3803 /* Check whether non-maskable FIQ (NMFI) support is enabled.
3804 * If this bit is set software is not allowed to mask
3805 * FIQs, but is allowed to set CPSR_F to 0.
3806 */
3807 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
3808 (val & CPSR_F)) {
3809 qemu_log_mask(LOG_GUEST_ERROR,
3810 "Ignoring attempt to enable CPSR_F flag "
3811 "(non-maskable FIQ [NMFI] support enabled)\n");
3812 mask &= ~CPSR_F;
3813 }
3814 }
3815 }
3816
3817 env->daif &= ~(CPSR_AIF & mask);
3818 env->daif |= val & CPSR_AIF & mask;
3819
3820 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
3821 if (bad_mode_switch(env, val & CPSR_M)) {
3822 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
3823 * We choose to ignore the attempt and leave the CPSR M field
3824 * untouched.
3825 */
3826 mask &= ~CPSR_M;
3827 } else {
3828 switch_mode(env, val & CPSR_M);
3829 }
3830 }
3831 mask &= ~CACHED_CPSR_BITS;
3832 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
3833 }
3834
3835 /* Sign/zero extend */
3836 uint32_t HELPER(sxtb16)(uint32_t x)
3837 {
3838 uint32_t res;
3839 res = (uint16_t)(int8_t)x;
3840 res |= (uint32_t)(int8_t)(x >> 16) << 16;
3841 return res;
3842 }
3843
3844 uint32_t HELPER(uxtb16)(uint32_t x)
3845 {
3846 uint32_t res;
3847 res = (uint16_t)(uint8_t)x;
3848 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
3849 return res;
3850 }
3851
3852 uint32_t HELPER(clz)(uint32_t x)
3853 {
3854 return clz32(x);
3855 }
3856
3857 int32_t HELPER(sdiv)(int32_t num, int32_t den)
3858 {
3859 if (den == 0)
3860 return 0;
3861 if (num == INT_MIN && den == -1)
3862 return INT_MIN;
3863 return num / den;
3864 }
3865
3866 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
3867 {
3868 if (den == 0)
3869 return 0;
3870 return num / den;
3871 }
3872
3873 uint32_t HELPER(rbit)(uint32_t x)
3874 {
3875 x = ((x & 0xff000000) >> 24)
3876 | ((x & 0x00ff0000) >> 8)
3877 | ((x & 0x0000ff00) << 8)
3878 | ((x & 0x000000ff) << 24);
3879 x = ((x & 0xf0f0f0f0) >> 4)
3880 | ((x & 0x0f0f0f0f) << 4);
3881 x = ((x & 0x88888888) >> 3)
3882 | ((x & 0x44444444) >> 1)
3883 | ((x & 0x22222222) << 1)
3884 | ((x & 0x11111111) << 3);
3885 return x;
3886 }
3887
3888 #if defined(CONFIG_USER_ONLY)
3889
3890 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
3891 int mmu_idx)
3892 {
3893 ARMCPU *cpu = ARM_CPU(cs);
3894 CPUARMState *env = &cpu->env;
3895
3896 env->exception.vaddress = address;
3897 if (rw == 2) {
3898 cs->exception_index = EXCP_PREFETCH_ABORT;
3899 } else {
3900 cs->exception_index = EXCP_DATA_ABORT;
3901 }
3902 return 1;
3903 }
3904
3905 /* These should probably raise undefined insn exceptions. */
3906 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3907 {
3908 ARMCPU *cpu = arm_env_get_cpu(env);
3909
3910 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
3911 }
3912
3913 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3914 {
3915 ARMCPU *cpu = arm_env_get_cpu(env);
3916
3917 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
3918 return 0;
3919 }
3920
3921 void switch_mode(CPUARMState *env, int mode)
3922 {
3923 ARMCPU *cpu = arm_env_get_cpu(env);
3924
3925 if (mode != ARM_CPU_MODE_USR) {
3926 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
3927 }
3928 }
3929
3930 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3931 {
3932 ARMCPU *cpu = arm_env_get_cpu(env);
3933
3934 cpu_abort(CPU(cpu), "banked r13 write\n");
3935 }
3936
3937 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3938 {
3939 ARMCPU *cpu = arm_env_get_cpu(env);
3940
3941 cpu_abort(CPU(cpu), "banked r13 read\n");
3942 return 0;
3943 }
3944
3945 unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
3946 {
3947 return 1;
3948 }
3949
3950 #else
3951
3952 /* Map CPU modes onto saved register banks. */
3953 int bank_number(int mode)
3954 {
3955 switch (mode) {
3956 case ARM_CPU_MODE_USR:
3957 case ARM_CPU_MODE_SYS:
3958 return 0;
3959 case ARM_CPU_MODE_SVC:
3960 return 1;
3961 case ARM_CPU_MODE_ABT:
3962 return 2;
3963 case ARM_CPU_MODE_UND:
3964 return 3;
3965 case ARM_CPU_MODE_IRQ:
3966 return 4;
3967 case ARM_CPU_MODE_FIQ:
3968 return 5;
3969 case ARM_CPU_MODE_HYP:
3970 return 6;
3971 case ARM_CPU_MODE_MON:
3972 return 7;
3973 }
3974 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
3975 }
3976
3977 void switch_mode(CPUARMState *env, int mode)
3978 {
3979 int old_mode;
3980 int i;
3981
3982 old_mode = env->uncached_cpsr & CPSR_M;
3983 if (mode == old_mode)
3984 return;
3985
3986 if (old_mode == ARM_CPU_MODE_FIQ) {
3987 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
3988 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
3989 } else if (mode == ARM_CPU_MODE_FIQ) {
3990 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
3991 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
3992 }
3993
3994 i = bank_number(old_mode);
3995 env->banked_r13[i] = env->regs[13];
3996 env->banked_r14[i] = env->regs[14];
3997 env->banked_spsr[i] = env->spsr;
3998
3999 i = bank_number(mode);
4000 env->regs[13] = env->banked_r13[i];
4001 env->regs[14] = env->banked_r14[i];
4002 env->spsr = env->banked_spsr[i];
4003 }
4004
4005 /* Physical Interrupt Target EL Lookup Table
4006 *
4007 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
4008 *
4009 * The below multi-dimensional table is used for looking up the target
4010 * exception level given numerous condition criteria. Specifically, the
4011 * target EL is based on SCR and HCR routing controls as well as the
4012 * currently executing EL and secure state.
4013 *
4014 * Dimensions:
4015 * target_el_table[2][2][2][2][2][4]
4016 * | | | | | +--- Current EL
4017 * | | | | +------ Non-secure(0)/Secure(1)
4018 * | | | +--------- HCR mask override
4019 * | | +------------ SCR exec state control
4020 * | +--------------- SCR mask override
4021 * +------------------ 32-bit(0)/64-bit(1) EL3
4022 *
4023 * The table values are as such:
4024 * 0-3 = EL0-EL3
4025 * -1 = Cannot occur
4026 *
4027 * The ARM ARM target EL table includes entries indicating that an "exception
4028 * is not taken". The two cases where this is applicable are:
4029 * 1) An exception is taken from EL3 but the SCR does not have the exception
4030 * routed to EL3.
4031 * 2) An exception is taken from EL2 but the HCR does not have the exception
4032 * routed to EL2.
4033 * In these two cases, the below table contain a target of EL1. This value is
4034 * returned as it is expected that the consumer of the table data will check
4035 * for "target EL >= current EL" to ensure the exception is not taken.
4036 *
4037 * SCR HCR
4038 * 64 EA AMO From
4039 * BIT IRQ IMO Non-secure Secure
4040 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
4041 */
4042 const int8_t target_el_table[2][2][2][2][2][4] = {
4043 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
4044 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
4045 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
4046 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
4047 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
4048 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
4049 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
4050 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
4051 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
4052 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
4053 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
4054 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
4055 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
4056 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
4057 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
4058 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
4059 };
4060
4061 /*
4062 * Determine the target EL for physical exceptions
4063 */
4064 static inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
4065 uint32_t cur_el, bool secure)
4066 {
4067 CPUARMState *env = cs->env_ptr;
4068 int rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
4069 int scr;
4070 int hcr;
4071 int target_el;
4072 int is64 = arm_el_is_aa64(env, 3);
4073
4074 switch (excp_idx) {
4075 case EXCP_IRQ:
4076 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
4077 hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
4078 break;
4079 case EXCP_FIQ:
4080 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
4081 hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
4082 break;
4083 default:
4084 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
4085 hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
4086 break;
4087 };
4088
4089 /* If HCR.TGE is set then HCR is treated as being 1 */
4090 hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
4091
4092 /* Perform a table-lookup for the target EL given the current state */
4093 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
4094
4095 assert(target_el > 0);
4096
4097 return target_el;
4098 }
4099
4100 /*
4101 * Determine the target EL for a given exception type.
4102 */
4103 unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
4104 {
4105 ARMCPU *cpu = ARM_CPU(cs);
4106 CPUARMState *env = &cpu->env;
4107 unsigned int cur_el = arm_current_el(env);
4108 unsigned int target_el;
4109 bool secure = arm_is_secure(env);
4110
4111 switch (excp_idx) {
4112 case EXCP_HVC:
4113 case EXCP_HYP_TRAP:
4114 target_el = 2;
4115 break;
4116 case EXCP_SMC:
4117 target_el = 3;
4118 break;
4119 case EXCP_FIQ:
4120 case EXCP_IRQ:
4121 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
4122 break;
4123 case EXCP_VIRQ:
4124 case EXCP_VFIQ:
4125 target_el = 1;
4126 break;
4127 default:
4128 target_el = MAX(cur_el, 1);
4129 break;
4130 }
4131 return target_el;
4132 }
4133
4134 static void v7m_push(CPUARMState *env, uint32_t val)
4135 {
4136 CPUState *cs = CPU(arm_env_get_cpu(env));
4137
4138 env->regs[13] -= 4;
4139 stl_phys(cs->as, env->regs[13], val);
4140 }
4141
4142 static uint32_t v7m_pop(CPUARMState *env)
4143 {
4144 CPUState *cs = CPU(arm_env_get_cpu(env));
4145 uint32_t val;
4146
4147 val = ldl_phys(cs->as, env->regs[13]);
4148 env->regs[13] += 4;
4149 return val;
4150 }
4151
4152 /* Switch to V7M main or process stack pointer. */
4153 static void switch_v7m_sp(CPUARMState *env, int process)
4154 {
4155 uint32_t tmp;
4156 if (env->v7m.current_sp != process) {
4157 tmp = env->v7m.other_sp;
4158 env->v7m.other_sp = env->regs[13];
4159 env->regs[13] = tmp;
4160 env->v7m.current_sp = process;
4161 }
4162 }
4163
4164 static void do_v7m_exception_exit(CPUARMState *env)
4165 {
4166 uint32_t type;
4167 uint32_t xpsr;
4168
4169 type = env->regs[15];
4170 if (env->v7m.exception != 0)
4171 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
4172
4173 /* Switch to the target stack. */
4174 switch_v7m_sp(env, (type & 4) != 0);
4175 /* Pop registers. */
4176 env->regs[0] = v7m_pop(env);
4177 env->regs[1] = v7m_pop(env);
4178 env->regs[2] = v7m_pop(env);
4179 env->regs[3] = v7m_pop(env);
4180 env->regs[12] = v7m_pop(env);
4181 env->regs[14] = v7m_pop(env);
4182 env->regs[15] = v7m_pop(env);
4183 xpsr = v7m_pop(env);
4184 xpsr_write(env, xpsr, 0xfffffdff);
4185 /* Undo stack alignment. */
4186 if (xpsr & 0x200)
4187 env->regs[13] |= 4;
4188 /* ??? The exception return type specifies Thread/Handler mode. However
4189 this is also implied by the xPSR value. Not sure what to do
4190 if there is a mismatch. */
4191 /* ??? Likewise for mismatches between the CONTROL register and the stack
4192 pointer. */
4193 }
4194
4195 void arm_v7m_cpu_do_interrupt(CPUState *cs)
4196 {
4197 ARMCPU *cpu = ARM_CPU(cs);
4198 CPUARMState *env = &cpu->env;
4199 uint32_t xpsr = xpsr_read(env);
4200 uint32_t lr;
4201 uint32_t addr;
4202
4203 arm_log_exception(cs->exception_index);
4204
4205 lr = 0xfffffff1;
4206 if (env->v7m.current_sp)
4207 lr |= 4;
4208 if (env->v7m.exception == 0)
4209 lr |= 8;
4210
4211 /* For exceptions we just mark as pending on the NVIC, and let that
4212 handle it. */
4213 /* TODO: Need to escalate if the current priority is higher than the
4214 one we're raising. */
4215 switch (cs->exception_index) {
4216 case EXCP_UDEF:
4217 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
4218 return;
4219 case EXCP_SWI:
4220 /* The PC already points to the next instruction. */
4221 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
4222 return;
4223 case EXCP_PREFETCH_ABORT:
4224 case EXCP_DATA_ABORT:
4225 /* TODO: if we implemented the MPU registers, this is where we
4226 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
4227 */
4228 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
4229 return;
4230 case EXCP_BKPT:
4231 if (semihosting_enabled) {
4232 int nr;
4233 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
4234 if (nr == 0xab) {
4235 env->regs[15] += 2;
4236 env->regs[0] = do_arm_semihosting(env);
4237 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4238 return;
4239 }
4240 }
4241 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
4242 return;
4243 case EXCP_IRQ:
4244 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
4245 break;
4246 case EXCP_EXCEPTION_EXIT:
4247 do_v7m_exception_exit(env);
4248 return;
4249 default:
4250 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
4251 return; /* Never happens. Keep compiler happy. */
4252 }
4253
4254 /* Align stack pointer. */
4255 /* ??? Should only do this if Configuration Control Register
4256 STACKALIGN bit is set. */
4257 if (env->regs[13] & 4) {
4258 env->regs[13] -= 4;
4259 xpsr |= 0x200;
4260 }
4261 /* Switch to the handler mode. */
4262 v7m_push(env, xpsr);
4263 v7m_push(env, env->regs[15]);
4264 v7m_push(env, env->regs[14]);
4265 v7m_push(env, env->regs[12]);
4266 v7m_push(env, env->regs[3]);
4267 v7m_push(env, env->regs[2]);
4268 v7m_push(env, env->regs[1]);
4269 v7m_push(env, env->regs[0]);
4270 switch_v7m_sp(env, 0);
4271 /* Clear IT bits */
4272 env->condexec_bits = 0;
4273 env->regs[14] = lr;
4274 addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
4275 env->regs[15] = addr & 0xfffffffe;
4276 env->thumb = addr & 1;
4277 }
4278
4279 /* Handle a CPU exception. */
4280 void arm_cpu_do_interrupt(CPUState *cs)
4281 {
4282 ARMCPU *cpu = ARM_CPU(cs);
4283 CPUARMState *env = &cpu->env;
4284 uint32_t addr;
4285 uint32_t mask;
4286 int new_mode;
4287 uint32_t offset;
4288 uint32_t moe;
4289
4290 assert(!IS_M(env));
4291
4292 arm_log_exception(cs->exception_index);
4293
4294 if (arm_is_psci_call(cpu, cs->exception_index)) {
4295 arm_handle_psci_call(cpu);
4296 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
4297 return;
4298 }
4299
4300 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
4301 switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
4302 case EC_BREAKPOINT:
4303 case EC_BREAKPOINT_SAME_EL:
4304 moe = 1;
4305 break;
4306 case EC_WATCHPOINT:
4307 case EC_WATCHPOINT_SAME_EL:
4308 moe = 10;
4309 break;
4310 case EC_AA32_BKPT:
4311 moe = 3;
4312 break;
4313 case EC_VECTORCATCH:
4314 moe = 5;
4315 break;
4316 default:
4317 moe = 0;
4318 break;
4319 }
4320
4321 if (moe) {
4322 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
4323 }
4324
4325 /* TODO: Vectored interrupt controller. */
4326 switch (cs->exception_index) {
4327 case EXCP_UDEF:
4328 new_mode = ARM_CPU_MODE_UND;
4329 addr = 0x04;
4330 mask = CPSR_I;
4331 if (env->thumb)
4332 offset = 2;
4333 else
4334 offset = 4;
4335 break;
4336 case EXCP_SWI:
4337 if (semihosting_enabled) {
4338 /* Check for semihosting interrupt. */
4339 if (env->thumb) {
4340 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
4341 & 0xff;
4342 } else {
4343 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
4344 & 0xffffff;
4345 }
4346 /* Only intercept calls from privileged modes, to provide some
4347 semblance of security. */
4348 if (((mask == 0x123456 && !env->thumb)
4349 || (mask == 0xab && env->thumb))
4350 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
4351 env->regs[0] = do_arm_semihosting(env);
4352 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4353 return;
4354 }
4355 }
4356 new_mode = ARM_CPU_MODE_SVC;
4357 addr = 0x08;
4358 mask = CPSR_I;
4359 /* The PC already points to the next instruction. */
4360 offset = 0;
4361 break;
4362 case EXCP_BKPT:
4363 /* See if this is a semihosting syscall. */
4364 if (env->thumb && semihosting_enabled) {
4365 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
4366 if (mask == 0xab
4367 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
4368 env->regs[15] += 2;
4369 env->regs[0] = do_arm_semihosting(env);
4370 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4371 return;
4372 }
4373 }
4374 env->exception.fsr = 2;
4375 /* Fall through to prefetch abort. */
4376 case EXCP_PREFETCH_ABORT:
4377 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
4378 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
4379 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
4380 env->exception.fsr, (uint32_t)env->exception.vaddress);
4381 new_mode = ARM_CPU_MODE_ABT;
4382 addr = 0x0c;
4383 mask = CPSR_A | CPSR_I;
4384 offset = 4;
4385 break;
4386 case EXCP_DATA_ABORT:
4387 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
4388 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
4389 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
4390 env->exception.fsr,
4391 (uint32_t)env->exception.vaddress);
4392 new_mode = ARM_CPU_MODE_ABT;
4393 addr = 0x10;
4394 mask = CPSR_A | CPSR_I;
4395 offset = 8;
4396 break;
4397 case EXCP_IRQ:
4398 new_mode = ARM_CPU_MODE_IRQ;
4399 addr = 0x18;
4400 /* Disable IRQ and imprecise data aborts. */
4401 mask = CPSR_A | CPSR_I;
4402 offset = 4;
4403 if (env->cp15.scr_el3 & SCR_IRQ) {
4404 /* IRQ routed to monitor mode */
4405 new_mode = ARM_CPU_MODE_MON;
4406 mask |= CPSR_F;
4407 }
4408 break;
4409 case EXCP_FIQ:
4410 new_mode = ARM_CPU_MODE_FIQ;
4411 addr = 0x1c;
4412 /* Disable FIQ, IRQ and imprecise data aborts. */
4413 mask = CPSR_A | CPSR_I | CPSR_F;
4414 if (env->cp15.scr_el3 & SCR_FIQ) {
4415 /* FIQ routed to monitor mode */
4416 new_mode = ARM_CPU_MODE_MON;
4417 }
4418 offset = 4;
4419 break;
4420 case EXCP_SMC:
4421 new_mode = ARM_CPU_MODE_MON;
4422 addr = 0x08;
4423 mask = CPSR_A | CPSR_I | CPSR_F;
4424 offset = 0;
4425 break;
4426 default:
4427 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
4428 return; /* Never happens. Keep compiler happy. */
4429 }
4430
4431 if (new_mode == ARM_CPU_MODE_MON) {
4432 addr += env->cp15.mvbar;
4433 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
4434 /* High vectors. When enabled, base address cannot be remapped. */
4435 addr += 0xffff0000;
4436 } else {
4437 /* ARM v7 architectures provide a vector base address register to remap
4438 * the interrupt vector table.
4439 * This register is only followed in non-monitor mode, and is banked.
4440 * Note: only bits 31:5 are valid.
4441 */
4442 addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
4443 }
4444
4445 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
4446 env->cp15.scr_el3 &= ~SCR_NS;
4447 }
4448
4449 switch_mode (env, new_mode);
4450 /* For exceptions taken to AArch32 we must clear the SS bit in both
4451 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
4452 */
4453 env->uncached_cpsr &= ~PSTATE_SS;
4454 env->spsr = cpsr_read(env);
4455 /* Clear IT bits. */
4456 env->condexec_bits = 0;
4457 /* Switch to the new mode, and to the correct instruction set. */
4458 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
4459 env->daif |= mask;
4460 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
4461 * and we should just guard the thumb mode on V4 */
4462 if (arm_feature(env, ARM_FEATURE_V4T)) {
4463 env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
4464 }
4465 env->regs[14] = env->regs[15] + offset;
4466 env->regs[15] = addr;
4467 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
4468 }
4469
4470 /* Check section/page access permissions.
4471 Returns the page protection flags, or zero if the access is not
4472 permitted. */
4473 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
4474 int access_type, int is_user)
4475 {
4476 int prot_ro;
4477
4478 if (domain_prot == 3) {
4479 return PAGE_READ | PAGE_WRITE;
4480 }
4481
4482 if (access_type == 1)
4483 prot_ro = 0;
4484 else
4485 prot_ro = PAGE_READ;
4486
4487 switch (ap) {
4488 case 0:
4489 if (arm_feature(env, ARM_FEATURE_V7)) {
4490 return 0;
4491 }
4492 if (access_type == 1)
4493 return 0;
4494 switch (A32_BANKED_CURRENT_REG_GET(env, sctlr) & (SCTLR_S | SCTLR_R)) {
4495 case SCTLR_S:
4496 return is_user ? 0 : PAGE_READ;
4497 case SCTLR_R:
4498 return PAGE_READ;
4499 default:
4500 return 0;
4501 }
4502 case 1:
4503 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
4504 case 2:
4505 if (is_user)
4506 return prot_ro;
4507 else
4508 return PAGE_READ | PAGE_WRITE;
4509 case 3:
4510 return PAGE_READ | PAGE_WRITE;
4511 case 4: /* Reserved. */
4512 return 0;
4513 case 5:
4514 return is_user ? 0 : prot_ro;
4515 case 6:
4516 return prot_ro;
4517 case 7:
4518 if (!arm_feature (env, ARM_FEATURE_V6K))
4519 return 0;
4520 return prot_ro;
4521 default:
4522 abort();
4523 }
4524 }
4525
4526 static bool get_level1_table_address(CPUARMState *env, uint32_t *table,
4527 uint32_t address)
4528 {
4529 /* Get the TCR bank based on our security state */
4530 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
4531
4532 /* We only get here if EL1 is running in AArch32. If EL3 is running in
4533 * AArch32 there is a secure and non-secure instance of the translation
4534 * table registers.
4535 */
4536 if (address & tcr->mask) {
4537 if (tcr->raw_tcr & TTBCR_PD1) {
4538 /* Translation table walk disabled for TTBR1 */
4539 return false;
4540 }
4541 *table = A32_BANKED_CURRENT_REG_GET(env, ttbr1) & 0xffffc000;
4542 } else {
4543 if (tcr->raw_tcr & TTBCR_PD0) {
4544 /* Translation table walk disabled for TTBR0 */
4545 return false;
4546 }
4547 *table = A32_BANKED_CURRENT_REG_GET(env, ttbr0) & tcr->base_mask;
4548 }
4549 *table |= (address >> 18) & 0x3ffc;
4550 return true;
4551 }
4552
4553 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
4554 int is_user, hwaddr *phys_ptr,
4555 int *prot, target_ulong *page_size)
4556 {
4557 CPUState *cs = CPU(arm_env_get_cpu(env));
4558 int code;
4559 uint32_t table;
4560 uint32_t desc;
4561 int type;
4562 int ap;
4563 int domain = 0;
4564 int domain_prot;
4565 hwaddr phys_addr;
4566
4567 /* Pagetable walk. */
4568 /* Lookup l1 descriptor. */
4569 if (!get_level1_table_address(env, &table, address)) {
4570 /* Section translation fault if page walk is disabled by PD0 or PD1 */
4571 code = 5;
4572 goto do_fault;
4573 }
4574 desc = ldl_phys(cs->as, table);
4575 type = (desc & 3);
4576 domain = (desc >> 5) & 0x0f;
4577 domain_prot = (A32_BANKED_CURRENT_REG_GET(env, dacr) >> (domain * 2)) & 3;
4578 if (type == 0) {
4579 /* Section translation fault. */
4580 code = 5;
4581 goto do_fault;
4582 }
4583 if (domain_prot == 0 || domain_prot == 2) {
4584 if (type == 2)
4585 code = 9; /* Section domain fault. */
4586 else
4587 code = 11; /* Page domain fault. */
4588 goto do_fault;
4589 }
4590 if (type == 2) {
4591 /* 1Mb section. */
4592 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
4593 ap = (desc >> 10) & 3;
4594 code = 13;
4595 *page_size = 1024 * 1024;
4596 } else {
4597 /* Lookup l2 entry. */
4598 if (type == 1) {
4599 /* Coarse pagetable. */
4600 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
4601 } else {
4602 /* Fine pagetable. */
4603 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
4604 }
4605 desc = ldl_phys(cs->as, table);
4606 switch (desc & 3) {
4607 case 0: /* Page translation fault. */
4608 code = 7;
4609 goto do_fault;
4610 case 1: /* 64k page. */
4611 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
4612 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
4613 *page_size = 0x10000;
4614 break;
4615 case 2: /* 4k page. */
4616 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
4617 ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
4618 *page_size = 0x1000;
4619 break;
4620 case 3: /* 1k page. */
4621 if (type == 1) {
4622 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4623 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
4624 } else {
4625 /* Page translation fault. */
4626 code = 7;
4627 goto do_fault;
4628 }
4629 } else {
4630 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
4631 }
4632 ap = (desc >> 4) & 3;
4633 *page_size = 0x400;
4634 break;
4635 default:
4636 /* Never happens, but compiler isn't smart enough to tell. */
4637 abort();
4638 }
4639 code = 15;
4640 }
4641 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
4642 if (!*prot) {
4643 /* Access permission fault. */
4644 goto do_fault;
4645 }
4646 *prot |= PAGE_EXEC;
4647 *phys_ptr = phys_addr;
4648 return 0;
4649 do_fault:
4650 return code | (domain << 4);
4651 }
4652
4653 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
4654 int is_user, hwaddr *phys_ptr,
4655 int *prot, target_ulong *page_size)
4656 {
4657 CPUState *cs = CPU(arm_env_get_cpu(env));
4658 int code;
4659 uint32_t table;
4660 uint32_t desc;
4661 uint32_t xn;
4662 uint32_t pxn = 0;
4663 int type;
4664 int ap;
4665 int domain = 0;
4666 int domain_prot;
4667 hwaddr phys_addr;
4668
4669 /* Pagetable walk. */
4670 /* Lookup l1 descriptor. */
4671 if (!get_level1_table_address(env, &table, address)) {
4672 /* Section translation fault if page walk is disabled by PD0 or PD1 */
4673 code = 5;
4674 goto do_fault;
4675 }
4676 desc = ldl_phys(cs->as, table);
4677 type = (desc & 3);
4678 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
4679 /* Section translation fault, or attempt to use the encoding
4680 * which is Reserved on implementations without PXN.
4681 */
4682 code = 5;
4683 goto do_fault;
4684 }
4685 if ((type == 1) || !(desc & (1 << 18))) {
4686 /* Page or Section. */
4687 domain = (desc >> 5) & 0x0f;
4688 }
4689 domain_prot = (A32_BANKED_CURRENT_REG_GET(env, dacr) >> (domain * 2)) & 3;
4690 if (domain_prot == 0 || domain_prot == 2) {
4691 if (type != 1) {
4692 code = 9; /* Section domain fault. */
4693 } else {
4694 code = 11; /* Page domain fault. */
4695 }
4696 goto do_fault;
4697 }
4698 if (type != 1) {
4699 if (desc & (1 << 18)) {
4700 /* Supersection. */
4701 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
4702 *page_size = 0x1000000;
4703 } else {
4704 /* Section. */
4705 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
4706 *page_size = 0x100000;
4707 }
4708 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
4709 xn = desc & (1 << 4);
4710 pxn = desc & 1;
4711 code = 13;
4712 } else {
4713 if (arm_feature(env, ARM_FEATURE_PXN)) {
4714 pxn = (desc >> 2) & 1;
4715 }
4716 /* Lookup l2 entry. */
4717 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
4718 desc = ldl_phys(cs->as, table);
4719 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
4720 switch (desc & 3) {
4721 case 0: /* Page translation fault. */
4722 code = 7;
4723 goto do_fault;
4724 case 1: /* 64k page. */
4725 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
4726 xn = desc & (1 << 15);
4727 *page_size = 0x10000;
4728 break;
4729 case 2: case 3: /* 4k page. */
4730 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
4731 xn = desc & 1;
4732 *page_size = 0x1000;
4733 break;
4734 default:
4735 /* Never happens, but compiler isn't smart enough to tell. */
4736 abort();
4737 }
4738 code = 15;
4739 }
4740 if (domain_prot == 3) {
4741 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4742 } else {
4743 if (pxn && !is_user) {
4744 xn = 1;
4745 }
4746 if (xn && access_type == 2)
4747 goto do_fault;
4748
4749 /* The simplified model uses AP[0] as an access control bit. */
4750 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_AFE)
4751 && (ap & 1) == 0) {
4752 /* Access flag fault. */
4753 code = (code == 15) ? 6 : 3;
4754 goto do_fault;
4755 }
4756 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
4757 if (!*prot) {
4758 /* Access permission fault. */
4759 goto do_fault;
4760 }
4761 if (!xn) {
4762 *prot |= PAGE_EXEC;
4763 }
4764 }
4765 *phys_ptr = phys_addr;
4766 return 0;
4767 do_fault:
4768 return code | (domain << 4);
4769 }
4770
4771 /* Fault type for long-descriptor MMU fault reporting; this corresponds
4772 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
4773 */
4774 typedef enum {
4775 translation_fault = 1,
4776 access_fault = 2,
4777 permission_fault = 3,
4778 } MMUFaultType;
4779
4780 static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
4781 int access_type, int is_user,
4782 hwaddr *phys_ptr, int *prot,
4783 target_ulong *page_size_ptr)
4784 {
4785 CPUState *cs = CPU(arm_env_get_cpu(env));
4786 /* Read an LPAE long-descriptor translation table. */
4787 MMUFaultType fault_type = translation_fault;
4788 uint32_t level = 1;
4789 uint32_t epd;
4790 int32_t tsz;
4791 uint32_t tg;
4792 uint64_t ttbr;
4793 int ttbr_select;
4794 hwaddr descaddr, descmask;
4795 uint32_t tableattrs;
4796 target_ulong page_size;
4797 uint32_t attrs;
4798 int32_t granule_sz = 9;
4799 int32_t va_size = 32;
4800 int32_t tbi = 0;
4801 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
4802
4803 if (arm_el_is_aa64(env, 1)) {
4804 va_size = 64;
4805 if (extract64(address, 55, 1))
4806 tbi = extract64(tcr->raw_tcr, 38, 1);
4807 else
4808 tbi = extract64(tcr->raw_tcr, 37, 1);
4809 tbi *= 8;
4810 }
4811
4812 /* Determine whether this address is in the region controlled by
4813 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
4814 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
4815 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
4816 */
4817 uint32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
4818 if (arm_el_is_aa64(env, 1)) {
4819 t0sz = MIN(t0sz, 39);
4820 t0sz = MAX(t0sz, 16);
4821 }
4822 uint32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
4823 if (arm_el_is_aa64(env, 1)) {
4824 t1sz = MIN(t1sz, 39);
4825 t1sz = MAX(t1sz, 16);
4826 }
4827 if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
4828 /* there is a ttbr0 region and we are in it (high bits all zero) */
4829 ttbr_select = 0;
4830 } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) {
4831 /* there is a ttbr1 region and we are in it (high bits all one) */
4832 ttbr_select = 1;
4833 } else if (!t0sz) {
4834 /* ttbr0 region is "everything not in the ttbr1 region" */
4835 ttbr_select = 0;
4836 } else if (!t1sz) {
4837 /* ttbr1 region is "everything not in the ttbr0 region" */
4838 ttbr_select = 1;
4839 } else {
4840 /* in the gap between the two regions, this is a Translation fault */
4841 fault_type = translation_fault;
4842 goto do_fault;
4843 }
4844
4845 /* Note that QEMU ignores shareability and cacheability attributes,
4846 * so we don't need to do anything with the SH, ORGN, IRGN fields
4847 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
4848 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
4849 * implement any ASID-like capability so we can ignore it (instead
4850 * we will always flush the TLB any time the ASID is changed).
4851 */
4852 if (ttbr_select == 0) {
4853 ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr0);
4854 epd = extract32(tcr->raw_tcr, 7, 1);
4855 tsz = t0sz;
4856
4857 tg = extract32(tcr->raw_tcr, 14, 2);
4858 if (tg == 1) { /* 64KB pages */
4859 granule_sz = 13;
4860 }
4861 if (tg == 2) { /* 16KB pages */
4862 granule_sz = 11;
4863 }
4864 } else {
4865 ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr1);
4866 epd = extract32(tcr->raw_tcr, 23, 1);
4867 tsz = t1sz;
4868
4869 tg = extract32(tcr->raw_tcr, 30, 2);
4870 if (tg == 3) { /* 64KB pages */
4871 granule_sz = 13;
4872 }
4873 if (tg == 1) { /* 16KB pages */
4874 granule_sz = 11;
4875 }
4876 }
4877
4878 if (epd) {
4879 /* Translation table walk disabled => Translation fault on TLB miss */
4880 goto do_fault;
4881 }
4882
4883 /* The starting level depends on the virtual address size (which can be
4884 * up to 48 bits) and the translation granule size. It indicates the number
4885 * of strides (granule_sz bits at a time) needed to consume the bits
4886 * of the input address. In the pseudocode this is:
4887 * level = 4 - RoundUp((inputsize - grainsize) / stride)
4888 * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
4889 * our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
4890 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
4891 * = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
4892 * = 4 - (va_size - tsz - 4) / granule_sz;
4893 */
4894 level = 4 - (va_size - tsz - 4) / granule_sz;
4895
4896 /* Clear the vaddr bits which aren't part of the within-region address,
4897 * so that we don't have to special case things when calculating the
4898 * first descriptor address.
4899 */
4900 if (tsz) {
4901 address &= (1ULL << (va_size - tsz)) - 1;
4902 }
4903
4904 descmask = (1ULL << (granule_sz + 3)) - 1;
4905
4906 /* Now we can extract the actual base address from the TTBR */
4907 descaddr = extract64(ttbr, 0, 48);
4908 descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
4909
4910 tableattrs = 0;
4911 for (;;) {
4912 uint64_t descriptor;
4913
4914 descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
4915 descaddr &= ~7ULL;
4916 descriptor = ldq_phys(cs->as, descaddr);
4917 if (!(descriptor & 1) ||
4918 (!(descriptor & 2) && (level == 3))) {
4919 /* Invalid, or the Reserved level 3 encoding */
4920 goto do_fault;
4921 }
4922 descaddr = descriptor & 0xfffffff000ULL;
4923
4924 if ((descriptor & 2) && (level < 3)) {
4925 /* Table entry. The top five bits are attributes which may
4926 * propagate down through lower levels of the table (and
4927 * which are all arranged so that 0 means "no effect", so
4928 * we can gather them up by ORing in the bits at each level).
4929 */
4930 tableattrs |= extract64(descriptor, 59, 5);
4931 level++;
4932 continue;
4933 }
4934 /* Block entry at level 1 or 2, or page entry at level 3.
4935 * These are basically the same thing, although the number
4936 * of bits we pull in from the vaddr varies.
4937 */
4938 page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
4939 descaddr |= (address & (page_size - 1));
4940 /* Extract attributes from the descriptor and merge with table attrs */
4941 attrs = extract64(descriptor, 2, 10)
4942 | (extract64(descriptor, 52, 12) << 10);
4943 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
4944 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
4945 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
4946 * means "force PL1 access only", which means forcing AP[1] to 0.
4947 */
4948 if (extract32(tableattrs, 2, 1)) {
4949 attrs &= ~(1 << 4);
4950 }
4951 /* Since we're always in the Non-secure state, NSTable is ignored. */
4952 break;
4953 }
4954 /* Here descaddr is the final physical address, and attributes
4955 * are all in attrs.
4956 */
4957 fault_type = access_fault;
4958 if ((attrs & (1 << 8)) == 0) {
4959 /* Access flag */
4960 goto do_fault;
4961 }
4962 fault_type = permission_fault;
4963 if (is_user && !(attrs & (1 << 4))) {
4964 /* Unprivileged access not enabled */
4965 goto do_fault;
4966 }
4967 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4968 if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) ||
4969 (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) ||
4970 (!is_user && (attrs & (1 << 11)))) {
4971 /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally
4972 * treat XN/UXN as UXN for v8.
4973 */
4974 if (access_type == 2) {
4975 goto do_fault;
4976 }
4977 *prot &= ~PAGE_EXEC;
4978 }
4979 if (attrs & (1 << 5)) {
4980 /* Write access forbidden */
4981 if (access_type == 1) {
4982 goto do_fault;
4983 }
4984 *prot &= ~PAGE_WRITE;
4985 }
4986
4987 *phys_ptr = descaddr;
4988 *page_size_ptr = page_size;
4989 return 0;
4990
4991 do_fault:
4992 /* Long-descriptor format IFSR/DFSR value */
4993 return (1 << 9) | (fault_type << 2) | level;
4994 }
4995
4996 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
4997 int access_type, int is_user,
4998 hwaddr *phys_ptr, int *prot)
4999 {
5000 int n;
5001 uint32_t mask;
5002 uint32_t base;
5003
5004 *phys_ptr = address;
5005 for (n = 7; n >= 0; n--) {
5006 base = env->cp15.c6_region[n];
5007 if ((base & 1) == 0)
5008 continue;
5009 mask = 1 << ((base >> 1) & 0x1f);
5010 /* Keep this shift separate from the above to avoid an
5011 (undefined) << 32. */
5012 mask = (mask << 1) - 1;
5013 if (((base ^ address) & ~mask) == 0)
5014 break;
5015 }
5016 if (n < 0)
5017 return 2;
5018
5019 if (access_type == 2) {
5020 mask = env->cp15.pmsav5_insn_ap;
5021 } else {
5022 mask = env->cp15.pmsav5_data_ap;
5023 }
5024 mask = (mask >> (n * 4)) & 0xf;
5025 switch (mask) {
5026 case 0:
5027 return 1;
5028 case 1:
5029 if (is_user)
5030 return 1;
5031 *prot = PAGE_READ | PAGE_WRITE;
5032 break;
5033 case 2:
5034 *prot = PAGE_READ;
5035 if (!is_user)
5036 *prot |= PAGE_WRITE;
5037 break;
5038 case 3:
5039 *prot = PAGE_READ | PAGE_WRITE;
5040 break;
5041 case 5:
5042 if (is_user)
5043 return 1;
5044 *prot = PAGE_READ;
5045 break;
5046 case 6:
5047 *prot = PAGE_READ;
5048 break;
5049 default:
5050 /* Bad permission. */
5051 return 1;
5052 }
5053 *prot |= PAGE_EXEC;
5054 return 0;
5055 }
5056
5057 /* get_phys_addr - get the physical address for this virtual address
5058 *
5059 * Find the physical address corresponding to the given virtual address,
5060 * by doing a translation table walk on MMU based systems or using the
5061 * MPU state on MPU based systems.
5062 *
5063 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
5064 * prot and page_size are not filled in, and the return value provides
5065 * information on why the translation aborted, in the format of a
5066 * DFSR/IFSR fault register, with the following caveats:
5067 * * we honour the short vs long DFSR format differences.
5068 * * the WnR bit is never set (the caller must do this).
5069 * * for MPU based systems we don't bother to return a full FSR format
5070 * value.
5071 *
5072 * @env: CPUARMState
5073 * @address: virtual address to get physical address for
5074 * @access_type: 0 for read, 1 for write, 2 for execute
5075 * @is_user: 0 for privileged access, 1 for user
5076 * @phys_ptr: set to the physical address corresponding to the virtual address
5077 * @prot: set to the permissions for the page containing phys_ptr
5078 * @page_size: set to the size of the page containing phys_ptr
5079 */
5080 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
5081 int access_type, int is_user,
5082 hwaddr *phys_ptr, int *prot,
5083 target_ulong *page_size)
5084 {
5085 /* This is not entirely correct as get_phys_addr() can also be called
5086 * from ats_write() for an address translation of a specific regime.
5087 */
5088 uint32_t sctlr = A32_BANKED_CURRENT_REG_GET(env, sctlr);
5089
5090 /* Fast Context Switch Extension. */
5091 if (address < 0x02000000) {
5092 address += A32_BANKED_CURRENT_REG_GET(env, fcseidr);
5093 }
5094
5095 if ((sctlr & SCTLR_M) == 0) {
5096 /* MMU/MPU disabled. */
5097 *phys_ptr = address;
5098 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
5099 *page_size = TARGET_PAGE_SIZE;
5100 return 0;
5101 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
5102 *page_size = TARGET_PAGE_SIZE;
5103 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
5104 prot);
5105 } else if (extended_addresses_enabled(env)) {
5106 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
5107 prot, page_size);
5108 } else if (sctlr & SCTLR_XP) {
5109 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
5110 prot, page_size);
5111 } else {
5112 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
5113 prot, page_size);
5114 }
5115 }
5116
5117 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
5118 int access_type, int mmu_idx)
5119 {
5120 ARMCPU *cpu = ARM_CPU(cs);
5121 CPUARMState *env = &cpu->env;
5122 hwaddr phys_addr;
5123 target_ulong page_size;
5124 int prot;
5125 int ret, is_user;
5126 uint32_t syn;
5127 bool same_el = (arm_current_el(env) != 0);
5128
5129 is_user = mmu_idx == MMU_USER_IDX;
5130 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
5131 &page_size);
5132 if (ret == 0) {
5133 /* Map a single [sub]page. */
5134 phys_addr &= TARGET_PAGE_MASK;
5135 address &= TARGET_PAGE_MASK;
5136 tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
5137 return 0;
5138 }
5139
5140 /* AArch64 syndrome does not have an LPAE bit */
5141 syn = ret & ~(1 << 9);
5142
5143 /* For insn and data aborts we assume there is no instruction syndrome
5144 * information; this is always true for exceptions reported to EL1.
5145 */
5146 if (access_type == 2) {
5147 syn = syn_insn_abort(same_el, 0, 0, syn);
5148 cs->exception_index = EXCP_PREFETCH_ABORT;
5149 } else {
5150 syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
5151 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
5152 ret |= (1 << 11);
5153 }
5154 cs->exception_index = EXCP_DATA_ABORT;
5155 }
5156
5157 env->exception.syndrome = syn;
5158 env->exception.vaddress = address;
5159 env->exception.fsr = ret;
5160 return 1;
5161 }
5162
5163 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
5164 {
5165 ARMCPU *cpu = ARM_CPU(cs);
5166 hwaddr phys_addr;
5167 target_ulong page_size;
5168 int prot;
5169 int ret;
5170
5171 ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
5172
5173 if (ret != 0) {
5174 return -1;
5175 }
5176
5177 return phys_addr;
5178 }
5179
5180 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
5181 {
5182 if ((env->uncached_cpsr & CPSR_M) == mode) {
5183 env->regs[13] = val;
5184 } else {
5185 env->banked_r13[bank_number(mode)] = val;
5186 }
5187 }
5188
5189 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
5190 {
5191 if ((env->uncached_cpsr & CPSR_M) == mode) {
5192 return env->regs[13];
5193 } else {
5194 return env->banked_r13[bank_number(mode)];
5195 }
5196 }
5197
5198 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5199 {
5200 ARMCPU *cpu = arm_env_get_cpu(env);
5201
5202 switch (reg) {
5203 case 0: /* APSR */
5204 return xpsr_read(env) & 0xf8000000;
5205 case 1: /* IAPSR */
5206 return xpsr_read(env) & 0xf80001ff;
5207 case 2: /* EAPSR */
5208 return xpsr_read(env) & 0xff00fc00;
5209 case 3: /* xPSR */
5210 return xpsr_read(env) & 0xff00fdff;
5211 case 5: /* IPSR */
5212 return xpsr_read(env) & 0x000001ff;
5213 case 6: /* EPSR */
5214 return xpsr_read(env) & 0x0700fc00;
5215 case 7: /* IEPSR */
5216 return xpsr_read(env) & 0x0700edff;
5217 case 8: /* MSP */
5218 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
5219 case 9: /* PSP */
5220 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
5221 case 16: /* PRIMASK */
5222 return (env->daif & PSTATE_I) != 0;
5223 case 17: /* BASEPRI */
5224 case 18: /* BASEPRI_MAX */
5225 return env->v7m.basepri;
5226 case 19: /* FAULTMASK */
5227 return (env->daif & PSTATE_F) != 0;
5228 case 20: /* CONTROL */
5229 return env->v7m.control;
5230 default:
5231 /* ??? For debugging only. */
5232 cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
5233 return 0;
5234 }
5235 }
5236
5237 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5238 {
5239 ARMCPU *cpu = arm_env_get_cpu(env);
5240
5241 switch (reg) {
5242 case 0: /* APSR */
5243 xpsr_write(env, val, 0xf8000000);
5244 break;
5245 case 1: /* IAPSR */
5246 xpsr_write(env, val, 0xf8000000);
5247 break;
5248 case 2: /* EAPSR */
5249 xpsr_write(env, val, 0xfe00fc00);
5250 break;
5251 case 3: /* xPSR */
5252 xpsr_write(env, val, 0xfe00fc00);
5253 break;
5254 case 5: /* IPSR */
5255 /* IPSR bits are readonly. */
5256 break;
5257 case 6: /* EPSR */
5258 xpsr_write(env, val, 0x0600fc00);
5259 break;
5260 case 7: /* IEPSR */
5261 xpsr_write(env, val, 0x0600fc00);
5262 break;
5263 case 8: /* MSP */
5264 if (env->v7m.current_sp)
5265 env->v7m.other_sp = val;
5266 else
5267 env->regs[13] = val;
5268 break;
5269 case 9: /* PSP */
5270 if (env->v7m.current_sp)
5271 env->regs[13] = val;
5272 else
5273 env->v7m.other_sp = val;
5274 break;
5275 case 16: /* PRIMASK */
5276 if (val & 1) {
5277 env->daif |= PSTATE_I;
5278 } else {
5279 env->daif &= ~PSTATE_I;
5280 }
5281 break;
5282 case 17: /* BASEPRI */
5283 env->v7m.basepri = val & 0xff;
5284 break;
5285 case 18: /* BASEPRI_MAX */
5286 val &= 0xff;
5287 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
5288 env->v7m.basepri = val;
5289 break;
5290 case 19: /* FAULTMASK */
5291 if (val & 1) {
5292 env->daif |= PSTATE_F;
5293 } else {
5294 env->daif &= ~PSTATE_F;
5295 }
5296 break;
5297 case 20: /* CONTROL */
5298 env->v7m.control = val & 3;
5299 switch_v7m_sp(env, (val & 2) != 0);
5300 break;
5301 default:
5302 /* ??? For debugging only. */
5303 cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
5304 return;
5305 }
5306 }
5307
5308 #endif
5309
5310 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
5311 {
5312 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
5313 * Note that we do not implement the (architecturally mandated)
5314 * alignment fault for attempts to use this on Device memory
5315 * (which matches the usual QEMU behaviour of not implementing either
5316 * alignment faults or any memory attribute handling).
5317 */
5318
5319 ARMCPU *cpu = arm_env_get_cpu(env);
5320 uint64_t blocklen = 4 << cpu->dcz_blocksize;
5321 uint64_t vaddr = vaddr_in & ~(blocklen - 1);
5322
5323 #ifndef CONFIG_USER_ONLY
5324 {
5325 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
5326 * the block size so we might have to do more than one TLB lookup.
5327 * We know that in fact for any v8 CPU the page size is at least 4K
5328 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
5329 * 1K as an artefact of legacy v5 subpage support being present in the
5330 * same QEMU executable.
5331 */
5332 int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
5333 void *hostaddr[maxidx];
5334 int try, i;
5335
5336 for (try = 0; try < 2; try++) {
5337
5338 for (i = 0; i < maxidx; i++) {
5339 hostaddr[i] = tlb_vaddr_to_host(env,
5340 vaddr + TARGET_PAGE_SIZE * i,
5341 1, cpu_mmu_index(env));
5342 if (!hostaddr[i]) {
5343 break;
5344 }
5345 }
5346 if (i == maxidx) {
5347 /* If it's all in the TLB it's fair game for just writing to;
5348 * we know we don't need to update dirty status, etc.
5349 */
5350 for (i = 0; i < maxidx - 1; i++) {
5351 memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
5352 }
5353 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
5354 return;
5355 }
5356 /* OK, try a store and see if we can populate the tlb. This
5357 * might cause an exception if the memory isn't writable,
5358 * in which case we will longjmp out of here. We must for
5359 * this purpose use the actual register value passed to us
5360 * so that we get the fault address right.
5361 */
5362 helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA());
5363 /* Now we can populate the other TLB entries, if any */
5364 for (i = 0; i < maxidx; i++) {
5365 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
5366 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
5367 helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA());
5368 }
5369 }
5370 }
5371
5372 /* Slow path (probably attempt to do this to an I/O device or
5373 * similar, or clearing of a block of code we have translations
5374 * cached for). Just do a series of byte writes as the architecture
5375 * demands. It's not worth trying to use a cpu_physical_memory_map(),
5376 * memset(), unmap() sequence here because:
5377 * + we'd need to account for the blocksize being larger than a page
5378 * + the direct-RAM access case is almost always going to be dealt
5379 * with in the fastpath code above, so there's no speed benefit
5380 * + we would have to deal with the map returning NULL because the
5381 * bounce buffer was in use
5382 */
5383 for (i = 0; i < blocklen; i++) {
5384 helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA());
5385 }
5386 }
5387 #else
5388 memset(g2h(vaddr), 0, blocklen);
5389 #endif
5390 }
5391
5392 /* Note that signed overflow is undefined in C. The following routines are
5393 careful to use unsigned types where modulo arithmetic is required.
5394 Failure to do so _will_ break on newer gcc. */
5395
5396 /* Signed saturating arithmetic. */
5397
5398 /* Perform 16-bit signed saturating addition. */
5399 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
5400 {
5401 uint16_t res;
5402
5403 res = a + b;
5404 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
5405 if (a & 0x8000)
5406 res = 0x8000;
5407 else
5408 res = 0x7fff;
5409 }
5410 return res;
5411 }
5412
5413 /* Perform 8-bit signed saturating addition. */
5414 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
5415 {
5416 uint8_t res;
5417
5418 res = a + b;
5419 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
5420 if (a & 0x80)
5421 res = 0x80;
5422 else
5423 res = 0x7f;
5424 }
5425 return res;
5426 }
5427
5428 /* Perform 16-bit signed saturating subtraction. */
5429 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
5430 {
5431 uint16_t res;
5432
5433 res = a - b;
5434 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
5435 if (a & 0x8000)
5436 res = 0x8000;
5437 else
5438 res = 0x7fff;
5439 }
5440 return res;
5441 }
5442
5443 /* Perform 8-bit signed saturating subtraction. */
5444 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
5445 {
5446 uint8_t res;
5447
5448 res = a - b;
5449 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
5450 if (a & 0x80)
5451 res = 0x80;
5452 else
5453 res = 0x7f;
5454 }
5455 return res;
5456 }
5457
5458 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
5459 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
5460 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
5461 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
5462 #define PFX q
5463
5464 #include "op_addsub.h"
5465
5466 /* Unsigned saturating arithmetic. */
5467 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
5468 {
5469 uint16_t res;
5470 res = a + b;
5471 if (res < a)
5472 res = 0xffff;
5473 return res;
5474 }
5475
5476 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
5477 {
5478 if (a > b)
5479 return a - b;
5480 else
5481 return 0;
5482 }
5483
5484 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
5485 {
5486 uint8_t res;
5487 res = a + b;
5488 if (res < a)
5489 res = 0xff;
5490 return res;
5491 }
5492
5493 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
5494 {
5495 if (a > b)
5496 return a - b;
5497 else
5498 return 0;
5499 }
5500
5501 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
5502 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
5503 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
5504 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
5505 #define PFX uq
5506
5507 #include "op_addsub.h"
5508
5509 /* Signed modulo arithmetic. */
5510 #define SARITH16(a, b, n, op) do { \
5511 int32_t sum; \
5512 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
5513 RESULT(sum, n, 16); \
5514 if (sum >= 0) \
5515 ge |= 3 << (n * 2); \
5516 } while(0)
5517
5518 #define SARITH8(a, b, n, op) do { \
5519 int32_t sum; \
5520 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
5521 RESULT(sum, n, 8); \
5522 if (sum >= 0) \
5523 ge |= 1 << n; \
5524 } while(0)
5525
5526
5527 #define ADD16(a, b, n) SARITH16(a, b, n, +)
5528 #define SUB16(a, b, n) SARITH16(a, b, n, -)
5529 #define ADD8(a, b, n) SARITH8(a, b, n, +)
5530 #define SUB8(a, b, n) SARITH8(a, b, n, -)
5531 #define PFX s
5532 #define ARITH_GE
5533
5534 #include "op_addsub.h"
5535
5536 /* Unsigned modulo arithmetic. */
5537 #define ADD16(a, b, n) do { \
5538 uint32_t sum; \
5539 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
5540 RESULT(sum, n, 16); \
5541 if ((sum >> 16) == 1) \
5542 ge |= 3 << (n * 2); \
5543 } while(0)
5544
5545 #define ADD8(a, b, n) do { \
5546 uint32_t sum; \
5547 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
5548 RESULT(sum, n, 8); \
5549 if ((sum >> 8) == 1) \
5550 ge |= 1 << n; \
5551 } while(0)
5552
5553 #define SUB16(a, b, n) do { \
5554 uint32_t sum; \
5555 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
5556 RESULT(sum, n, 16); \
5557 if ((sum >> 16) == 0) \
5558 ge |= 3 << (n * 2); \
5559 } while(0)
5560
5561 #define SUB8(a, b, n) do { \
5562 uint32_t sum; \
5563 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
5564 RESULT(sum, n, 8); \
5565 if ((sum >> 8) == 0) \
5566 ge |= 1 << n; \
5567 } while(0)
5568
5569 #define PFX u
5570 #define ARITH_GE
5571
5572 #include "op_addsub.h"
5573
5574 /* Halved signed arithmetic. */
5575 #define ADD16(a, b, n) \
5576 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
5577 #define SUB16(a, b, n) \
5578 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
5579 #define ADD8(a, b, n) \
5580 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
5581 #define SUB8(a, b, n) \
5582 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
5583 #define PFX sh
5584
5585 #include "op_addsub.h"
5586
5587 /* Halved unsigned arithmetic. */
5588 #define ADD16(a, b, n) \
5589 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
5590 #define SUB16(a, b, n) \
5591 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
5592 #define ADD8(a, b, n) \
5593 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
5594 #define SUB8(a, b, n) \
5595 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
5596 #define PFX uh
5597
5598 #include "op_addsub.h"
5599
5600 static inline uint8_t do_usad(uint8_t a, uint8_t b)
5601 {
5602 if (a > b)
5603 return a - b;
5604 else
5605 return b - a;
5606 }
5607
5608 /* Unsigned sum of absolute byte differences. */
5609 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
5610 {
5611 uint32_t sum;
5612 sum = do_usad(a, b);
5613 sum += do_usad(a >> 8, b >> 8);
5614 sum += do_usad(a >> 16, b >>16);
5615 sum += do_usad(a >> 24, b >> 24);
5616 return sum;
5617 }
5618
5619 /* For ARMv6 SEL instruction. */
5620 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
5621 {
5622 uint32_t mask;
5623
5624 mask = 0;
5625 if (flags & 1)
5626 mask |= 0xff;
5627 if (flags & 2)
5628 mask |= 0xff00;
5629 if (flags & 4)
5630 mask |= 0xff0000;
5631 if (flags & 8)
5632 mask |= 0xff000000;
5633 return (a & mask) | (b & ~mask);
5634 }
5635
5636 /* VFP support. We follow the convention used for VFP instructions:
5637 Single precision routines have a "s" suffix, double precision a
5638 "d" suffix. */
5639
5640 /* Convert host exception flags to vfp form. */
5641 static inline int vfp_exceptbits_from_host(int host_bits)
5642 {
5643 int target_bits = 0;
5644
5645 if (host_bits & float_flag_invalid)
5646 target_bits |= 1;
5647 if (host_bits & float_flag_divbyzero)
5648 target_bits |= 2;
5649 if (host_bits & float_flag_overflow)
5650 target_bits |= 4;
5651 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
5652 target_bits |= 8;
5653 if (host_bits & float_flag_inexact)
5654 target_bits |= 0x10;
5655 if (host_bits & float_flag_input_denormal)
5656 target_bits |= 0x80;
5657 return target_bits;
5658 }
5659
5660 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
5661 {
5662 int i;
5663 uint32_t fpscr;
5664
5665 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
5666 | (env->vfp.vec_len << 16)
5667 | (env->vfp.vec_stride << 20);
5668 i = get_float_exception_flags(&env->vfp.fp_status);
5669 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
5670 fpscr |= vfp_exceptbits_from_host(i);
5671 return fpscr;
5672 }
5673
5674 uint32_t vfp_get_fpscr(CPUARMState *env)
5675 {
5676 return HELPER(vfp_get_fpscr)(env);
5677 }
5678
5679 /* Convert vfp exception flags to target form. */
5680 static inline int vfp_exceptbits_to_host(int target_bits)
5681 {
5682 int host_bits = 0;
5683
5684 if (target_bits & 1)
5685 host_bits |= float_flag_invalid;
5686 if (target_bits & 2)
5687 host_bits |= float_flag_divbyzero;
5688 if (target_bits & 4)
5689 host_bits |= float_flag_overflow;
5690 if (target_bits & 8)
5691 host_bits |= float_flag_underflow;
5692 if (target_bits & 0x10)
5693 host_bits |= float_flag_inexact;
5694 if (target_bits & 0x80)
5695 host_bits |= float_flag_input_denormal;
5696 return host_bits;
5697 }
5698
5699 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
5700 {
5701 int i;
5702 uint32_t changed;
5703
5704 changed = env->vfp.xregs[ARM_VFP_FPSCR];
5705 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
5706 env->vfp.vec_len = (val >> 16) & 7;
5707 env->vfp.vec_stride = (val >> 20) & 3;
5708
5709 changed ^= val;
5710 if (changed & (3 << 22)) {
5711 i = (val >> 22) & 3;
5712 switch (i) {
5713 case FPROUNDING_TIEEVEN:
5714 i = float_round_nearest_even;
5715 break;
5716 case FPROUNDING_POSINF:
5717 i = float_round_up;
5718 break;
5719 case FPROUNDING_NEGINF:
5720 i = float_round_down;
5721 break;
5722 case FPROUNDING_ZERO:
5723 i = float_round_to_zero;
5724 break;
5725 }
5726 set_float_rounding_mode(i, &env->vfp.fp_status);
5727 }
5728 if (changed & (1 << 24)) {
5729 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
5730 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
5731 }
5732 if (changed & (1 << 25))
5733 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
5734
5735 i = vfp_exceptbits_to_host(val);
5736 set_float_exception_flags(i, &env->vfp.fp_status);
5737 set_float_exception_flags(0, &env->vfp.standard_fp_status);
5738 }
5739
5740 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
5741 {
5742 HELPER(vfp_set_fpscr)(env, val);
5743 }
5744
5745 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
5746
5747 #define VFP_BINOP(name) \
5748 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
5749 { \
5750 float_status *fpst = fpstp; \
5751 return float32_ ## name(a, b, fpst); \
5752 } \
5753 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
5754 { \
5755 float_status *fpst = fpstp; \
5756 return float64_ ## name(a, b, fpst); \
5757 }
5758 VFP_BINOP(add)
5759 VFP_BINOP(sub)
5760 VFP_BINOP(mul)
5761 VFP_BINOP(div)
5762 VFP_BINOP(min)
5763 VFP_BINOP(max)
5764 VFP_BINOP(minnum)
5765 VFP_BINOP(maxnum)
5766 #undef VFP_BINOP
5767
5768 float32 VFP_HELPER(neg, s)(float32 a)
5769 {
5770 return float32_chs(a);
5771 }
5772
5773 float64 VFP_HELPER(neg, d)(float64 a)
5774 {
5775 return float64_chs(a);
5776 }
5777
5778 float32 VFP_HELPER(abs, s)(float32 a)
5779 {
5780 return float32_abs(a);
5781 }
5782
5783 float64 VFP_HELPER(abs, d)(float64 a)
5784 {
5785 return float64_abs(a);
5786 }
5787
5788 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
5789 {
5790 return float32_sqrt(a, &env->vfp.fp_status);
5791 }
5792
5793 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
5794 {
5795 return float64_sqrt(a, &env->vfp.fp_status);
5796 }
5797
5798 /* XXX: check quiet/signaling case */
5799 #define DO_VFP_cmp(p, type) \
5800 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
5801 { \
5802 uint32_t flags; \
5803 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
5804 case 0: flags = 0x6; break; \
5805 case -1: flags = 0x8; break; \
5806 case 1: flags = 0x2; break; \
5807 default: case 2: flags = 0x3; break; \
5808 } \
5809 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
5810 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
5811 } \
5812 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
5813 { \
5814 uint32_t flags; \
5815 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
5816 case 0: flags = 0x6; break; \
5817 case -1: flags = 0x8; break; \
5818 case 1: flags = 0x2; break; \
5819 default: case 2: flags = 0x3; break; \
5820 } \
5821 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
5822 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
5823 }
5824 DO_VFP_cmp(s, float32)
5825 DO_VFP_cmp(d, float64)
5826 #undef DO_VFP_cmp
5827
5828 /* Integer to float and float to integer conversions */
5829
5830 #define CONV_ITOF(name, fsz, sign) \
5831 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
5832 { \
5833 float_status *fpst = fpstp; \
5834 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
5835 }
5836
5837 #define CONV_FTOI(name, fsz, sign, round) \
5838 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
5839 { \
5840 float_status *fpst = fpstp; \
5841 if (float##fsz##_is_any_nan(x)) { \
5842 float_raise(float_flag_invalid, fpst); \
5843 return 0; \
5844 } \
5845 return float##fsz##_to_##sign##int32##round(x, fpst); \
5846 }
5847
5848 #define FLOAT_CONVS(name, p, fsz, sign) \
5849 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
5850 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
5851 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
5852
5853 FLOAT_CONVS(si, s, 32, )
5854 FLOAT_CONVS(si, d, 64, )
5855 FLOAT_CONVS(ui, s, 32, u)
5856 FLOAT_CONVS(ui, d, 64, u)
5857
5858 #undef CONV_ITOF
5859 #undef CONV_FTOI
5860 #undef FLOAT_CONVS
5861
5862 /* floating point conversion */
5863 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
5864 {
5865 float64 r = float32_to_float64(x, &env->vfp.fp_status);
5866 /* ARM requires that S<->D conversion of any kind of NaN generates
5867 * a quiet NaN by forcing the most significant frac bit to 1.
5868 */
5869 return float64_maybe_silence_nan(r);
5870 }
5871
5872 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
5873 {
5874 float32 r = float64_to_float32(x, &env->vfp.fp_status);
5875 /* ARM requires that S<->D conversion of any kind of NaN generates
5876 * a quiet NaN by forcing the most significant frac bit to 1.
5877 */
5878 return float32_maybe_silence_nan(r);
5879 }
5880
5881 /* VFP3 fixed point conversion. */
5882 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
5883 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
5884 void *fpstp) \
5885 { \
5886 float_status *fpst = fpstp; \
5887 float##fsz tmp; \
5888 tmp = itype##_to_##float##fsz(x, fpst); \
5889 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
5890 }
5891
5892 /* Notice that we want only input-denormal exception flags from the
5893 * scalbn operation: the other possible flags (overflow+inexact if
5894 * we overflow to infinity, output-denormal) aren't correct for the
5895 * complete scale-and-convert operation.
5896 */
5897 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
5898 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
5899 uint32_t shift, \
5900 void *fpstp) \
5901 { \
5902 float_status *fpst = fpstp; \
5903 int old_exc_flags = get_float_exception_flags(fpst); \
5904 float##fsz tmp; \
5905 if (float##fsz##_is_any_nan(x)) { \
5906 float_raise(float_flag_invalid, fpst); \
5907 return 0; \
5908 } \
5909 tmp = float##fsz##_scalbn(x, shift, fpst); \
5910 old_exc_flags |= get_float_exception_flags(fpst) \
5911 & float_flag_input_denormal; \
5912 set_float_exception_flags(old_exc_flags, fpst); \
5913 return float##fsz##_to_##itype##round(tmp, fpst); \
5914 }
5915
5916 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
5917 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
5918 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
5919 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
5920
5921 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
5922 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
5923 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
5924
5925 VFP_CONV_FIX(sh, d, 64, 64, int16)
5926 VFP_CONV_FIX(sl, d, 64, 64, int32)
5927 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
5928 VFP_CONV_FIX(uh, d, 64, 64, uint16)
5929 VFP_CONV_FIX(ul, d, 64, 64, uint32)
5930 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
5931 VFP_CONV_FIX(sh, s, 32, 32, int16)
5932 VFP_CONV_FIX(sl, s, 32, 32, int32)
5933 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
5934 VFP_CONV_FIX(uh, s, 32, 32, uint16)
5935 VFP_CONV_FIX(ul, s, 32, 32, uint32)
5936 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
5937 #undef VFP_CONV_FIX
5938 #undef VFP_CONV_FIX_FLOAT
5939 #undef VFP_CONV_FLOAT_FIX_ROUND
5940
5941 /* Set the current fp rounding mode and return the old one.
5942 * The argument is a softfloat float_round_ value.
5943 */
5944 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
5945 {
5946 float_status *fp_status = &env->vfp.fp_status;
5947
5948 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
5949 set_float_rounding_mode(rmode, fp_status);
5950
5951 return prev_rmode;
5952 }
5953
5954 /* Set the current fp rounding mode in the standard fp status and return
5955 * the old one. This is for NEON instructions that need to change the
5956 * rounding mode but wish to use the standard FPSCR values for everything
5957 * else. Always set the rounding mode back to the correct value after
5958 * modifying it.
5959 * The argument is a softfloat float_round_ value.
5960 */
5961 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
5962 {
5963 float_status *fp_status = &env->vfp.standard_fp_status;
5964
5965 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
5966 set_float_rounding_mode(rmode, fp_status);
5967
5968 return prev_rmode;
5969 }
5970
5971 /* Half precision conversions. */
5972 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
5973 {
5974 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5975 float32 r = float16_to_float32(make_float16(a), ieee, s);
5976 if (ieee) {
5977 return float32_maybe_silence_nan(r);
5978 }
5979 return r;
5980 }
5981
5982 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
5983 {
5984 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5985 float16 r = float32_to_float16(a, ieee, s);
5986 if (ieee) {
5987 r = float16_maybe_silence_nan(r);
5988 }
5989 return float16_val(r);
5990 }
5991
5992 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
5993 {
5994 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
5995 }
5996
5997 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
5998 {
5999 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
6000 }
6001
6002 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
6003 {
6004 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
6005 }
6006
6007 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
6008 {
6009 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
6010 }
6011
6012 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
6013 {
6014 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6015 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
6016 if (ieee) {
6017 return float64_maybe_silence_nan(r);
6018 }
6019 return r;
6020 }
6021
6022 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
6023 {
6024 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6025 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
6026 if (ieee) {
6027 r = float16_maybe_silence_nan(r);
6028 }
6029 return float16_val(r);
6030 }
6031
6032 #define float32_two make_float32(0x40000000)
6033 #define float32_three make_float32(0x40400000)
6034 #define float32_one_point_five make_float32(0x3fc00000)
6035
6036 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
6037 {
6038 float_status *s = &env->vfp.standard_fp_status;
6039 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
6040 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
6041 if (!(float32_is_zero(a) || float32_is_zero(b))) {
6042 float_raise(float_flag_input_denormal, s);
6043 }
6044 return float32_two;
6045 }
6046 return float32_sub(float32_two, float32_mul(a, b, s), s);
6047 }
6048
6049 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
6050 {
6051 float_status *s = &env->vfp.standard_fp_status;
6052 float32 product;
6053 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
6054 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
6055 if (!(float32_is_zero(a) || float32_is_zero(b))) {
6056 float_raise(float_flag_input_denormal, s);
6057 }
6058 return float32_one_point_five;
6059 }
6060 product = float32_mul(a, b, s);
6061 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
6062 }
6063
6064 /* NEON helpers. */
6065
6066 /* Constants 256 and 512 are used in some helpers; we avoid relying on
6067 * int->float conversions at run-time. */
6068 #define float64_256 make_float64(0x4070000000000000LL)
6069 #define float64_512 make_float64(0x4080000000000000LL)
6070 #define float32_maxnorm make_float32(0x7f7fffff)
6071 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
6072
6073 /* Reciprocal functions
6074 *
6075 * The algorithm that must be used to calculate the estimate
6076 * is specified by the ARM ARM, see FPRecipEstimate()
6077 */
6078
6079 static float64 recip_estimate(float64 a, float_status *real_fp_status)
6080 {
6081 /* These calculations mustn't set any fp exception flags,
6082 * so we use a local copy of the fp_status.
6083 */
6084 float_status dummy_status = *real_fp_status;
6085 float_status *s = &dummy_status;
6086 /* q = (int)(a * 512.0) */
6087 float64 q = float64_mul(float64_512, a, s);
6088 int64_t q_int = float64_to_int64_round_to_zero(q, s);
6089
6090 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
6091 q = int64_to_float64(q_int, s);
6092 q = float64_add(q, float64_half, s);
6093 q = float64_div(q, float64_512, s);
6094 q = float64_div(float64_one, q, s);
6095
6096 /* s = (int)(256.0 * r + 0.5) */
6097 q = float64_mul(q, float64_256, s);
6098 q = float64_add(q, float64_half, s);
6099 q_int = float64_to_int64_round_to_zero(q, s);
6100
6101 /* return (double)s / 256.0 */
6102 return float64_div(int64_to_float64(q_int, s), float64_256, s);
6103 }
6104
6105 /* Common wrapper to call recip_estimate */
6106 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
6107 {
6108 uint64_t val64 = float64_val(num);
6109 uint64_t frac = extract64(val64, 0, 52);
6110 int64_t exp = extract64(val64, 52, 11);
6111 uint64_t sbit;
6112 float64 scaled, estimate;
6113
6114 /* Generate the scaled number for the estimate function */
6115 if (exp == 0) {
6116 if (extract64(frac, 51, 1) == 0) {
6117 exp = -1;
6118 frac = extract64(frac, 0, 50) << 2;
6119 } else {
6120 frac = extract64(frac, 0, 51) << 1;
6121 }
6122 }
6123
6124 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
6125 scaled = make_float64((0x3feULL << 52)
6126 | extract64(frac, 44, 8) << 44);
6127
6128 estimate = recip_estimate(scaled, fpst);
6129
6130 /* Build new result */
6131 val64 = float64_val(estimate);
6132 sbit = 0x8000000000000000ULL & val64;
6133 exp = off - exp;
6134 frac = extract64(val64, 0, 52);
6135
6136 if (exp == 0) {
6137 frac = 1ULL << 51 | extract64(frac, 1, 51);
6138 } else if (exp == -1) {
6139 frac = 1ULL << 50 | extract64(frac, 2, 50);
6140 exp = 0;
6141 }
6142
6143 return make_float64(sbit | (exp << 52) | frac);
6144 }
6145
6146 static bool round_to_inf(float_status *fpst, bool sign_bit)
6147 {
6148 switch (fpst->float_rounding_mode) {
6149 case float_round_nearest_even: /* Round to Nearest */
6150 return true;
6151 case float_round_up: /* Round to +Inf */
6152 return !sign_bit;
6153 case float_round_down: /* Round to -Inf */
6154 return sign_bit;
6155 case float_round_to_zero: /* Round to Zero */
6156 return false;
6157 }
6158
6159 g_assert_not_reached();
6160 }
6161
6162 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
6163 {
6164 float_status *fpst = fpstp;
6165 float32 f32 = float32_squash_input_denormal(input, fpst);
6166 uint32_t f32_val = float32_val(f32);
6167 uint32_t f32_sbit = 0x80000000ULL & f32_val;
6168 int32_t f32_exp = extract32(f32_val, 23, 8);
6169 uint32_t f32_frac = extract32(f32_val, 0, 23);
6170 float64 f64, r64;
6171 uint64_t r64_val;
6172 int64_t r64_exp;
6173 uint64_t r64_frac;
6174
6175 if (float32_is_any_nan(f32)) {
6176 float32 nan = f32;
6177 if (float32_is_signaling_nan(f32)) {
6178 float_raise(float_flag_invalid, fpst);
6179 nan = float32_maybe_silence_nan(f32);
6180 }
6181 if (fpst->default_nan_mode) {
6182 nan = float32_default_nan;
6183 }
6184 return nan;
6185 } else if (float32_is_infinity(f32)) {
6186 return float32_set_sign(float32_zero, float32_is_neg(f32));
6187 } else if (float32_is_zero(f32)) {
6188 float_raise(float_flag_divbyzero, fpst);
6189 return float32_set_sign(float32_infinity, float32_is_neg(f32));
6190 } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
6191 /* Abs(value) < 2.0^-128 */
6192 float_raise(float_flag_overflow | float_flag_inexact, fpst);
6193 if (round_to_inf(fpst, f32_sbit)) {
6194 return float32_set_sign(float32_infinity, float32_is_neg(f32));
6195 } else {
6196 return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
6197 }
6198 } else if (f32_exp >= 253 && fpst->flush_to_zero) {
6199 float_raise(float_flag_underflow, fpst);
6200 return float32_set_sign(float32_zero, float32_is_neg(f32));
6201 }
6202
6203
6204 f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
6205 r64 = call_recip_estimate(f64, 253, fpst);
6206 r64_val = float64_val(r64);
6207 r64_exp = extract64(r64_val, 52, 11);
6208 r64_frac = extract64(r64_val, 0, 52);
6209
6210 /* result = sign : result_exp<7:0> : fraction<51:29>; */
6211 return make_float32(f32_sbit |
6212 (r64_exp & 0xff) << 23 |
6213 extract64(r64_frac, 29, 24));
6214 }
6215
6216 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
6217 {
6218 float_status *fpst = fpstp;
6219 float64 f64 = float64_squash_input_denormal(input, fpst);
6220 uint64_t f64_val = float64_val(f64);
6221 uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
6222 int64_t f64_exp = extract64(f64_val, 52, 11);
6223 float64 r64;
6224 uint64_t r64_val;
6225 int64_t r64_exp;
6226 uint64_t r64_frac;
6227
6228 /* Deal with any special cases */
6229 if (float64_is_any_nan(f64)) {
6230 float64 nan = f64;
6231 if (float64_is_signaling_nan(f64)) {
6232 float_raise(float_flag_invalid, fpst);
6233 nan = float64_maybe_silence_nan(f64);
6234 }
6235 if (fpst->default_nan_mode) {
6236 nan = float64_default_nan;
6237 }
6238 return nan;
6239 } else if (float64_is_infinity(f64)) {
6240 return float64_set_sign(float64_zero, float64_is_neg(f64));
6241 } else if (float64_is_zero(f64)) {
6242 float_raise(float_flag_divbyzero, fpst);
6243 return float64_set_sign(float64_infinity, float64_is_neg(f64));
6244 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
6245 /* Abs(value) < 2.0^-1024 */
6246 float_raise(float_flag_overflow | float_flag_inexact, fpst);
6247 if (round_to_inf(fpst, f64_sbit)) {
6248 return float64_set_sign(float64_infinity, float64_is_neg(f64));
6249 } else {
6250 return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
6251 }
6252 } else if (f64_exp >= 1023 && fpst->flush_to_zero) {
6253 float_raise(float_flag_underflow, fpst);
6254 return float64_set_sign(float64_zero, float64_is_neg(f64));
6255 }
6256
6257 r64 = call_recip_estimate(f64, 2045, fpst);
6258 r64_val = float64_val(r64);
6259 r64_exp = extract64(r64_val, 52, 11);
6260 r64_frac = extract64(r64_val, 0, 52);
6261
6262 /* result = sign : result_exp<10:0> : fraction<51:0> */
6263 return make_float64(f64_sbit |
6264 ((r64_exp & 0x7ff) << 52) |
6265 r64_frac);
6266 }
6267
6268 /* The algorithm that must be used to calculate the estimate
6269 * is specified by the ARM ARM.
6270 */
6271 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
6272 {
6273 /* These calculations mustn't set any fp exception flags,
6274 * so we use a local copy of the fp_status.
6275 */
6276 float_status dummy_status = *real_fp_status;
6277 float_status *s = &dummy_status;
6278 float64 q;
6279 int64_t q_int;
6280
6281 if (float64_lt(a, float64_half, s)) {
6282 /* range 0.25 <= a < 0.5 */
6283
6284 /* a in units of 1/512 rounded down */
6285 /* q0 = (int)(a * 512.0); */
6286 q = float64_mul(float64_512, a, s);
6287 q_int = float64_to_int64_round_to_zero(q, s);
6288
6289 /* reciprocal root r */
6290 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
6291 q = int64_to_float64(q_int, s);
6292 q = float64_add(q, float64_half, s);
6293 q = float64_div(q, float64_512, s);
6294 q = float64_sqrt(q, s);
6295 q = float64_div(float64_one, q, s);
6296 } else {
6297 /* range 0.5 <= a < 1.0 */
6298
6299 /* a in units of 1/256 rounded down */
6300 /* q1 = (int)(a * 256.0); */
6301 q = float64_mul(float64_256, a, s);
6302 int64_t q_int = float64_to_int64_round_to_zero(q, s);
6303
6304 /* reciprocal root r */
6305 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
6306 q = int64_to_float64(q_int, s);
6307 q = float64_add(q, float64_half, s);
6308 q = float64_div(q, float64_256, s);
6309 q = float64_sqrt(q, s);
6310 q = float64_div(float64_one, q, s);
6311 }
6312 /* r in units of 1/256 rounded to nearest */
6313 /* s = (int)(256.0 * r + 0.5); */
6314
6315 q = float64_mul(q, float64_256,s );
6316 q = float64_add(q, float64_half, s);
6317 q_int = float64_to_int64_round_to_zero(q, s);
6318
6319 /* return (double)s / 256.0;*/
6320 return float64_div(int64_to_float64(q_int, s), float64_256, s);
6321 }
6322
6323 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
6324 {
6325 float_status *s = fpstp;
6326 float32 f32 = float32_squash_input_denormal(input, s);
6327 uint32_t val = float32_val(f32);
6328 uint32_t f32_sbit = 0x80000000 & val;
6329 int32_t f32_exp = extract32(val, 23, 8);
6330 uint32_t f32_frac = extract32(val, 0, 23);
6331 uint64_t f64_frac;
6332 uint64_t val64;
6333 int result_exp;
6334 float64 f64;
6335
6336 if (float32_is_any_nan(f32)) {
6337 float32 nan = f32;
6338 if (float32_is_signaling_nan(f32)) {
6339 float_raise(float_flag_invalid, s);
6340 nan = float32_maybe_silence_nan(f32);
6341 }
6342 if (s->default_nan_mode) {
6343 nan = float32_default_nan;
6344 }
6345 return nan;
6346 } else if (float32_is_zero(f32)) {
6347 float_raise(float_flag_divbyzero, s);
6348 return float32_set_sign(float32_infinity, float32_is_neg(f32));
6349 } else if (float32_is_neg(f32)) {
6350 float_raise(float_flag_invalid, s);
6351 return float32_default_nan;
6352 } else if (float32_is_infinity(f32)) {
6353 return float32_zero;
6354 }
6355
6356 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
6357 * preserving the parity of the exponent. */
6358
6359 f64_frac = ((uint64_t) f32_frac) << 29;
6360 if (f32_exp == 0) {
6361 while (extract64(f64_frac, 51, 1) == 0) {
6362 f64_frac = f64_frac << 1;
6363 f32_exp = f32_exp-1;
6364 }
6365 f64_frac = extract64(f64_frac, 0, 51) << 1;
6366 }
6367
6368 if (extract64(f32_exp, 0, 1) == 0) {
6369 f64 = make_float64(((uint64_t) f32_sbit) << 32
6370 | (0x3feULL << 52)
6371 | f64_frac);
6372 } else {
6373 f64 = make_float64(((uint64_t) f32_sbit) << 32
6374 | (0x3fdULL << 52)
6375 | f64_frac);
6376 }
6377
6378 result_exp = (380 - f32_exp) / 2;
6379
6380 f64 = recip_sqrt_estimate(f64, s);
6381
6382 val64 = float64_val(f64);
6383
6384 val = ((result_exp & 0xff) << 23)
6385 | ((val64 >> 29) & 0x7fffff);
6386 return make_float32(val);
6387 }
6388
6389 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
6390 {
6391 float_status *s = fpstp;
6392 float64 f64 = float64_squash_input_denormal(input, s);
6393 uint64_t val = float64_val(f64);
6394 uint64_t f64_sbit = 0x8000000000000000ULL & val;
6395 int64_t f64_exp = extract64(val, 52, 11);
6396 uint64_t f64_frac = extract64(val, 0, 52);
6397 int64_t result_exp;
6398 uint64_t result_frac;
6399
6400 if (float64_is_any_nan(f64)) {
6401 float64 nan = f64;
6402 if (float64_is_signaling_nan(f64)) {
6403 float_raise(float_flag_invalid, s);
6404 nan = float64_maybe_silence_nan(f64);
6405 }
6406 if (s->default_nan_mode) {
6407 nan = float64_default_nan;
6408 }
6409 return nan;
6410 } else if (float64_is_zero(f64)) {
6411 float_raise(float_flag_divbyzero, s);
6412 return float64_set_sign(float64_infinity, float64_is_neg(f64));
6413 } else if (float64_is_neg(f64)) {
6414 float_raise(float_flag_invalid, s);
6415 return float64_default_nan;
6416 } else if (float64_is_infinity(f64)) {
6417 return float64_zero;
6418 }
6419
6420 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
6421 * preserving the parity of the exponent. */
6422
6423 if (f64_exp == 0) {
6424 while (extract64(f64_frac, 51, 1) == 0) {
6425 f64_frac = f64_frac << 1;
6426 f64_exp = f64_exp - 1;
6427 }
6428 f64_frac = extract64(f64_frac, 0, 51) << 1;
6429 }
6430
6431 if (extract64(f64_exp, 0, 1) == 0) {
6432 f64 = make_float64(f64_sbit
6433 | (0x3feULL << 52)
6434 | f64_frac);
6435 } else {
6436 f64 = make_float64(f64_sbit
6437 | (0x3fdULL << 52)
6438 | f64_frac);
6439 }
6440
6441 result_exp = (3068 - f64_exp) / 2;
6442
6443 f64 = recip_sqrt_estimate(f64, s);
6444
6445 result_frac = extract64(float64_val(f64), 0, 52);
6446
6447 return make_float64(f64_sbit |
6448 ((result_exp & 0x7ff) << 52) |
6449 result_frac);
6450 }
6451
6452 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
6453 {
6454 float_status *s = fpstp;
6455 float64 f64;
6456
6457 if ((a & 0x80000000) == 0) {
6458 return 0xffffffff;
6459 }
6460
6461 f64 = make_float64((0x3feULL << 52)
6462 | ((int64_t)(a & 0x7fffffff) << 21));
6463
6464 f64 = recip_estimate(f64, s);
6465
6466 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
6467 }
6468
6469 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
6470 {
6471 float_status *fpst = fpstp;
6472 float64 f64;
6473
6474 if ((a & 0xc0000000) == 0) {
6475 return 0xffffffff;
6476 }
6477
6478 if (a & 0x80000000) {
6479 f64 = make_float64((0x3feULL << 52)
6480 | ((uint64_t)(a & 0x7fffffff) << 21));
6481 } else { /* bits 31-30 == '01' */
6482 f64 = make_float64((0x3fdULL << 52)
6483 | ((uint64_t)(a & 0x3fffffff) << 22));
6484 }
6485
6486 f64 = recip_sqrt_estimate(f64, fpst);
6487
6488 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
6489 }
6490
6491 /* VFPv4 fused multiply-accumulate */
6492 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
6493 {
6494 float_status *fpst = fpstp;
6495 return float32_muladd(a, b, c, 0, fpst);
6496 }
6497
6498 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
6499 {
6500 float_status *fpst = fpstp;
6501 return float64_muladd(a, b, c, 0, fpst);
6502 }
6503
6504 /* ARMv8 round to integral */
6505 float32 HELPER(rints_exact)(float32 x, void *fp_status)
6506 {
6507 return float32_round_to_int(x, fp_status);
6508 }
6509
6510 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
6511 {
6512 return float64_round_to_int(x, fp_status);
6513 }
6514
6515 float32 HELPER(rints)(float32 x, void *fp_status)
6516 {
6517 int old_flags = get_float_exception_flags(fp_status), new_flags;
6518 float32 ret;
6519
6520 ret = float32_round_to_int(x, fp_status);
6521
6522 /* Suppress any inexact exceptions the conversion produced */
6523 if (!(old_flags & float_flag_inexact)) {
6524 new_flags = get_float_exception_flags(fp_status);
6525 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
6526 }
6527
6528 return ret;
6529 }
6530
6531 float64 HELPER(rintd)(float64 x, void *fp_status)
6532 {
6533 int old_flags = get_float_exception_flags(fp_status), new_flags;
6534 float64 ret;
6535
6536 ret = float64_round_to_int(x, fp_status);
6537
6538 new_flags = get_float_exception_flags(fp_status);
6539
6540 /* Suppress any inexact exceptions the conversion produced */
6541 if (!(old_flags & float_flag_inexact)) {
6542 new_flags = get_float_exception_flags(fp_status);
6543 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
6544 }
6545
6546 return ret;
6547 }
6548
6549 /* Convert ARM rounding mode to softfloat */
6550 int arm_rmode_to_sf(int rmode)
6551 {
6552 switch (rmode) {
6553 case FPROUNDING_TIEAWAY:
6554 rmode = float_round_ties_away;
6555 break;
6556 case FPROUNDING_ODD:
6557 /* FIXME: add support for TIEAWAY and ODD */
6558 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
6559 rmode);
6560 case FPROUNDING_TIEEVEN:
6561 default:
6562 rmode = float_round_nearest_even;
6563 break;
6564 case FPROUNDING_POSINF:
6565 rmode = float_round_up;
6566 break;
6567 case FPROUNDING_NEGINF:
6568 rmode = float_round_down;
6569 break;
6570 case FPROUNDING_ZERO:
6571 rmode = float_round_to_zero;
6572 break;
6573 }
6574 return rmode;
6575 }
6576
6577 /* CRC helpers.
6578 * The upper bytes of val (above the number specified by 'bytes') must have
6579 * been zeroed out by the caller.
6580 */
6581 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
6582 {
6583 uint8_t buf[4];
6584
6585 stl_le_p(buf, val);
6586
6587 /* zlib crc32 converts the accumulator and output to one's complement. */
6588 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
6589 }
6590
6591 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
6592 {
6593 uint8_t buf[4];
6594
6595 stl_le_p(buf, val);
6596
6597 /* Linux crc32c converts the output to one's complement. */
6598 return crc32c(acc, buf, bytes) ^ 0xffffffff;
6599 }
AR7 emulation for QEMU