hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "qemu/osdep.h"
  31 #include "hw/hw.h"
  32 #include "hw/loader.h"
  33 #include "sysemu/arch_init.h"
  34 #include "hw/i2c/smbus.h"
  35 #include "hw/boards.h"
  36 #include "hw/timer/mc146818rtc.h"
  37 #include "hw/xen/xen.h"
  38 #include "sysemu/kvm.h"
  39 #include "hw/kvm/clock.h"
  40 #include "hw/pci-host/q35.h"
  41 #include "exec/address-spaces.h"
  42 #include "hw/i386/pc.h"
  43 #include "hw/i386/ich9.h"
  44 #include "hw/smbios/smbios.h"
  45 #include "hw/ide/pci.h"
  46 #include "hw/ide/ahci.h"
  47 #include "hw/usb.h"
  48 #include "qemu/error-report.h"
  49 #include "migration/migration.h"
  50
  51 /* ICH9 AHCI has 6 ports */
  52 #define MAX_SATA_PORTS     6
  53
  54 /* PC hardware initialisation */
  55 static void pc_q35_init(MachineState *machine)
  56 {
  57     PCMachineState *pcms = PC_MACHINE(machine);
  58     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
  59     Q35PCIHost *q35_host;
  60     PCIHostState *phb;
  61     PCIBus *host_bus;
  62     PCIDevice *lpc;
  63     DeviceState *lpc_dev;
  64     BusState *idebus[MAX_SATA_PORTS];
  65     ISADevice *rtc_state;
  66     MemoryRegion *system_io = get_system_io();
  67     MemoryRegion *pci_memory;
  68     MemoryRegion *rom_memory;
  69     MemoryRegion *ram_memory;
  70     GSIState *gsi_state;
  71     ISABus *isa_bus;
  72     qemu_irq *gsi;
  73     qemu_irq *i8259;
  74     int i;
  75     ICH9LPCState *ich9_lpc;
  76     PCIDevice *ahci;
  77     ram_addr_t lowmem;
  78     DriveInfo *hd[MAX_SATA_PORTS];
  79     MachineClass *mc = MACHINE_GET_CLASS(machine);
  80
  81     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
  82      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
  83      * also known as MMCFG).
  84      * If it doesn't, we need to split it in chunks below and above 4G.
  85      * In any case, try to make sure that guest addresses aligned at
  86      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
  87      */
  88     if (machine->ram_size >= 0xb0000000) {
  89         lowmem = 0x80000000;
  90     } else {
  91         lowmem = 0xb0000000;
  92     }
  93
  94     /* Handle the machine opt max-ram-below-4g.  It is basically doing
  95      * min(qemu limit, user limit).
  96      */
  97     if (!pcms->max_ram_below_4g) {
  98         pcms->max_ram_below_4g = 1ULL << 32; /* default: 4G */;
  99     }
 100     if (lowmem > pcms->max_ram_below_4g) {
 101         lowmem = pcms->max_ram_below_4g;
 102         if (machine->ram_size - lowmem > lowmem &&
 103             lowmem & ((1ULL << 30) - 1)) {
 104             error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64
 105                          ") not a multiple of 1G; possible bad performance.",
 106                          pcms->max_ram_below_4g);
 107         }
 108     }
 109
 110     if (machine->ram_size >= lowmem) {
 111         pcms->above_4g_mem_size = machine->ram_size - lowmem;
 112         pcms->below_4g_mem_size = lowmem;
 113     } else {
 114         pcms->above_4g_mem_size = 0;
 115         pcms->below_4g_mem_size = machine->ram_size;
 116     }
 117
 118     if (xen_enabled()) {
 119         xen_hvm_init(pcms, &ram_memory);
 120     }
 121
 122     pc_cpus_init(pcms);
 123
 124     kvmclock_create();
 125
 126     /* pci enabled */
 127     if (pcmc->pci_enabled) {
 128         pci_memory = g_new(MemoryRegion, 1);
 129         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 130         rom_memory = pci_memory;
 131     } else {
 132         pci_memory = NULL;
 133         rom_memory = get_system_memory();
 134     }
 135
 136     pc_guest_info_init(pcms);
 137
 138     if (pcmc->smbios_defaults) {
 139         /* These values are guest ABI, do not change */
 140         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 141                             mc->name, pcmc->smbios_legacy_mode,
 142                             pcmc->smbios_uuid_encoded,
 143                             SMBIOS_ENTRY_POINT_21);
 144     }
 145
 146     /* allocate ram and load rom/bios */
 147     if (!xen_enabled()) {
 148         pc_memory_init(pcms, get_system_memory(),
 149                        rom_memory, &ram_memory);
 150     }
 151
 152     /* irq lines */
 153     gsi_state = g_malloc0(sizeof(*gsi_state));
 154     if (kvm_ioapic_in_kernel()) {
 155         kvm_pc_setup_irq_routing(pcmc->pci_enabled);
 156         gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 157                                  GSI_NUM_PINS);
 158     } else {
 159         gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 160     }
 161
 162     /* create pci host bus */
 163     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 164
 165     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 166     object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory),
 167                              MCH_HOST_PROP_RAM_MEM, NULL);
 168     object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory),
 169                              MCH_HOST_PROP_PCI_MEM, NULL);
 170     object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()),
 171                              MCH_HOST_PROP_SYSTEM_MEM, NULL);
 172     object_property_set_link(OBJECT(q35_host), OBJECT(system_io),
 173                              MCH_HOST_PROP_IO_MEM, NULL);
 174     object_property_set_int(OBJECT(q35_host), pcms->below_4g_mem_size,
 175                             PCI_HOST_BELOW_4G_MEM_SIZE, NULL);
 176     object_property_set_int(OBJECT(q35_host), pcms->above_4g_mem_size,
 177                             PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
 178     /* pci */
 179     qdev_init_nofail(DEVICE(q35_host));
 180     phb = PCI_HOST_BRIDGE(q35_host);
 181     host_bus = phb->bus;
 182     /* create ISA bus */
 183     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 184                                           ICH9_LPC_FUNC), true,
 185                                           TYPE_ICH9_LPC_DEVICE);
 186
 187     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 188                              TYPE_HOTPLUG_HANDLER,
 189                              (Object **)&pcms->acpi_dev,
 190                              object_property_allow_set_link,
 191                              OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
 192     object_property_set_link(OBJECT(machine), OBJECT(lpc),
 193                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 194
 195     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 196     lpc_dev = DEVICE(lpc);
 197     for (i = 0; i < GSI_NUM_PINS; i++) {
 198         qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, gsi[i]);
 199     }
 200     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 201                  ICH9_LPC_NB_PIRQS);
 202     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 203     isa_bus = ich9_lpc->isa_bus;
 204
 205     if (kvm_pic_in_kernel()) {
 206         i8259 = kvm_i8259_init(isa_bus);
 207     } else if (xen_enabled()) {
 208         i8259 = xen_interrupt_controller_init();
 209     } else {
 210         i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
 211     }
 212
 213     for (i = 0; i < ISA_NUM_IRQS; i++) {
 214         gsi_state->i8259_irq[i] = i8259[i];
 215     }
 216     if (pcmc->pci_enabled) {
 217         ioapic_init_gsi(gsi_state, "q35");
 218     }
 219
 220     pc_register_ferr_irq(gsi[13]);
 221
 222     assert(pcms->vmport != ON_OFF_AUTO__MAX);
 223     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 224         pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
 225     }
 226
 227     /* init basic PC hardware */
 228     pc_basic_device_init(isa_bus, gsi, &rtc_state, !mc->no_floppy,
 229                          (pcms->vmport != ON_OFF_AUTO_ON), 0xff0104);
 230
 231     /* connect pm stuff to lpc */
 232     ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms));
 233
 234     /* ahci and SATA device, for q35 1 ahci controller is built-in */
 235     ahci = pci_create_simple_multifunction(host_bus,
 236                                            PCI_DEVFN(ICH9_SATA1_DEV,
 237                                                      ICH9_SATA1_FUNC),
 238                                            true, "ich9-ahci");
 239     idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 240     idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 241     g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports);
 242     ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports);
 243     ahci_ide_create_devs(ahci, hd);
 244
 245     if (machine_usb(machine)) {
 246         /* Should we create 6 UHCI according to ich9 spec? */
 247         ehci_create_ich9_with_companions(host_bus, 0x1d);
 248     }
 249
 250     /* TODO: Populate SPD eeprom data.  */
 251     smbus_eeprom_init(ich9_smb_init(host_bus,
 252                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 253                                     0xb100),
 254                       8, NULL, 0);
 255
 256     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 257
 258     /* the rest devices to which pci devfn is automatically assigned */
 259     pc_vga_init(isa_bus, host_bus);
 260     pc_nic_init(isa_bus, host_bus);
 261     if (pcmc->pci_enabled) {
 262         pc_pci_device_init(host_bus);
 263     }
 264
 265     if (pcms->acpi_nvdimm_state.is_enabled) {
 266         nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io,
 267                                pcms->fw_cfg, OBJECT(pcms));
 268     }
 269 }
 270
 271 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 272     static void pc_init_##suffix(MachineState *machine) \
 273     { \
 274         void (*compat)(MachineState *m) = (compatfn); \
 275         if (compat) { \
 276             compat(machine); \
 277         } \
 278         pc_q35_init(machine); \
 279     } \
 280     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 281
 282
 283 static void pc_q35_machine_options(MachineClass *m)
 284 {
 285     m->family = "pc_q35";
 286     m->desc = "Standard PC (Q35 + ICH9, 2009)";
 287     m->hot_add_cpu = pc_hot_add_cpu;
 288     m->units_per_default_bus = 1;
 289     m->default_machine_opts = "firmware=bios-256k.bin";
 290     m->default_display = "std";
 291     m->no_floppy = 1;
 292     m->has_dynamic_sysbus = true;
 293 }
 294
 295 static void pc_q35_2_7_machine_options(MachineClass *m)
 296 {
 297     pc_q35_machine_options(m);
 298     m->alias = "q35";
 299 }
 300
 301 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
 302                    pc_q35_2_7_machine_options);
 303
 304 static void pc_q35_2_6_machine_options(MachineClass *m)
 305 {
 306     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 307     pc_q35_2_7_machine_options(m);
 308     m->alias = NULL;
 309     pcmc->legacy_cpu_hotplug = true;
 310     SET_MACHINE_COMPAT(m, PC_COMPAT_2_6);
 311 }
 312
 313 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
 314                    pc_q35_2_6_machine_options);
 315
 316 static void pc_q35_2_5_machine_options(MachineClass *m)
 317 {
 318     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 319     pc_q35_2_6_machine_options(m);
 320     pcmc->save_tsc_khz = false;
 321     m->legacy_fw_cfg_order = 1;
 322     SET_MACHINE_COMPAT(m, PC_COMPAT_2_5);
 323 }
 324
 325 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 326                    pc_q35_2_5_machine_options);
 327
 328 static void pc_q35_2_4_machine_options(MachineClass *m)
 329 {
 330     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 331     pc_q35_2_5_machine_options(m);
 332     m->hw_version = "2.4.0";
 333     pcmc->broken_reserved_end = true;
 334     SET_MACHINE_COMPAT(m, PC_COMPAT_2_4);
 335 }
 336
 337 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 338                    pc_q35_2_4_machine_options);