include/hw/i386/ich9.h

   1 #ifndef HW_ICH9_H
   2 #define HW_ICH9_H
   3
   4 #include "hw/hw.h"
   5 #include "hw/isa/isa.h"
   6 #include "hw/sysbus.h"
   7 #include "hw/i386/pc.h"
   8 #include "hw/isa/apm.h"
   9 #include "hw/i386/ioapic.h"
  10 #include "hw/pci/pci.h"
  11 #include "hw/pci/pcie_host.h"
  12 #include "hw/pci/pci_bridge.h"
  13 #include "hw/acpi/acpi.h"
  14 #include "hw/acpi/ich9.h"
  15 #include "hw/pci/pci_bus.h"
  16
  17 void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
  18 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
  19 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
  20 void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled, bool enable_tco);
  21 I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
  22
  23 void ich9_generate_smi(void);
  24 void ich9_generate_nmi(void);
  25
  26 #define ICH9_CC_SIZE                            (16 * 1024)     /* 16KB */
  27
  28 #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
  29 #define ICH9_LPC_DEVICE(obj) \
  30      OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
  31
  32 typedef struct ICH9LPCState {
  33     /* ICH9 LPC PCI to ISA bridge */
  34     PCIDevice d;
  35
  36     /* (pci device, intx) -> pirq
  37      * In real chipset case, the unused slots are never used
  38      * as ICH9 supports only D25-D32 irq routing.
  39      * On the other hand in qemu case, any slot/function can be populated
  40      * via command line option.
  41      * So fallback interrupt routing for any devices in any slots is necessary.
  42     */
  43     uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
  44
  45     APMState apm;
  46     ICH9LPCPMRegs pm;
  47     uint32_t sci_level; /* track sci level */
  48
  49     /* 10.1 Chipset Configuration registers(Memory Space)
  50      which is pointed by RCBA */
  51     uint8_t chip_config[ICH9_CC_SIZE];
  52
  53     /*
  54      * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
  55      *
  56      * register contents and IO memory region
  57      */
  58     uint8_t rst_cnt;
  59     MemoryRegion rst_cnt_mem;
  60
  61     /* isa bus */
  62     ISABus *isa_bus;
  63     MemoryRegion rbca_mem;
  64     Notifier machine_ready;
  65
  66     qemu_irq *pic;
  67     qemu_irq *ioapic;
  68 } ICH9LPCState;
  69
  70 Object *ich9_lpc_find(void);
  71
  72 #define Q35_MASK(bit, ms_bit, ls_bit) \
  73 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
  74
  75 /* ICH9: Chipset Configuration Registers */
  76 #define ICH9_CC_ADDR_MASK                       (ICH9_CC_SIZE - 1)
  77
  78 #define ICH9_CC
  79 #define ICH9_CC_D28IP                           0x310C
  80 #define ICH9_CC_D28IP_SHIFT                     4
  81 #define ICH9_CC_D28IP_MASK                      0xf
  82 #define ICH9_CC_D28IP_DEFAULT                   0x00214321
  83 #define ICH9_CC_D31IR                           0x3140
  84 #define ICH9_CC_D30IR                           0x3142
  85 #define ICH9_CC_D29IR                           0x3144
  86 #define ICH9_CC_D28IR                           0x3146
  87 #define ICH9_CC_D27IR                           0x3148
  88 #define ICH9_CC_D26IR                           0x314C
  89 #define ICH9_CC_D25IR                           0x3150
  90 #define ICH9_CC_DIR_DEFAULT                     0x3210
  91 #define ICH9_CC_D30IR_DEFAULT                   0x0
  92 #define ICH9_CC_DIR_SHIFT                       4
  93 #define ICH9_CC_DIR_MASK                        0x7
  94 #define ICH9_CC_OIC                             0x31FF
  95 #define ICH9_CC_OIC_AEN                         0x1
  96 #define ICH9_CC_GCS                             0x3410
  97 #define ICH9_CC_GCS_DEFAULT                     0x00000020
  98 #define ICH9_CC_GCS_NO_REBOOT                   (1 << 5)
  99
 100 /* D28:F[0-5] */
 101 #define ICH9_PCIE_DEV                           28
 102 #define ICH9_PCIE_FUNC_MAX                      6
 103
 104
 105 /* D29:F0 USB UHCI Controller #1 */
 106 #define ICH9_USB_UHCI1_DEV                      29
 107 #define ICH9_USB_UHCI1_FUNC                     0
 108
 109 /* D30:F0 DMI-to-PCI bridge */
 110 #define ICH9_D2P_BRIDGE                         "ICH9 D2P BRIDGE"
 111 #define ICH9_D2P_BRIDGE_SAVEVM_VERSION          0
 112
 113 #define ICH9_D2P_BRIDGE_DEV                     30
 114 #define ICH9_D2P_BRIDGE_FUNC                    0
 115
 116 #define ICH9_D2P_SECONDARY_DEFAULT              (256 - 8)
 117
 118 #define ICH9_D2P_A2_REVISION                    0x92
 119
 120 /* D31:F0 LPC Processor Interface */
 121 #define ICH9_RST_CNT_IOPORT                     0xCF9
 122
 123 /* D31:F1 LPC controller */
 124 #define ICH9_A2_LPC                             "ICH9 A2 LPC"
 125 #define ICH9_A2_LPC_SAVEVM_VERSION              0
 126
 127 #define ICH9_LPC_DEV                            31
 128 #define ICH9_LPC_FUNC                           0
 129
 130 #define ICH9_A2_LPC_REVISION                    0x2
 131 #define ICH9_LPC_NB_PIRQS                       8       /* PCI A-H */
 132
 133 #define ICH9_LPC_PMBASE                         0x40
 134 #define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK       Q35_MASK(32, 15, 7)
 135 #define ICH9_LPC_PMBASE_RTE                     0x1
 136 #define ICH9_LPC_PMBASE_DEFAULT                 0x1
 137 #define ICH9_LPC_ACPI_CTRL                      0x44
 138 #define ICH9_LPC_ACPI_CTRL_ACPI_EN              0x80
 139 #define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK     Q35_MASK(8, 2, 0)
 140 #define ICH9_LPC_ACPI_CTRL_9                    0x0
 141 #define ICH9_LPC_ACPI_CTRL_10                   0x1
 142 #define ICH9_LPC_ACPI_CTRL_11                   0x2
 143 #define ICH9_LPC_ACPI_CTRL_20                   0x4
 144 #define ICH9_LPC_ACPI_CTRL_21                   0x5
 145 #define ICH9_LPC_ACPI_CTRL_DEFAULT              0x0
 146
 147 #define ICH9_LPC_PIRQA_ROUT                     0x60
 148 #define ICH9_LPC_PIRQB_ROUT                     0x61
 149 #define ICH9_LPC_PIRQC_ROUT                     0x62
 150 #define ICH9_LPC_PIRQD_ROUT                     0x63
 151
 152 #define ICH9_LPC_PIRQE_ROUT                     0x68
 153 #define ICH9_LPC_PIRQF_ROUT                     0x69
 154 #define ICH9_LPC_PIRQG_ROUT                     0x6a
 155 #define ICH9_LPC_PIRQH_ROUT                     0x6b
 156
 157 #define ICH9_LPC_PIRQ_ROUT_IRQEN                0x80
 158 #define ICH9_LPC_PIRQ_ROUT_MASK                 Q35_MASK(8, 3, 0)
 159 #define ICH9_LPC_PIRQ_ROUT_DEFAULT              0x80
 160
 161 #define ICH9_LPC_GEN_PMCON_1                    0xa0
 162 #define ICH9_LPC_GEN_PMCON_1_SMI_LOCK           (1 << 4)
 163 #define ICH9_LPC_GEN_PMCON_2                    0xa2
 164 #define ICH9_LPC_GEN_PMCON_3                    0xa4
 165 #define ICH9_LPC_GEN_PMCON_LOCK                 0xa6
 166
 167 #define ICH9_LPC_RCBA                           0xf0
 168 #define ICH9_LPC_RCBA_BA_MASK                   Q35_MASK(32, 31, 14)
 169 #define ICH9_LPC_RCBA_EN                        0x1
 170 #define ICH9_LPC_RCBA_DEFAULT                   0x0
 171
 172 #define ICH9_LPC_PIC_NUM_PINS                   16
 173 #define ICH9_LPC_IOAPIC_NUM_PINS                24
 174
 175 /* D31:F2 SATA Controller #1 */
 176 #define ICH9_SATA1_DEV                          31
 177 #define ICH9_SATA1_FUNC                         2
 178
 179 /* D30:F1 power management I/O registers
 180    offset from the address ICH9_LPC_PMBASE */
 181
 182 /* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
 183 #define ICH9_PMIO_SIZE                          128
 184 #define ICH9_PMIO_MASK                          (ICH9_PMIO_SIZE - 1)
 185
 186 #define ICH9_PMIO_PM1_STS                       0x00
 187 #define ICH9_PMIO_PM1_EN                        0x02
 188 #define ICH9_PMIO_PM1_CNT                       0x04
 189 #define ICH9_PMIO_PM1_TMR                       0x08
 190 #define ICH9_PMIO_GPE0_STS                      0x20
 191 #define ICH9_PMIO_GPE0_EN                       0x28
 192 #define ICH9_PMIO_GPE0_LEN                      16
 193 #define ICH9_PMIO_SMI_EN                        0x30
 194 #define ICH9_PMIO_SMI_EN_APMC_EN                (1 << 5)
 195 #define ICH9_PMIO_SMI_EN_TCO_EN                 (1 << 13)
 196 #define ICH9_PMIO_SMI_STS                       0x34
 197 #define ICH9_PMIO_TCO_RLD                       0x60
 198 #define ICH9_PMIO_TCO_LEN                       32
 199
 200 /* FADT ACPI_ENABLE/ACPI_DISABLE */
 201 #define ICH9_APM_ACPI_ENABLE                    0x2
 202 #define ICH9_APM_ACPI_DISABLE                   0x3
 203
 204
 205 /* D31:F3 SMBus controller */
 206 #define ICH9_A2_SMB_REVISION                    0x02
 207 #define ICH9_SMB_PI                             0x00
 208
 209 #define ICH9_SMB_SMBMBAR0                       0x10
 210 #define ICH9_SMB_SMBMBAR1                       0x14
 211 #define ICH9_SMB_SMBM_BAR                       0
 212 #define ICH9_SMB_SMBM_SIZE                      (1 << 8)
 213 #define ICH9_SMB_SMB_BASE                       0x20
 214 #define ICH9_SMB_SMB_BASE_BAR                   4
 215 #define ICH9_SMB_SMB_BASE_SIZE                  (1 << 5)
 216 #define ICH9_SMB_HOSTC                          0x40
 217 #define ICH9_SMB_HOSTC_SSRESET                  ((uint8_t)(1 << 3))
 218 #define ICH9_SMB_HOSTC_I2C_EN                   ((uint8_t)(1 << 2))
 219 #define ICH9_SMB_HOSTC_SMB_SMI_EN               ((uint8_t)(1 << 1))
 220 #define ICH9_SMB_HOSTC_HST_EN                   ((uint8_t)(1 << 0))
 221
 222 /* D31:F3 SMBus I/O and memory mapped I/O registers */
 223 #define ICH9_SMB_DEV                            31
 224 #define ICH9_SMB_FUNC                           3
 225
 226 #define ICH9_SMB_HST_STS                        0x00
 227 #define ICH9_SMB_HST_CNT                        0x02
 228 #define ICH9_SMB_HST_CMD                        0x03
 229 #define ICH9_SMB_XMIT_SLVA                      0x04
 230 #define ICH9_SMB_HST_D0                         0x05
 231 #define ICH9_SMB_HST_D1                         0x06
 232 #define ICH9_SMB_HOST_BLOCK_DB                  0x07
 233
 234 #endif /* HW_ICH9_H */