?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Add .dir-locals.el file to configure emacs coding style
[qemu/ar7.git] / target-i386 / kvm.c
blob80d1a7e01e544042ea8641f3a542381fc2f61448
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm_int.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "hw/i386/apic_internal.h"
34 #include "hw/i386/apic-msidef.h"
35 #include "exec/ioport.h"
36 #include "standard-headers/asm-x86/hyperv.h"
37 #include "hw/pci/pci.h"
38 #include "migration/migration.h"
39 #include "exec/memattrs.h"
40
41 //#define DEBUG_KVM
42
43 #ifdef DEBUG_KVM
44 #define DPRINTF(fmt, ...) \
45 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
46 #else
47 #define DPRINTF(fmt, ...) \
48 do { } while (0)
49 #endif
50
51 #define MSR_KVM_WALL_CLOCK 0x11
52 #define MSR_KVM_SYSTEM_TIME 0x12
53
54 #ifndef BUS_MCEERR_AR
55 #define BUS_MCEERR_AR 4
56 #endif
57 #ifndef BUS_MCEERR_AO
58 #define BUS_MCEERR_AO 5
59 #endif
60
61 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
62 KVM_CAP_INFO(SET_TSS_ADDR),
63 KVM_CAP_INFO(EXT_CPUID),
64 KVM_CAP_INFO(MP_STATE),
65 KVM_CAP_LAST_INFO
66 };
67
68 static bool has_msr_star;
69 static bool has_msr_hsave_pa;
70 static bool has_msr_tsc_aux;
71 static bool has_msr_tsc_adjust;
72 static bool has_msr_tsc_deadline;
73 static bool has_msr_feature_control;
74 static bool has_msr_async_pf_en;
75 static bool has_msr_pv_eoi_en;
76 static bool has_msr_misc_enable;
77 static bool has_msr_smbase;
78 static bool has_msr_bndcfgs;
79 static bool has_msr_kvm_steal_time;
80 static int lm_capable_kernel;
81 static bool has_msr_hv_hypercall;
82 static bool has_msr_hv_vapic;
83 static bool has_msr_hv_tsc;
84 static bool has_msr_hv_crash;
85 static bool has_msr_mtrr;
86 static bool has_msr_xss;
87
88 static bool has_msr_architectural_pmu;
89 static uint32_t num_architectural_pmu_counters;
90
91 bool kvm_has_smm(void)
92 {
93 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
94 }
95
96 bool kvm_allows_irq0_override(void)
97 {
98 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
99 }
100
101 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
102 {
103 struct kvm_cpuid2 *cpuid;
104 int r, size;
105
106 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
107 cpuid = g_malloc0(size);
108 cpuid->nent = max;
109 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
110 if (r == 0 && cpuid->nent >= max) {
111 r = -E2BIG;
112 }
113 if (r < 0) {
114 if (r == -E2BIG) {
115 g_free(cpuid);
116 return NULL;
117 } else {
118 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
119 strerror(-r));
120 exit(1);
121 }
122 }
123 return cpuid;
124 }
125
126 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
127 * for all entries.
128 */
129 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
130 {
131 struct kvm_cpuid2 *cpuid;
132 int max = 1;
133 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
134 max *= 2;
135 }
136 return cpuid;
137 }
138
139 static const struct kvm_para_features {
140 int cap;
141 int feature;
142 } para_features[] = {
143 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
144 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
145 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
146 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
147 };
148
149 static int get_para_features(KVMState *s)
150 {
151 int i, features = 0;
152
153 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
154 if (kvm_check_extension(s, para_features[i].cap)) {
155 features |= (1 << para_features[i].feature);
156 }
157 }
158
159 return features;
160 }
161
162
163 /* Returns the value for a specific register on the cpuid entry
164 */
165 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
166 {
167 uint32_t ret = 0;
168 switch (reg) {
169 case R_EAX:
170 ret = entry->eax;
171 break;
172 case R_EBX:
173 ret = entry->ebx;
174 break;
175 case R_ECX:
176 ret = entry->ecx;
177 break;
178 case R_EDX:
179 ret = entry->edx;
180 break;
181 }
182 return ret;
183 }
184
185 /* Find matching entry for function/index on kvm_cpuid2 struct
186 */
187 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
188 uint32_t function,
189 uint32_t index)
190 {
191 int i;
192 for (i = 0; i < cpuid->nent; ++i) {
193 if (cpuid->entries[i].function == function &&
194 cpuid->entries[i].index == index) {
195 return &cpuid->entries[i];
196 }
197 }
198 /* not found: */
199 return NULL;
200 }
201
202 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
203 uint32_t index, int reg)
204 {
205 struct kvm_cpuid2 *cpuid;
206 uint32_t ret = 0;
207 uint32_t cpuid_1_edx;
208 bool found = false;
209
210 cpuid = get_supported_cpuid(s);
211
212 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
213 if (entry) {
214 found = true;
215 ret = cpuid_entry_get_reg(entry, reg);
216 }
217
218 /* Fixups for the data returned by KVM, below */
219
220 if (function == 1 && reg == R_EDX) {
221 /* KVM before 2.6.30 misreports the following features */
222 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
223 } else if (function == 1 && reg == R_ECX) {
224 /* We can set the hypervisor flag, even if KVM does not return it on
225 * GET_SUPPORTED_CPUID
226 */
227 ret |= CPUID_EXT_HYPERVISOR;
228 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
229 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
230 * and the irqchip is in the kernel.
231 */
232 if (kvm_irqchip_in_kernel() &&
233 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
234 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
235 }
236
237 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
238 * without the in-kernel irqchip
239 */
240 if (!kvm_irqchip_in_kernel()) {
241 ret &= ~CPUID_EXT_X2APIC;
242 }
243 } else if (function == 6 && reg == R_EAX) {
244 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
245 } else if (function == 0x80000001 && reg == R_EDX) {
246 /* On Intel, kvm returns cpuid according to the Intel spec,
247 * so add missing bits according to the AMD spec:
248 */
249 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
250 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
251 }
252
253 g_free(cpuid);
254
255 /* fallback for older kernels */
256 if ((function == KVM_CPUID_FEATURES) && !found) {
257 ret = get_para_features(s);
258 }
259
260 return ret;
261 }
262
263 typedef struct HWPoisonPage {
264 ram_addr_t ram_addr;
265 QLIST_ENTRY(HWPoisonPage) list;
266 } HWPoisonPage;
267
268 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
269 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
270
271 static void kvm_unpoison_all(void *param)
272 {
273 HWPoisonPage *page, *next_page;
274
275 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
276 QLIST_REMOVE(page, list);
277 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
278 g_free(page);
279 }
280 }
281
282 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
283 {
284 HWPoisonPage *page;
285
286 QLIST_FOREACH(page, &hwpoison_page_list, list) {
287 if (page->ram_addr == ram_addr) {
288 return;
289 }
290 }
291 page = g_new(HWPoisonPage, 1);
292 page->ram_addr = ram_addr;
293 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
294 }
295
296 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
297 int *max_banks)
298 {
299 int r;
300
301 r = kvm_check_extension(s, KVM_CAP_MCE);
302 if (r > 0) {
303 *max_banks = r;
304 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
305 }
306 return -ENOSYS;
307 }
308
309 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
310 {
311 CPUX86State *env = &cpu->env;
312 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
313 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
314 uint64_t mcg_status = MCG_STATUS_MCIP;
315
316 if (code == BUS_MCEERR_AR) {
317 status |= MCI_STATUS_AR | 0x134;
318 mcg_status |= MCG_STATUS_EIPV;
319 } else {
320 status |= 0xc0;
321 mcg_status |= MCG_STATUS_RIPV;
322 }
323 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
324 (MCM_ADDR_PHYS << 6) | 0xc,
325 cpu_x86_support_mca_broadcast(env) ?
326 MCE_INJECT_BROADCAST : 0);
327 }
328
329 static void hardware_memory_error(void)
330 {
331 fprintf(stderr, "Hardware memory error!\n");
332 exit(1);
333 }
334
335 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
336 {
337 X86CPU *cpu = X86_CPU(c);
338 CPUX86State *env = &cpu->env;
339 ram_addr_t ram_addr;
340 hwaddr paddr;
341
342 if ((env->mcg_cap & MCG_SER_P) && addr
343 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
344 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
345 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
346 fprintf(stderr, "Hardware memory error for memory used by "
347 "QEMU itself instead of guest system!\n");
348 /* Hope we are lucky for AO MCE */
349 if (code == BUS_MCEERR_AO) {
350 return 0;
351 } else {
352 hardware_memory_error();
353 }
354 }
355 kvm_hwpoison_page_add(ram_addr);
356 kvm_mce_inject(cpu, paddr, code);
357 } else {
358 if (code == BUS_MCEERR_AO) {
359 return 0;
360 } else if (code == BUS_MCEERR_AR) {
361 hardware_memory_error();
362 } else {
363 return 1;
364 }
365 }
366 return 0;
367 }
368
369 int kvm_arch_on_sigbus(int code, void *addr)
370 {
371 X86CPU *cpu = X86_CPU(first_cpu);
372
373 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
374 ram_addr_t ram_addr;
375 hwaddr paddr;
376
377 /* Hope we are lucky for AO MCE */
378 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
379 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
380 addr, &paddr)) {
381 fprintf(stderr, "Hardware memory error for memory used by "
382 "QEMU itself instead of guest system!: %p\n", addr);
383 return 0;
384 }
385 kvm_hwpoison_page_add(ram_addr);
386 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
387 } else {
388 if (code == BUS_MCEERR_AO) {
389 return 0;
390 } else if (code == BUS_MCEERR_AR) {
391 hardware_memory_error();
392 } else {
393 return 1;
394 }
395 }
396 return 0;
397 }
398
399 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
400 {
401 CPUX86State *env = &cpu->env;
402
403 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
404 unsigned int bank, bank_num = env->mcg_cap & 0xff;
405 struct kvm_x86_mce mce;
406
407 env->exception_injected = -1;
408
409 /*
410 * There must be at least one bank in use if an MCE is pending.
411 * Find it and use its values for the event injection.
412 */
413 for (bank = 0; bank < bank_num; bank++) {
414 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
415 break;
416 }
417 }
418 assert(bank < bank_num);
419
420 mce.bank = bank;
421 mce.status = env->mce_banks[bank * 4 + 1];
422 mce.mcg_status = env->mcg_status;
423 mce.addr = env->mce_banks[bank * 4 + 2];
424 mce.misc = env->mce_banks[bank * 4 + 3];
425
426 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
427 }
428 return 0;
429 }
430
431 static void cpu_update_state(void *opaque, int running, RunState state)
432 {
433 CPUX86State *env = opaque;
434
435 if (running) {
436 env->tsc_valid = false;
437 }
438 }
439
440 unsigned long kvm_arch_vcpu_id(CPUState *cs)
441 {
442 X86CPU *cpu = X86_CPU(cs);
443 return cpu->apic_id;
444 }
445
446 #ifndef KVM_CPUID_SIGNATURE_NEXT
447 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
448 #endif
449
450 static bool hyperv_hypercall_available(X86CPU *cpu)
451 {
452 return cpu->hyperv_vapic ||
453 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
454 }
455
456 static bool hyperv_enabled(X86CPU *cpu)
457 {
458 CPUState *cs = CPU(cpu);
459 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
460 (hyperv_hypercall_available(cpu) ||
461 cpu->hyperv_time ||
462 cpu->hyperv_relaxed_timing ||
463 cpu->hyperv_crash);
464 }
465
466 static Error *invtsc_mig_blocker;
467
468 #define KVM_MAX_CPUID_ENTRIES 100
469
470 int kvm_arch_init_vcpu(CPUState *cs)
471 {
472 struct {
473 struct kvm_cpuid2 cpuid;
474 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
475 } QEMU_PACKED cpuid_data;
476 X86CPU *cpu = X86_CPU(cs);
477 CPUX86State *env = &cpu->env;
478 uint32_t limit, i, j, cpuid_i;
479 uint32_t unused;
480 struct kvm_cpuid_entry2 *c;
481 uint32_t signature[3];
482 int kvm_base = KVM_CPUID_SIGNATURE;
483 int r;
484
485 memset(&cpuid_data, 0, sizeof(cpuid_data));
486
487 cpuid_i = 0;
488
489 /* Paravirtualization CPUIDs */
490 if (hyperv_enabled(cpu)) {
491 c = &cpuid_data.entries[cpuid_i++];
492 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
493 memcpy(signature, "Microsoft Hv", 12);
494 c->eax = HYPERV_CPUID_MIN;
495 c->ebx = signature[0];
496 c->ecx = signature[1];
497 c->edx = signature[2];
498
499 c = &cpuid_data.entries[cpuid_i++];
500 c->function = HYPERV_CPUID_INTERFACE;
501 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
502 c->eax = signature[0];
503 c->ebx = 0;
504 c->ecx = 0;
505 c->edx = 0;
506
507 c = &cpuid_data.entries[cpuid_i++];
508 c->function = HYPERV_CPUID_VERSION;
509 c->eax = 0x00001bbc;
510 c->ebx = 0x00060001;
511
512 c = &cpuid_data.entries[cpuid_i++];
513 c->function = HYPERV_CPUID_FEATURES;
514 if (cpu->hyperv_relaxed_timing) {
515 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
516 }
517 if (cpu->hyperv_vapic) {
518 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
519 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
520 has_msr_hv_vapic = true;
521 }
522 if (cpu->hyperv_time &&
523 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
524 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
525 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
526 c->eax |= 0x200;
527 has_msr_hv_tsc = true;
528 }
529 if (cpu->hyperv_crash && has_msr_hv_crash) {
530 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
531 }
532
533 c = &cpuid_data.entries[cpuid_i++];
534 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
535 if (cpu->hyperv_relaxed_timing) {
536 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
537 }
538 if (has_msr_hv_vapic) {
539 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
540 }
541 c->ebx = cpu->hyperv_spinlock_attempts;
542
543 c = &cpuid_data.entries[cpuid_i++];
544 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
545 c->eax = 0x40;
546 c->ebx = 0x40;
547
548 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
549 has_msr_hv_hypercall = true;
550 }
551
552 if (cpu->expose_kvm) {
553 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
554 c = &cpuid_data.entries[cpuid_i++];
555 c->function = KVM_CPUID_SIGNATURE | kvm_base;
556 c->eax = KVM_CPUID_FEATURES | kvm_base;
557 c->ebx = signature[0];
558 c->ecx = signature[1];
559 c->edx = signature[2];
560
561 c = &cpuid_data.entries[cpuid_i++];
562 c->function = KVM_CPUID_FEATURES | kvm_base;
563 c->eax = env->features[FEAT_KVM];
564
565 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
566
567 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
568
569 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
570 }
571
572 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
573
574 for (i = 0; i <= limit; i++) {
575 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
576 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
577 abort();
578 }
579 c = &cpuid_data.entries[cpuid_i++];
580
581 switch (i) {
582 case 2: {
583 /* Keep reading function 2 till all the input is received */
584 int times;
585
586 c->function = i;
587 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
588 KVM_CPUID_FLAG_STATE_READ_NEXT;
589 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
590 times = c->eax & 0xff;
591
592 for (j = 1; j < times; ++j) {
593 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
594 fprintf(stderr, "cpuid_data is full, no space for "
595 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
596 abort();
597 }
598 c = &cpuid_data.entries[cpuid_i++];
599 c->function = i;
600 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
601 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
602 }
603 break;
604 }
605 case 4:
606 case 0xb:
607 case 0xd:
608 for (j = 0; ; j++) {
609 if (i == 0xd && j == 64) {
610 break;
611 }
612 c->function = i;
613 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
614 c->index = j;
615 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
616
617 if (i == 4 && c->eax == 0) {
618 break;
619 }
620 if (i == 0xb && !(c->ecx & 0xff00)) {
621 break;
622 }
623 if (i == 0xd && c->eax == 0) {
624 continue;
625 }
626 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
627 fprintf(stderr, "cpuid_data is full, no space for "
628 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
629 abort();
630 }
631 c = &cpuid_data.entries[cpuid_i++];
632 }
633 break;
634 default:
635 c->function = i;
636 c->flags = 0;
637 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
638 break;
639 }
640 }
641
642 if (limit >= 0x0a) {
643 uint32_t ver;
644
645 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
646 if ((ver & 0xff) > 0) {
647 has_msr_architectural_pmu = true;
648 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
649
650 /* Shouldn't be more than 32, since that's the number of bits
651 * available in EBX to tell us _which_ counters are available.
652 * Play it safe.
653 */
654 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
655 num_architectural_pmu_counters = MAX_GP_COUNTERS;
656 }
657 }
658 }
659
660 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
661
662 for (i = 0x80000000; i <= limit; i++) {
663 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
664 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
665 abort();
666 }
667 c = &cpuid_data.entries[cpuid_i++];
668
669 c->function = i;
670 c->flags = 0;
671 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
672 }
673
674 /* Call Centaur's CPUID instructions they are supported. */
675 if (env->cpuid_xlevel2 > 0) {
676 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
677
678 for (i = 0xC0000000; i <= limit; i++) {
679 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
680 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
681 abort();
682 }
683 c = &cpuid_data.entries[cpuid_i++];
684
685 c->function = i;
686 c->flags = 0;
687 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
688 }
689 }
690
691 cpuid_data.cpuid.nent = cpuid_i;
692
693 if (((env->cpuid_version >> 8)&0xF) >= 6
694 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
695 (CPUID_MCE | CPUID_MCA)
696 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
697 uint64_t mcg_cap;
698 int banks;
699 int ret;
700
701 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
702 if (ret < 0) {
703 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
704 return ret;
705 }
706
707 if (banks > MCE_BANKS_DEF) {
708 banks = MCE_BANKS_DEF;
709 }
710 mcg_cap &= MCE_CAP_DEF;
711 mcg_cap |= banks;
712 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
713 if (ret < 0) {
714 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
715 return ret;
716 }
717
718 env->mcg_cap = mcg_cap;
719 }
720
721 qemu_add_vm_change_state_handler(cpu_update_state, env);
722
723 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
724 if (c) {
725 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
726 !!(c->ecx & CPUID_EXT_SMX);
727 }
728
729 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
730 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
731 /* for migration */
732 error_setg(&invtsc_mig_blocker,
733 "State blocked by non-migratable CPU device"
734 " (invtsc flag)");
735 migrate_add_blocker(invtsc_mig_blocker);
736 /* for savevm */
737 vmstate_x86_cpu.unmigratable = 1;
738 }
739
740 cpuid_data.cpuid.padding = 0;
741 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
742 if (r) {
743 return r;
744 }
745
746 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
747 if (r && env->tsc_khz) {
748 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
749 if (r < 0) {
750 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
751 return r;
752 }
753 }
754
755 if (kvm_has_xsave()) {
756 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
757 }
758
759 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
760 has_msr_mtrr = true;
761 }
762
763 return 0;
764 }
765
766 void kvm_arch_reset_vcpu(X86CPU *cpu)
767 {
768 CPUX86State *env = &cpu->env;
769
770 env->exception_injected = -1;
771 env->interrupt_injected = -1;
772 env->xcr0 = 1;
773 if (kvm_irqchip_in_kernel()) {
774 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
775 KVM_MP_STATE_UNINITIALIZED;
776 } else {
777 env->mp_state = KVM_MP_STATE_RUNNABLE;
778 }
779 }
780
781 void kvm_arch_do_init_vcpu(X86CPU *cpu)
782 {
783 CPUX86State *env = &cpu->env;
784
785 /* APs get directly into wait-for-SIPI state. */
786 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
787 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
788 }
789 }
790
791 static int kvm_get_supported_msrs(KVMState *s)
792 {
793 static int kvm_supported_msrs;
794 int ret = 0;
795
796 /* first time */
797 if (kvm_supported_msrs == 0) {
798 struct kvm_msr_list msr_list, *kvm_msr_list;
799
800 kvm_supported_msrs = -1;
801
802 /* Obtain MSR list from KVM. These are the MSRs that we must
803 * save/restore */
804 msr_list.nmsrs = 0;
805 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
806 if (ret < 0 && ret != -E2BIG) {
807 return ret;
808 }
809 /* Old kernel modules had a bug and could write beyond the provided
810 memory. Allocate at least a safe amount of 1K. */
811 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
812 msr_list.nmsrs *
813 sizeof(msr_list.indices[0])));
814
815 kvm_msr_list->nmsrs = msr_list.nmsrs;
816 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
817 if (ret >= 0) {
818 int i;
819
820 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
821 if (kvm_msr_list->indices[i] == MSR_STAR) {
822 has_msr_star = true;
823 continue;
824 }
825 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
826 has_msr_hsave_pa = true;
827 continue;
828 }
829 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
830 has_msr_tsc_aux = true;
831 continue;
832 }
833 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
834 has_msr_tsc_adjust = true;
835 continue;
836 }
837 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
838 has_msr_tsc_deadline = true;
839 continue;
840 }
841 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
842 has_msr_smbase = true;
843 continue;
844 }
845 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
846 has_msr_misc_enable = true;
847 continue;
848 }
849 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
850 has_msr_bndcfgs = true;
851 continue;
852 }
853 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
854 has_msr_xss = true;
855 continue;
856 }
857 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
858 has_msr_hv_crash = true;
859 continue;
860 }
861 }
862 }
863
864 g_free(kvm_msr_list);
865 }
866
867 return ret;
868 }
869
870 static Notifier smram_machine_done;
871 static KVMMemoryListener smram_listener;
872 static AddressSpace smram_address_space;
873 static MemoryRegion smram_as_root;
874 static MemoryRegion smram_as_mem;
875
876 static void register_smram_listener(Notifier *n, void *unused)
877 {
878 MemoryRegion *smram =
879 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
880
881 /* Outer container... */
882 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
883 memory_region_set_enabled(&smram_as_root, true);
884
885 /* ... with two regions inside: normal system memory with low
886 * priority, and...
887 */
888 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
889 get_system_memory(), 0, ~0ull);
890 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
891 memory_region_set_enabled(&smram_as_mem, true);
892
893 if (smram) {
894 /* ... SMRAM with higher priority */
895 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
896 memory_region_set_enabled(smram, true);
897 }
898
899 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
900 kvm_memory_listener_register(kvm_state, &smram_listener,
901 &smram_address_space, 1);
902 }
903
904 int kvm_arch_init(MachineState *ms, KVMState *s)
905 {
906 uint64_t identity_base = 0xfffbc000;
907 uint64_t shadow_mem;
908 int ret;
909 struct utsname utsname;
910
911 ret = kvm_get_supported_msrs(s);
912 if (ret < 0) {
913 return ret;
914 }
915
916 uname(&utsname);
917 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
918
919 /*
920 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
921 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
922 * Since these must be part of guest physical memory, we need to allocate
923 * them, both by setting their start addresses in the kernel and by
924 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
925 *
926 * Older KVM versions may not support setting the identity map base. In
927 * that case we need to stick with the default, i.e. a 256K maximum BIOS
928 * size.
929 */
930 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
931 /* Allows up to 16M BIOSes. */
932 identity_base = 0xfeffc000;
933
934 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
935 if (ret < 0) {
936 return ret;
937 }
938 }
939
940 /* Set TSS base one page after EPT identity map. */
941 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
942 if (ret < 0) {
943 return ret;
944 }
945
946 /* Tell fw_cfg to notify the BIOS to reserve the range. */
947 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
948 if (ret < 0) {
949 fprintf(stderr, "e820_add_entry() table is full\n");
950 return ret;
951 }
952 qemu_register_reset(kvm_unpoison_all, NULL);
953
954 shadow_mem = machine_kvm_shadow_mem(ms);
955 if (shadow_mem != -1) {
956 shadow_mem /= 4096;
957 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
958 if (ret < 0) {
959 return ret;
960 }
961 }
962
963 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
964 smram_machine_done.notify = register_smram_listener;
965 qemu_add_machine_init_done_notifier(&smram_machine_done);
966 }
967 return 0;
968 }
969
970 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
971 {
972 lhs->selector = rhs->selector;
973 lhs->base = rhs->base;
974 lhs->limit = rhs->limit;
975 lhs->type = 3;
976 lhs->present = 1;
977 lhs->dpl = 3;
978 lhs->db = 0;
979 lhs->s = 1;
980 lhs->l = 0;
981 lhs->g = 0;
982 lhs->avl = 0;
983 lhs->unusable = 0;
984 }
985
986 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
987 {
988 unsigned flags = rhs->flags;
989 lhs->selector = rhs->selector;
990 lhs->base = rhs->base;
991 lhs->limit = rhs->limit;
992 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
993 lhs->present = (flags & DESC_P_MASK) != 0;
994 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
995 lhs->db = (flags >> DESC_B_SHIFT) & 1;
996 lhs->s = (flags & DESC_S_MASK) != 0;
997 lhs->l = (flags >> DESC_L_SHIFT) & 1;
998 lhs->g = (flags & DESC_G_MASK) != 0;
999 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1000 lhs->unusable = 0;
1001 lhs->padding = 0;
1002 }
1003
1004 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1005 {
1006 lhs->selector = rhs->selector;
1007 lhs->base = rhs->base;
1008 lhs->limit = rhs->limit;
1009 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1010 (rhs->present * DESC_P_MASK) |
1011 (rhs->dpl << DESC_DPL_SHIFT) |
1012 (rhs->db << DESC_B_SHIFT) |
1013 (rhs->s * DESC_S_MASK) |
1014 (rhs->l << DESC_L_SHIFT) |
1015 (rhs->g * DESC_G_MASK) |
1016 (rhs->avl * DESC_AVL_MASK);
1017 }
1018
1019 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1020 {
1021 if (set) {
1022 *kvm_reg = *qemu_reg;
1023 } else {
1024 *qemu_reg = *kvm_reg;
1025 }
1026 }
1027
1028 static int kvm_getput_regs(X86CPU *cpu, int set)
1029 {
1030 CPUX86State *env = &cpu->env;
1031 struct kvm_regs regs;
1032 int ret = 0;
1033
1034 if (!set) {
1035 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1036 if (ret < 0) {
1037 return ret;
1038 }
1039 }
1040
1041 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1042 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1043 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1044 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1045 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1046 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1047 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1048 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1049 #ifdef TARGET_X86_64
1050 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1051 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1052 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1053 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1054 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1055 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1056 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1057 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1058 #endif
1059
1060 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1061 kvm_getput_reg(&regs.rip, &env->eip, set);
1062
1063 if (set) {
1064 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1065 }
1066
1067 return ret;
1068 }
1069
1070 static int kvm_put_fpu(X86CPU *cpu)
1071 {
1072 CPUX86State *env = &cpu->env;
1073 struct kvm_fpu fpu;
1074 int i;
1075
1076 memset(&fpu, 0, sizeof fpu);
1077 fpu.fsw = env->fpus & ~(7 << 11);
1078 fpu.fsw |= (env->fpstt & 7) << 11;
1079 fpu.fcw = env->fpuc;
1080 fpu.last_opcode = env->fpop;
1081 fpu.last_ip = env->fpip;
1082 fpu.last_dp = env->fpdp;
1083 for (i = 0; i < 8; ++i) {
1084 fpu.ftwx |= (!env->fptags[i]) << i;
1085 }
1086 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1087 for (i = 0; i < CPU_NB_REGS; i++) {
1088 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0));
1089 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1));
1090 }
1091 fpu.mxcsr = env->mxcsr;
1092
1093 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1094 }
1095
1096 #define XSAVE_FCW_FSW 0
1097 #define XSAVE_FTW_FOP 1
1098 #define XSAVE_CWD_RIP 2
1099 #define XSAVE_CWD_RDP 4
1100 #define XSAVE_MXCSR 6
1101 #define XSAVE_ST_SPACE 8
1102 #define XSAVE_XMM_SPACE 40
1103 #define XSAVE_XSTATE_BV 128
1104 #define XSAVE_YMMH_SPACE 144
1105 #define XSAVE_BNDREGS 240
1106 #define XSAVE_BNDCSR 256
1107 #define XSAVE_OPMASK 272
1108 #define XSAVE_ZMM_Hi256 288
1109 #define XSAVE_Hi16_ZMM 416
1110
1111 static int kvm_put_xsave(X86CPU *cpu)
1112 {
1113 CPUX86State *env = &cpu->env;
1114 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1115 uint16_t cwd, swd, twd;
1116 uint8_t *xmm, *ymmh, *zmmh;
1117 int i, r;
1118
1119 if (!kvm_has_xsave()) {
1120 return kvm_put_fpu(cpu);
1121 }
1122
1123 memset(xsave, 0, sizeof(struct kvm_xsave));
1124 twd = 0;
1125 swd = env->fpus & ~(7 << 11);
1126 swd |= (env->fpstt & 7) << 11;
1127 cwd = env->fpuc;
1128 for (i = 0; i < 8; ++i) {
1129 twd |= (!env->fptags[i]) << i;
1130 }
1131 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1132 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1133 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1134 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1135 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1136 sizeof env->fpregs);
1137 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1138 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1139 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1140 sizeof env->bnd_regs);
1141 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1142 sizeof(env->bndcs_regs));
1143 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1144 sizeof env->opmask_regs);
1145
1146 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1147 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1148 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1149 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1150 stq_p(xmm, env->xmm_regs[i].XMM_Q(0));
1151 stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1));
1152 stq_p(ymmh, env->xmm_regs[i].XMM_Q(2));
1153 stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3));
1154 stq_p(zmmh, env->xmm_regs[i].XMM_Q(4));
1155 stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5));
1156 stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6));
1157 stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7));
1158 }
1159
1160 #ifdef TARGET_X86_64
1161 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1162 16 * sizeof env->xmm_regs[16]);
1163 #endif
1164 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1165 return r;
1166 }
1167
1168 static int kvm_put_xcrs(X86CPU *cpu)
1169 {
1170 CPUX86State *env = &cpu->env;
1171 struct kvm_xcrs xcrs = {};
1172
1173 if (!kvm_has_xcrs()) {
1174 return 0;
1175 }
1176
1177 xcrs.nr_xcrs = 1;
1178 xcrs.flags = 0;
1179 xcrs.xcrs[0].xcr = 0;
1180 xcrs.xcrs[0].value = env->xcr0;
1181 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1182 }
1183
1184 static int kvm_put_sregs(X86CPU *cpu)
1185 {
1186 CPUX86State *env = &cpu->env;
1187 struct kvm_sregs sregs;
1188
1189 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1190 if (env->interrupt_injected >= 0) {
1191 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1192 (uint64_t)1 << (env->interrupt_injected % 64);
1193 }
1194
1195 if ((env->eflags & VM_MASK)) {
1196 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1197 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1198 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1199 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1200 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1201 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1202 } else {
1203 set_seg(&sregs.cs, &env->segs[R_CS]);
1204 set_seg(&sregs.ds, &env->segs[R_DS]);
1205 set_seg(&sregs.es, &env->segs[R_ES]);
1206 set_seg(&sregs.fs, &env->segs[R_FS]);
1207 set_seg(&sregs.gs, &env->segs[R_GS]);
1208 set_seg(&sregs.ss, &env->segs[R_SS]);
1209 }
1210
1211 set_seg(&sregs.tr, &env->tr);
1212 set_seg(&sregs.ldt, &env->ldt);
1213
1214 sregs.idt.limit = env->idt.limit;
1215 sregs.idt.base = env->idt.base;
1216 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1217 sregs.gdt.limit = env->gdt.limit;
1218 sregs.gdt.base = env->gdt.base;
1219 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1220
1221 sregs.cr0 = env->cr[0];
1222 sregs.cr2 = env->cr[2];
1223 sregs.cr3 = env->cr[3];
1224 sregs.cr4 = env->cr[4];
1225
1226 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1227 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1228
1229 sregs.efer = env->efer;
1230
1231 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1232 }
1233
1234 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1235 uint32_t index, uint64_t value)
1236 {
1237 entry->index = index;
1238 entry->reserved = 0;
1239 entry->data = value;
1240 }
1241
1242 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1243 {
1244 CPUX86State *env = &cpu->env;
1245 struct {
1246 struct kvm_msrs info;
1247 struct kvm_msr_entry entries[1];
1248 } msr_data;
1249 struct kvm_msr_entry *msrs = msr_data.entries;
1250
1251 if (!has_msr_tsc_deadline) {
1252 return 0;
1253 }
1254
1255 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1256
1257 msr_data.info = (struct kvm_msrs) {
1258 .nmsrs = 1,
1259 };
1260
1261 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1262 }
1263
1264 /*
1265 * Provide a separate write service for the feature control MSR in order to
1266 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1267 * before writing any other state because forcibly leaving nested mode
1268 * invalidates the VCPU state.
1269 */
1270 static int kvm_put_msr_feature_control(X86CPU *cpu)
1271 {
1272 struct {
1273 struct kvm_msrs info;
1274 struct kvm_msr_entry entry;
1275 } msr_data;
1276
1277 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1278 cpu->env.msr_ia32_feature_control);
1279
1280 msr_data.info = (struct kvm_msrs) {
1281 .nmsrs = 1,
1282 };
1283
1284 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1285 }
1286
1287 static int kvm_put_msrs(X86CPU *cpu, int level)
1288 {
1289 CPUX86State *env = &cpu->env;
1290 struct {
1291 struct kvm_msrs info;
1292 struct kvm_msr_entry entries[150];
1293 } msr_data;
1294 struct kvm_msr_entry *msrs = msr_data.entries;
1295 int n = 0, i;
1296
1297 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1298 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1299 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1300 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1301 if (has_msr_star) {
1302 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1303 }
1304 if (has_msr_hsave_pa) {
1305 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1306 }
1307 if (has_msr_tsc_aux) {
1308 kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux);
1309 }
1310 if (has_msr_tsc_adjust) {
1311 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1312 }
1313 if (has_msr_misc_enable) {
1314 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1315 env->msr_ia32_misc_enable);
1316 }
1317 if (has_msr_smbase) {
1318 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1319 }
1320 if (has_msr_bndcfgs) {
1321 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1322 }
1323 if (has_msr_xss) {
1324 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1325 }
1326 #ifdef TARGET_X86_64
1327 if (lm_capable_kernel) {
1328 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1329 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1330 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1331 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1332 }
1333 #endif
1334 /*
1335 * The following MSRs have side effects on the guest or are too heavy
1336 * for normal writeback. Limit them to reset or full state updates.
1337 */
1338 if (level >= KVM_PUT_RESET_STATE) {
1339 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1340 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1341 env->system_time_msr);
1342 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1343 if (has_msr_async_pf_en) {
1344 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1345 env->async_pf_en_msr);
1346 }
1347 if (has_msr_pv_eoi_en) {
1348 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1349 env->pv_eoi_en_msr);
1350 }
1351 if (has_msr_kvm_steal_time) {
1352 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1353 env->steal_time_msr);
1354 }
1355 if (has_msr_architectural_pmu) {
1356 /* Stop the counter. */
1357 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1358 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1359
1360 /* Set the counter values. */
1361 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1362 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1363 env->msr_fixed_counters[i]);
1364 }
1365 for (i = 0; i < num_architectural_pmu_counters; i++) {
1366 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1367 env->msr_gp_counters[i]);
1368 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1369 env->msr_gp_evtsel[i]);
1370 }
1371 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1372 env->msr_global_status);
1373 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1374 env->msr_global_ovf_ctrl);
1375
1376 /* Now start the PMU. */
1377 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1378 env->msr_fixed_ctr_ctrl);
1379 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1380 env->msr_global_ctrl);
1381 }
1382 if (has_msr_hv_hypercall) {
1383 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1384 env->msr_hv_guest_os_id);
1385 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1386 env->msr_hv_hypercall);
1387 }
1388 if (has_msr_hv_vapic) {
1389 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1390 env->msr_hv_vapic);
1391 }
1392 if (has_msr_hv_tsc) {
1393 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1394 env->msr_hv_tsc);
1395 }
1396 if (has_msr_hv_crash) {
1397 int j;
1398
1399 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1400 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j,
1401 env->msr_hv_crash_params[j]);
1402
1403 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL,
1404 HV_X64_MSR_CRASH_CTL_NOTIFY);
1405 }
1406 if (has_msr_mtrr) {
1407 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1408 kvm_msr_entry_set(&msrs[n++],
1409 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1410 kvm_msr_entry_set(&msrs[n++],
1411 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1412 kvm_msr_entry_set(&msrs[n++],
1413 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1414 kvm_msr_entry_set(&msrs[n++],
1415 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1416 kvm_msr_entry_set(&msrs[n++],
1417 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1418 kvm_msr_entry_set(&msrs[n++],
1419 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1420 kvm_msr_entry_set(&msrs[n++],
1421 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1422 kvm_msr_entry_set(&msrs[n++],
1423 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1424 kvm_msr_entry_set(&msrs[n++],
1425 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1426 kvm_msr_entry_set(&msrs[n++],
1427 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1428 kvm_msr_entry_set(&msrs[n++],
1429 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1430 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1431 kvm_msr_entry_set(&msrs[n++],
1432 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1433 kvm_msr_entry_set(&msrs[n++],
1434 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1435 }
1436 }
1437
1438 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1439 * kvm_put_msr_feature_control. */
1440 }
1441 if (env->mcg_cap) {
1442 int i;
1443
1444 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1445 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1446 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1447 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1448 }
1449 }
1450
1451 msr_data.info = (struct kvm_msrs) {
1452 .nmsrs = n,
1453 };
1454
1455 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1456
1457 }
1458
1459
1460 static int kvm_get_fpu(X86CPU *cpu)
1461 {
1462 CPUX86State *env = &cpu->env;
1463 struct kvm_fpu fpu;
1464 int i, ret;
1465
1466 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1467 if (ret < 0) {
1468 return ret;
1469 }
1470
1471 env->fpstt = (fpu.fsw >> 11) & 7;
1472 env->fpus = fpu.fsw;
1473 env->fpuc = fpu.fcw;
1474 env->fpop = fpu.last_opcode;
1475 env->fpip = fpu.last_ip;
1476 env->fpdp = fpu.last_dp;
1477 for (i = 0; i < 8; ++i) {
1478 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1479 }
1480 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1481 for (i = 0; i < CPU_NB_REGS; i++) {
1482 env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1483 env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1484 }
1485 env->mxcsr = fpu.mxcsr;
1486
1487 return 0;
1488 }
1489
1490 static int kvm_get_xsave(X86CPU *cpu)
1491 {
1492 CPUX86State *env = &cpu->env;
1493 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1494 int ret, i;
1495 const uint8_t *xmm, *ymmh, *zmmh;
1496 uint16_t cwd, swd, twd;
1497
1498 if (!kvm_has_xsave()) {
1499 return kvm_get_fpu(cpu);
1500 }
1501
1502 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1503 if (ret < 0) {
1504 return ret;
1505 }
1506
1507 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1508 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1509 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1510 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1511 env->fpstt = (swd >> 11) & 7;
1512 env->fpus = swd;
1513 env->fpuc = cwd;
1514 for (i = 0; i < 8; ++i) {
1515 env->fptags[i] = !((twd >> i) & 1);
1516 }
1517 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1518 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1519 env->mxcsr = xsave->region[XSAVE_MXCSR];
1520 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1521 sizeof env->fpregs);
1522 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1523 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1524 sizeof env->bnd_regs);
1525 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1526 sizeof(env->bndcs_regs));
1527 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1528 sizeof env->opmask_regs);
1529
1530 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1531 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1532 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1533 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1534 env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm);
1535 env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8);
1536 env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh);
1537 env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8);
1538 env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh);
1539 env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8);
1540 env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16);
1541 env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24);
1542 }
1543
1544 #ifdef TARGET_X86_64
1545 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1546 16 * sizeof env->xmm_regs[16]);
1547 #endif
1548 return 0;
1549 }
1550
1551 static int kvm_get_xcrs(X86CPU *cpu)
1552 {
1553 CPUX86State *env = &cpu->env;
1554 int i, ret;
1555 struct kvm_xcrs xcrs;
1556
1557 if (!kvm_has_xcrs()) {
1558 return 0;
1559 }
1560
1561 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1562 if (ret < 0) {
1563 return ret;
1564 }
1565
1566 for (i = 0; i < xcrs.nr_xcrs; i++) {
1567 /* Only support xcr0 now */
1568 if (xcrs.xcrs[i].xcr == 0) {
1569 env->xcr0 = xcrs.xcrs[i].value;
1570 break;
1571 }
1572 }
1573 return 0;
1574 }
1575
1576 static int kvm_get_sregs(X86CPU *cpu)
1577 {
1578 CPUX86State *env = &cpu->env;
1579 struct kvm_sregs sregs;
1580 uint32_t hflags;
1581 int bit, i, ret;
1582
1583 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1584 if (ret < 0) {
1585 return ret;
1586 }
1587
1588 /* There can only be one pending IRQ set in the bitmap at a time, so try
1589 to find it and save its number instead (-1 for none). */
1590 env->interrupt_injected = -1;
1591 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1592 if (sregs.interrupt_bitmap[i]) {
1593 bit = ctz64(sregs.interrupt_bitmap[i]);
1594 env->interrupt_injected = i * 64 + bit;
1595 break;
1596 }
1597 }
1598
1599 get_seg(&env->segs[R_CS], &sregs.cs);
1600 get_seg(&env->segs[R_DS], &sregs.ds);
1601 get_seg(&env->segs[R_ES], &sregs.es);
1602 get_seg(&env->segs[R_FS], &sregs.fs);
1603 get_seg(&env->segs[R_GS], &sregs.gs);
1604 get_seg(&env->segs[R_SS], &sregs.ss);
1605
1606 get_seg(&env->tr, &sregs.tr);
1607 get_seg(&env->ldt, &sregs.ldt);
1608
1609 env->idt.limit = sregs.idt.limit;
1610 env->idt.base = sregs.idt.base;
1611 env->gdt.limit = sregs.gdt.limit;
1612 env->gdt.base = sregs.gdt.base;
1613
1614 env->cr[0] = sregs.cr0;
1615 env->cr[2] = sregs.cr2;
1616 env->cr[3] = sregs.cr3;
1617 env->cr[4] = sregs.cr4;
1618
1619 env->efer = sregs.efer;
1620
1621 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1622
1623 #define HFLAG_COPY_MASK \
1624 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1625 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1626 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1627 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1628
1629 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1630 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1631 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1632 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1633 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1634 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1635 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1636
1637 if (env->efer & MSR_EFER_LMA) {
1638 hflags |= HF_LMA_MASK;
1639 }
1640
1641 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1642 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1643 } else {
1644 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1645 (DESC_B_SHIFT - HF_CS32_SHIFT);
1646 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1647 (DESC_B_SHIFT - HF_SS32_SHIFT);
1648 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1649 !(hflags & HF_CS32_MASK)) {
1650 hflags |= HF_ADDSEG_MASK;
1651 } else {
1652 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1653 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1654 }
1655 }
1656 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1657
1658 return 0;
1659 }
1660
1661 static int kvm_get_msrs(X86CPU *cpu)
1662 {
1663 CPUX86State *env = &cpu->env;
1664 struct {
1665 struct kvm_msrs info;
1666 struct kvm_msr_entry entries[150];
1667 } msr_data;
1668 struct kvm_msr_entry *msrs = msr_data.entries;
1669 int ret, i, n;
1670
1671 n = 0;
1672 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1673 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1674 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1675 msrs[n++].index = MSR_PAT;
1676 if (has_msr_star) {
1677 msrs[n++].index = MSR_STAR;
1678 }
1679 if (has_msr_hsave_pa) {
1680 msrs[n++].index = MSR_VM_HSAVE_PA;
1681 }
1682 if (has_msr_tsc_aux) {
1683 msrs[n++].index = MSR_TSC_AUX;
1684 }
1685 if (has_msr_tsc_adjust) {
1686 msrs[n++].index = MSR_TSC_ADJUST;
1687 }
1688 if (has_msr_tsc_deadline) {
1689 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1690 }
1691 if (has_msr_misc_enable) {
1692 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1693 }
1694 if (has_msr_smbase) {
1695 msrs[n++].index = MSR_IA32_SMBASE;
1696 }
1697 if (has_msr_feature_control) {
1698 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1699 }
1700 if (has_msr_bndcfgs) {
1701 msrs[n++].index = MSR_IA32_BNDCFGS;
1702 }
1703 if (has_msr_xss) {
1704 msrs[n++].index = MSR_IA32_XSS;
1705 }
1706
1707
1708 if (!env->tsc_valid) {
1709 msrs[n++].index = MSR_IA32_TSC;
1710 env->tsc_valid = !runstate_is_running();
1711 }
1712
1713 #ifdef TARGET_X86_64
1714 if (lm_capable_kernel) {
1715 msrs[n++].index = MSR_CSTAR;
1716 msrs[n++].index = MSR_KERNELGSBASE;
1717 msrs[n++].index = MSR_FMASK;
1718 msrs[n++].index = MSR_LSTAR;
1719 }
1720 #endif
1721 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1722 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1723 if (has_msr_async_pf_en) {
1724 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1725 }
1726 if (has_msr_pv_eoi_en) {
1727 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1728 }
1729 if (has_msr_kvm_steal_time) {
1730 msrs[n++].index = MSR_KVM_STEAL_TIME;
1731 }
1732 if (has_msr_architectural_pmu) {
1733 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1734 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1735 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1736 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1737 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1738 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1739 }
1740 for (i = 0; i < num_architectural_pmu_counters; i++) {
1741 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1742 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1743 }
1744 }
1745
1746 if (env->mcg_cap) {
1747 msrs[n++].index = MSR_MCG_STATUS;
1748 msrs[n++].index = MSR_MCG_CTL;
1749 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1750 msrs[n++].index = MSR_MC0_CTL + i;
1751 }
1752 }
1753
1754 if (has_msr_hv_hypercall) {
1755 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1756 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1757 }
1758 if (has_msr_hv_vapic) {
1759 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1760 }
1761 if (has_msr_hv_tsc) {
1762 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1763 }
1764 if (has_msr_hv_crash) {
1765 int j;
1766
1767 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
1768 msrs[n++].index = HV_X64_MSR_CRASH_P0 + j;
1769 }
1770 }
1771 if (has_msr_mtrr) {
1772 msrs[n++].index = MSR_MTRRdefType;
1773 msrs[n++].index = MSR_MTRRfix64K_00000;
1774 msrs[n++].index = MSR_MTRRfix16K_80000;
1775 msrs[n++].index = MSR_MTRRfix16K_A0000;
1776 msrs[n++].index = MSR_MTRRfix4K_C0000;
1777 msrs[n++].index = MSR_MTRRfix4K_C8000;
1778 msrs[n++].index = MSR_MTRRfix4K_D0000;
1779 msrs[n++].index = MSR_MTRRfix4K_D8000;
1780 msrs[n++].index = MSR_MTRRfix4K_E0000;
1781 msrs[n++].index = MSR_MTRRfix4K_E8000;
1782 msrs[n++].index = MSR_MTRRfix4K_F0000;
1783 msrs[n++].index = MSR_MTRRfix4K_F8000;
1784 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1785 msrs[n++].index = MSR_MTRRphysBase(i);
1786 msrs[n++].index = MSR_MTRRphysMask(i);
1787 }
1788 }
1789
1790 msr_data.info = (struct kvm_msrs) {
1791 .nmsrs = n,
1792 };
1793
1794 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1795 if (ret < 0) {
1796 return ret;
1797 }
1798
1799 for (i = 0; i < ret; i++) {
1800 uint32_t index = msrs[i].index;
1801 switch (index) {
1802 case MSR_IA32_SYSENTER_CS:
1803 env->sysenter_cs = msrs[i].data;
1804 break;
1805 case MSR_IA32_SYSENTER_ESP:
1806 env->sysenter_esp = msrs[i].data;
1807 break;
1808 case MSR_IA32_SYSENTER_EIP:
1809 env->sysenter_eip = msrs[i].data;
1810 break;
1811 case MSR_PAT:
1812 env->pat = msrs[i].data;
1813 break;
1814 case MSR_STAR:
1815 env->star = msrs[i].data;
1816 break;
1817 #ifdef TARGET_X86_64
1818 case MSR_CSTAR:
1819 env->cstar = msrs[i].data;
1820 break;
1821 case MSR_KERNELGSBASE:
1822 env->kernelgsbase = msrs[i].data;
1823 break;
1824 case MSR_FMASK:
1825 env->fmask = msrs[i].data;
1826 break;
1827 case MSR_LSTAR:
1828 env->lstar = msrs[i].data;
1829 break;
1830 #endif
1831 case MSR_IA32_TSC:
1832 env->tsc = msrs[i].data;
1833 break;
1834 case MSR_TSC_AUX:
1835 env->tsc_aux = msrs[i].data;
1836 break;
1837 case MSR_TSC_ADJUST:
1838 env->tsc_adjust = msrs[i].data;
1839 break;
1840 case MSR_IA32_TSCDEADLINE:
1841 env->tsc_deadline = msrs[i].data;
1842 break;
1843 case MSR_VM_HSAVE_PA:
1844 env->vm_hsave = msrs[i].data;
1845 break;
1846 case MSR_KVM_SYSTEM_TIME:
1847 env->system_time_msr = msrs[i].data;
1848 break;
1849 case MSR_KVM_WALL_CLOCK:
1850 env->wall_clock_msr = msrs[i].data;
1851 break;
1852 case MSR_MCG_STATUS:
1853 env->mcg_status = msrs[i].data;
1854 break;
1855 case MSR_MCG_CTL:
1856 env->mcg_ctl = msrs[i].data;
1857 break;
1858 case MSR_IA32_MISC_ENABLE:
1859 env->msr_ia32_misc_enable = msrs[i].data;
1860 break;
1861 case MSR_IA32_SMBASE:
1862 env->smbase = msrs[i].data;
1863 break;
1864 case MSR_IA32_FEATURE_CONTROL:
1865 env->msr_ia32_feature_control = msrs[i].data;
1866 break;
1867 case MSR_IA32_BNDCFGS:
1868 env->msr_bndcfgs = msrs[i].data;
1869 break;
1870 case MSR_IA32_XSS:
1871 env->xss = msrs[i].data;
1872 break;
1873 default:
1874 if (msrs[i].index >= MSR_MC0_CTL &&
1875 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1876 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1877 }
1878 break;
1879 case MSR_KVM_ASYNC_PF_EN:
1880 env->async_pf_en_msr = msrs[i].data;
1881 break;
1882 case MSR_KVM_PV_EOI_EN:
1883 env->pv_eoi_en_msr = msrs[i].data;
1884 break;
1885 case MSR_KVM_STEAL_TIME:
1886 env->steal_time_msr = msrs[i].data;
1887 break;
1888 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1889 env->msr_fixed_ctr_ctrl = msrs[i].data;
1890 break;
1891 case MSR_CORE_PERF_GLOBAL_CTRL:
1892 env->msr_global_ctrl = msrs[i].data;
1893 break;
1894 case MSR_CORE_PERF_GLOBAL_STATUS:
1895 env->msr_global_status = msrs[i].data;
1896 break;
1897 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1898 env->msr_global_ovf_ctrl = msrs[i].data;
1899 break;
1900 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1901 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1902 break;
1903 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1904 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1905 break;
1906 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1907 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1908 break;
1909 case HV_X64_MSR_HYPERCALL:
1910 env->msr_hv_hypercall = msrs[i].data;
1911 break;
1912 case HV_X64_MSR_GUEST_OS_ID:
1913 env->msr_hv_guest_os_id = msrs[i].data;
1914 break;
1915 case HV_X64_MSR_APIC_ASSIST_PAGE:
1916 env->msr_hv_vapic = msrs[i].data;
1917 break;
1918 case HV_X64_MSR_REFERENCE_TSC:
1919 env->msr_hv_tsc = msrs[i].data;
1920 break;
1921 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
1922 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
1923 break;
1924 case MSR_MTRRdefType:
1925 env->mtrr_deftype = msrs[i].data;
1926 break;
1927 case MSR_MTRRfix64K_00000:
1928 env->mtrr_fixed[0] = msrs[i].data;
1929 break;
1930 case MSR_MTRRfix16K_80000:
1931 env->mtrr_fixed[1] = msrs[i].data;
1932 break;
1933 case MSR_MTRRfix16K_A0000:
1934 env->mtrr_fixed[2] = msrs[i].data;
1935 break;
1936 case MSR_MTRRfix4K_C0000:
1937 env->mtrr_fixed[3] = msrs[i].data;
1938 break;
1939 case MSR_MTRRfix4K_C8000:
1940 env->mtrr_fixed[4] = msrs[i].data;
1941 break;
1942 case MSR_MTRRfix4K_D0000:
1943 env->mtrr_fixed[5] = msrs[i].data;
1944 break;
1945 case MSR_MTRRfix4K_D8000:
1946 env->mtrr_fixed[6] = msrs[i].data;
1947 break;
1948 case MSR_MTRRfix4K_E0000:
1949 env->mtrr_fixed[7] = msrs[i].data;
1950 break;
1951 case MSR_MTRRfix4K_E8000:
1952 env->mtrr_fixed[8] = msrs[i].data;
1953 break;
1954 case MSR_MTRRfix4K_F0000:
1955 env->mtrr_fixed[9] = msrs[i].data;
1956 break;
1957 case MSR_MTRRfix4K_F8000:
1958 env->mtrr_fixed[10] = msrs[i].data;
1959 break;
1960 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
1961 if (index & 1) {
1962 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
1963 } else {
1964 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
1965 }
1966 break;
1967 }
1968 }
1969
1970 return 0;
1971 }
1972
1973 static int kvm_put_mp_state(X86CPU *cpu)
1974 {
1975 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1976
1977 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1978 }
1979
1980 static int kvm_get_mp_state(X86CPU *cpu)
1981 {
1982 CPUState *cs = CPU(cpu);
1983 CPUX86State *env = &cpu->env;
1984 struct kvm_mp_state mp_state;
1985 int ret;
1986
1987 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1988 if (ret < 0) {
1989 return ret;
1990 }
1991 env->mp_state = mp_state.mp_state;
1992 if (kvm_irqchip_in_kernel()) {
1993 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1994 }
1995 return 0;
1996 }
1997
1998 static int kvm_get_apic(X86CPU *cpu)
1999 {
2000 DeviceState *apic = cpu->apic_state;
2001 struct kvm_lapic_state kapic;
2002 int ret;
2003
2004 if (apic && kvm_irqchip_in_kernel()) {
2005 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2006 if (ret < 0) {
2007 return ret;
2008 }
2009
2010 kvm_get_apic_state(apic, &kapic);
2011 }
2012 return 0;
2013 }
2014
2015 static int kvm_put_apic(X86CPU *cpu)
2016 {
2017 DeviceState *apic = cpu->apic_state;
2018 struct kvm_lapic_state kapic;
2019
2020 if (apic && kvm_irqchip_in_kernel()) {
2021 kvm_put_apic_state(apic, &kapic);
2022
2023 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
2024 }
2025 return 0;
2026 }
2027
2028 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2029 {
2030 CPUState *cs = CPU(cpu);
2031 CPUX86State *env = &cpu->env;
2032 struct kvm_vcpu_events events = {};
2033
2034 if (!kvm_has_vcpu_events()) {
2035 return 0;
2036 }
2037
2038 events.exception.injected = (env->exception_injected >= 0);
2039 events.exception.nr = env->exception_injected;
2040 events.exception.has_error_code = env->has_error_code;
2041 events.exception.error_code = env->error_code;
2042 events.exception.pad = 0;
2043
2044 events.interrupt.injected = (env->interrupt_injected >= 0);
2045 events.interrupt.nr = env->interrupt_injected;
2046 events.interrupt.soft = env->soft_interrupt;
2047
2048 events.nmi.injected = env->nmi_injected;
2049 events.nmi.pending = env->nmi_pending;
2050 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2051 events.nmi.pad = 0;
2052
2053 events.sipi_vector = env->sipi_vector;
2054
2055 if (has_msr_smbase) {
2056 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2057 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2058 if (kvm_irqchip_in_kernel()) {
2059 /* As soon as these are moved to the kernel, remove them
2060 * from cs->interrupt_request.
2061 */
2062 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2063 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2064 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2065 } else {
2066 /* Keep these in cs->interrupt_request. */
2067 events.smi.pending = 0;
2068 events.smi.latched_init = 0;
2069 }
2070 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2071 }
2072
2073 events.flags = 0;
2074 if (level >= KVM_PUT_RESET_STATE) {
2075 events.flags |=
2076 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2077 }
2078
2079 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2080 }
2081
2082 static int kvm_get_vcpu_events(X86CPU *cpu)
2083 {
2084 CPUX86State *env = &cpu->env;
2085 struct kvm_vcpu_events events;
2086 int ret;
2087
2088 if (!kvm_has_vcpu_events()) {
2089 return 0;
2090 }
2091
2092 memset(&events, 0, sizeof(events));
2093 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2094 if (ret < 0) {
2095 return ret;
2096 }
2097 env->exception_injected =
2098 events.exception.injected ? events.exception.nr : -1;
2099 env->has_error_code = events.exception.has_error_code;
2100 env->error_code = events.exception.error_code;
2101
2102 env->interrupt_injected =
2103 events.interrupt.injected ? events.interrupt.nr : -1;
2104 env->soft_interrupt = events.interrupt.soft;
2105
2106 env->nmi_injected = events.nmi.injected;
2107 env->nmi_pending = events.nmi.pending;
2108 if (events.nmi.masked) {
2109 env->hflags2 |= HF2_NMI_MASK;
2110 } else {
2111 env->hflags2 &= ~HF2_NMI_MASK;
2112 }
2113
2114 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2115 if (events.smi.smm) {
2116 env->hflags |= HF_SMM_MASK;
2117 } else {
2118 env->hflags &= ~HF_SMM_MASK;
2119 }
2120 if (events.smi.pending) {
2121 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2122 } else {
2123 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2124 }
2125 if (events.smi.smm_inside_nmi) {
2126 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2127 } else {
2128 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2129 }
2130 if (events.smi.latched_init) {
2131 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2132 } else {
2133 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2134 }
2135 }
2136
2137 env->sipi_vector = events.sipi_vector;
2138
2139 return 0;
2140 }
2141
2142 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2143 {
2144 CPUState *cs = CPU(cpu);
2145 CPUX86State *env = &cpu->env;
2146 int ret = 0;
2147 unsigned long reinject_trap = 0;
2148
2149 if (!kvm_has_vcpu_events()) {
2150 if (env->exception_injected == 1) {
2151 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2152 } else if (env->exception_injected == 3) {
2153 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2154 }
2155 env->exception_injected = -1;
2156 }
2157
2158 /*
2159 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2160 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2161 * by updating the debug state once again if single-stepping is on.
2162 * Another reason to call kvm_update_guest_debug here is a pending debug
2163 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2164 * reinject them via SET_GUEST_DEBUG.
2165 */
2166 if (reinject_trap ||
2167 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2168 ret = kvm_update_guest_debug(cs, reinject_trap);
2169 }
2170 return ret;
2171 }
2172
2173 static int kvm_put_debugregs(X86CPU *cpu)
2174 {
2175 CPUX86State *env = &cpu->env;
2176 struct kvm_debugregs dbgregs;
2177 int i;
2178
2179 if (!kvm_has_debugregs()) {
2180 return 0;
2181 }
2182
2183 for (i = 0; i < 4; i++) {
2184 dbgregs.db[i] = env->dr[i];
2185 }
2186 dbgregs.dr6 = env->dr[6];
2187 dbgregs.dr7 = env->dr[7];
2188 dbgregs.flags = 0;
2189
2190 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2191 }
2192
2193 static int kvm_get_debugregs(X86CPU *cpu)
2194 {
2195 CPUX86State *env = &cpu->env;
2196 struct kvm_debugregs dbgregs;
2197 int i, ret;
2198
2199 if (!kvm_has_debugregs()) {
2200 return 0;
2201 }
2202
2203 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2204 if (ret < 0) {
2205 return ret;
2206 }
2207 for (i = 0; i < 4; i++) {
2208 env->dr[i] = dbgregs.db[i];
2209 }
2210 env->dr[4] = env->dr[6] = dbgregs.dr6;
2211 env->dr[5] = env->dr[7] = dbgregs.dr7;
2212
2213 return 0;
2214 }
2215
2216 int kvm_arch_put_registers(CPUState *cpu, int level)
2217 {
2218 X86CPU *x86_cpu = X86_CPU(cpu);
2219 int ret;
2220
2221 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2222
2223 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2224 ret = kvm_put_msr_feature_control(x86_cpu);
2225 if (ret < 0) {
2226 return ret;
2227 }
2228 }
2229
2230 ret = kvm_getput_regs(x86_cpu, 1);
2231 if (ret < 0) {
2232 return ret;
2233 }
2234 ret = kvm_put_xsave(x86_cpu);
2235 if (ret < 0) {
2236 return ret;
2237 }
2238 ret = kvm_put_xcrs(x86_cpu);
2239 if (ret < 0) {
2240 return ret;
2241 }
2242 ret = kvm_put_sregs(x86_cpu);
2243 if (ret < 0) {
2244 return ret;
2245 }
2246 /* must be before kvm_put_msrs */
2247 ret = kvm_inject_mce_oldstyle(x86_cpu);
2248 if (ret < 0) {
2249 return ret;
2250 }
2251 ret = kvm_put_msrs(x86_cpu, level);
2252 if (ret < 0) {
2253 return ret;
2254 }
2255 if (level >= KVM_PUT_RESET_STATE) {
2256 ret = kvm_put_mp_state(x86_cpu);
2257 if (ret < 0) {
2258 return ret;
2259 }
2260 ret = kvm_put_apic(x86_cpu);
2261 if (ret < 0) {
2262 return ret;
2263 }
2264 }
2265
2266 ret = kvm_put_tscdeadline_msr(x86_cpu);
2267 if (ret < 0) {
2268 return ret;
2269 }
2270
2271 ret = kvm_put_vcpu_events(x86_cpu, level);
2272 if (ret < 0) {
2273 return ret;
2274 }
2275 ret = kvm_put_debugregs(x86_cpu);
2276 if (ret < 0) {
2277 return ret;
2278 }
2279 /* must be last */
2280 ret = kvm_guest_debug_workarounds(x86_cpu);
2281 if (ret < 0) {
2282 return ret;
2283 }
2284 return 0;
2285 }
2286
2287 int kvm_arch_get_registers(CPUState *cs)
2288 {
2289 X86CPU *cpu = X86_CPU(cs);
2290 int ret;
2291
2292 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2293
2294 ret = kvm_getput_regs(cpu, 0);
2295 if (ret < 0) {
2296 return ret;
2297 }
2298 ret = kvm_get_xsave(cpu);
2299 if (ret < 0) {
2300 return ret;
2301 }
2302 ret = kvm_get_xcrs(cpu);
2303 if (ret < 0) {
2304 return ret;
2305 }
2306 ret = kvm_get_sregs(cpu);
2307 if (ret < 0) {
2308 return ret;
2309 }
2310 ret = kvm_get_msrs(cpu);
2311 if (ret < 0) {
2312 return ret;
2313 }
2314 ret = kvm_get_mp_state(cpu);
2315 if (ret < 0) {
2316 return ret;
2317 }
2318 ret = kvm_get_apic(cpu);
2319 if (ret < 0) {
2320 return ret;
2321 }
2322 ret = kvm_get_vcpu_events(cpu);
2323 if (ret < 0) {
2324 return ret;
2325 }
2326 ret = kvm_get_debugregs(cpu);
2327 if (ret < 0) {
2328 return ret;
2329 }
2330 return 0;
2331 }
2332
2333 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2334 {
2335 X86CPU *x86_cpu = X86_CPU(cpu);
2336 CPUX86State *env = &x86_cpu->env;
2337 int ret;
2338
2339 /* Inject NMI */
2340 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2341 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2342 qemu_mutex_lock_iothread();
2343 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2344 qemu_mutex_unlock_iothread();
2345 DPRINTF("injected NMI\n");
2346 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2347 if (ret < 0) {
2348 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2349 strerror(-ret));
2350 }
2351 }
2352 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2353 qemu_mutex_lock_iothread();
2354 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2355 qemu_mutex_unlock_iothread();
2356 DPRINTF("injected SMI\n");
2357 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2358 if (ret < 0) {
2359 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2360 strerror(-ret));
2361 }
2362 }
2363 }
2364
2365 if (!kvm_irqchip_in_kernel()) {
2366 qemu_mutex_lock_iothread();
2367 }
2368
2369 /* Force the VCPU out of its inner loop to process any INIT requests
2370 * or (for userspace APIC, but it is cheap to combine the checks here)
2371 * pending TPR access reports.
2372 */
2373 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2374 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2375 !(env->hflags & HF_SMM_MASK)) {
2376 cpu->exit_request = 1;
2377 }
2378 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2379 cpu->exit_request = 1;
2380 }
2381 }
2382
2383 if (!kvm_irqchip_in_kernel()) {
2384 /* Try to inject an interrupt if the guest can accept it */
2385 if (run->ready_for_interrupt_injection &&
2386 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2387 (env->eflags & IF_MASK)) {
2388 int irq;
2389
2390 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2391 irq = cpu_get_pic_interrupt(env);
2392 if (irq >= 0) {
2393 struct kvm_interrupt intr;
2394
2395 intr.irq = irq;
2396 DPRINTF("injected interrupt %d\n", irq);
2397 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2398 if (ret < 0) {
2399 fprintf(stderr,
2400 "KVM: injection failed, interrupt lost (%s)\n",
2401 strerror(-ret));
2402 }
2403 }
2404 }
2405
2406 /* If we have an interrupt but the guest is not ready to receive an
2407 * interrupt, request an interrupt window exit. This will
2408 * cause a return to userspace as soon as the guest is ready to
2409 * receive interrupts. */
2410 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2411 run->request_interrupt_window = 1;
2412 } else {
2413 run->request_interrupt_window = 0;
2414 }
2415
2416 DPRINTF("setting tpr\n");
2417 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2418
2419 qemu_mutex_unlock_iothread();
2420 }
2421 }
2422
2423 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2424 {
2425 X86CPU *x86_cpu = X86_CPU(cpu);
2426 CPUX86State *env = &x86_cpu->env;
2427
2428 if (run->flags & KVM_RUN_X86_SMM) {
2429 env->hflags |= HF_SMM_MASK;
2430 } else {
2431 env->hflags &= HF_SMM_MASK;
2432 }
2433 if (run->if_flag) {
2434 env->eflags |= IF_MASK;
2435 } else {
2436 env->eflags &= ~IF_MASK;
2437 }
2438
2439 /* We need to protect the apic state against concurrent accesses from
2440 * different threads in case the userspace irqchip is used. */
2441 if (!kvm_irqchip_in_kernel()) {
2442 qemu_mutex_lock_iothread();
2443 }
2444 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2445 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2446 if (!kvm_irqchip_in_kernel()) {
2447 qemu_mutex_unlock_iothread();
2448 }
2449 return cpu_get_mem_attrs(env);
2450 }
2451
2452 int kvm_arch_process_async_events(CPUState *cs)
2453 {
2454 X86CPU *cpu = X86_CPU(cs);
2455 CPUX86State *env = &cpu->env;
2456
2457 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2458 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2459 assert(env->mcg_cap);
2460
2461 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2462
2463 kvm_cpu_synchronize_state(cs);
2464
2465 if (env->exception_injected == EXCP08_DBLE) {
2466 /* this means triple fault */
2467 qemu_system_reset_request();
2468 cs->exit_request = 1;
2469 return 0;
2470 }
2471 env->exception_injected = EXCP12_MCHK;
2472 env->has_error_code = 0;
2473
2474 cs->halted = 0;
2475 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2476 env->mp_state = KVM_MP_STATE_RUNNABLE;
2477 }
2478 }
2479
2480 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2481 !(env->hflags & HF_SMM_MASK)) {
2482 kvm_cpu_synchronize_state(cs);
2483 do_cpu_init(cpu);
2484 }
2485
2486 if (kvm_irqchip_in_kernel()) {
2487 return 0;
2488 }
2489
2490 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2491 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2492 apic_poll_irq(cpu->apic_state);
2493 }
2494 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2495 (env->eflags & IF_MASK)) ||
2496 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2497 cs->halted = 0;
2498 }
2499 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2500 kvm_cpu_synchronize_state(cs);
2501 do_cpu_sipi(cpu);
2502 }
2503 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2504 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2505 kvm_cpu_synchronize_state(cs);
2506 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2507 env->tpr_access_type);
2508 }
2509
2510 return cs->halted;
2511 }
2512
2513 static int kvm_handle_halt(X86CPU *cpu)
2514 {
2515 CPUState *cs = CPU(cpu);
2516 CPUX86State *env = &cpu->env;
2517
2518 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2519 (env->eflags & IF_MASK)) &&
2520 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2521 cs->halted = 1;
2522 return EXCP_HLT;
2523 }
2524
2525 return 0;
2526 }
2527
2528 static int kvm_handle_tpr_access(X86CPU *cpu)
2529 {
2530 CPUState *cs = CPU(cpu);
2531 struct kvm_run *run = cs->kvm_run;
2532
2533 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2534 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2535 : TPR_ACCESS_READ);
2536 return 1;
2537 }
2538
2539 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2540 {
2541 static const uint8_t int3 = 0xcc;
2542
2543 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2544 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2545 return -EINVAL;
2546 }
2547 return 0;
2548 }
2549
2550 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2551 {
2552 uint8_t int3;
2553
2554 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2555 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2556 return -EINVAL;
2557 }
2558 return 0;
2559 }
2560
2561 static struct {
2562 target_ulong addr;
2563 int len;
2564 int type;
2565 } hw_breakpoint[4];
2566
2567 static int nb_hw_breakpoint;
2568
2569 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2570 {
2571 int n;
2572
2573 for (n = 0; n < nb_hw_breakpoint; n++) {
2574 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2575 (hw_breakpoint[n].len == len || len == -1)) {
2576 return n;
2577 }
2578 }
2579 return -1;
2580 }
2581
2582 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2583 target_ulong len, int type)
2584 {
2585 switch (type) {
2586 case GDB_BREAKPOINT_HW:
2587 len = 1;
2588 break;
2589 case GDB_WATCHPOINT_WRITE:
2590 case GDB_WATCHPOINT_ACCESS:
2591 switch (len) {
2592 case 1:
2593 break;
2594 case 2:
2595 case 4:
2596 case 8:
2597 if (addr & (len - 1)) {
2598 return -EINVAL;
2599 }
2600 break;
2601 default:
2602 return -EINVAL;
2603 }
2604 break;
2605 default:
2606 return -ENOSYS;
2607 }
2608
2609 if (nb_hw_breakpoint == 4) {
2610 return -ENOBUFS;
2611 }
2612 if (find_hw_breakpoint(addr, len, type) >= 0) {
2613 return -EEXIST;
2614 }
2615 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2616 hw_breakpoint[nb_hw_breakpoint].len = len;
2617 hw_breakpoint[nb_hw_breakpoint].type = type;
2618 nb_hw_breakpoint++;
2619
2620 return 0;
2621 }
2622
2623 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2624 target_ulong len, int type)
2625 {
2626 int n;
2627
2628 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2629 if (n < 0) {
2630 return -ENOENT;
2631 }
2632 nb_hw_breakpoint--;
2633 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2634
2635 return 0;
2636 }
2637
2638 void kvm_arch_remove_all_hw_breakpoints(void)
2639 {
2640 nb_hw_breakpoint = 0;
2641 }
2642
2643 static CPUWatchpoint hw_watchpoint;
2644
2645 static int kvm_handle_debug(X86CPU *cpu,
2646 struct kvm_debug_exit_arch *arch_info)
2647 {
2648 CPUState *cs = CPU(cpu);
2649 CPUX86State *env = &cpu->env;
2650 int ret = 0;
2651 int n;
2652
2653 if (arch_info->exception == 1) {
2654 if (arch_info->dr6 & (1 << 14)) {
2655 if (cs->singlestep_enabled) {
2656 ret = EXCP_DEBUG;
2657 }
2658 } else {
2659 for (n = 0; n < 4; n++) {
2660 if (arch_info->dr6 & (1 << n)) {
2661 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2662 case 0x0:
2663 ret = EXCP_DEBUG;
2664 break;
2665 case 0x1:
2666 ret = EXCP_DEBUG;
2667 cs->watchpoint_hit = &hw_watchpoint;
2668 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2669 hw_watchpoint.flags = BP_MEM_WRITE;
2670 break;
2671 case 0x3:
2672 ret = EXCP_DEBUG;
2673 cs->watchpoint_hit = &hw_watchpoint;
2674 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2675 hw_watchpoint.flags = BP_MEM_ACCESS;
2676 break;
2677 }
2678 }
2679 }
2680 }
2681 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2682 ret = EXCP_DEBUG;
2683 }
2684 if (ret == 0) {
2685 cpu_synchronize_state(cs);
2686 assert(env->exception_injected == -1);
2687
2688 /* pass to guest */
2689 env->exception_injected = arch_info->exception;
2690 env->has_error_code = 0;
2691 }
2692
2693 return ret;
2694 }
2695
2696 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2697 {
2698 const uint8_t type_code[] = {
2699 [GDB_BREAKPOINT_HW] = 0x0,
2700 [GDB_WATCHPOINT_WRITE] = 0x1,
2701 [GDB_WATCHPOINT_ACCESS] = 0x3
2702 };
2703 const uint8_t len_code[] = {
2704 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2705 };
2706 int n;
2707
2708 if (kvm_sw_breakpoints_active(cpu)) {
2709 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2710 }
2711 if (nb_hw_breakpoint > 0) {
2712 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2713 dbg->arch.debugreg[7] = 0x0600;
2714 for (n = 0; n < nb_hw_breakpoint; n++) {
2715 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2716 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2717 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2718 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2719 }
2720 }
2721 }
2722
2723 static bool host_supports_vmx(void)
2724 {
2725 uint32_t ecx, unused;
2726
2727 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2728 return ecx & CPUID_EXT_VMX;
2729 }
2730
2731 #define VMX_INVALID_GUEST_STATE 0x80000021
2732
2733 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2734 {
2735 X86CPU *cpu = X86_CPU(cs);
2736 uint64_t code;
2737 int ret;
2738
2739 switch (run->exit_reason) {
2740 case KVM_EXIT_HLT:
2741 DPRINTF("handle_hlt\n");
2742 qemu_mutex_lock_iothread();
2743 ret = kvm_handle_halt(cpu);
2744 qemu_mutex_unlock_iothread();
2745 break;
2746 case KVM_EXIT_SET_TPR:
2747 ret = 0;
2748 break;
2749 case KVM_EXIT_TPR_ACCESS:
2750 qemu_mutex_lock_iothread();
2751 ret = kvm_handle_tpr_access(cpu);
2752 qemu_mutex_unlock_iothread();
2753 break;
2754 case KVM_EXIT_FAIL_ENTRY:
2755 code = run->fail_entry.hardware_entry_failure_reason;
2756 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2757 code);
2758 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2759 fprintf(stderr,
2760 "\nIf you're running a guest on an Intel machine without "
2761 "unrestricted mode\n"
2762 "support, the failure can be most likely due to the guest "
2763 "entering an invalid\n"
2764 "state for Intel VT. For example, the guest maybe running "
2765 "in big real mode\n"
2766 "which is not supported on less recent Intel processors."
2767 "\n\n");
2768 }
2769 ret = -1;
2770 break;
2771 case KVM_EXIT_EXCEPTION:
2772 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2773 run->ex.exception, run->ex.error_code);
2774 ret = -1;
2775 break;
2776 case KVM_EXIT_DEBUG:
2777 DPRINTF("kvm_exit_debug\n");
2778 qemu_mutex_lock_iothread();
2779 ret = kvm_handle_debug(cpu, &run->debug.arch);
2780 qemu_mutex_unlock_iothread();
2781 break;
2782 default:
2783 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2784 ret = -1;
2785 break;
2786 }
2787
2788 return ret;
2789 }
2790
2791 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2792 {
2793 X86CPU *cpu = X86_CPU(cs);
2794 CPUX86State *env = &cpu->env;
2795
2796 kvm_cpu_synchronize_state(cs);
2797 return !(env->cr[0] & CR0_PE_MASK) ||
2798 ((env->segs[R_CS].selector & 3) != 3);
2799 }
2800
2801 void kvm_arch_init_irq_routing(KVMState *s)
2802 {
2803 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2804 /* If kernel can't do irq routing, interrupt source
2805 * override 0->2 cannot be set up as required by HPET.
2806 * So we have to disable it.
2807 */
2808 no_hpet = 1;
2809 }
2810 /* We know at this point that we're using the in-kernel
2811 * irqchip, so we can use irqfds, and on x86 we know
2812 * we can use msi via irqfd and GSI routing.
2813 */
2814 kvm_msi_via_irqfd_allowed = true;
2815 kvm_gsi_routing_allowed = true;
2816 }
2817
2818 /* Classic KVM device assignment interface. Will remain x86 only. */
2819 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2820 uint32_t flags, uint32_t *dev_id)
2821 {
2822 struct kvm_assigned_pci_dev dev_data = {
2823 .segnr = dev_addr->domain,
2824 .busnr = dev_addr->bus,
2825 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2826 .flags = flags,
2827 };
2828 int ret;
2829
2830 dev_data.assigned_dev_id =
2831 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2832
2833 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2834 if (ret < 0) {
2835 return ret;
2836 }
2837
2838 *dev_id = dev_data.assigned_dev_id;
2839
2840 return 0;
2841 }
2842
2843 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2844 {
2845 struct kvm_assigned_pci_dev dev_data = {
2846 .assigned_dev_id = dev_id,
2847 };
2848
2849 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2850 }
2851
2852 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2853 uint32_t irq_type, uint32_t guest_irq)
2854 {
2855 struct kvm_assigned_irq assigned_irq = {
2856 .assigned_dev_id = dev_id,
2857 .guest_irq = guest_irq,
2858 .flags = irq_type,
2859 };
2860
2861 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2862 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2863 } else {
2864 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2865 }
2866 }
2867
2868 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2869 uint32_t guest_irq)
2870 {
2871 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2872 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2873
2874 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2875 }
2876
2877 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2878 {
2879 struct kvm_assigned_pci_dev dev_data = {
2880 .assigned_dev_id = dev_id,
2881 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2882 };
2883
2884 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2885 }
2886
2887 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2888 uint32_t type)
2889 {
2890 struct kvm_assigned_irq assigned_irq = {
2891 .assigned_dev_id = dev_id,
2892 .flags = type,
2893 };
2894
2895 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2896 }
2897
2898 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2899 {
2900 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2901 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2902 }
2903
2904 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2905 {
2906 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2907 KVM_DEV_IRQ_GUEST_MSI, virq);
2908 }
2909
2910 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2911 {
2912 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2913 KVM_DEV_IRQ_HOST_MSI);
2914 }
2915
2916 bool kvm_device_msix_supported(KVMState *s)
2917 {
2918 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2919 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2920 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2921 }
2922
2923 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2924 uint32_t nr_vectors)
2925 {
2926 struct kvm_assigned_msix_nr msix_nr = {
2927 .assigned_dev_id = dev_id,
2928 .entry_nr = nr_vectors,
2929 };
2930
2931 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2932 }
2933
2934 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2935 int virq)
2936 {
2937 struct kvm_assigned_msix_entry msix_entry = {
2938 .assigned_dev_id = dev_id,
2939 .gsi = virq,
2940 .entry = vector,
2941 };
2942
2943 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2944 }
2945
2946 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2947 {
2948 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2949 KVM_DEV_IRQ_GUEST_MSIX, 0);
2950 }
2951
2952 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2953 {
2954 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2955 KVM_DEV_IRQ_HOST_MSIX);
2956 }
2957
2958 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
2959 uint64_t address, uint32_t data)
2960 {
2961 return 0;
2962 }
2963
2964 int kvm_arch_msi_data_to_gsi(uint32_t data)
2965 {
2966 abort();
2967 }
AR7 emulation for QEMU