hw/arm/stellaris.c

   1 /*
   2  * Luminary Micro Stellaris peripherals
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "hw/sysbus.h"
  13 #include "hw/ssi/ssi.h"
  14 #include "hw/arm/boot.h"
  15 #include "qemu/timer.h"
  16 #include "hw/i2c/i2c.h"
  17 #include "net/net.h"
  18 #include "hw/boards.h"
  19 #include "qemu/log.h"
  20 #include "exec/address-spaces.h"
  21 #include "sysemu/sysemu.h"
  22 #include "hw/arm/armv7m.h"
  23 #include "hw/char/pl011.h"
  24 #include "hw/input/gamepad.h"
  25 #include "hw/irq.h"
  26 #include "hw/watchdog/cmsdk-apb-watchdog.h"
  27 #include "migration/vmstate.h"
  28 #include "hw/misc/unimp.h"
  29 #include "hw/qdev-clock.h"
  30 #include "cpu.h"
  31 #include "qom/object.h"
  32
  33 #define GPIO_A 0
  34 #define GPIO_B 1
  35 #define GPIO_C 2
  36 #define GPIO_D 3
  37 #define GPIO_E 4
  38 #define GPIO_F 5
  39 #define GPIO_G 6
  40
  41 #define BP_OLED_I2C  0x01
  42 #define BP_OLED_SSI  0x02
  43 #define BP_GAMEPAD   0x04
  44
  45 #define NUM_IRQ_LINES 64
  46
  47 typedef const struct {
  48     const char *name;
  49     uint32_t did0;
  50     uint32_t did1;
  51     uint32_t dc0;
  52     uint32_t dc1;
  53     uint32_t dc2;
  54     uint32_t dc3;
  55     uint32_t dc4;
  56     uint32_t peripherals;
  57 } stellaris_board_info;
  58
  59 /* General purpose timer module.  */
  60
  61 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
  62 OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM)
  63
  64 struct gptm_state {
  65     SysBusDevice parent_obj;
  66
  67     MemoryRegion iomem;
  68     uint32_t config;
  69     uint32_t mode[2];
  70     uint32_t control;
  71     uint32_t state;
  72     uint32_t mask;
  73     uint32_t load[2];
  74     uint32_t match[2];
  75     uint32_t prescale[2];
  76     uint32_t match_prescale[2];
  77     uint32_t rtc;
  78     int64_t tick[2];
  79     struct gptm_state *opaque[2];
  80     QEMUTimer *timer[2];
  81     /* The timers have an alternate output used to trigger the ADC.  */
  82     qemu_irq trigger;
  83     qemu_irq irq;
  84 };
  85
  86 static void gptm_update_irq(gptm_state *s)
  87 {
  88     int level;
  89     level = (s->state & s->mask) != 0;
  90     qemu_set_irq(s->irq, level);
  91 }
  92
  93 static void gptm_stop(gptm_state *s, int n)
  94 {
  95     timer_del(s->timer[n]);
  96 }
  97
  98 static void gptm_reload(gptm_state *s, int n, int reset)
  99 {
 100     int64_t tick;
 101     if (reset)
 102         tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 103     else
 104         tick = s->tick[n];
 105
 106     if (s->config == 0) {
 107         /* 32-bit CountDown.  */
 108         uint32_t count;
 109         count = s->load[0] | (s->load[1] << 16);
 110         tick += (int64_t)count * system_clock_scale;
 111     } else if (s->config == 1) {
 112         /* 32-bit RTC.  1Hz tick.  */
 113         tick += NANOSECONDS_PER_SECOND;
 114     } else if (s->mode[n] == 0xa) {
 115         /* PWM mode.  Not implemented.  */
 116     } else {
 117         qemu_log_mask(LOG_UNIMP,
 118                       "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
 119                       s->mode[n]);
 120         return;
 121     }
 122     s->tick[n] = tick;
 123     timer_mod(s->timer[n], tick);
 124 }
 125
 126 static void gptm_tick(void *opaque)
 127 {
 128     gptm_state **p = (gptm_state **)opaque;
 129     gptm_state *s;
 130     int n;
 131
 132     s = *p;
 133     n = p - s->opaque;
 134     if (s->config == 0) {
 135         s->state |= 1;
 136         if ((s->control & 0x20)) {
 137             /* Output trigger.  */
 138             qemu_irq_pulse(s->trigger);
 139         }
 140         if (s->mode[0] & 1) {
 141             /* One-shot.  */
 142             s->control &= ~1;
 143         } else {
 144             /* Periodic.  */
 145             gptm_reload(s, 0, 0);
 146         }
 147     } else if (s->config == 1) {
 148         /* RTC.  */
 149         uint32_t match;
 150         s->rtc++;
 151         match = s->match[0] | (s->match[1] << 16);
 152         if (s->rtc > match)
 153             s->rtc = 0;
 154         if (s->rtc == 0) {
 155             s->state |= 8;
 156         }
 157         gptm_reload(s, 0, 0);
 158     } else if (s->mode[n] == 0xa) {
 159         /* PWM mode.  Not implemented.  */
 160     } else {
 161         qemu_log_mask(LOG_UNIMP,
 162                       "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
 163                       s->mode[n]);
 164     }
 165     gptm_update_irq(s);
 166 }
 167
 168 static uint64_t gptm_read(void *opaque, hwaddr offset,
 169                           unsigned size)
 170 {
 171     gptm_state *s = (gptm_state *)opaque;
 172
 173     switch (offset) {
 174     case 0x00: /* CFG */
 175         return s->config;
 176     case 0x04: /* TAMR */
 177         return s->mode[0];
 178     case 0x08: /* TBMR */
 179         return s->mode[1];
 180     case 0x0c: /* CTL */
 181         return s->control;
 182     case 0x18: /* IMR */
 183         return s->mask;
 184     case 0x1c: /* RIS */
 185         return s->state;
 186     case 0x20: /* MIS */
 187         return s->state & s->mask;
 188     case 0x24: /* CR */
 189         return 0;
 190     case 0x28: /* TAILR */
 191         return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
 192     case 0x2c: /* TBILR */
 193         return s->load[1];
 194     case 0x30: /* TAMARCHR */
 195         return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
 196     case 0x34: /* TBMATCHR */
 197         return s->match[1];
 198     case 0x38: /* TAPR */
 199         return s->prescale[0];
 200     case 0x3c: /* TBPR */
 201         return s->prescale[1];
 202     case 0x40: /* TAPMR */
 203         return s->match_prescale[0];
 204     case 0x44: /* TBPMR */
 205         return s->match_prescale[1];
 206     case 0x48: /* TAR */
 207         if (s->config == 1) {
 208             return s->rtc;
 209         }
 210         qemu_log_mask(LOG_UNIMP,
 211                       "GPTM: read of TAR but timer read not supported\n");
 212         return 0;
 213     case 0x4c: /* TBR */
 214         qemu_log_mask(LOG_UNIMP,
 215                       "GPTM: read of TBR but timer read not supported\n");
 216         return 0;
 217     default:
 218         qemu_log_mask(LOG_GUEST_ERROR,
 219                       "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n",
 220                       offset);
 221         return 0;
 222     }
 223 }
 224
 225 static void gptm_write(void *opaque, hwaddr offset,
 226                        uint64_t value, unsigned size)
 227 {
 228     gptm_state *s = (gptm_state *)opaque;
 229     uint32_t oldval;
 230
 231     /* The timers should be disabled before changing the configuration.
 232        We take advantage of this and defer everything until the timer
 233        is enabled.  */
 234     switch (offset) {
 235     case 0x00: /* CFG */
 236         s->config = value;
 237         break;
 238     case 0x04: /* TAMR */
 239         s->mode[0] = value;
 240         break;
 241     case 0x08: /* TBMR */
 242         s->mode[1] = value;
 243         break;
 244     case 0x0c: /* CTL */
 245         oldval = s->control;
 246         s->control = value;
 247         /* TODO: Implement pause.  */
 248         if ((oldval ^ value) & 1) {
 249             if (value & 1) {
 250                 gptm_reload(s, 0, 1);
 251             } else {
 252                 gptm_stop(s, 0);
 253             }
 254         }
 255         if (((oldval ^ value) & 0x100) && s->config >= 4) {
 256             if (value & 0x100) {
 257                 gptm_reload(s, 1, 1);
 258             } else {
 259                 gptm_stop(s, 1);
 260             }
 261         }
 262         break;
 263     case 0x18: /* IMR */
 264         s->mask = value & 0x77;
 265         gptm_update_irq(s);
 266         break;
 267     case 0x24: /* CR */
 268         s->state &= ~value;
 269         break;
 270     case 0x28: /* TAILR */
 271         s->load[0] = value & 0xffff;
 272         if (s->config < 4) {
 273             s->load[1] = value >> 16;
 274         }
 275         break;
 276     case 0x2c: /* TBILR */
 277         s->load[1] = value & 0xffff;
 278         break;
 279     case 0x30: /* TAMARCHR */
 280         s->match[0] = value & 0xffff;
 281         if (s->config < 4) {
 282             s->match[1] = value >> 16;
 283         }
 284         break;
 285     case 0x34: /* TBMATCHR */
 286         s->match[1] = value >> 16;
 287         break;
 288     case 0x38: /* TAPR */
 289         s->prescale[0] = value;
 290         break;
 291     case 0x3c: /* TBPR */
 292         s->prescale[1] = value;
 293         break;
 294     case 0x40: /* TAPMR */
 295         s->match_prescale[0] = value;
 296         break;
 297     case 0x44: /* TBPMR */
 298         s->match_prescale[0] = value;
 299         break;
 300     default:
 301         qemu_log_mask(LOG_GUEST_ERROR,
 302                       "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n",
 303                       offset);
 304     }
 305     gptm_update_irq(s);
 306 }
 307
 308 static const MemoryRegionOps gptm_ops = {
 309     .read = gptm_read,
 310     .write = gptm_write,
 311     .endianness = DEVICE_NATIVE_ENDIAN,
 312 };
 313
 314 static const VMStateDescription vmstate_stellaris_gptm = {
 315     .name = "stellaris_gptm",
 316     .version_id = 1,
 317     .minimum_version_id = 1,
 318     .fields = (VMStateField[]) {
 319         VMSTATE_UINT32(config, gptm_state),
 320         VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
 321         VMSTATE_UINT32(control, gptm_state),
 322         VMSTATE_UINT32(state, gptm_state),
 323         VMSTATE_UINT32(mask, gptm_state),
 324         VMSTATE_UNUSED(8),
 325         VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
 326         VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
 327         VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
 328         VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
 329         VMSTATE_UINT32(rtc, gptm_state),
 330         VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
 331         VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
 332         VMSTATE_END_OF_LIST()
 333     }
 334 };
 335
 336 static void stellaris_gptm_init(Object *obj)
 337 {
 338     DeviceState *dev = DEVICE(obj);
 339     gptm_state *s = STELLARIS_GPTM(obj);
 340     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 341
 342     sysbus_init_irq(sbd, &s->irq);
 343     qdev_init_gpio_out(dev, &s->trigger, 1);
 344
 345     memory_region_init_io(&s->iomem, obj, &gptm_ops, s,
 346                           "gptm", 0x1000);
 347     sysbus_init_mmio(sbd, &s->iomem);
 348
 349     s->opaque[0] = s->opaque[1] = s;
 350 }
 351
 352 static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
 353 {
 354     gptm_state *s = STELLARIS_GPTM(dev);
 355     s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
 356     s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
 357 }
 358
 359 /* System controller.  */
 360
 361 #define TYPE_STELLARIS_SYS "stellaris-sys"
 362 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
 363
 364 struct ssys_state {
 365     SysBusDevice parent_obj;
 366
 367     MemoryRegion iomem;
 368     uint32_t pborctl;
 369     uint32_t ldopctl;
 370     uint32_t int_status;
 371     uint32_t int_mask;
 372     uint32_t resc;
 373     uint32_t rcc;
 374     uint32_t rcc2;
 375     uint32_t rcgc[3];
 376     uint32_t scgc[3];
 377     uint32_t dcgc[3];
 378     uint32_t clkvclr;
 379     uint32_t ldoarst;
 380     qemu_irq irq;
 381     Clock *sysclk;
 382     /* Properties (all read-only registers) */
 383     uint32_t user0;
 384     uint32_t user1;
 385     uint32_t did0;
 386     uint32_t did1;
 387     uint32_t dc0;
 388     uint32_t dc1;
 389     uint32_t dc2;
 390     uint32_t dc3;
 391     uint32_t dc4;
 392 };
 393
 394 static void ssys_update(ssys_state *s)
 395 {
 396   qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
 397 }
 398
 399 static uint32_t pllcfg_sandstorm[16] = {
 400     0x31c0, /* 1 Mhz */
 401     0x1ae0, /* 1.8432 Mhz */
 402     0x18c0, /* 2 Mhz */
 403     0xd573, /* 2.4576 Mhz */
 404     0x37a6, /* 3.57954 Mhz */
 405     0x1ae2, /* 3.6864 Mhz */
 406     0x0c40, /* 4 Mhz */
 407     0x98bc, /* 4.906 Mhz */
 408     0x935b, /* 4.9152 Mhz */
 409     0x09c0, /* 5 Mhz */
 410     0x4dee, /* 5.12 Mhz */
 411     0x0c41, /* 6 Mhz */
 412     0x75db, /* 6.144 Mhz */
 413     0x1ae6, /* 7.3728 Mhz */
 414     0x0600, /* 8 Mhz */
 415     0x585b /* 8.192 Mhz */
 416 };
 417
 418 static uint32_t pllcfg_fury[16] = {
 419     0x3200, /* 1 Mhz */
 420     0x1b20, /* 1.8432 Mhz */
 421     0x1900, /* 2 Mhz */
 422     0xf42b, /* 2.4576 Mhz */
 423     0x37e3, /* 3.57954 Mhz */
 424     0x1b21, /* 3.6864 Mhz */
 425     0x0c80, /* 4 Mhz */
 426     0x98ee, /* 4.906 Mhz */
 427     0xd5b4, /* 4.9152 Mhz */
 428     0x0a00, /* 5 Mhz */
 429     0x4e27, /* 5.12 Mhz */
 430     0x1902, /* 6 Mhz */
 431     0xec1c, /* 6.144 Mhz */
 432     0x1b23, /* 7.3728 Mhz */
 433     0x0640, /* 8 Mhz */
 434     0xb11c /* 8.192 Mhz */
 435 };
 436
 437 #define DID0_VER_MASK        0x70000000
 438 #define DID0_VER_0           0x00000000
 439 #define DID0_VER_1           0x10000000
 440
 441 #define DID0_CLASS_MASK      0x00FF0000
 442 #define DID0_CLASS_SANDSTORM 0x00000000
 443 #define DID0_CLASS_FURY      0x00010000
 444
 445 static int ssys_board_class(const ssys_state *s)
 446 {
 447     uint32_t did0 = s->did0;
 448     switch (did0 & DID0_VER_MASK) {
 449     case DID0_VER_0:
 450         return DID0_CLASS_SANDSTORM;
 451     case DID0_VER_1:
 452         switch (did0 & DID0_CLASS_MASK) {
 453         case DID0_CLASS_SANDSTORM:
 454         case DID0_CLASS_FURY:
 455             return did0 & DID0_CLASS_MASK;
 456         }
 457         /* for unknown classes, fall through */
 458     default:
 459         /* This can only happen if the hardwired constant did0 value
 460          * in this board's stellaris_board_info struct is wrong.
 461          */
 462         g_assert_not_reached();
 463     }
 464 }
 465
 466 static uint64_t ssys_read(void *opaque, hwaddr offset,
 467                           unsigned size)
 468 {
 469     ssys_state *s = (ssys_state *)opaque;
 470
 471     switch (offset) {
 472     case 0x000: /* DID0 */
 473         return s->did0;
 474     case 0x004: /* DID1 */
 475         return s->did1;
 476     case 0x008: /* DC0 */
 477         return s->dc0;
 478     case 0x010: /* DC1 */
 479         return s->dc1;
 480     case 0x014: /* DC2 */
 481         return s->dc2;
 482     case 0x018: /* DC3 */
 483         return s->dc3;
 484     case 0x01c: /* DC4 */
 485         return s->dc4;
 486     case 0x030: /* PBORCTL */
 487         return s->pborctl;
 488     case 0x034: /* LDOPCTL */
 489         return s->ldopctl;
 490     case 0x040: /* SRCR0 */
 491         return 0;
 492     case 0x044: /* SRCR1 */
 493         return 0;
 494     case 0x048: /* SRCR2 */
 495         return 0;
 496     case 0x050: /* RIS */
 497         return s->int_status;
 498     case 0x054: /* IMC */
 499         return s->int_mask;
 500     case 0x058: /* MISC */
 501         return s->int_status & s->int_mask;
 502     case 0x05c: /* RESC */
 503         return s->resc;
 504     case 0x060: /* RCC */
 505         return s->rcc;
 506     case 0x064: /* PLLCFG */
 507         {
 508             int xtal;
 509             xtal = (s->rcc >> 6) & 0xf;
 510             switch (ssys_board_class(s)) {
 511             case DID0_CLASS_FURY:
 512                 return pllcfg_fury[xtal];
 513             case DID0_CLASS_SANDSTORM:
 514                 return pllcfg_sandstorm[xtal];
 515             default:
 516                 g_assert_not_reached();
 517             }
 518         }
 519     case 0x070: /* RCC2 */
 520         return s->rcc2;
 521     case 0x100: /* RCGC0 */
 522         return s->rcgc[0];
 523     case 0x104: /* RCGC1 */
 524         return s->rcgc[1];
 525     case 0x108: /* RCGC2 */
 526         return s->rcgc[2];
 527     case 0x110: /* SCGC0 */
 528         return s->scgc[0];
 529     case 0x114: /* SCGC1 */
 530         return s->scgc[1];
 531     case 0x118: /* SCGC2 */
 532         return s->scgc[2];
 533     case 0x120: /* DCGC0 */
 534         return s->dcgc[0];
 535     case 0x124: /* DCGC1 */
 536         return s->dcgc[1];
 537     case 0x128: /* DCGC2 */
 538         return s->dcgc[2];
 539     case 0x150: /* CLKVCLR */
 540         return s->clkvclr;
 541     case 0x160: /* LDOARST */
 542         return s->ldoarst;
 543     case 0x1e0: /* USER0 */
 544         return s->user0;
 545     case 0x1e4: /* USER1 */
 546         return s->user1;
 547     default:
 548         qemu_log_mask(LOG_GUEST_ERROR,
 549                       "SSYS: read at bad offset 0x%x\n", (int)offset);
 550         return 0;
 551     }
 552 }
 553
 554 static bool ssys_use_rcc2(ssys_state *s)
 555 {
 556     return (s->rcc2 >> 31) & 0x1;
 557 }
 558
 559 /*
 560  * Calculate the system clock period. We only want to propagate
 561  * this change to the rest of the system if we're not being called
 562  * from migration post-load.
 563  */
 564 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
 565 {
 566     /*
 567      * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc.  Input
 568      * clock is 200MHz, which is a period of 5 ns. Dividing the clock
 569      * frequency by X is the same as multiplying the period by X.
 570      */
 571     if (ssys_use_rcc2(s)) {
 572         system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
 573     } else {
 574         system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
 575     }
 576     clock_set_ns(s->sysclk, system_clock_scale);
 577     if (propagate_clock) {
 578         clock_propagate(s->sysclk);
 579     }
 580 }
 581
 582 static void ssys_write(void *opaque, hwaddr offset,
 583                        uint64_t value, unsigned size)
 584 {
 585     ssys_state *s = (ssys_state *)opaque;
 586
 587     switch (offset) {
 588     case 0x030: /* PBORCTL */
 589         s->pborctl = value & 0xffff;
 590         break;
 591     case 0x034: /* LDOPCTL */
 592         s->ldopctl = value & 0x1f;
 593         break;
 594     case 0x040: /* SRCR0 */
 595     case 0x044: /* SRCR1 */
 596     case 0x048: /* SRCR2 */
 597         qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n");
 598         break;
 599     case 0x054: /* IMC */
 600         s->int_mask = value & 0x7f;
 601         break;
 602     case 0x058: /* MISC */
 603         s->int_status &= ~value;
 604         break;
 605     case 0x05c: /* RESC */
 606         s->resc = value & 0x3f;
 607         break;
 608     case 0x060: /* RCC */
 609         if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 610             /* PLL enable.  */
 611             s->int_status |= (1 << 6);
 612         }
 613         s->rcc = value;
 614         ssys_calculate_system_clock(s, true);
 615         break;
 616     case 0x070: /* RCC2 */
 617         if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 618             break;
 619         }
 620
 621         if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 622             /* PLL enable.  */
 623             s->int_status |= (1 << 6);
 624         }
 625         s->rcc2 = value;
 626         ssys_calculate_system_clock(s, true);
 627         break;
 628     case 0x100: /* RCGC0 */
 629         s->rcgc[0] = value;
 630         break;
 631     case 0x104: /* RCGC1 */
 632         s->rcgc[1] = value;
 633         break;
 634     case 0x108: /* RCGC2 */
 635         s->rcgc[2] = value;
 636         break;
 637     case 0x110: /* SCGC0 */
 638         s->scgc[0] = value;
 639         break;
 640     case 0x114: /* SCGC1 */
 641         s->scgc[1] = value;
 642         break;
 643     case 0x118: /* SCGC2 */
 644         s->scgc[2] = value;
 645         break;
 646     case 0x120: /* DCGC0 */
 647         s->dcgc[0] = value;
 648         break;
 649     case 0x124: /* DCGC1 */
 650         s->dcgc[1] = value;
 651         break;
 652     case 0x128: /* DCGC2 */
 653         s->dcgc[2] = value;
 654         break;
 655     case 0x150: /* CLKVCLR */
 656         s->clkvclr = value;
 657         break;
 658     case 0x160: /* LDOARST */
 659         s->ldoarst = value;
 660         break;
 661     default:
 662         qemu_log_mask(LOG_GUEST_ERROR,
 663                       "SSYS: write at bad offset 0x%x\n", (int)offset);
 664     }
 665     ssys_update(s);
 666 }
 667
 668 static const MemoryRegionOps ssys_ops = {
 669     .read = ssys_read,
 670     .write = ssys_write,
 671     .endianness = DEVICE_NATIVE_ENDIAN,
 672 };
 673
 674 static void stellaris_sys_reset_enter(Object *obj, ResetType type)
 675 {
 676     ssys_state *s = STELLARIS_SYS(obj);
 677
 678     s->pborctl = 0x7ffd;
 679     s->rcc = 0x078e3ac0;
 680
 681     if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 682         s->rcc2 = 0;
 683     } else {
 684         s->rcc2 = 0x07802810;
 685     }
 686     s->rcgc[0] = 1;
 687     s->scgc[0] = 1;
 688     s->dcgc[0] = 1;
 689 }
 690
 691 static void stellaris_sys_reset_hold(Object *obj)
 692 {
 693     ssys_state *s = STELLARIS_SYS(obj);
 694
 695     /* OK to propagate clocks from the hold phase */
 696     ssys_calculate_system_clock(s, true);
 697 }
 698
 699 static void stellaris_sys_reset_exit(Object *obj)
 700 {
 701 }
 702
 703 static int stellaris_sys_post_load(void *opaque, int version_id)
 704 {
 705     ssys_state *s = opaque;
 706
 707     ssys_calculate_system_clock(s, false);
 708
 709     return 0;
 710 }
 711
 712 static const VMStateDescription vmstate_stellaris_sys = {
 713     .name = "stellaris_sys",
 714     .version_id = 2,
 715     .minimum_version_id = 1,
 716     .post_load = stellaris_sys_post_load,
 717     .fields = (VMStateField[]) {
 718         VMSTATE_UINT32(pborctl, ssys_state),
 719         VMSTATE_UINT32(ldopctl, ssys_state),
 720         VMSTATE_UINT32(int_mask, ssys_state),
 721         VMSTATE_UINT32(int_status, ssys_state),
 722         VMSTATE_UINT32(resc, ssys_state),
 723         VMSTATE_UINT32(rcc, ssys_state),
 724         VMSTATE_UINT32_V(rcc2, ssys_state, 2),
 725         VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
 726         VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
 727         VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
 728         VMSTATE_UINT32(clkvclr, ssys_state),
 729         VMSTATE_UINT32(ldoarst, ssys_state),
 730         /* No field for sysclk -- handled in post-load instead */
 731         VMSTATE_END_OF_LIST()
 732     }
 733 };
 734
 735 static Property stellaris_sys_properties[] = {
 736     DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
 737     DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
 738     DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
 739     DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
 740     DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
 741     DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
 742     DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
 743     DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
 744     DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
 745     DEFINE_PROP_END_OF_LIST()
 746 };
 747
 748 static void stellaris_sys_instance_init(Object *obj)
 749 {
 750     ssys_state *s = STELLARIS_SYS(obj);
 751     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
 752
 753     memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
 754     sysbus_init_mmio(sbd, &s->iomem);
 755     sysbus_init_irq(sbd, &s->irq);
 756     s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
 757 }
 758
 759 static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq,
 760                                        stellaris_board_info *board,
 761                                        uint8_t *macaddr)
 762 {
 763     DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS);
 764     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 765
 766     /* Most devices come preprogrammed with a MAC address in the user data. */
 767     qdev_prop_set_uint32(dev, "user0",
 768                          macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16));
 769     qdev_prop_set_uint32(dev, "user1",
 770                          macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16));
 771     qdev_prop_set_uint32(dev, "did0", board->did0);
 772     qdev_prop_set_uint32(dev, "did1", board->did1);
 773     qdev_prop_set_uint32(dev, "dc0", board->dc0);
 774     qdev_prop_set_uint32(dev, "dc1", board->dc1);
 775     qdev_prop_set_uint32(dev, "dc2", board->dc2);
 776     qdev_prop_set_uint32(dev, "dc3", board->dc3);
 777     qdev_prop_set_uint32(dev, "dc4", board->dc4);
 778
 779     sysbus_realize_and_unref(sbd, &error_fatal);
 780     sysbus_mmio_map(sbd, 0, base);
 781     sysbus_connect_irq(sbd, 0, irq);
 782
 783     /*
 784      * Normally we should not be resetting devices like this during
 785      * board creation. For the moment we need to do so, because
 786      * system_clock_scale will only get set when the STELLARIS_SYS
 787      * device is reset, and we need its initial value to pass to
 788      * the watchdog device. This hack can be removed once the
 789      * watchdog has been converted to use a Clock input instead.
 790      */
 791     device_cold_reset(dev);
 792
 793     return dev;
 794 }
 795
 796 /* I2C controller.  */
 797
 798 #define TYPE_STELLARIS_I2C "stellaris-i2c"
 799 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
 800
 801 struct stellaris_i2c_state {
 802     SysBusDevice parent_obj;
 803
 804     I2CBus *bus;
 805     qemu_irq irq;
 806     MemoryRegion iomem;
 807     uint32_t msa;
 808     uint32_t mcs;
 809     uint32_t mdr;
 810     uint32_t mtpr;
 811     uint32_t mimr;
 812     uint32_t mris;
 813     uint32_t mcr;
 814 };
 815
 816 #define STELLARIS_I2C_MCS_BUSY    0x01
 817 #define STELLARIS_I2C_MCS_ERROR   0x02
 818 #define STELLARIS_I2C_MCS_ADRACK  0x04
 819 #define STELLARIS_I2C_MCS_DATACK  0x08
 820 #define STELLARIS_I2C_MCS_ARBLST  0x10
 821 #define STELLARIS_I2C_MCS_IDLE    0x20
 822 #define STELLARIS_I2C_MCS_BUSBSY  0x40
 823
 824 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
 825                                    unsigned size)
 826 {
 827     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 828
 829     switch (offset) {
 830     case 0x00: /* MSA */
 831         return s->msa;
 832     case 0x04: /* MCS */
 833         /* We don't emulate timing, so the controller is never busy.  */
 834         return s->mcs | STELLARIS_I2C_MCS_IDLE;
 835     case 0x08: /* MDR */
 836         return s->mdr;
 837     case 0x0c: /* MTPR */
 838         return s->mtpr;
 839     case 0x10: /* MIMR */
 840         return s->mimr;
 841     case 0x14: /* MRIS */
 842         return s->mris;
 843     case 0x18: /* MMIS */
 844         return s->mris & s->mimr;
 845     case 0x20: /* MCR */
 846         return s->mcr;
 847     default:
 848         qemu_log_mask(LOG_GUEST_ERROR,
 849                       "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
 850         return 0;
 851     }
 852 }
 853
 854 static void stellaris_i2c_update(stellaris_i2c_state *s)
 855 {
 856     int level;
 857
 858     level = (s->mris & s->mimr) != 0;
 859     qemu_set_irq(s->irq, level);
 860 }
 861
 862 static void stellaris_i2c_write(void *opaque, hwaddr offset,
 863                                 uint64_t value, unsigned size)
 864 {
 865     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 866
 867     switch (offset) {
 868     case 0x00: /* MSA */
 869         s->msa = value & 0xff;
 870         break;
 871     case 0x04: /* MCS */
 872         if ((s->mcr & 0x10) == 0) {
 873             /* Disabled.  Do nothing.  */
 874             break;
 875         }
 876         /* Grab the bus if this is starting a transfer.  */
 877         if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 878             if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
 879                 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
 880             } else {
 881                 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
 882                 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
 883             }
 884         }
 885         /* If we don't have the bus then indicate an error.  */
 886         if (!i2c_bus_busy(s->bus)
 887                 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 888             s->mcs |= STELLARIS_I2C_MCS_ERROR;
 889             break;
 890         }
 891         s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
 892         if (value & 1) {
 893             /* Transfer a byte.  */
 894             /* TODO: Handle errors.  */
 895             if (s->msa & 1) {
 896                 /* Recv */
 897                 s->mdr = i2c_recv(s->bus);
 898             } else {
 899                 /* Send */
 900                 i2c_send(s->bus, s->mdr);
 901             }
 902             /* Raise an interrupt.  */
 903             s->mris |= 1;
 904         }
 905         if (value & 4) {
 906             /* Finish transfer.  */
 907             i2c_end_transfer(s->bus);
 908             s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
 909         }
 910         break;
 911     case 0x08: /* MDR */
 912         s->mdr = value & 0xff;
 913         break;
 914     case 0x0c: /* MTPR */
 915         s->mtpr = value & 0xff;
 916         break;
 917     case 0x10: /* MIMR */
 918         s->mimr = 1;
 919         break;
 920     case 0x1c: /* MICR */
 921         s->mris &= ~value;
 922         break;
 923     case 0x20: /* MCR */
 924         if (value & 1) {
 925             qemu_log_mask(LOG_UNIMP,
 926                           "stellaris_i2c: Loopback not implemented\n");
 927         }
 928         if (value & 0x20) {
 929             qemu_log_mask(LOG_UNIMP,
 930                           "stellaris_i2c: Slave mode not implemented\n");
 931         }
 932         s->mcr = value & 0x31;
 933         break;
 934     default:
 935         qemu_log_mask(LOG_GUEST_ERROR,
 936                       "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
 937     }
 938     stellaris_i2c_update(s);
 939 }
 940
 941 static void stellaris_i2c_reset(stellaris_i2c_state *s)
 942 {
 943     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
 944         i2c_end_transfer(s->bus);
 945
 946     s->msa = 0;
 947     s->mcs = 0;
 948     s->mdr = 0;
 949     s->mtpr = 1;
 950     s->mimr = 0;
 951     s->mris = 0;
 952     s->mcr = 0;
 953     stellaris_i2c_update(s);
 954 }
 955
 956 static const MemoryRegionOps stellaris_i2c_ops = {
 957     .read = stellaris_i2c_read,
 958     .write = stellaris_i2c_write,
 959     .endianness = DEVICE_NATIVE_ENDIAN,
 960 };
 961
 962 static const VMStateDescription vmstate_stellaris_i2c = {
 963     .name = "stellaris_i2c",
 964     .version_id = 1,
 965     .minimum_version_id = 1,
 966     .fields = (VMStateField[]) {
 967         VMSTATE_UINT32(msa, stellaris_i2c_state),
 968         VMSTATE_UINT32(mcs, stellaris_i2c_state),
 969         VMSTATE_UINT32(mdr, stellaris_i2c_state),
 970         VMSTATE_UINT32(mtpr, stellaris_i2c_state),
 971         VMSTATE_UINT32(mimr, stellaris_i2c_state),
 972         VMSTATE_UINT32(mris, stellaris_i2c_state),
 973         VMSTATE_UINT32(mcr, stellaris_i2c_state),
 974         VMSTATE_END_OF_LIST()
 975     }
 976 };
 977
 978 static void stellaris_i2c_init(Object *obj)
 979 {
 980     DeviceState *dev = DEVICE(obj);
 981     stellaris_i2c_state *s = STELLARIS_I2C(obj);
 982     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 983     I2CBus *bus;
 984
 985     sysbus_init_irq(sbd, &s->irq);
 986     bus = i2c_init_bus(dev, "i2c");
 987     s->bus = bus;
 988
 989     memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
 990                           "i2c", 0x1000);
 991     sysbus_init_mmio(sbd, &s->iomem);
 992     /* ??? For now we only implement the master interface.  */
 993     stellaris_i2c_reset(s);
 994 }
 995
 996 /* Analogue to Digital Converter.  This is only partially implemented,
 997    enough for applications that use a combined ADC and timer tick.  */
 998
 999 #define STELLARIS_ADC_EM_CONTROLLER 0
1000 #define STELLARIS_ADC_EM_COMP       1
1001 #define STELLARIS_ADC_EM_EXTERNAL   4
1002 #define STELLARIS_ADC_EM_TIMER      5
1003 #define STELLARIS_ADC_EM_PWM0       6
1004 #define STELLARIS_ADC_EM_PWM1       7
1005 #define STELLARIS_ADC_EM_PWM2       8
1006
1007 #define STELLARIS_ADC_FIFO_EMPTY    0x0100
1008 #define STELLARIS_ADC_FIFO_FULL     0x1000
1009
1010 #define TYPE_STELLARIS_ADC "stellaris-adc"
1011 typedef struct StellarisADCState stellaris_adc_state;
1012 DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
1013                          TYPE_STELLARIS_ADC)
1014
1015 struct StellarisADCState {
1016     SysBusDevice parent_obj;
1017
1018     MemoryRegion iomem;
1019     uint32_t actss;
1020     uint32_t ris;
1021     uint32_t im;
1022     uint32_t emux;
1023     uint32_t ostat;
1024     uint32_t ustat;
1025     uint32_t sspri;
1026     uint32_t sac;
1027     struct {
1028         uint32_t state;
1029         uint32_t data[16];
1030     } fifo[4];
1031     uint32_t ssmux[4];
1032     uint32_t ssctl[4];
1033     uint32_t noise;
1034     qemu_irq irq[4];
1035 };
1036
1037 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
1038 {
1039     int tail;
1040
1041     tail = s->fifo[n].state & 0xf;
1042     if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
1043         s->ustat |= 1 << n;
1044     } else {
1045         s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
1046         s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
1047         if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
1048             s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
1049     }
1050     return s->fifo[n].data[tail];
1051 }
1052
1053 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
1054                                      uint32_t value)
1055 {
1056     int head;
1057
1058     /* TODO: Real hardware has limited size FIFOs.  We have a full 16 entry
1059        FIFO fir each sequencer.  */
1060     head = (s->fifo[n].state >> 4) & 0xf;
1061     if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
1062         s->ostat |= 1 << n;
1063         return;
1064     }
1065     s->fifo[n].data[head] = value;
1066     head = (head + 1) & 0xf;
1067     s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
1068     s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
1069     if ((s->fifo[n].state & 0xf) == head)
1070         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
1071 }
1072
1073 static void stellaris_adc_update(stellaris_adc_state *s)
1074 {
1075     int level;
1076     int n;
1077
1078     for (n = 0; n < 4; n++) {
1079         level = (s->ris & s->im & (1 << n)) != 0;
1080         qemu_set_irq(s->irq[n], level);
1081     }
1082 }
1083
1084 static void stellaris_adc_trigger(void *opaque, int irq, int level)
1085 {
1086     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1087     int n;
1088
1089     for (n = 0; n < 4; n++) {
1090         if ((s->actss & (1 << n)) == 0) {
1091             continue;
1092         }
1093
1094         if (((s->emux >> (n * 4)) & 0xff) != 5) {
1095             continue;
1096         }
1097
1098         /* Some applications use the ADC as a random number source, so introduce
1099            some variation into the signal.  */
1100         s->noise = s->noise * 314159 + 1;
1101         /* ??? actual inputs not implemented.  Return an arbitrary value.  */
1102         stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
1103         s->ris |= (1 << n);
1104         stellaris_adc_update(s);
1105     }
1106 }
1107
1108 static void stellaris_adc_reset(stellaris_adc_state *s)
1109 {
1110     int n;
1111
1112     for (n = 0; n < 4; n++) {
1113         s->ssmux[n] = 0;
1114         s->ssctl[n] = 0;
1115         s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1116     }
1117 }
1118
1119 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
1120                                    unsigned size)
1121 {
1122     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1123
1124     /* TODO: Implement this.  */
1125     if (offset >= 0x40 && offset < 0xc0) {
1126         int n;
1127         n = (offset - 0x40) >> 5;
1128         switch (offset & 0x1f) {
1129         case 0x00: /* SSMUX */
1130             return s->ssmux[n];
1131         case 0x04: /* SSCTL */
1132             return s->ssctl[n];
1133         case 0x08: /* SSFIFO */
1134             return stellaris_adc_fifo_read(s, n);
1135         case 0x0c: /* SSFSTAT */
1136             return s->fifo[n].state;
1137         default:
1138             break;
1139         }
1140     }
1141     switch (offset) {
1142     case 0x00: /* ACTSS */
1143         return s->actss;
1144     case 0x04: /* RIS */
1145         return s->ris;
1146     case 0x08: /* IM */
1147         return s->im;
1148     case 0x0c: /* ISC */
1149         return s->ris & s->im;
1150     case 0x10: /* OSTAT */
1151         return s->ostat;
1152     case 0x14: /* EMUX */
1153         return s->emux;
1154     case 0x18: /* USTAT */
1155         return s->ustat;
1156     case 0x20: /* SSPRI */
1157         return s->sspri;
1158     case 0x30: /* SAC */
1159         return s->sac;
1160     default:
1161         qemu_log_mask(LOG_GUEST_ERROR,
1162                       "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
1163         return 0;
1164     }
1165 }
1166
1167 static void stellaris_adc_write(void *opaque, hwaddr offset,
1168                                 uint64_t value, unsigned size)
1169 {
1170     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1171
1172     /* TODO: Implement this.  */
1173     if (offset >= 0x40 && offset < 0xc0) {
1174         int n;
1175         n = (offset - 0x40) >> 5;
1176         switch (offset & 0x1f) {
1177         case 0x00: /* SSMUX */
1178             s->ssmux[n] = value & 0x33333333;
1179             return;
1180         case 0x04: /* SSCTL */
1181             if (value != 6) {
1182                 qemu_log_mask(LOG_UNIMP,
1183                               "ADC: Unimplemented sequence %" PRIx64 "\n",
1184                               value);
1185             }
1186             s->ssctl[n] = value;
1187             return;
1188         default:
1189             break;
1190         }
1191     }
1192     switch (offset) {
1193     case 0x00: /* ACTSS */
1194         s->actss = value & 0xf;
1195         break;
1196     case 0x08: /* IM */
1197         s->im = value;
1198         break;
1199     case 0x0c: /* ISC */
1200         s->ris &= ~value;
1201         break;
1202     case 0x10: /* OSTAT */
1203         s->ostat &= ~value;
1204         break;
1205     case 0x14: /* EMUX */
1206         s->emux = value;
1207         break;
1208     case 0x18: /* USTAT */
1209         s->ustat &= ~value;
1210         break;
1211     case 0x20: /* SSPRI */
1212         s->sspri = value;
1213         break;
1214     case 0x28: /* PSSI */
1215         qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
1216         break;
1217     case 0x30: /* SAC */
1218         s->sac = value;
1219         break;
1220     default:
1221         qemu_log_mask(LOG_GUEST_ERROR,
1222                       "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
1223     }
1224     stellaris_adc_update(s);
1225 }
1226
1227 static const MemoryRegionOps stellaris_adc_ops = {
1228     .read = stellaris_adc_read,
1229     .write = stellaris_adc_write,
1230     .endianness = DEVICE_NATIVE_ENDIAN,
1231 };
1232
1233 static const VMStateDescription vmstate_stellaris_adc = {
1234     .name = "stellaris_adc",
1235     .version_id = 1,
1236     .minimum_version_id = 1,
1237     .fields = (VMStateField[]) {
1238         VMSTATE_UINT32(actss, stellaris_adc_state),
1239         VMSTATE_UINT32(ris, stellaris_adc_state),
1240         VMSTATE_UINT32(im, stellaris_adc_state),
1241         VMSTATE_UINT32(emux, stellaris_adc_state),
1242         VMSTATE_UINT32(ostat, stellaris_adc_state),
1243         VMSTATE_UINT32(ustat, stellaris_adc_state),
1244         VMSTATE_UINT32(sspri, stellaris_adc_state),
1245         VMSTATE_UINT32(sac, stellaris_adc_state),
1246         VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1247         VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1248         VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1249         VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1250         VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1251         VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1252         VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1253         VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1254         VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1255         VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1256         VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1257         VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1258         VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1259         VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1260         VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1261         VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1262         VMSTATE_UINT32(noise, stellaris_adc_state),
1263         VMSTATE_END_OF_LIST()
1264     }
1265 };
1266
1267 static void stellaris_adc_init(Object *obj)
1268 {
1269     DeviceState *dev = DEVICE(obj);
1270     stellaris_adc_state *s = STELLARIS_ADC(obj);
1271     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1272     int n;
1273
1274     for (n = 0; n < 4; n++) {
1275         sysbus_init_irq(sbd, &s->irq[n]);
1276     }
1277
1278     memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
1279                           "adc", 0x1000);
1280     sysbus_init_mmio(sbd, &s->iomem);
1281     stellaris_adc_reset(s);
1282     qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
1283 }
1284
1285 /* Board init.  */
1286 static stellaris_board_info stellaris_boards[] = {
1287   { "LM3S811EVB",
1288     0,
1289     0x0032000e,
1290     0x001f001f, /* dc0 */
1291     0x001132bf,
1292     0x01071013,
1293     0x3f0f01ff,
1294     0x0000001f,
1295     BP_OLED_I2C
1296   },
1297   { "LM3S6965EVB",
1298     0x10010002,
1299     0x1073402e,
1300     0x00ff007f, /* dc0 */
1301     0x001133ff,
1302     0x030f5317,
1303     0x0f0f87ff,
1304     0x5000007f,
1305     BP_OLED_SSI | BP_GAMEPAD
1306   }
1307 };
1308
1309 static void stellaris_init(MachineState *ms, stellaris_board_info *board)
1310 {
1311     static const int uart_irq[] = {5, 6, 33, 34};
1312     static const int timer_irq[] = {19, 21, 23, 35};
1313     static const uint32_t gpio_addr[7] =
1314       { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1315         0x40024000, 0x40025000, 0x40026000};
1316     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1317
1318     /* Memory map of SoC devices, from
1319      * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
1320      * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
1321      *
1322      * 40000000 wdtimer
1323      * 40002000 i2c (unimplemented)
1324      * 40004000 GPIO
1325      * 40005000 GPIO
1326      * 40006000 GPIO
1327      * 40007000 GPIO
1328      * 40008000 SSI
1329      * 4000c000 UART
1330      * 4000d000 UART
1331      * 4000e000 UART
1332      * 40020000 i2c
1333      * 40021000 i2c (unimplemented)
1334      * 40024000 GPIO
1335      * 40025000 GPIO
1336      * 40026000 GPIO
1337      * 40028000 PWM (unimplemented)
1338      * 4002c000 QEI (unimplemented)
1339      * 4002d000 QEI (unimplemented)
1340      * 40030000 gptimer
1341      * 40031000 gptimer
1342      * 40032000 gptimer
1343      * 40033000 gptimer
1344      * 40038000 ADC
1345      * 4003c000 analogue comparator (unimplemented)
1346      * 40048000 ethernet
1347      * 400fc000 hibernation module (unimplemented)
1348      * 400fd000 flash memory control (unimplemented)
1349      * 400fe000 system control
1350      */
1351
1352     DeviceState *gpio_dev[7], *nvic;
1353     qemu_irq gpio_in[7][8];
1354     qemu_irq gpio_out[7][8];
1355     qemu_irq adc;
1356     int sram_size;
1357     int flash_size;
1358     I2CBus *i2c;
1359     DeviceState *dev;
1360     DeviceState *ssys_dev;
1361     int i;
1362     int j;
1363
1364     MemoryRegion *sram = g_new(MemoryRegion, 1);
1365     MemoryRegion *flash = g_new(MemoryRegion, 1);
1366     MemoryRegion *system_memory = get_system_memory();
1367
1368     flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1369     sram_size = ((board->dc0 >> 18) + 1) * 1024;
1370
1371     /* Flash programming is done via the SCU, so pretend it is ROM.  */
1372     memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
1373                            &error_fatal);
1374     memory_region_add_subregion(system_memory, 0, flash);
1375
1376     memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1377                            &error_fatal);
1378     memory_region_add_subregion(system_memory, 0x20000000, sram);
1379
1380     nvic = qdev_new(TYPE_ARMV7M);
1381     qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
1382     qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
1383     qdev_prop_set_bit(nvic, "enable-bitband", true);
1384     object_property_set_link(OBJECT(nvic), "memory",
1385                              OBJECT(get_system_memory()), &error_abort);
1386     /* This will exit with an error if the user passed us a bad cpu_type */
1387     sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
1388
1389     if (board->dc1 & (1 << 16)) {
1390         dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1391                                     qdev_get_gpio_in(nvic, 14),
1392                                     qdev_get_gpio_in(nvic, 15),
1393                                     qdev_get_gpio_in(nvic, 16),
1394                                     qdev_get_gpio_in(nvic, 17),
1395                                     NULL);
1396         adc = qdev_get_gpio_in(dev, 0);
1397     } else {
1398         adc = NULL;
1399     }
1400     for (i = 0; i < 4; i++) {
1401         if (board->dc2 & (0x10000 << i)) {
1402             dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
1403                                        0x40030000 + i * 0x1000,
1404                                        qdev_get_gpio_in(nvic, timer_irq[i]));
1405             /* TODO: This is incorrect, but we get away with it because
1406                the ADC output is only ever pulsed.  */
1407             qdev_connect_gpio_out(dev, 0, adc);
1408         }
1409     }
1410
1411     ssys_dev = stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
1412                                   board, nd_table[0].macaddr.a);
1413
1414
1415     if (board->dc1 & (1 << 3)) { /* watchdog present */
1416         dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
1417
1418         qdev_connect_clock_in(dev, "WDOGCLK",
1419                               qdev_get_clock_out(ssys_dev, "SYSCLK"));
1420
1421         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1422         sysbus_mmio_map(SYS_BUS_DEVICE(dev),
1423                         0,
1424                         0x40000000u);
1425         sysbus_connect_irq(SYS_BUS_DEVICE(dev),
1426                            0,
1427                            qdev_get_gpio_in(nvic, 18));
1428     }
1429
1430
1431     for (i = 0; i < 7; i++) {
1432         if (board->dc4 & (1 << i)) {
1433             gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1434                                                qdev_get_gpio_in(nvic,
1435                                                                 gpio_irq[i]));
1436             for (j = 0; j < 8; j++) {
1437                 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1438                 gpio_out[i][j] = NULL;
1439             }
1440         }
1441     }
1442
1443     if (board->dc2 & (1 << 12)) {
1444         dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
1445                                    qdev_get_gpio_in(nvic, 8));
1446         i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1447         if (board->peripherals & BP_OLED_I2C) {
1448             i2c_slave_create_simple(i2c, "ssd0303", 0x3d);
1449         }
1450     }
1451
1452     for (i = 0; i < 4; i++) {
1453         if (board->dc2 & (1 << i)) {
1454             pl011_luminary_create(0x4000c000 + i * 0x1000,
1455                                   qdev_get_gpio_in(nvic, uart_irq[i]),
1456                                   serial_hd(i));
1457         }
1458     }
1459     if (board->dc2 & (1 << 4)) {
1460         dev = sysbus_create_simple("pl022", 0x40008000,
1461                                    qdev_get_gpio_in(nvic, 7));
1462         if (board->peripherals & BP_OLED_SSI) {
1463             void *bus;
1464             DeviceState *sddev;
1465             DeviceState *ssddev;
1466
1467             /* Some boards have both an OLED controller and SD card connected to
1468              * the same SSI port, with the SD card chip select connected to a
1469              * GPIO pin.  Technically the OLED chip select is connected to the
1470              * SSI Fss pin.  We do not bother emulating that as both devices
1471              * should never be selected simultaneously, and our OLED controller
1472              * ignores stray 0xff commands that occur when deselecting the SD
1473              * card.
1474              */
1475             bus = qdev_get_child_bus(dev, "ssi");
1476
1477             sddev = ssi_create_peripheral(bus, "ssi-sd");
1478             ssddev = ssi_create_peripheral(bus, "ssd0323");
1479             gpio_out[GPIO_D][0] = qemu_irq_split(
1480                     qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
1481                     qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1482             gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1483
1484             /* Make sure the select pin is high.  */
1485             qemu_irq_raise(gpio_out[GPIO_D][0]);
1486         }
1487     }
1488     if (board->dc4 & (1 << 28)) {
1489         DeviceState *enet;
1490
1491         qemu_check_nic_model(&nd_table[0], "stellaris");
1492
1493         enet = qdev_new("stellaris_enet");
1494         qdev_set_nic_properties(enet, &nd_table[0]);
1495         sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal);
1496         sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1497         sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1498     }
1499     if (board->peripherals & BP_GAMEPAD) {
1500         qemu_irq gpad_irq[5];
1501         static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1502
1503         gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1504         gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1505         gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1506         gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1507         gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1508
1509         stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1510     }
1511     for (i = 0; i < 7; i++) {
1512         if (board->dc4 & (1 << i)) {
1513             for (j = 0; j < 8; j++) {
1514                 if (gpio_out[i][j]) {
1515                     qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1516                 }
1517             }
1518         }
1519     }
1520
1521     /* Add dummy regions for the devices we don't implement yet,
1522      * so guest accesses don't cause unlogged crashes.
1523      */
1524     create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1525     create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1526     create_unimplemented_device("PWM", 0x40028000, 0x1000);
1527     create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1528     create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1529     create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1530     create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1531     create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1532
1533     armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size);
1534 }
1535
1536 /* FIXME: Figure out how to generate these from stellaris_boards.  */
1537 static void lm3s811evb_init(MachineState *machine)
1538 {
1539     stellaris_init(machine, &stellaris_boards[0]);
1540 }
1541
1542 static void lm3s6965evb_init(MachineState *machine)
1543 {
1544     stellaris_init(machine, &stellaris_boards[1]);
1545 }
1546
1547 static void lm3s811evb_class_init(ObjectClass *oc, void *data)
1548 {
1549     MachineClass *mc = MACHINE_CLASS(oc);
1550
1551     mc->desc = "Stellaris LM3S811EVB";
1552     mc->init = lm3s811evb_init;
1553     mc->ignore_memory_transaction_failures = true;
1554     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1555 }
1556
1557 static const TypeInfo lm3s811evb_type = {
1558     .name = MACHINE_TYPE_NAME("lm3s811evb"),
1559     .parent = TYPE_MACHINE,
1560     .class_init = lm3s811evb_class_init,
1561 };
1562
1563 static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
1564 {
1565     MachineClass *mc = MACHINE_CLASS(oc);
1566
1567     mc->desc = "Stellaris LM3S6965EVB";
1568     mc->init = lm3s6965evb_init;
1569     mc->ignore_memory_transaction_failures = true;
1570     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1571 }
1572
1573 static const TypeInfo lm3s6965evb_type = {
1574     .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1575     .parent = TYPE_MACHINE,
1576     .class_init = lm3s6965evb_class_init,
1577 };
1578
1579 static void stellaris_machine_init(void)
1580 {
1581     type_register_static(&lm3s811evb_type);
1582     type_register_static(&lm3s6965evb_type);
1583 }
1584
1585 type_init(stellaris_machine_init)
1586
1587 static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1588 {
1589     DeviceClass *dc = DEVICE_CLASS(klass);
1590
1591     dc->vmsd = &vmstate_stellaris_i2c;
1592 }
1593
1594 static const TypeInfo stellaris_i2c_info = {
1595     .name          = TYPE_STELLARIS_I2C,
1596     .parent        = TYPE_SYS_BUS_DEVICE,
1597     .instance_size = sizeof(stellaris_i2c_state),
1598     .instance_init = stellaris_i2c_init,
1599     .class_init    = stellaris_i2c_class_init,
1600 };
1601
1602 static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
1603 {
1604     DeviceClass *dc = DEVICE_CLASS(klass);
1605
1606     dc->vmsd = &vmstate_stellaris_gptm;
1607     dc->realize = stellaris_gptm_realize;
1608 }
1609
1610 static const TypeInfo stellaris_gptm_info = {
1611     .name          = TYPE_STELLARIS_GPTM,
1612     .parent        = TYPE_SYS_BUS_DEVICE,
1613     .instance_size = sizeof(gptm_state),
1614     .instance_init = stellaris_gptm_init,
1615     .class_init    = stellaris_gptm_class_init,
1616 };
1617
1618 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1619 {
1620     DeviceClass *dc = DEVICE_CLASS(klass);
1621
1622     dc->vmsd = &vmstate_stellaris_adc;
1623 }
1624
1625 static const TypeInfo stellaris_adc_info = {
1626     .name          = TYPE_STELLARIS_ADC,
1627     .parent        = TYPE_SYS_BUS_DEVICE,
1628     .instance_size = sizeof(stellaris_adc_state),
1629     .instance_init = stellaris_adc_init,
1630     .class_init    = stellaris_adc_class_init,
1631 };
1632
1633 static void stellaris_sys_class_init(ObjectClass *klass, void *data)
1634 {
1635     DeviceClass *dc = DEVICE_CLASS(klass);
1636     ResettableClass *rc = RESETTABLE_CLASS(klass);
1637
1638     dc->vmsd = &vmstate_stellaris_sys;
1639     rc->phases.enter = stellaris_sys_reset_enter;
1640     rc->phases.hold = stellaris_sys_reset_hold;
1641     rc->phases.exit = stellaris_sys_reset_exit;
1642     device_class_set_props(dc, stellaris_sys_properties);
1643 }
1644
1645 static const TypeInfo stellaris_sys_info = {
1646     .name = TYPE_STELLARIS_SYS,
1647     .parent = TYPE_SYS_BUS_DEVICE,
1648     .instance_size = sizeof(ssys_state),
1649     .instance_init = stellaris_sys_instance_init,
1650     .class_init = stellaris_sys_class_init,
1651 };
1652
1653 static void stellaris_register_types(void)
1654 {
1655     type_register_static(&stellaris_i2c_info);
1656     type_register_static(&stellaris_gptm_info);
1657     type_register_static(&stellaris_adc_info);
1658     type_register_static(&stellaris_sys_info);
1659 }
1660
1661 type_init(stellaris_register_types)