2 * ARM V2M MPS2 board emulation.
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
13 * FPGA but is otherwise the same as the 2). Since the CPU itself
14 * and most of the devices are in the FPGA, the details of the board
15 * as seen by the guest depend significantly on the FPGA image.
16 * We model the following FPGA images:
17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
18 * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
19 * "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
20 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
22 * Links to the TRM for the board itself and to the various Application
23 * Notes which document the FPGA images can be found here:
24 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
27 #include "qemu/osdep.h"
28 #include "qemu/units.h"
29 #include "qemu/cutils.h"
30 #include "qapi/error.h"
31 #include "qemu/error-report.h"
32 #include "hw/arm/boot.h"
33 #include "hw/arm/armv7m.h"
34 #include "hw/or-irq.h"
35 #include "hw/boards.h"
36 #include "exec/address-spaces.h"
37 #include "sysemu/sysemu.h"
38 #include "hw/misc/unimp.h"
39 #include "hw/char/cmsdk-apb-uart.h"
40 #include "hw/timer/cmsdk-apb-timer.h"
41 #include "hw/timer/cmsdk-apb-dualtimer.h"
42 #include "hw/misc/mps2-scc.h"
43 #include "hw/misc/mps2-fpgaio.h"
44 #include "hw/ssi/pl022.h"
45 #include "hw/i2c/arm_sbcon_i2c.h"
46 #include "hw/net/lan9118.h"
48 #include "hw/watchdog/cmsdk-apb-watchdog.h"
49 #include "hw/qdev-clock.h"
50 #include "qom/object.h"
52 typedef enum MPS2FPGAType
{
59 struct MPS2MachineClass
{
61 MPS2FPGAType fpga_type
;
68 struct MPS2MachineState
{
73 MemoryRegion ssram1_m
;
75 MemoryRegion ssram23_m
;
76 MemoryRegion blockram
;
77 MemoryRegion blockram_m1
;
78 MemoryRegion blockram_m2
;
79 MemoryRegion blockram_m3
;
81 /* FPGA APB subsystem */
84 /* CMSDK APB subsystem */
85 CMSDKAPBDualTimer dualtimer
;
86 CMSDKAPBWatchdog watchdog
;
87 CMSDKAPBTimer timer
[2];
91 #define TYPE_MPS2_MACHINE "mps2"
92 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
93 #define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386")
94 #define TYPE_MPS2_AN500_MACHINE MACHINE_TYPE_NAME("mps2-an500")
95 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
97 OBJECT_DECLARE_TYPE(MPS2MachineState
, MPS2MachineClass
, MPS2_MACHINE
)
99 /* Main SYSCLK frequency in Hz */
100 #define SYSCLK_FRQ 25000000
102 /* Initialize the auxiliary RAM region @mr and map it into
103 * the memory map at @base.
105 static void make_ram(MemoryRegion
*mr
, const char *name
,
106 hwaddr base
, hwaddr size
)
108 memory_region_init_ram(mr
, NULL
, name
, size
, &error_fatal
);
109 memory_region_add_subregion(get_system_memory(), base
, mr
);
112 /* Create an alias of an entire original MemoryRegion @orig
113 * located at @base in the memory map.
115 static void make_ram_alias(MemoryRegion
*mr
, const char *name
,
116 MemoryRegion
*orig
, hwaddr base
)
118 memory_region_init_alias(mr
, NULL
, name
, orig
, 0,
119 memory_region_size(orig
));
120 memory_region_add_subregion(get_system_memory(), base
, mr
);
123 static void mps2_common_init(MachineState
*machine
)
125 MPS2MachineState
*mms
= MPS2_MACHINE(machine
);
126 MPS2MachineClass
*mmc
= MPS2_MACHINE_GET_CLASS(machine
);
127 MemoryRegion
*system_memory
= get_system_memory();
128 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
129 DeviceState
*armv7m
, *sccdev
;
132 if (strcmp(machine
->cpu_type
, mc
->default_cpu_type
) != 0) {
133 error_report("This board can only be used with CPU %s",
134 mc
->default_cpu_type
);
138 if (machine
->ram_size
!= mc
->default_ram_size
) {
139 char *sz
= size_to_str(mc
->default_ram_size
);
140 error_report("Invalid RAM size, should be %s", sz
);
145 /* This clock doesn't need migration because it is fixed-frequency */
146 mms
->sysclk
= clock_new(OBJECT(machine
), "SYSCLK");
147 clock_set_hz(mms
->sysclk
, SYSCLK_FRQ
);
149 /* The FPGA images have an odd combination of different RAMs,
150 * because in hardware they are different implementations and
151 * connected to different buses, giving varying performance/size
152 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
153 * call the 16MB our "system memory", as it's the largest lump.
156 * 0x21000000 .. 0x21ffffff : PSRAM (16MB)
158 * 0x00000000 .. 0x003fffff : ZBT SSRAM1
159 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
160 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
161 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
163 * 0x01000000 .. 0x01003fff : block RAM (16K)
164 * 0x01004000 .. 0x01007fff : mirror of above
165 * 0x01008000 .. 0x0100bfff : mirror of above
166 * 0x0100c000 .. 0x0100ffff : mirror of above
168 * 0x00000000 .. 0x0003ffff : FPGA block RAM
169 * 0x00400000 .. 0x007fffff : ZBT SSRAM1
170 * 0x20000000 .. 0x2001ffff : SRAM
171 * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
173 * 0x60000000 .. 0x60ffffff : PSRAM (16MB)
175 * The AN385/AN386 has a feature where the lowest 16K can be mapped
176 * either to the bottom of the ZBT SSRAM1 or to the block RAM.
177 * This is of no use for QEMU so we don't implement it (as if
178 * zbt_boot_ctrl is always zero).
180 memory_region_add_subregion(system_memory
, mmc
->psram_base
, machine
->ram
);
182 if (mmc
->has_block_ram
) {
183 make_ram(&mms
->blockram
, "mps.blockram", 0x01000000, 0x4000);
184 make_ram_alias(&mms
->blockram_m1
, "mps.blockram_m1",
185 &mms
->blockram
, 0x01004000);
186 make_ram_alias(&mms
->blockram_m2
, "mps.blockram_m2",
187 &mms
->blockram
, 0x01008000);
188 make_ram_alias(&mms
->blockram_m3
, "mps.blockram_m3",
189 &mms
->blockram
, 0x0100c000);
192 switch (mmc
->fpga_type
) {
196 make_ram(&mms
->ssram1
, "mps.ssram1", 0x0, 0x400000);
197 make_ram_alias(&mms
->ssram1_m
, "mps.ssram1_m", &mms
->ssram1
, 0x400000);
198 make_ram(&mms
->ssram23
, "mps.ssram23", 0x20000000, 0x400000);
199 make_ram_alias(&mms
->ssram23_m
, "mps.ssram23_m",
200 &mms
->ssram23
, 0x20400000);
203 make_ram(&mms
->blockram
, "mps.blockram", 0x0, 0x40000);
204 make_ram(&mms
->ssram1
, "mps.ssram1", 0x00400000, 0x00800000);
205 make_ram(&mms
->sram
, "mps.sram", 0x20000000, 0x20000);
206 make_ram(&mms
->ssram23
, "mps.ssram23", 0x20400000, 0x400000);
209 g_assert_not_reached();
212 object_initialize_child(OBJECT(mms
), "armv7m", &mms
->armv7m
, TYPE_ARMV7M
);
213 armv7m
= DEVICE(&mms
->armv7m
);
214 switch (mmc
->fpga_type
) {
218 qdev_prop_set_uint32(armv7m
, "num-irq", 32);
221 qdev_prop_set_uint32(armv7m
, "num-irq", 64);
224 g_assert_not_reached();
226 qdev_prop_set_string(armv7m
, "cpu-type", machine
->cpu_type
);
227 qdev_prop_set_bit(armv7m
, "enable-bitband", true);
228 object_property_set_link(OBJECT(&mms
->armv7m
), "memory",
229 OBJECT(system_memory
), &error_abort
);
230 sysbus_realize(SYS_BUS_DEVICE(&mms
->armv7m
), &error_fatal
);
232 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
233 create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
234 create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
235 create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
236 create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
237 create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
238 /* These three ranges all cover multiple devices; we may implement
239 * some of them below (in which case the real device takes precedence
240 * over the unimplemented-region mapping).
242 create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
243 0x40000000, 0x00010000);
244 create_unimplemented_device("CMSDK AHB peripheral region @0x40010000",
245 0x40010000, 0x00010000);
246 create_unimplemented_device("Extra peripheral region @0x40020000",
247 0x40020000, 0x00010000);
249 create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
250 create_unimplemented_device("VGA", 0x41000000, 0x0200000);
252 switch (mmc
->fpga_type
) {
257 /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
258 * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
261 DeviceState
*orgate_dev
;
263 orgate
= object_new(TYPE_OR_IRQ
);
264 object_property_set_int(orgate
, "num-lines", 6, &error_fatal
);
265 qdev_realize(DEVICE(orgate
), NULL
, &error_fatal
);
266 orgate_dev
= DEVICE(orgate
);
267 qdev_connect_gpio_out(orgate_dev
, 0, qdev_get_gpio_in(armv7m
, 12));
269 for (i
= 0; i
< 5; i
++) {
270 static const hwaddr uartbase
[] = {0x40004000, 0x40005000,
271 0x40006000, 0x40007000,
273 /* RX irq number; TX irq is always one greater */
274 static const int uartirq
[] = {0, 2, 4, 18, 20};
275 qemu_irq txovrint
= NULL
, rxovrint
= NULL
;
278 txovrint
= qdev_get_gpio_in(orgate_dev
, i
* 2);
279 rxovrint
= qdev_get_gpio_in(orgate_dev
, i
* 2 + 1);
282 cmsdk_apb_uart_create(uartbase
[i
],
283 qdev_get_gpio_in(armv7m
, uartirq
[i
] + 1),
284 qdev_get_gpio_in(armv7m
, uartirq
[i
]),
287 serial_hd(i
), SYSCLK_FRQ
);
293 /* The overflow IRQs for all UARTs are ORed together.
294 * Tx and Rx IRQs for each UART are ORed together.
297 DeviceState
*orgate_dev
;
299 orgate
= object_new(TYPE_OR_IRQ
);
300 object_property_set_int(orgate
, "num-lines", 10, &error_fatal
);
301 qdev_realize(DEVICE(orgate
), NULL
, &error_fatal
);
302 orgate_dev
= DEVICE(orgate
);
303 qdev_connect_gpio_out(orgate_dev
, 0, qdev_get_gpio_in(armv7m
, 12));
305 for (i
= 0; i
< 5; i
++) {
306 /* system irq numbers for the combined tx/rx for each UART */
307 static const int uart_txrx_irqno
[] = {0, 2, 45, 46, 56};
308 static const hwaddr uartbase
[] = {0x40004000, 0x40005000,
309 0x4002c000, 0x4002d000,
312 DeviceState
*txrx_orgate_dev
;
314 txrx_orgate
= object_new(TYPE_OR_IRQ
);
315 object_property_set_int(txrx_orgate
, "num-lines", 2, &error_fatal
);
316 qdev_realize(DEVICE(txrx_orgate
), NULL
, &error_fatal
);
317 txrx_orgate_dev
= DEVICE(txrx_orgate
);
318 qdev_connect_gpio_out(txrx_orgate_dev
, 0,
319 qdev_get_gpio_in(armv7m
, uart_txrx_irqno
[i
]));
320 cmsdk_apb_uart_create(uartbase
[i
],
321 qdev_get_gpio_in(txrx_orgate_dev
, 0),
322 qdev_get_gpio_in(txrx_orgate_dev
, 1),
323 qdev_get_gpio_in(orgate_dev
, i
* 2),
324 qdev_get_gpio_in(orgate_dev
, i
* 2 + 1),
326 serial_hd(i
), SYSCLK_FRQ
);
331 g_assert_not_reached();
333 for (i
= 0; i
< 4; i
++) {
334 static const hwaddr gpiobase
[] = {0x40010000, 0x40011000,
335 0x40012000, 0x40013000};
336 create_unimplemented_device("cmsdk-ahb-gpio", gpiobase
[i
], 0x1000);
339 /* CMSDK APB subsystem */
340 for (i
= 0; i
< ARRAY_SIZE(mms
->timer
); i
++) {
341 g_autofree
char *name
= g_strdup_printf("timer%d", i
);
342 hwaddr base
= 0x40000000 + i
* 0x1000;
346 object_initialize_child(OBJECT(mms
), name
, &mms
->timer
[i
],
347 TYPE_CMSDK_APB_TIMER
);
348 sbd
= SYS_BUS_DEVICE(&mms
->timer
[i
]);
349 qdev_connect_clock_in(DEVICE(&mms
->timer
[i
]), "pclk", mms
->sysclk
);
350 sysbus_realize_and_unref(sbd
, &error_fatal
);
351 sysbus_mmio_map(sbd
, 0, base
);
352 sysbus_connect_irq(sbd
, 0, qdev_get_gpio_in(armv7m
, irqno
));
355 object_initialize_child(OBJECT(mms
), "dualtimer", &mms
->dualtimer
,
356 TYPE_CMSDK_APB_DUALTIMER
);
357 qdev_connect_clock_in(DEVICE(&mms
->dualtimer
), "TIMCLK", mms
->sysclk
);
358 sysbus_realize(SYS_BUS_DEVICE(&mms
->dualtimer
), &error_fatal
);
359 sysbus_connect_irq(SYS_BUS_DEVICE(&mms
->dualtimer
), 0,
360 qdev_get_gpio_in(armv7m
, 10));
361 sysbus_mmio_map(SYS_BUS_DEVICE(&mms
->dualtimer
), 0, 0x40002000);
362 object_initialize_child(OBJECT(mms
), "watchdog", &mms
->watchdog
,
363 TYPE_CMSDK_APB_WATCHDOG
);
364 qdev_connect_clock_in(DEVICE(&mms
->watchdog
), "WDOGCLK", mms
->sysclk
);
365 sysbus_realize(SYS_BUS_DEVICE(&mms
->watchdog
), &error_fatal
);
366 sysbus_connect_irq(SYS_BUS_DEVICE(&mms
->watchdog
), 0,
367 qdev_get_gpio_in_named(armv7m
, "NMI", 0));
368 sysbus_mmio_map(SYS_BUS_DEVICE(&mms
->watchdog
), 0, 0x40008000);
370 /* FPGA APB subsystem */
371 object_initialize_child(OBJECT(mms
), "scc", &mms
->scc
, TYPE_MPS2_SCC
);
372 sccdev
= DEVICE(&mms
->scc
);
373 qdev_prop_set_uint32(sccdev
, "scc-cfg4", 0x2);
374 qdev_prop_set_uint32(sccdev
, "scc-aid", 0x00200008);
375 qdev_prop_set_uint32(sccdev
, "scc-id", mmc
->scc_id
);
376 sysbus_realize(SYS_BUS_DEVICE(&mms
->scc
), &error_fatal
);
377 sysbus_mmio_map(SYS_BUS_DEVICE(sccdev
), 0, 0x4002f000);
378 object_initialize_child(OBJECT(mms
), "fpgaio",
379 &mms
->fpgaio
, TYPE_MPS2_FPGAIO
);
380 qdev_prop_set_uint32(DEVICE(&mms
->fpgaio
), "prescale-clk", 25000000);
381 sysbus_realize(SYS_BUS_DEVICE(&mms
->fpgaio
), &error_fatal
);
382 sysbus_mmio_map(SYS_BUS_DEVICE(&mms
->fpgaio
), 0, 0x40028000);
383 sysbus_create_simple(TYPE_PL022
, 0x40025000, /* External ADC */
384 qdev_get_gpio_in(armv7m
, 22));
385 for (i
= 0; i
< 2; i
++) {
386 static const int spi_irqno
[] = {11, 24};
387 static const hwaddr spibase
[] = {0x40020000, /* APB */
388 0x40021000, /* LCD */
389 0x40026000, /* Shield0 */
390 0x40027000}; /* Shield1 */
391 DeviceState
*orgate_dev
;
395 orgate
= object_new(TYPE_OR_IRQ
);
396 object_property_set_int(orgate
, "num-lines", 2, &error_fatal
);
397 orgate_dev
= DEVICE(orgate
);
398 qdev_realize(orgate_dev
, NULL
, &error_fatal
);
399 qdev_connect_gpio_out(orgate_dev
, 0,
400 qdev_get_gpio_in(armv7m
, spi_irqno
[i
]));
401 for (j
= 0; j
< 2; j
++) {
402 sysbus_create_simple(TYPE_PL022
, spibase
[2 * i
+ j
],
403 qdev_get_gpio_in(orgate_dev
, j
));
406 for (i
= 0; i
< 4; i
++) {
407 static const hwaddr i2cbase
[] = {0x40022000, /* Touch */
408 0x40023000, /* Audio */
409 0x40029000, /* Shield0 */
410 0x4002a000}; /* Shield1 */
411 sysbus_create_simple(TYPE_ARM_SBCON_I2C
, i2cbase
[i
], NULL
);
413 create_unimplemented_device("i2s", 0x40024000, 0x400);
415 /* In hardware this is a LAN9220; the LAN9118 is software compatible
416 * except that it doesn't support the checksum-offload feature.
418 lan9118_init(&nd_table
[0], mmc
->ethernet_base
,
419 qdev_get_gpio_in(armv7m
,
420 mmc
->fpga_type
== FPGA_AN511
? 47 : 13));
422 system_clock_scale
= NANOSECONDS_PER_SECOND
/ SYSCLK_FRQ
;
424 armv7m_load_kernel(ARM_CPU(first_cpu
), machine
->kernel_filename
,
428 static void mps2_class_init(ObjectClass
*oc
, void *data
)
430 MachineClass
*mc
= MACHINE_CLASS(oc
);
432 mc
->init
= mps2_common_init
;
434 mc
->default_ram_size
= 16 * MiB
;
435 mc
->default_ram_id
= "mps.ram";
438 static void mps2_an385_class_init(ObjectClass
*oc
, void *data
)
440 MachineClass
*mc
= MACHINE_CLASS(oc
);
441 MPS2MachineClass
*mmc
= MPS2_MACHINE_CLASS(oc
);
443 mc
->desc
= "ARM MPS2 with AN385 FPGA image for Cortex-M3";
444 mmc
->fpga_type
= FPGA_AN385
;
445 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
446 mmc
->scc_id
= 0x41043850;
447 mmc
->psram_base
= 0x21000000;
448 mmc
->ethernet_base
= 0x40200000;
449 mmc
->has_block_ram
= true;
452 static void mps2_an386_class_init(ObjectClass
*oc
, void *data
)
454 MachineClass
*mc
= MACHINE_CLASS(oc
);
455 MPS2MachineClass
*mmc
= MPS2_MACHINE_CLASS(oc
);
457 mc
->desc
= "ARM MPS2 with AN386 FPGA image for Cortex-M4";
458 mmc
->fpga_type
= FPGA_AN386
;
459 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m4");
460 mmc
->scc_id
= 0x41043860;
461 mmc
->psram_base
= 0x21000000;
462 mmc
->ethernet_base
= 0x40200000;
463 mmc
->has_block_ram
= true;
466 static void mps2_an500_class_init(ObjectClass
*oc
, void *data
)
468 MachineClass
*mc
= MACHINE_CLASS(oc
);
469 MPS2MachineClass
*mmc
= MPS2_MACHINE_CLASS(oc
);
471 mc
->desc
= "ARM MPS2 with AN500 FPGA image for Cortex-M7";
472 mmc
->fpga_type
= FPGA_AN500
;
473 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m7");
474 mmc
->scc_id
= 0x41045000;
475 mmc
->psram_base
= 0x60000000;
476 mmc
->ethernet_base
= 0xa0000000;
477 mmc
->has_block_ram
= false;
480 static void mps2_an511_class_init(ObjectClass
*oc
, void *data
)
482 MachineClass
*mc
= MACHINE_CLASS(oc
);
483 MPS2MachineClass
*mmc
= MPS2_MACHINE_CLASS(oc
);
485 mc
->desc
= "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
486 mmc
->fpga_type
= FPGA_AN511
;
487 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
488 mmc
->scc_id
= 0x41045110;
489 mmc
->psram_base
= 0x21000000;
490 mmc
->ethernet_base
= 0x40200000;
491 mmc
->has_block_ram
= false;
494 static const TypeInfo mps2_info
= {
495 .name
= TYPE_MPS2_MACHINE
,
496 .parent
= TYPE_MACHINE
,
498 .instance_size
= sizeof(MPS2MachineState
),
499 .class_size
= sizeof(MPS2MachineClass
),
500 .class_init
= mps2_class_init
,
503 static const TypeInfo mps2_an385_info
= {
504 .name
= TYPE_MPS2_AN385_MACHINE
,
505 .parent
= TYPE_MPS2_MACHINE
,
506 .class_init
= mps2_an385_class_init
,
509 static const TypeInfo mps2_an386_info
= {
510 .name
= TYPE_MPS2_AN386_MACHINE
,
511 .parent
= TYPE_MPS2_MACHINE
,
512 .class_init
= mps2_an386_class_init
,
515 static const TypeInfo mps2_an500_info
= {
516 .name
= TYPE_MPS2_AN500_MACHINE
,
517 .parent
= TYPE_MPS2_MACHINE
,
518 .class_init
= mps2_an500_class_init
,
521 static const TypeInfo mps2_an511_info
= {
522 .name
= TYPE_MPS2_AN511_MACHINE
,
523 .parent
= TYPE_MPS2_MACHINE
,
524 .class_init
= mps2_an511_class_init
,
527 static void mps2_machine_init(void)
529 type_register_static(&mps2_info
);
530 type_register_static(&mps2_an385_info
);
531 type_register_static(&mps2_an386_info
);
532 type_register_static(&mps2_an500_info
);
533 type_register_static(&mps2_an511_info
);
536 type_init(mps2_machine_init
);