2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
23 #include "qemu/host-utils.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "sysemu/kvm.h"
29 /*****************************************************************************/
30 /* Exceptions processing helpers */
32 void helper_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
35 do_raise_exception_err(env
, exception
, error_code
, 0);
38 void helper_raise_exception(CPUMIPSState
*env
, uint32_t exception
)
40 do_raise_exception(env
, exception
, GETPC());
43 void helper_raise_exception_debug(CPUMIPSState
*env
)
45 do_raise_exception(env
, EXCP_DEBUG
, 0);
48 static void raise_exception(CPUMIPSState
*env
, uint32_t exception
)
50 do_raise_exception(env
, exception
, 0);
53 #if defined(CONFIG_USER_ONLY)
54 #define HELPER_LD(name, insn, type) \
55 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
56 int mem_idx, uintptr_t retaddr) \
58 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
61 #define HELPER_LD(name, insn, type) \
62 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
63 int mem_idx, uintptr_t retaddr) \
67 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
68 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
70 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
71 case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr); \
75 HELPER_LD(lw
, ldl
, int32_t)
76 #if defined(TARGET_MIPS64)
77 HELPER_LD(ld
, ldq
, int64_t)
81 #if defined(CONFIG_USER_ONLY)
82 #define HELPER_ST(name, insn, type) \
83 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
84 type val, int mem_idx, uintptr_t retaddr) \
86 cpu_##insn##_data_ra(env, addr, val, retaddr); \
89 #define HELPER_ST(name, insn, type) \
90 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
91 type val, int mem_idx, uintptr_t retaddr) \
95 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
96 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
98 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
100 cpu_##insn##_error_ra(env, addr, val, retaddr); \
105 HELPER_ST(sb
, stb
, uint8_t)
106 HELPER_ST(sw
, stl
, uint32_t)
107 #if defined(TARGET_MIPS64)
108 HELPER_ST(sd
, stq
, uint64_t)
112 /* 64 bits arithmetic for 32 bits hosts */
113 static inline uint64_t get_HILO(CPUMIPSState
*env
)
115 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) | (uint32_t)env
->active_tc
.LO
[0];
118 static inline target_ulong
set_HIT0_LO(CPUMIPSState
*env
, uint64_t HILO
)
120 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
121 return env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
124 static inline target_ulong
set_HI_LOT0(CPUMIPSState
*env
, uint64_t HILO
)
126 target_ulong tmp
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
127 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
131 /* Multiplication variants of the vr54xx. */
132 target_ulong
helper_muls(CPUMIPSState
*env
, target_ulong arg1
,
135 return set_HI_LOT0(env
, 0 - ((int64_t)(int32_t)arg1
*
136 (int64_t)(int32_t)arg2
));
139 target_ulong
helper_mulsu(CPUMIPSState
*env
, target_ulong arg1
,
142 return set_HI_LOT0(env
, 0 - (uint64_t)(uint32_t)arg1
*
143 (uint64_t)(uint32_t)arg2
);
146 target_ulong
helper_macc(CPUMIPSState
*env
, target_ulong arg1
,
149 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
150 (int64_t)(int32_t)arg2
);
153 target_ulong
helper_macchi(CPUMIPSState
*env
, target_ulong arg1
,
156 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
157 (int64_t)(int32_t)arg2
);
160 target_ulong
helper_maccu(CPUMIPSState
*env
, target_ulong arg1
,
163 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) +
164 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
167 target_ulong
helper_macchiu(CPUMIPSState
*env
, target_ulong arg1
,
170 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) +
171 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
174 target_ulong
helper_msac(CPUMIPSState
*env
, target_ulong arg1
,
177 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
178 (int64_t)(int32_t)arg2
);
181 target_ulong
helper_msachi(CPUMIPSState
*env
, target_ulong arg1
,
184 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
185 (int64_t)(int32_t)arg2
);
188 target_ulong
helper_msacu(CPUMIPSState
*env
, target_ulong arg1
,
191 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) -
192 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
195 target_ulong
helper_msachiu(CPUMIPSState
*env
, target_ulong arg1
,
198 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) -
199 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
202 target_ulong
helper_mulhi(CPUMIPSState
*env
, target_ulong arg1
,
205 return set_HIT0_LO(env
, (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
208 target_ulong
helper_mulhiu(CPUMIPSState
*env
, target_ulong arg1
,
211 return set_HIT0_LO(env
, (uint64_t)(uint32_t)arg1
*
212 (uint64_t)(uint32_t)arg2
);
215 target_ulong
helper_mulshi(CPUMIPSState
*env
, target_ulong arg1
,
218 return set_HIT0_LO(env
, 0 - (int64_t)(int32_t)arg1
*
219 (int64_t)(int32_t)arg2
);
222 target_ulong
helper_mulshiu(CPUMIPSState
*env
, target_ulong arg1
,
225 return set_HIT0_LO(env
, 0 - (uint64_t)(uint32_t)arg1
*
226 (uint64_t)(uint32_t)arg2
);
229 static inline target_ulong
bitswap(target_ulong v
)
231 v
= ((v
>> 1) & (target_ulong
)0x5555555555555555ULL
) |
232 ((v
& (target_ulong
)0x5555555555555555ULL
) << 1);
233 v
= ((v
>> 2) & (target_ulong
)0x3333333333333333ULL
) |
234 ((v
& (target_ulong
)0x3333333333333333ULL
) << 2);
235 v
= ((v
>> 4) & (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) |
236 ((v
& (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) << 4);
241 target_ulong
helper_dbitswap(target_ulong rt
)
247 target_ulong
helper_bitswap(target_ulong rt
)
249 return (int32_t)bitswap(rt
);
252 target_ulong
helper_rotx(target_ulong rs
, uint32_t shift
, uint32_t shiftx
,
256 uint64_t tmp0
= ((uint64_t)rs
) << 32 | ((uint64_t)rs
& 0xffffffff);
257 uint64_t tmp1
= tmp0
;
258 for (i
= 0; i
<= 46; i
++) {
266 if (stripe
!= 0 && !(i
& 0x4)) {
270 if (tmp0
& (1LL << (i
+ 16))) {
278 uint64_t tmp2
= tmp1
;
279 for (i
= 0; i
<= 38; i
++) {
288 if (tmp1
& (1LL << (i
+ 8))) {
296 uint64_t tmp3
= tmp2
;
297 for (i
= 0; i
<= 34; i
++) {
305 if (tmp2
& (1LL << (i
+ 4))) {
313 uint64_t tmp4
= tmp3
;
314 for (i
= 0; i
<= 32; i
++) {
322 if (tmp3
& (1LL << (i
+ 2))) {
330 uint64_t tmp5
= tmp4
;
331 for (i
= 0; i
<= 31; i
++) {
335 if (tmp4
& (1LL << (i
+ 1))) {
343 return (int64_t)(int32_t)(uint32_t)tmp5
;
346 #ifndef CONFIG_USER_ONLY
348 static inline hwaddr
do_translate_address(CPUMIPSState
*env
,
349 target_ulong address
,
350 int rw
, uintptr_t retaddr
)
353 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
355 lladdr
= cpu_mips_translate_address(env
, address
, rw
);
357 if (lladdr
== -1LL) {
358 cpu_loop_exit_restore(cs
, retaddr
);
364 #define HELPER_LD_ATOMIC(name, insn, almask) \
365 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
367 if (arg & almask) { \
368 if (!(env->hflags & MIPS_HFLAG_DM)) { \
369 env->CP0_BadVAddr = arg; \
371 do_raise_exception(env, EXCP_AdEL, GETPC()); \
373 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
374 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
377 HELPER_LD_ATOMIC(ll
, lw
, 0x3)
379 HELPER_LD_ATOMIC(lld
, ld
, 0x7)
381 #undef HELPER_LD_ATOMIC
383 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
384 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
385 target_ulong arg2, int mem_idx) \
389 if (arg2 & almask) { \
390 if (!(env->hflags & MIPS_HFLAG_DM)) { \
391 env->CP0_BadVAddr = arg2; \
393 do_raise_exception(env, EXCP_AdES, GETPC()); \
395 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
396 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
397 if (tmp == env->llval) { \
398 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
404 HELPER_ST_ATOMIC(sc
, lw
, sw
, 0x3)
406 HELPER_ST_ATOMIC(scd
, ld
, sd
, 0x7)
408 #undef HELPER_ST_ATOMIC
411 #ifdef TARGET_WORDS_BIGENDIAN
412 #define GET_LMASK(v) ((v) & 3)
413 #define GET_OFFSET(addr, offset) (addr + (offset))
415 #define GET_LMASK(v) (((v) & 3) ^ 3)
416 #define GET_OFFSET(addr, offset) (addr - (offset))
419 void helper_swl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
422 do_sb(env
, arg2
, (uint8_t)(arg1
>> 24), mem_idx
, GETPC());
424 if (GET_LMASK(arg2
) <= 2) {
425 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16), mem_idx
,
429 if (GET_LMASK(arg2
) <= 1) {
430 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8), mem_idx
,
434 if (GET_LMASK(arg2
) == 0) {
435 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)arg1
, mem_idx
,
440 void helper_swr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
443 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
445 if (GET_LMASK(arg2
) >= 1) {
446 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
450 if (GET_LMASK(arg2
) >= 2) {
451 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
455 if (GET_LMASK(arg2
) == 3) {
456 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
461 #if defined(TARGET_MIPS64)
462 /* "half" load and stores. We must do the memory access inline,
463 or fault handling won't work. */
465 #ifdef TARGET_WORDS_BIGENDIAN
466 #define GET_LMASK64(v) ((v) & 7)
468 #define GET_LMASK64(v) (((v) & 7) ^ 7)
471 void helper_sdl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
474 do_sb(env
, arg2
, (uint8_t)(arg1
>> 56), mem_idx
, GETPC());
476 if (GET_LMASK64(arg2
) <= 6) {
477 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48), mem_idx
,
481 if (GET_LMASK64(arg2
) <= 5) {
482 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40), mem_idx
,
486 if (GET_LMASK64(arg2
) <= 4) {
487 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32), mem_idx
,
491 if (GET_LMASK64(arg2
) <= 3) {
492 do_sb(env
, GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24), mem_idx
,
496 if (GET_LMASK64(arg2
) <= 2) {
497 do_sb(env
, GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16), mem_idx
,
501 if (GET_LMASK64(arg2
) <= 1) {
502 do_sb(env
, GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8), mem_idx
,
506 if (GET_LMASK64(arg2
) <= 0) {
507 do_sb(env
, GET_OFFSET(arg2
, 7), (uint8_t)arg1
, mem_idx
,
512 void helper_sdr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
515 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
517 if (GET_LMASK64(arg2
) >= 1) {
518 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
522 if (GET_LMASK64(arg2
) >= 2) {
523 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
527 if (GET_LMASK64(arg2
) >= 3) {
528 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
532 if (GET_LMASK64(arg2
) >= 4) {
533 do_sb(env
, GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32), mem_idx
,
537 if (GET_LMASK64(arg2
) >= 5) {
538 do_sb(env
, GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40), mem_idx
,
542 if (GET_LMASK64(arg2
) >= 6) {
543 do_sb(env
, GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48), mem_idx
,
547 if (GET_LMASK64(arg2
) == 7) {
548 do_sb(env
, GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56), mem_idx
,
552 #endif /* TARGET_MIPS64 */
554 static const int multiple_regs
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
556 void helper_lwm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
559 target_ulong base_reglist
= reglist
& 0xf;
560 target_ulong do_r31
= reglist
& 0x10;
562 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
565 for (i
= 0; i
< base_reglist
; i
++) {
566 env
->active_tc
.gpr
[multiple_regs
[i
]] =
567 (target_long
)do_lw(env
, addr
, mem_idx
, GETPC());
573 env
->active_tc
.gpr
[31] = (target_long
)do_lw(env
, addr
, mem_idx
,
578 void helper_swm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
581 target_ulong base_reglist
= reglist
& 0xf;
582 target_ulong do_r31
= reglist
& 0x10;
584 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
587 for (i
= 0; i
< base_reglist
; i
++) {
588 do_sw(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
595 do_sw(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
599 #if defined(TARGET_MIPS64)
600 void helper_ldm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
603 target_ulong base_reglist
= reglist
& 0xf;
604 target_ulong do_r31
= reglist
& 0x10;
606 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
609 for (i
= 0; i
< base_reglist
; i
++) {
610 env
->active_tc
.gpr
[multiple_regs
[i
]] = do_ld(env
, addr
, mem_idx
,
617 env
->active_tc
.gpr
[31] = do_ld(env
, addr
, mem_idx
, GETPC());
621 void helper_sdm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
624 target_ulong base_reglist
= reglist
& 0xf;
625 target_ulong do_r31
= reglist
& 0x10;
627 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
630 for (i
= 0; i
< base_reglist
; i
++) {
631 do_sd(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
638 do_sd(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
643 #ifndef CONFIG_USER_ONLY
645 static bool mips_vpe_is_wfi(MIPSCPU
*c
)
647 CPUState
*cpu
= CPU(c
);
648 CPUMIPSState
*env
= &c
->env
;
650 /* If the VPE is halted but otherwise active, it means it's waiting for
652 return cpu
->halted
&& mips_vpe_active(env
);
655 static bool mips_vp_is_wfi(MIPSCPU
*c
)
657 CPUState
*cpu
= CPU(c
);
658 CPUMIPSState
*env
= &c
->env
;
660 return cpu
->halted
&& mips_vp_active(env
);
663 static inline void mips_vpe_wake(MIPSCPU
*c
)
665 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
666 because there might be other conditions that state that c should
668 cpu_interrupt(CPU(c
), CPU_INTERRUPT_WAKE
);
671 static inline void mips_vpe_sleep(MIPSCPU
*cpu
)
673 CPUState
*cs
= CPU(cpu
);
675 /* The VPE was shut off, really go to bed.
676 Reset any old _WAKE requests. */
678 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
681 static inline void mips_tc_wake(MIPSCPU
*cpu
, int tc
)
683 CPUMIPSState
*c
= &cpu
->env
;
685 /* FIXME: TC reschedule. */
686 if (mips_vpe_active(c
) && !mips_vpe_is_wfi(cpu
)) {
691 static inline void mips_tc_sleep(MIPSCPU
*cpu
, int tc
)
693 CPUMIPSState
*c
= &cpu
->env
;
695 /* FIXME: TC reschedule. */
696 if (!mips_vpe_active(c
)) {
703 * @env: CPU from which mapping is performed.
704 * @tc: Should point to an int with the value of the global TC index.
706 * This function will transform @tc into a local index within the
707 * returned #CPUMIPSState.
709 /* FIXME: This code assumes that all VPEs have the same number of TCs,
710 which depends on runtime setup. Can probably be fixed by
711 walking the list of CPUMIPSStates. */
712 static CPUMIPSState
*mips_cpu_map_tc(CPUMIPSState
*env
, int *tc
)
720 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))) {
721 /* Not allowed to address other CPUs. */
722 *tc
= env
->current_tc
;
726 cs
= CPU(mips_env_get_cpu(env
));
727 vpe_idx
= tc_idx
/ cs
->nr_threads
;
728 *tc
= tc_idx
% cs
->nr_threads
;
729 other_cs
= qemu_get_cpu(vpe_idx
);
730 if (other_cs
== NULL
) {
733 cpu
= MIPS_CPU(other_cs
);
737 /* The per VPE CP0_Status register shares some fields with the per TC
738 CP0_TCStatus registers. These fields are wired to the same registers,
739 so changes to either of them should be reflected on both registers.
741 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
743 These helper call synchronizes the regs for a given cpu. */
745 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
746 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
749 /* Called for updates to CP0_TCStatus. */
750 static void sync_c0_tcstatus(CPUMIPSState
*cpu
, int tc
,
754 uint32_t tcu
, tmx
, tasid
, tksu
;
755 uint32_t mask
= ((1U << CP0St_CU3
)
762 tcu
= (v
>> CP0TCSt_TCU0
) & 0xf;
763 tmx
= (v
>> CP0TCSt_TMX
) & 0x1;
764 tasid
= v
& cpu
->CP0_EntryHi_ASID_mask
;
765 tksu
= (v
>> CP0TCSt_TKSU
) & 0x3;
767 status
= tcu
<< CP0St_CU0
;
768 status
|= tmx
<< CP0St_MX
;
769 status
|= tksu
<< CP0St_KSU
;
771 cpu
->CP0_Status
&= ~mask
;
772 cpu
->CP0_Status
|= status
;
774 /* Sync the TASID with EntryHi. */
775 cpu
->CP0_EntryHi
&= ~cpu
->CP0_EntryHi_ASID_mask
;
776 cpu
->CP0_EntryHi
|= tasid
;
781 /* Called for updates to CP0_EntryHi. */
782 static void sync_c0_entryhi(CPUMIPSState
*cpu
, int tc
)
785 uint32_t asid
, v
= cpu
->CP0_EntryHi
;
787 asid
= v
& cpu
->CP0_EntryHi_ASID_mask
;
789 if (tc
== cpu
->current_tc
) {
790 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
792 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
795 *tcst
&= ~cpu
->CP0_EntryHi_ASID_mask
;
800 target_ulong
helper_mfc0_mvpcontrol(CPUMIPSState
*env
)
802 return env
->mvp
->CP0_MVPControl
;
805 target_ulong
helper_mfc0_mvpconf0(CPUMIPSState
*env
)
807 return env
->mvp
->CP0_MVPConf0
;
810 target_ulong
helper_mfc0_mvpconf1(CPUMIPSState
*env
)
812 return env
->mvp
->CP0_MVPConf1
;
815 target_ulong
helper_mfc0_random(CPUMIPSState
*env
)
817 return (int32_t)cpu_mips_get_random(env
);
820 target_ulong
helper_mfc0_tcstatus(CPUMIPSState
*env
)
822 return env
->active_tc
.CP0_TCStatus
;
825 target_ulong
helper_mftc0_tcstatus(CPUMIPSState
*env
)
827 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
828 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
830 if (other_tc
== other
->current_tc
)
831 return other
->active_tc
.CP0_TCStatus
;
833 return other
->tcs
[other_tc
].CP0_TCStatus
;
836 target_ulong
helper_mfc0_tcbind(CPUMIPSState
*env
)
838 return env
->active_tc
.CP0_TCBind
;
841 target_ulong
helper_mftc0_tcbind(CPUMIPSState
*env
)
843 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
844 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
846 if (other_tc
== other
->current_tc
)
847 return other
->active_tc
.CP0_TCBind
;
849 return other
->tcs
[other_tc
].CP0_TCBind
;
852 target_ulong
helper_mfc0_tcrestart(CPUMIPSState
*env
)
854 return env
->active_tc
.PC
;
857 target_ulong
helper_mftc0_tcrestart(CPUMIPSState
*env
)
859 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
860 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
862 if (other_tc
== other
->current_tc
)
863 return other
->active_tc
.PC
;
865 return other
->tcs
[other_tc
].PC
;
868 target_ulong
helper_mfc0_tchalt(CPUMIPSState
*env
)
870 return env
->active_tc
.CP0_TCHalt
;
873 target_ulong
helper_mftc0_tchalt(CPUMIPSState
*env
)
875 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
876 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
878 if (other_tc
== other
->current_tc
)
879 return other
->active_tc
.CP0_TCHalt
;
881 return other
->tcs
[other_tc
].CP0_TCHalt
;
884 target_ulong
helper_mfc0_tccontext(CPUMIPSState
*env
)
886 return env
->active_tc
.CP0_TCContext
;
889 target_ulong
helper_mftc0_tccontext(CPUMIPSState
*env
)
891 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
892 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
894 if (other_tc
== other
->current_tc
)
895 return other
->active_tc
.CP0_TCContext
;
897 return other
->tcs
[other_tc
].CP0_TCContext
;
900 target_ulong
helper_mfc0_tcschedule(CPUMIPSState
*env
)
902 return env
->active_tc
.CP0_TCSchedule
;
905 target_ulong
helper_mftc0_tcschedule(CPUMIPSState
*env
)
907 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
908 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
910 if (other_tc
== other
->current_tc
)
911 return other
->active_tc
.CP0_TCSchedule
;
913 return other
->tcs
[other_tc
].CP0_TCSchedule
;
916 target_ulong
helper_mfc0_tcschefback(CPUMIPSState
*env
)
918 return env
->active_tc
.CP0_TCScheFBack
;
921 target_ulong
helper_mftc0_tcschefback(CPUMIPSState
*env
)
923 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
924 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
926 if (other_tc
== other
->current_tc
)
927 return other
->active_tc
.CP0_TCScheFBack
;
929 return other
->tcs
[other_tc
].CP0_TCScheFBack
;
932 target_ulong
helper_mfc0_count(CPUMIPSState
*env
)
935 qemu_mutex_lock_iothread();
936 count
= (int32_t) cpu_mips_get_count(env
);
937 qemu_mutex_unlock_iothread();
941 target_ulong
helper_mftc0_entryhi(CPUMIPSState
*env
)
943 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
944 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
946 return other
->CP0_EntryHi
;
949 target_ulong
helper_mftc0_cause(CPUMIPSState
*env
)
951 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
953 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
955 if (other_tc
== other
->current_tc
) {
956 tccause
= other
->CP0_Cause
;
958 tccause
= other
->CP0_Cause
;
964 target_ulong
helper_mftc0_status(CPUMIPSState
*env
)
966 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
967 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
969 return other
->CP0_Status
;
972 target_ulong
helper_mfc0_lladdr(CPUMIPSState
*env
)
974 return (int32_t)(env
->lladdr
>> env
->CP0_LLAddr_shift
);
977 target_ulong
helper_mfc0_maar(CPUMIPSState
*env
)
979 return (int32_t) env
->CP0_MAAR
[env
->CP0_MAARI
];
982 target_ulong
helper_mfhc0_maar(CPUMIPSState
*env
)
984 return env
->CP0_MAAR
[env
->CP0_MAARI
] >> 32;
987 target_ulong
helper_mfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
989 return (int32_t)env
->CP0_WatchLo
[sel
];
992 target_ulong
helper_mfc0_watchhi(CPUMIPSState
*env
, uint32_t sel
)
994 return env
->CP0_WatchHi
[sel
];
997 target_ulong
helper_mfc0_debug(CPUMIPSState
*env
)
999 target_ulong t0
= env
->CP0_Debug
;
1000 if (env
->hflags
& MIPS_HFLAG_DM
)
1001 t0
|= 1 << CP0DB_DM
;
1006 target_ulong
helper_mftc0_debug(CPUMIPSState
*env
)
1008 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1010 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1012 if (other_tc
== other
->current_tc
)
1013 tcstatus
= other
->active_tc
.CP0_Debug_tcstatus
;
1015 tcstatus
= other
->tcs
[other_tc
].CP0_Debug_tcstatus
;
1017 /* XXX: Might be wrong, check with EJTAG spec. */
1018 return (other
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1019 (tcstatus
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1022 #if defined(TARGET_MIPS64)
1023 target_ulong
helper_dmfc0_tcrestart(CPUMIPSState
*env
)
1025 return env
->active_tc
.PC
;
1028 target_ulong
helper_dmfc0_tchalt(CPUMIPSState
*env
)
1030 return env
->active_tc
.CP0_TCHalt
;
1033 target_ulong
helper_dmfc0_tccontext(CPUMIPSState
*env
)
1035 return env
->active_tc
.CP0_TCContext
;
1038 target_ulong
helper_dmfc0_tcschedule(CPUMIPSState
*env
)
1040 return env
->active_tc
.CP0_TCSchedule
;
1043 target_ulong
helper_dmfc0_tcschefback(CPUMIPSState
*env
)
1045 return env
->active_tc
.CP0_TCScheFBack
;
1048 target_ulong
helper_dmfc0_lladdr(CPUMIPSState
*env
)
1050 return env
->lladdr
>> env
->CP0_LLAddr_shift
;
1053 target_ulong
helper_dmfc0_maar(CPUMIPSState
*env
)
1055 return env
->CP0_MAAR
[env
->CP0_MAARI
];
1058 target_ulong
helper_dmfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
1060 return env
->CP0_WatchLo
[sel
];
1062 #endif /* TARGET_MIPS64 */
1064 void helper_mtc0_index(CPUMIPSState
*env
, target_ulong arg1
)
1066 uint32_t index_p
= env
->CP0_Index
& 0x80000000;
1067 uint32_t tlb_index
= arg1
& 0x7fffffff;
1068 if (tlb_index
< env
->tlb
->nb_tlb
) {
1069 if (env
->insn_flags
& ISA_MIPS32R6
) {
1070 index_p
|= arg1
& 0x80000000;
1072 env
->CP0_Index
= index_p
| tlb_index
;
1076 void helper_mtc0_mvpcontrol(CPUMIPSState
*env
, target_ulong arg1
)
1081 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
1082 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
1083 (1 << CP0MVPCo_EVP
);
1084 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1085 mask
|= (1 << CP0MVPCo_STLB
);
1086 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (arg1
& mask
);
1088 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1090 env
->mvp
->CP0_MVPControl
= newval
;
1093 void helper_mtc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1098 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1099 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1100 newval
= (env
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1102 /* Yield scheduler intercept not implemented. */
1103 /* Gating storage scheduler intercept not implemented. */
1105 // TODO: Enable/disable TCs.
1107 env
->CP0_VPEControl
= newval
;
1110 void helper_mttc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1112 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1113 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1117 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1118 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1119 newval
= (other
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1121 /* TODO: Enable/disable TCs. */
1123 other
->CP0_VPEControl
= newval
;
1126 target_ulong
helper_mftc0_vpecontrol(CPUMIPSState
*env
)
1128 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1129 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1130 /* FIXME: Mask away return zero on read bits. */
1131 return other
->CP0_VPEControl
;
1134 target_ulong
helper_mftc0_vpeconf0(CPUMIPSState
*env
)
1136 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1137 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1139 return other
->CP0_VPEConf0
;
1142 void helper_mtc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1147 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
1148 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
1149 mask
|= (0xff << CP0VPEC0_XTC
);
1150 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1152 newval
= (env
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1154 // TODO: TC exclusive handling due to ERL/EXL.
1156 env
->CP0_VPEConf0
= newval
;
1159 void helper_mttc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1161 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1162 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1166 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1167 newval
= (other
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1169 /* TODO: TC exclusive handling due to ERL/EXL. */
1170 other
->CP0_VPEConf0
= newval
;
1173 void helper_mtc0_vpeconf1(CPUMIPSState
*env
, target_ulong arg1
)
1178 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1179 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
1180 (0xff << CP0VPEC1_NCP1
);
1181 newval
= (env
->CP0_VPEConf1
& ~mask
) | (arg1
& mask
);
1183 /* UDI not implemented. */
1184 /* CP2 not implemented. */
1186 // TODO: Handle FPU (CP1) binding.
1188 env
->CP0_VPEConf1
= newval
;
1191 void helper_mtc0_yqmask(CPUMIPSState
*env
, target_ulong arg1
)
1193 /* Yield qualifier inputs not implemented. */
1194 env
->CP0_YQMask
= 0x00000000;
1197 void helper_mtc0_vpeopt(CPUMIPSState
*env
, target_ulong arg1
)
1199 env
->CP0_VPEOpt
= arg1
& 0x0000ffff;
1202 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1204 void helper_mtc0_entrylo0(CPUMIPSState
*env
, target_ulong arg1
)
1206 /* 1k pages not implemented */
1207 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1208 env
->CP0_EntryLo0
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1209 | (rxi
<< (CP0EnLo_XI
- 30));
1212 #if defined(TARGET_MIPS64)
1213 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1215 void helper_dmtc0_entrylo0(CPUMIPSState
*env
, uint64_t arg1
)
1217 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1218 env
->CP0_EntryLo0
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1222 void helper_mtc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1224 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
1227 newval
= (env
->active_tc
.CP0_TCStatus
& ~mask
) | (arg1
& mask
);
1229 env
->active_tc
.CP0_TCStatus
= newval
;
1230 sync_c0_tcstatus(env
, env
->current_tc
, newval
);
1233 void helper_mttc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1235 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1236 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1238 if (other_tc
== other
->current_tc
)
1239 other
->active_tc
.CP0_TCStatus
= arg1
;
1241 other
->tcs
[other_tc
].CP0_TCStatus
= arg1
;
1242 sync_c0_tcstatus(other
, other_tc
, arg1
);
1245 void helper_mtc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1247 uint32_t mask
= (1 << CP0TCBd_TBE
);
1250 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1251 mask
|= (1 << CP0TCBd_CurVPE
);
1252 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1253 env
->active_tc
.CP0_TCBind
= newval
;
1256 void helper_mttc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1258 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1259 uint32_t mask
= (1 << CP0TCBd_TBE
);
1261 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1263 if (other
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1264 mask
|= (1 << CP0TCBd_CurVPE
);
1265 if (other_tc
== other
->current_tc
) {
1266 newval
= (other
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1267 other
->active_tc
.CP0_TCBind
= newval
;
1269 newval
= (other
->tcs
[other_tc
].CP0_TCBind
& ~mask
) | (arg1
& mask
);
1270 other
->tcs
[other_tc
].CP0_TCBind
= newval
;
1274 void helper_mtc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1276 env
->active_tc
.PC
= arg1
;
1277 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1279 /* MIPS16 not implemented. */
1282 void helper_mttc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1284 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1285 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1287 if (other_tc
== other
->current_tc
) {
1288 other
->active_tc
.PC
= arg1
;
1289 other
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1290 other
->lladdr
= 0ULL;
1291 /* MIPS16 not implemented. */
1293 other
->tcs
[other_tc
].PC
= arg1
;
1294 other
->tcs
[other_tc
].CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1295 other
->lladdr
= 0ULL;
1296 /* MIPS16 not implemented. */
1300 void helper_mtc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1302 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1304 env
->active_tc
.CP0_TCHalt
= arg1
& 0x1;
1306 // TODO: Halt TC / Restart (if allocated+active) TC.
1307 if (env
->active_tc
.CP0_TCHalt
& 1) {
1308 mips_tc_sleep(cpu
, env
->current_tc
);
1310 mips_tc_wake(cpu
, env
->current_tc
);
1314 void helper_mttc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1316 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1317 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1318 MIPSCPU
*other_cpu
= mips_env_get_cpu(other
);
1320 // TODO: Halt TC / Restart (if allocated+active) TC.
1322 if (other_tc
== other
->current_tc
)
1323 other
->active_tc
.CP0_TCHalt
= arg1
;
1325 other
->tcs
[other_tc
].CP0_TCHalt
= arg1
;
1328 mips_tc_sleep(other_cpu
, other_tc
);
1330 mips_tc_wake(other_cpu
, other_tc
);
1334 void helper_mtc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1336 env
->active_tc
.CP0_TCContext
= arg1
;
1339 void helper_mttc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1341 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1342 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1344 if (other_tc
== other
->current_tc
)
1345 other
->active_tc
.CP0_TCContext
= arg1
;
1347 other
->tcs
[other_tc
].CP0_TCContext
= arg1
;
1350 void helper_mtc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1352 env
->active_tc
.CP0_TCSchedule
= arg1
;
1355 void helper_mttc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1357 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1358 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1360 if (other_tc
== other
->current_tc
)
1361 other
->active_tc
.CP0_TCSchedule
= arg1
;
1363 other
->tcs
[other_tc
].CP0_TCSchedule
= arg1
;
1366 void helper_mtc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1368 env
->active_tc
.CP0_TCScheFBack
= arg1
;
1371 void helper_mttc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1373 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1374 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1376 if (other_tc
== other
->current_tc
)
1377 other
->active_tc
.CP0_TCScheFBack
= arg1
;
1379 other
->tcs
[other_tc
].CP0_TCScheFBack
= arg1
;
1382 void helper_mtc0_entrylo1(CPUMIPSState
*env
, target_ulong arg1
)
1384 /* 1k pages not implemented */
1385 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1386 env
->CP0_EntryLo1
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1387 | (rxi
<< (CP0EnLo_XI
- 30));
1390 #if defined(TARGET_MIPS64)
1391 void helper_dmtc0_entrylo1(CPUMIPSState
*env
, uint64_t arg1
)
1393 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1394 env
->CP0_EntryLo1
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1398 void helper_mtc0_context(CPUMIPSState
*env
, target_ulong arg1
)
1400 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (arg1
& ~0x007FFFFF);
1403 void update_pagemask(CPUMIPSState
*env
, target_ulong arg1
, int32_t *pagemask
)
1405 uint64_t mask
= arg1
>> (TARGET_PAGE_BITS
+ 1);
1406 if (!(env
->insn_flags
& ISA_MIPS32R6
) || (arg1
== ~0) ||
1407 (mask
== 0x0000 || mask
== 0x0003 || mask
== 0x000F ||
1408 mask
== 0x003F || mask
== 0x00FF || mask
== 0x03FF ||
1409 mask
== 0x0FFF || mask
== 0x3FFF || mask
== 0xFFFF)) {
1410 env
->CP0_PageMask
= arg1
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1414 void helper_mtc0_pagemask(CPUMIPSState
*env
, target_ulong arg1
)
1416 update_pagemask(env
, arg1
, &env
->CP0_PageMask
);
1419 void helper_mtc0_pagegrain(CPUMIPSState
*env
, target_ulong arg1
)
1421 /* SmartMIPS not implemented */
1422 /* 1k pages not implemented */
1423 env
->CP0_PageGrain
= (arg1
& env
->CP0_PageGrain_rw_bitmask
) |
1424 (env
->CP0_PageGrain
& ~env
->CP0_PageGrain_rw_bitmask
);
1425 compute_hflags(env
);
1426 restore_pamask(env
);
1429 void helper_mtc0_segctl0(CPUMIPSState
*env
, target_ulong arg1
)
1431 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
1433 env
->CP0_SegCtl0
= arg1
& CP0SC0_MASK
;
1437 void helper_mtc0_segctl1(CPUMIPSState
*env
, target_ulong arg1
)
1439 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
1441 env
->CP0_SegCtl1
= arg1
& CP0SC1_MASK
;
1445 void helper_mtc0_segctl2(CPUMIPSState
*env
, target_ulong arg1
)
1447 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
1449 env
->CP0_SegCtl2
= arg1
& CP0SC2_MASK
;
1453 void helper_mtc0_pwfield(CPUMIPSState
*env
, target_ulong arg1
)
1455 #if defined(TARGET_MIPS64)
1456 uint64_t mask
= 0x3F3FFFFFFFULL
;
1457 uint32_t old_ptei
= (env
->CP0_PWField
>> CP0PF_PTEI
) & 0x3FULL
;
1458 uint32_t new_ptei
= (arg1
>> CP0PF_PTEI
) & 0x3FULL
;
1460 if ((env
->insn_flags
& ISA_MIPS32R6
)) {
1461 if (((arg1
>> CP0PF_BDI
) & 0x3FULL
) < 12) {
1462 mask
&= ~(0x3FULL
<< CP0PF_BDI
);
1464 if (((arg1
>> CP0PF_GDI
) & 0x3FULL
) < 12) {
1465 mask
&= ~(0x3FULL
<< CP0PF_GDI
);
1467 if (((arg1
>> CP0PF_UDI
) & 0x3FULL
) < 12) {
1468 mask
&= ~(0x3FULL
<< CP0PF_UDI
);
1470 if (((arg1
>> CP0PF_MDI
) & 0x3FULL
) < 12) {
1471 mask
&= ~(0x3FULL
<< CP0PF_MDI
);
1473 if (((arg1
>> CP0PF_PTI
) & 0x3FULL
) < 12) {
1474 mask
&= ~(0x3FULL
<< CP0PF_PTI
);
1477 env
->CP0_PWField
= arg1
& mask
;
1479 if ((new_ptei
>= 32) ||
1480 ((env
->insn_flags
& ISA_MIPS32R6
) &&
1481 (new_ptei
== 0 || new_ptei
== 1))) {
1482 env
->CP0_PWField
= (env
->CP0_PWField
& ~0x3FULL
) |
1483 (old_ptei
<< CP0PF_PTEI
);
1486 uint32_t mask
= 0x3FFFFFFF;
1487 uint32_t old_ptew
= (env
->CP0_PWField
>> CP0PF_PTEW
) & 0x3F;
1488 uint32_t new_ptew
= (arg1
>> CP0PF_PTEW
) & 0x3F;
1490 if ((env
->insn_flags
& ISA_MIPS32R6
)) {
1491 if (((arg1
>> CP0PF_GDW
) & 0x3F) < 12) {
1492 mask
&= ~(0x3F << CP0PF_GDW
);
1494 if (((arg1
>> CP0PF_UDW
) & 0x3F) < 12) {
1495 mask
&= ~(0x3F << CP0PF_UDW
);
1497 if (((arg1
>> CP0PF_MDW
) & 0x3F) < 12) {
1498 mask
&= ~(0x3F << CP0PF_MDW
);
1500 if (((arg1
>> CP0PF_PTW
) & 0x3F) < 12) {
1501 mask
&= ~(0x3F << CP0PF_PTW
);
1504 env
->CP0_PWField
= arg1
& mask
;
1506 if ((new_ptew
>= 32) ||
1507 ((env
->insn_flags
& ISA_MIPS32R6
) &&
1508 (new_ptew
== 0 || new_ptew
== 1))) {
1509 env
->CP0_PWField
= (env
->CP0_PWField
& ~0x3F) |
1510 (old_ptew
<< CP0PF_PTEW
);
1515 void helper_mtc0_pwsize(CPUMIPSState
*env
, target_ulong arg1
)
1517 #if defined(TARGET_MIPS64)
1518 env
->CP0_PWSize
= arg1
& 0x3F7FFFFFFFULL
;
1520 env
->CP0_PWSize
= arg1
& 0x3FFFFFFF;
1524 void helper_mtc0_wired(CPUMIPSState
*env
, target_ulong arg1
)
1526 if (env
->insn_flags
& ISA_MIPS32R6
) {
1527 if (arg1
< env
->tlb
->nb_tlb
) {
1528 env
->CP0_Wired
= arg1
;
1531 env
->CP0_Wired
= arg1
% env
->tlb
->nb_tlb
;
1535 void helper_mtc0_pwctl(CPUMIPSState
*env
, target_ulong arg1
)
1537 #if defined(TARGET_MIPS64)
1538 /* PWEn = 0. Hardware page table walking is not implemented. */
1539 env
->CP0_PWCtl
= (env
->CP0_PWCtl
& 0x000000C0) | (arg1
& 0x5C00003F);
1541 env
->CP0_PWCtl
= (arg1
& 0x800000FF);
1545 void helper_mtc0_srsconf0(CPUMIPSState
*env
, target_ulong arg1
)
1547 env
->CP0_SRSConf0
|= arg1
& env
->CP0_SRSConf0_rw_bitmask
;
1550 void helper_mtc0_srsconf1(CPUMIPSState
*env
, target_ulong arg1
)
1552 env
->CP0_SRSConf1
|= arg1
& env
->CP0_SRSConf1_rw_bitmask
;
1555 void helper_mtc0_srsconf2(CPUMIPSState
*env
, target_ulong arg1
)
1557 env
->CP0_SRSConf2
|= arg1
& env
->CP0_SRSConf2_rw_bitmask
;
1560 void helper_mtc0_srsconf3(CPUMIPSState
*env
, target_ulong arg1
)
1562 env
->CP0_SRSConf3
|= arg1
& env
->CP0_SRSConf3_rw_bitmask
;
1565 void helper_mtc0_srsconf4(CPUMIPSState
*env
, target_ulong arg1
)
1567 env
->CP0_SRSConf4
|= arg1
& env
->CP0_SRSConf4_rw_bitmask
;
1570 void helper_mtc0_hwrena(CPUMIPSState
*env
, target_ulong arg1
)
1572 uint32_t mask
= 0x0000000F;
1574 if ((env
->CP0_Config1
& (1 << CP0C1_PC
)) &&
1575 (env
->insn_flags
& ISA_MIPS32R6
)) {
1578 if (env
->insn_flags
& ISA_MIPS32R6
) {
1581 if (env
->CP0_Config3
& (1 << CP0C3_ULRI
)) {
1584 if (arg1
& (1 << 29)) {
1585 env
->hflags
|= MIPS_HFLAG_HWRENA_ULR
;
1587 env
->hflags
&= ~MIPS_HFLAG_HWRENA_ULR
;
1591 env
->CP0_HWREna
= arg1
& mask
;
1594 void helper_mtc0_count(CPUMIPSState
*env
, target_ulong arg1
)
1596 qemu_mutex_lock_iothread();
1597 cpu_mips_store_count(env
, arg1
);
1598 qemu_mutex_unlock_iothread();
1601 void helper_mtc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1603 target_ulong old
, val
, mask
;
1604 mask
= (TARGET_PAGE_MASK
<< 1) | env
->CP0_EntryHi_ASID_mask
;
1605 if (((env
->CP0_Config4
>> CP0C4_IE
) & 0x3) >= 2) {
1606 mask
|= 1 << CP0EnHi_EHINV
;
1609 /* 1k pages not implemented */
1610 #if defined(TARGET_MIPS64)
1611 if (env
->insn_flags
& ISA_MIPS32R6
) {
1612 int entryhi_r
= extract64(arg1
, 62, 2);
1613 int config0_at
= extract32(env
->CP0_Config0
, 13, 2);
1614 bool no_supervisor
= (env
->CP0_Status_rw_bitmask
& 0x8) == 0;
1615 if ((entryhi_r
== 2) ||
1616 (entryhi_r
== 1 && (no_supervisor
|| config0_at
== 1))) {
1617 /* skip EntryHi.R field if new value is reserved */
1618 mask
&= ~(0x3ull
<< 62);
1621 mask
&= env
->SEGMask
;
1623 old
= env
->CP0_EntryHi
;
1624 val
= (arg1
& mask
) | (old
& ~mask
);
1625 env
->CP0_EntryHi
= val
;
1626 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1627 sync_c0_entryhi(env
, env
->current_tc
);
1629 /* If the ASID changes, flush qemu's TLB. */
1630 if ((old
& env
->CP0_EntryHi_ASID_mask
) !=
1631 (val
& env
->CP0_EntryHi_ASID_mask
)) {
1632 tlb_flush(CPU(mips_env_get_cpu(env
)));
1636 void helper_mttc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1638 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1639 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1641 other
->CP0_EntryHi
= arg1
;
1642 sync_c0_entryhi(other
, other_tc
);
1645 void helper_mtc0_compare(CPUMIPSState
*env
, target_ulong arg1
)
1647 qemu_mutex_lock_iothread();
1648 cpu_mips_store_compare(env
, arg1
);
1649 qemu_mutex_unlock_iothread();
1652 void helper_mtc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1654 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1657 old
= env
->CP0_Status
;
1658 cpu_mips_store_status(env
, arg1
);
1659 val
= env
->CP0_Status
;
1661 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1662 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1663 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1664 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1666 switch (cpu_mmu_index(env
, false)) {
1668 qemu_log(", ERL\n");
1670 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1671 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1672 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1674 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
1680 void helper_mttc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1682 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1683 uint32_t mask
= env
->CP0_Status_rw_bitmask
& ~0xf1000018;
1684 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1686 other
->CP0_Status
= (other
->CP0_Status
& ~mask
) | (arg1
& mask
);
1687 sync_c0_status(env
, other
, other_tc
);
1690 void helper_mtc0_intctl(CPUMIPSState
*env
, target_ulong arg1
)
1692 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000003e0) | (arg1
& 0x000003e0);
1695 void helper_mtc0_srsctl(CPUMIPSState
*env
, target_ulong arg1
)
1697 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
1698 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (arg1
& mask
);
1701 void helper_mtc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1703 qemu_mutex_lock_iothread();
1704 cpu_mips_store_cause(env
, arg1
);
1705 qemu_mutex_unlock_iothread();
1708 void helper_mttc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1710 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1711 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1713 cpu_mips_store_cause(other
, arg1
);
1716 target_ulong
helper_mftc0_epc(CPUMIPSState
*env
)
1718 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1719 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1721 return other
->CP0_EPC
;
1724 target_ulong
helper_mftc0_ebase(CPUMIPSState
*env
)
1726 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1727 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1729 return other
->CP0_EBase
;
1732 void helper_mtc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1734 target_ulong mask
= 0x3FFFF000 | env
->CP0_EBaseWG_rw_bitmask
;
1735 if (arg1
& env
->CP0_EBaseWG_rw_bitmask
) {
1736 mask
|= ~0x3FFFFFFF;
1738 env
->CP0_EBase
= (env
->CP0_EBase
& ~mask
) | (arg1
& mask
);
1741 void helper_mttc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1743 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1744 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1745 target_ulong mask
= 0x3FFFF000 | env
->CP0_EBaseWG_rw_bitmask
;
1746 if (arg1
& env
->CP0_EBaseWG_rw_bitmask
) {
1747 mask
|= ~0x3FFFFFFF;
1749 other
->CP0_EBase
= (other
->CP0_EBase
& ~mask
) | (arg1
& mask
);
1752 target_ulong
helper_mftc0_configx(CPUMIPSState
*env
, target_ulong idx
)
1754 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1755 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1758 case 0: return other
->CP0_Config0
;
1759 case 1: return other
->CP0_Config1
;
1760 case 2: return other
->CP0_Config2
;
1761 case 3: return other
->CP0_Config3
;
1762 /* 4 and 5 are reserved. */
1763 case 6: return other
->CP0_Config6
;
1764 case 7: return other
->CP0_Config7
;
1771 void helper_mtc0_config0(CPUMIPSState
*env
, target_ulong arg1
)
1773 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (arg1
& 0x00000007);
1776 void helper_mtc0_config2(CPUMIPSState
*env
, target_ulong arg1
)
1778 /* tertiary/secondary caches not implemented */
1779 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1782 void helper_mtc0_config3(CPUMIPSState
*env
, target_ulong arg1
)
1784 if (env
->insn_flags
& ASE_MICROMIPS
) {
1785 env
->CP0_Config3
= (env
->CP0_Config3
& ~(1 << CP0C3_ISA_ON_EXC
)) |
1786 (arg1
& (1 << CP0C3_ISA_ON_EXC
));
1790 void helper_mtc0_config4(CPUMIPSState
*env
, target_ulong arg1
)
1792 env
->CP0_Config4
= (env
->CP0_Config4
& (~env
->CP0_Config4_rw_bitmask
)) |
1793 (arg1
& env
->CP0_Config4_rw_bitmask
);
1796 void helper_mtc0_config5(CPUMIPSState
*env
, target_ulong arg1
)
1798 env
->CP0_Config5
= (env
->CP0_Config5
& (~env
->CP0_Config5_rw_bitmask
)) |
1799 (arg1
& env
->CP0_Config5_rw_bitmask
);
1800 compute_hflags(env
);
1803 void helper_mtc0_lladdr(CPUMIPSState
*env
, target_ulong arg1
)
1805 target_long mask
= env
->CP0_LLAddr_rw_bitmask
;
1806 arg1
= arg1
<< env
->CP0_LLAddr_shift
;
1807 env
->lladdr
= (env
->lladdr
& ~mask
) | (arg1
& mask
);
1810 #define MTC0_MAAR_MASK(env) \
1811 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1813 void helper_mtc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1815 env
->CP0_MAAR
[env
->CP0_MAARI
] = arg1
& MTC0_MAAR_MASK(env
);
1818 void helper_mthc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1820 env
->CP0_MAAR
[env
->CP0_MAARI
] =
1821 (((uint64_t) arg1
<< 32) & MTC0_MAAR_MASK(env
)) |
1822 (env
->CP0_MAAR
[env
->CP0_MAARI
] & 0x00000000ffffffffULL
);
1825 void helper_mtc0_maari(CPUMIPSState
*env
, target_ulong arg1
)
1827 int index
= arg1
& 0x3f;
1828 if (index
== 0x3f) {
1829 /* Software may write all ones to INDEX to determine the
1830 maximum value supported. */
1831 env
->CP0_MAARI
= MIPS_MAAR_MAX
- 1;
1832 } else if (index
< MIPS_MAAR_MAX
) {
1833 env
->CP0_MAARI
= index
;
1835 /* Other than the all ones, if the
1836 value written is not supported, then INDEX is unchanged
1837 from its previous value. */
1840 void helper_mtc0_watchlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1842 /* Watch exceptions for instructions, data loads, data stores
1844 env
->CP0_WatchLo
[sel
] = (arg1
& ~0x7);
1847 void helper_mtc0_watchhi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1849 int mask
= 0x40000FF8 | (env
->CP0_EntryHi_ASID_mask
<< CP0WH_ASID
);
1850 env
->CP0_WatchHi
[sel
] = arg1
& mask
;
1851 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & arg1
& 0x7);
1854 void helper_mtc0_xcontext(CPUMIPSState
*env
, target_ulong arg1
)
1856 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
1857 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (arg1
& ~mask
);
1860 void helper_mtc0_framemask(CPUMIPSState
*env
, target_ulong arg1
)
1862 env
->CP0_Framemask
= arg1
; /* XXX */
1865 void helper_mtc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1867 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (arg1
& 0x13300120);
1868 if (arg1
& (1 << CP0DB_DM
))
1869 env
->hflags
|= MIPS_HFLAG_DM
;
1871 env
->hflags
&= ~MIPS_HFLAG_DM
;
1874 void helper_mttc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1876 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1877 uint32_t val
= arg1
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
1878 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1880 /* XXX: Might be wrong, check with EJTAG spec. */
1881 if (other_tc
== other
->current_tc
)
1882 other
->active_tc
.CP0_Debug_tcstatus
= val
;
1884 other
->tcs
[other_tc
].CP0_Debug_tcstatus
= val
;
1885 other
->CP0_Debug
= (other
->CP0_Debug
&
1886 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1887 (arg1
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1890 void helper_mtc0_performance0(CPUMIPSState
*env
, target_ulong arg1
)
1892 env
->CP0_Performance0
= arg1
& 0x000007ff;
1895 void helper_mtc0_errctl(CPUMIPSState
*env
, target_ulong arg1
)
1897 int32_t wst
= arg1
& (1 << CP0EC_WST
);
1898 int32_t spr
= arg1
& (1 << CP0EC_SPR
);
1899 int32_t itc
= env
->itc_tag
? (arg1
& (1 << CP0EC_ITC
)) : 0;
1901 env
->CP0_ErrCtl
= wst
| spr
| itc
;
1903 if (itc
&& !wst
&& !spr
) {
1904 env
->hflags
|= MIPS_HFLAG_ITC_CACHE
;
1906 env
->hflags
&= ~MIPS_HFLAG_ITC_CACHE
;
1910 void helper_mtc0_taglo(CPUMIPSState
*env
, target_ulong arg1
)
1912 if (env
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
1913 /* If CACHE instruction is configured for ITC tags then make all
1914 CP0.TagLo bits writable. The actual write to ITC Configuration
1915 Tag will take care of the read-only bits. */
1916 env
->CP0_TagLo
= arg1
;
1918 env
->CP0_TagLo
= arg1
& 0xFFFFFCF6;
1922 void helper_mtc0_datalo(CPUMIPSState
*env
, target_ulong arg1
)
1924 env
->CP0_DataLo
= arg1
; /* XXX */
1927 void helper_mtc0_taghi(CPUMIPSState
*env
, target_ulong arg1
)
1929 env
->CP0_TagHi
= arg1
; /* XXX */
1932 void helper_mtc0_datahi(CPUMIPSState
*env
, target_ulong arg1
)
1934 env
->CP0_DataHi
= arg1
; /* XXX */
1937 /* MIPS MT functions */
1938 target_ulong
helper_mftgpr(CPUMIPSState
*env
, uint32_t sel
)
1940 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1941 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1943 if (other_tc
== other
->current_tc
)
1944 return other
->active_tc
.gpr
[sel
];
1946 return other
->tcs
[other_tc
].gpr
[sel
];
1949 target_ulong
helper_mftlo(CPUMIPSState
*env
, uint32_t sel
)
1951 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1952 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1954 if (other_tc
== other
->current_tc
)
1955 return other
->active_tc
.LO
[sel
];
1957 return other
->tcs
[other_tc
].LO
[sel
];
1960 target_ulong
helper_mfthi(CPUMIPSState
*env
, uint32_t sel
)
1962 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1963 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1965 if (other_tc
== other
->current_tc
)
1966 return other
->active_tc
.HI
[sel
];
1968 return other
->tcs
[other_tc
].HI
[sel
];
1971 target_ulong
helper_mftacx(CPUMIPSState
*env
, uint32_t sel
)
1973 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1974 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1976 if (other_tc
== other
->current_tc
)
1977 return other
->active_tc
.ACX
[sel
];
1979 return other
->tcs
[other_tc
].ACX
[sel
];
1982 target_ulong
helper_mftdsp(CPUMIPSState
*env
)
1984 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1985 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1987 if (other_tc
== other
->current_tc
)
1988 return other
->active_tc
.DSPControl
;
1990 return other
->tcs
[other_tc
].DSPControl
;
1993 void helper_mttgpr(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1995 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1996 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1998 if (other_tc
== other
->current_tc
)
1999 other
->active_tc
.gpr
[sel
] = arg1
;
2001 other
->tcs
[other_tc
].gpr
[sel
] = arg1
;
2004 void helper_mttlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
2006 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2007 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2009 if (other_tc
== other
->current_tc
)
2010 other
->active_tc
.LO
[sel
] = arg1
;
2012 other
->tcs
[other_tc
].LO
[sel
] = arg1
;
2015 void helper_mtthi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
2017 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2018 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2020 if (other_tc
== other
->current_tc
)
2021 other
->active_tc
.HI
[sel
] = arg1
;
2023 other
->tcs
[other_tc
].HI
[sel
] = arg1
;
2026 void helper_mttacx(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
2028 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2029 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2031 if (other_tc
== other
->current_tc
)
2032 other
->active_tc
.ACX
[sel
] = arg1
;
2034 other
->tcs
[other_tc
].ACX
[sel
] = arg1
;
2037 void helper_mttdsp(CPUMIPSState
*env
, target_ulong arg1
)
2039 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2040 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2042 if (other_tc
== other
->current_tc
)
2043 other
->active_tc
.DSPControl
= arg1
;
2045 other
->tcs
[other_tc
].DSPControl
= arg1
;
2048 /* MIPS MT functions */
2049 target_ulong
helper_dmt(void)
2055 target_ulong
helper_emt(void)
2061 target_ulong
helper_dvpe(CPUMIPSState
*env
)
2063 CPUState
*other_cs
= first_cpu
;
2064 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
2066 CPU_FOREACH(other_cs
) {
2067 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
2068 /* Turn off all VPEs except the one executing the dvpe. */
2069 if (&other_cpu
->env
!= env
) {
2070 other_cpu
->env
.mvp
->CP0_MVPControl
&= ~(1 << CP0MVPCo_EVP
);
2071 mips_vpe_sleep(other_cpu
);
2077 target_ulong
helper_evpe(CPUMIPSState
*env
)
2079 CPUState
*other_cs
= first_cpu
;
2080 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
2082 CPU_FOREACH(other_cs
) {
2083 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
2085 if (&other_cpu
->env
!= env
2086 /* If the VPE is WFI, don't disturb its sleep. */
2087 && !mips_vpe_is_wfi(other_cpu
)) {
2088 /* Enable the VPE. */
2089 other_cpu
->env
.mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
2090 mips_vpe_wake(other_cpu
); /* And wake it up. */
2095 #endif /* !CONFIG_USER_ONLY */
2097 void helper_fork(target_ulong arg1
, target_ulong arg2
)
2099 // arg1 = rt, arg2 = rs
2100 // TODO: store to TC register
2103 target_ulong
helper_yield(CPUMIPSState
*env
, target_ulong arg
)
2105 target_long arg1
= arg
;
2108 /* No scheduling policy implemented. */
2110 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
2111 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
2112 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
2113 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
2114 do_raise_exception(env
, EXCP_THREAD
, GETPC());
2117 } else if (arg1
== 0) {
2118 if (0 /* TODO: TC underflow */) {
2119 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
2120 do_raise_exception(env
, EXCP_THREAD
, GETPC());
2122 // TODO: Deallocate TC
2124 } else if (arg1
> 0) {
2125 /* Yield qualifier inputs not implemented. */
2126 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
2127 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
2128 do_raise_exception(env
, EXCP_THREAD
, GETPC());
2130 return env
->CP0_YQMask
;
2133 /* R6 Multi-threading */
2134 #ifndef CONFIG_USER_ONLY
2135 target_ulong
helper_dvp(CPUMIPSState
*env
)
2137 CPUState
*other_cs
= first_cpu
;
2138 target_ulong prev
= env
->CP0_VPControl
;
2140 if (!((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1)) {
2141 CPU_FOREACH(other_cs
) {
2142 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
2143 /* Turn off all VPs except the one executing the dvp. */
2144 if (&other_cpu
->env
!= env
) {
2145 mips_vpe_sleep(other_cpu
);
2148 env
->CP0_VPControl
|= (1 << CP0VPCtl_DIS
);
2153 target_ulong
helper_evp(CPUMIPSState
*env
)
2155 CPUState
*other_cs
= first_cpu
;
2156 target_ulong prev
= env
->CP0_VPControl
;
2158 if ((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1) {
2159 CPU_FOREACH(other_cs
) {
2160 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
2161 if ((&other_cpu
->env
!= env
) && !mips_vp_is_wfi(other_cpu
)) {
2162 /* If the VP is WFI, don't disturb its sleep.
2163 * Otherwise, wake it up. */
2164 mips_vpe_wake(other_cpu
);
2167 env
->CP0_VPControl
&= ~(1 << CP0VPCtl_DIS
);
2171 #endif /* !CONFIG_USER_ONLY */
2173 #ifndef CONFIG_USER_ONLY
2174 /* TLB management */
2175 static void r4k_mips_tlb_flush_extra (CPUMIPSState
*env
, int first
)
2177 /* Discard entries from env->tlb[first] onwards. */
2178 while (env
->tlb
->tlb_in_use
> first
) {
2179 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
2183 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo
)
2185 #if defined(TARGET_MIPS64)
2186 return extract64(entrylo
, 6, 54);
2188 return extract64(entrylo
, 6, 24) | /* PFN */
2189 (extract64(entrylo
, 32, 32) << 24); /* PFNX */
2193 static void r4k_fill_tlb(CPUMIPSState
*env
, int idx
)
2196 uint64_t mask
= env
->CP0_PageMask
>> (TARGET_PAGE_BITS
+ 1);
2198 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
2199 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2200 if (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) {
2205 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
2206 #if defined(TARGET_MIPS64)
2207 tlb
->VPN
&= env
->SEGMask
;
2209 tlb
->ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2210 tlb
->PageMask
= env
->CP0_PageMask
;
2211 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
2212 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
2213 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
2214 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
2215 tlb
->XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) & 1;
2216 tlb
->RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) & 1;
2217 tlb
->PFN
[0] = (get_tlb_pfn_from_entrylo(env
->CP0_EntryLo0
) & ~mask
) << 12;
2218 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
2219 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
2220 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
2221 tlb
->XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) & 1;
2222 tlb
->RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) & 1;
2223 tlb
->PFN
[1] = (get_tlb_pfn_from_entrylo(env
->CP0_EntryLo1
) & ~mask
) << 12;
2226 void r4k_helper_tlbinv(CPUMIPSState
*env
)
2230 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2232 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2233 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2234 if (!tlb
->G
&& tlb
->ASID
== ASID
) {
2238 cpu_mips_tlb_flush(env
);
2241 void r4k_helper_tlbinvf(CPUMIPSState
*env
)
2245 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2246 env
->tlb
->mmu
.r4k
.tlb
[idx
].EHINV
= 1;
2248 cpu_mips_tlb_flush(env
);
2251 void r4k_helper_tlbwi(CPUMIPSState
*env
)
2257 bool EHINV
, G
, V0
, D0
, V1
, D1
, XI0
, XI1
, RI0
, RI1
;
2259 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2260 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2261 VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
2262 #if defined(TARGET_MIPS64)
2263 VPN
&= env
->SEGMask
;
2265 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2266 EHINV
= (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) != 0;
2267 G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
2268 V0
= (env
->CP0_EntryLo0
& 2) != 0;
2269 D0
= (env
->CP0_EntryLo0
& 4) != 0;
2270 XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) &1;
2271 RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) &1;
2272 V1
= (env
->CP0_EntryLo1
& 2) != 0;
2273 D1
= (env
->CP0_EntryLo1
& 4) != 0;
2274 XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) &1;
2275 RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) &1;
2277 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2278 permissions on the current entry. */
2279 if (tlb
->VPN
!= VPN
|| tlb
->ASID
!= ASID
|| tlb
->G
!= G
||
2280 (!tlb
->EHINV
&& EHINV
) ||
2281 (tlb
->V0
&& !V0
) || (tlb
->D0
&& !D0
) ||
2282 (!tlb
->XI0
&& XI0
) || (!tlb
->RI0
&& RI0
) ||
2283 (tlb
->V1
&& !V1
) || (tlb
->D1
&& !D1
) ||
2284 (!tlb
->XI1
&& XI1
) || (!tlb
->RI1
&& RI1
)) {
2285 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2288 r4k_invalidate_tlb(env
, idx
, 0);
2289 r4k_fill_tlb(env
, idx
);
2292 void r4k_helper_tlbwr(CPUMIPSState
*env
)
2294 int r
= cpu_mips_get_random(env
);
2296 r4k_invalidate_tlb(env
, r
, 1);
2297 r4k_fill_tlb(env
, r
);
2300 void r4k_helper_tlbp(CPUMIPSState
*env
)
2309 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2310 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
2311 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2312 /* 1k pages are not supported. */
2313 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2314 tag
= env
->CP0_EntryHi
& ~mask
;
2315 VPN
= tlb
->VPN
& ~mask
;
2316 #if defined(TARGET_MIPS64)
2317 tag
&= env
->SEGMask
;
2319 /* Check ASID, virtual page number & size */
2320 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
&& !tlb
->EHINV
) {
2326 if (i
== env
->tlb
->nb_tlb
) {
2327 /* No match. Discard any shadow entries, if any of them match. */
2328 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
2329 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2330 /* 1k pages are not supported. */
2331 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2332 tag
= env
->CP0_EntryHi
& ~mask
;
2333 VPN
= tlb
->VPN
& ~mask
;
2334 #if defined(TARGET_MIPS64)
2335 tag
&= env
->SEGMask
;
2337 /* Check ASID, virtual page number & size */
2338 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
2339 r4k_mips_tlb_flush_extra (env
, i
);
2344 env
->CP0_Index
|= 0x80000000;
2348 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn
)
2350 #if defined(TARGET_MIPS64)
2351 return tlb_pfn
<< 6;
2353 return (extract64(tlb_pfn
, 0, 24) << 6) | /* PFN */
2354 (extract64(tlb_pfn
, 24, 32) << 32); /* PFNX */
2358 void r4k_helper_tlbr(CPUMIPSState
*env
)
2364 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2365 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2366 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2368 /* If this will change the current ASID, flush qemu's TLB. */
2369 if (ASID
!= tlb
->ASID
)
2370 cpu_mips_tlb_flush(env
);
2372 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2375 env
->CP0_EntryHi
= 1 << CP0EnHi_EHINV
;
2376 env
->CP0_PageMask
= 0;
2377 env
->CP0_EntryLo0
= 0;
2378 env
->CP0_EntryLo1
= 0;
2380 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
2381 env
->CP0_PageMask
= tlb
->PageMask
;
2382 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
2383 ((uint64_t)tlb
->RI0
<< CP0EnLo_RI
) |
2384 ((uint64_t)tlb
->XI0
<< CP0EnLo_XI
) | (tlb
->C0
<< 3) |
2385 get_entrylo_pfn_from_tlb(tlb
->PFN
[0] >> 12);
2386 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
2387 ((uint64_t)tlb
->RI1
<< CP0EnLo_RI
) |
2388 ((uint64_t)tlb
->XI1
<< CP0EnLo_XI
) | (tlb
->C1
<< 3) |
2389 get_entrylo_pfn_from_tlb(tlb
->PFN
[1] >> 12);
2393 void helper_tlbwi(CPUMIPSState
*env
)
2395 env
->tlb
->helper_tlbwi(env
);
2398 void helper_tlbwr(CPUMIPSState
*env
)
2400 env
->tlb
->helper_tlbwr(env
);
2403 void helper_tlbp(CPUMIPSState
*env
)
2405 env
->tlb
->helper_tlbp(env
);
2408 void helper_tlbr(CPUMIPSState
*env
)
2410 env
->tlb
->helper_tlbr(env
);
2413 void helper_tlbinv(CPUMIPSState
*env
)
2415 env
->tlb
->helper_tlbinv(env
);
2418 void helper_tlbinvf(CPUMIPSState
*env
)
2420 env
->tlb
->helper_tlbinvf(env
);
2424 target_ulong
helper_di(CPUMIPSState
*env
)
2426 target_ulong t0
= env
->CP0_Status
;
2428 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
2432 target_ulong
helper_ei(CPUMIPSState
*env
)
2434 target_ulong t0
= env
->CP0_Status
;
2436 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
2440 static void debug_pre_eret(CPUMIPSState
*env
)
2442 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2443 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2444 env
->active_tc
.PC
, env
->CP0_EPC
);
2445 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2446 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2447 if (env
->hflags
& MIPS_HFLAG_DM
)
2448 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2453 static void debug_post_eret(CPUMIPSState
*env
)
2455 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
2457 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2458 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2459 env
->active_tc
.PC
, env
->CP0_EPC
);
2460 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2461 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2462 if (env
->hflags
& MIPS_HFLAG_DM
)
2463 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2464 switch (cpu_mmu_index(env
, false)) {
2466 qemu_log(", ERL\n");
2468 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
2469 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
2470 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
2472 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
2478 static void set_pc(CPUMIPSState
*env
, target_ulong error_pc
)
2480 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
2482 env
->hflags
|= MIPS_HFLAG_M16
;
2484 env
->hflags
&= ~(MIPS_HFLAG_M16
);
2488 static inline void exception_return(CPUMIPSState
*env
)
2490 debug_pre_eret(env
);
2491 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
2492 set_pc(env
, env
->CP0_ErrorEPC
);
2493 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
2495 set_pc(env
, env
->CP0_EPC
);
2496 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
2498 compute_hflags(env
);
2499 debug_post_eret(env
);
2502 void helper_eret(CPUMIPSState
*env
)
2504 exception_return(env
);
2508 void helper_eretnc(CPUMIPSState
*env
)
2510 exception_return(env
);
2513 void helper_deret(CPUMIPSState
*env
)
2515 debug_pre_eret(env
);
2517 env
->hflags
&= ~MIPS_HFLAG_DM
;
2518 compute_hflags(env
);
2520 set_pc(env
, env
->CP0_DEPC
);
2522 debug_post_eret(env
);
2524 #endif /* !CONFIG_USER_ONLY */
2526 static inline void check_hwrena(CPUMIPSState
*env
, int reg
, uintptr_t pc
)
2528 if ((env
->hflags
& MIPS_HFLAG_CP0
) || (env
->CP0_HWREna
& (1 << reg
))) {
2531 do_raise_exception(env
, EXCP_RI
, pc
);
2534 target_ulong
helper_rdhwr_cpunum(CPUMIPSState
*env
)
2536 check_hwrena(env
, 0, GETPC());
2537 return env
->CP0_EBase
& 0x3ff;
2540 target_ulong
helper_rdhwr_synci_step(CPUMIPSState
*env
)
2542 check_hwrena(env
, 1, GETPC());
2543 return env
->SYNCI_Step
;
2546 target_ulong
helper_rdhwr_cc(CPUMIPSState
*env
)
2549 check_hwrena(env
, 2, GETPC());
2550 #ifdef CONFIG_USER_ONLY
2551 count
= env
->CP0_Count
;
2553 qemu_mutex_lock_iothread();
2554 count
= (int32_t)cpu_mips_get_count(env
);
2555 qemu_mutex_unlock_iothread();
2560 target_ulong
helper_rdhwr_ccres(CPUMIPSState
*env
)
2562 check_hwrena(env
, 3, GETPC());
2566 target_ulong
helper_rdhwr_performance(CPUMIPSState
*env
)
2568 check_hwrena(env
, 4, GETPC());
2569 return env
->CP0_Performance0
;
2572 target_ulong
helper_rdhwr_xnp(CPUMIPSState
*env
)
2574 check_hwrena(env
, 5, GETPC());
2575 return (env
->CP0_Config5
>> CP0C5_XNP
) & 1;
2578 void helper_pmon(CPUMIPSState
*env
, int function
)
2582 case 2: /* TODO: char inbyte(int waitflag); */
2583 if (env
->active_tc
.gpr
[4] == 0)
2584 env
->active_tc
.gpr
[2] = -1;
2586 case 11: /* TODO: char inbyte (void); */
2587 env
->active_tc
.gpr
[2] = -1;
2591 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
2597 unsigned char *fmt
= (void *)(uintptr_t)env
->active_tc
.gpr
[4];
2604 void helper_wait(CPUMIPSState
*env
)
2606 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
2609 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
2610 /* Last instruction in the block, PC was updated before
2611 - no need to recover PC and icount */
2612 raise_exception(env
, EXCP_HLT
);
2615 #if !defined(CONFIG_USER_ONLY)
2617 void mips_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
2618 MMUAccessType access_type
,
2619 int mmu_idx
, uintptr_t retaddr
)
2621 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2622 CPUMIPSState
*env
= &cpu
->env
;
2626 if (!(env
->hflags
& MIPS_HFLAG_DM
)) {
2627 env
->CP0_BadVAddr
= addr
;
2630 if (access_type
== MMU_DATA_STORE
) {
2634 if (access_type
== MMU_INST_FETCH
) {
2635 error_code
|= EXCP_INST_NOTAVAIL
;
2639 do_raise_exception_err(env
, excp
, error_code
, retaddr
);
2642 void tlb_fill(CPUState
*cs
, target_ulong addr
, int size
,
2643 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
2647 ret
= mips_cpu_handle_mmu_fault(cs
, addr
, size
, access_type
, mmu_idx
);
2649 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2650 CPUMIPSState
*env
= &cpu
->env
;
2652 do_raise_exception_err(env
, cs
->exception_index
,
2653 env
->error_code
, retaddr
);
2657 void mips_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2658 bool is_write
, bool is_exec
, int unused
,
2661 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2662 CPUMIPSState
*env
= &cpu
->env
;
2665 * Raising an exception with KVM enabled will crash because it won't be from
2666 * the main execution loop so the longjmp won't have a matching setjmp.
2667 * Until we can trigger a bus error exception through KVM lets just ignore
2670 if (kvm_enabled()) {
2675 raise_exception(env
, EXCP_IBE
);
2677 raise_exception(env
, EXCP_DBE
);
2680 #endif /* !CONFIG_USER_ONLY */
2682 /* Complex FPU operations which may need stack space. */
2684 #define FLOAT_TWO32 make_float32(1 << 30)
2685 #define FLOAT_TWO64 make_float64(1ULL << 62)
2687 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2688 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2690 /* convert MIPS rounding mode in FCR31 to IEEE library */
2691 unsigned int ieee_rm
[] = {
2692 float_round_nearest_even
,
2693 float_round_to_zero
,
2698 target_ulong
helper_cfc1(CPUMIPSState
*env
, uint32_t reg
)
2700 target_ulong arg1
= 0;
2704 arg1
= (int32_t)env
->active_fpu
.fcr0
;
2707 /* UFR Support - Read Status FR */
2708 if (env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) {
2709 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2711 ((env
->CP0_Status
& (1 << CP0St_FR
)) >> CP0St_FR
);
2713 do_raise_exception(env
, EXCP_RI
, GETPC());
2718 /* FRE Support - read Config5.FRE bit */
2719 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
2720 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2721 arg1
= (env
->CP0_Config5
>> CP0C5_FRE
) & 1;
2723 helper_raise_exception(env
, EXCP_RI
);
2728 arg1
= ((env
->active_fpu
.fcr31
>> 24) & 0xfe) | ((env
->active_fpu
.fcr31
>> 23) & 0x1);
2731 arg1
= env
->active_fpu
.fcr31
& 0x0003f07c;
2734 arg1
= (env
->active_fpu
.fcr31
& 0x00000f83) | ((env
->active_fpu
.fcr31
>> 22) & 0x4);
2737 arg1
= (int32_t)env
->active_fpu
.fcr31
;
2744 void helper_ctc1(CPUMIPSState
*env
, target_ulong arg1
, uint32_t fs
, uint32_t rt
)
2748 /* UFR Alias - Reset Status FR */
2749 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2752 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2753 env
->CP0_Status
&= ~(1 << CP0St_FR
);
2754 compute_hflags(env
);
2756 do_raise_exception(env
, EXCP_RI
, GETPC());
2760 /* UNFR Alias - Set Status FR */
2761 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2764 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2765 env
->CP0_Status
|= (1 << CP0St_FR
);
2766 compute_hflags(env
);
2768 do_raise_exception(env
, EXCP_RI
, GETPC());
2772 /* FRE Support - clear Config5.FRE bit */
2773 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2776 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2777 env
->CP0_Config5
&= ~(1 << CP0C5_FRE
);
2778 compute_hflags(env
);
2780 helper_raise_exception(env
, EXCP_RI
);
2784 /* FRE Support - set Config5.FRE bit */
2785 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2788 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2789 env
->CP0_Config5
|= (1 << CP0C5_FRE
);
2790 compute_hflags(env
);
2792 helper_raise_exception(env
, EXCP_RI
);
2796 if ((env
->insn_flags
& ISA_MIPS32R6
) || (arg1
& 0xffffff00)) {
2799 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0x017fffff) | ((arg1
& 0xfe) << 24) |
2800 ((arg1
& 0x1) << 23);
2803 if (arg1
& 0x007c0000)
2805 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfffc0f83) | (arg1
& 0x0003f07c);
2808 if (arg1
& 0x007c0000)
2810 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfefff07c) | (arg1
& 0x00000f83) |
2811 ((arg1
& 0x4) << 22);
2814 env
->active_fpu
.fcr31
= (arg1
& env
->active_fpu
.fcr31_rw_bitmask
) |
2815 (env
->active_fpu
.fcr31
& ~(env
->active_fpu
.fcr31_rw_bitmask
));
2818 if (env
->insn_flags
& ISA_MIPS32R6
) {
2819 do_raise_exception(env
, EXCP_RI
, GETPC());
2823 restore_fp_status(env
);
2824 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2825 if ((GET_FP_ENABLE(env
->active_fpu
.fcr31
) | 0x20) & GET_FP_CAUSE(env
->active_fpu
.fcr31
))
2826 do_raise_exception(env
, EXCP_FPE
, GETPC());
2829 int ieee_ex_to_mips(int xcpt
)
2833 if (xcpt
& float_flag_invalid
) {
2836 if (xcpt
& float_flag_overflow
) {
2839 if (xcpt
& float_flag_underflow
) {
2840 ret
|= FP_UNDERFLOW
;
2842 if (xcpt
& float_flag_divbyzero
) {
2845 if (xcpt
& float_flag_inexact
) {
2852 static inline void update_fcr31(CPUMIPSState
*env
, uintptr_t pc
)
2854 int tmp
= ieee_ex_to_mips(get_float_exception_flags(&env
->active_fpu
.fp_status
));
2856 SET_FP_CAUSE(env
->active_fpu
.fcr31
, tmp
);
2859 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2861 if (GET_FP_ENABLE(env
->active_fpu
.fcr31
) & tmp
) {
2862 do_raise_exception(env
, EXCP_FPE
, pc
);
2864 UPDATE_FP_FLAGS(env
->active_fpu
.fcr31
, tmp
);
2870 Single precition routines have a "s" suffix, double precision a
2871 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2872 paired single lower "pl", paired single upper "pu". */
2874 /* unary operations, modifying fp status */
2875 uint64_t helper_float_sqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
2877 fdt0
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2878 update_fcr31(env
, GETPC());
2882 uint32_t helper_float_sqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
2884 fst0
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2885 update_fcr31(env
, GETPC());
2889 uint64_t helper_float_cvtd_s(CPUMIPSState
*env
, uint32_t fst0
)
2893 fdt2
= float32_to_float64(fst0
, &env
->active_fpu
.fp_status
);
2894 update_fcr31(env
, GETPC());
2898 uint64_t helper_float_cvtd_w(CPUMIPSState
*env
, uint32_t wt0
)
2902 fdt2
= int32_to_float64(wt0
, &env
->active_fpu
.fp_status
);
2903 update_fcr31(env
, GETPC());
2907 uint64_t helper_float_cvtd_l(CPUMIPSState
*env
, uint64_t dt0
)
2911 fdt2
= int64_to_float64(dt0
, &env
->active_fpu
.fp_status
);
2912 update_fcr31(env
, GETPC());
2916 uint64_t helper_float_cvt_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2920 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2921 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2922 & (float_flag_invalid
| float_flag_overflow
)) {
2923 dt2
= FP_TO_INT64_OVERFLOW
;
2925 update_fcr31(env
, GETPC());
2929 uint64_t helper_float_cvt_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2933 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2934 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2935 & (float_flag_invalid
| float_flag_overflow
)) {
2936 dt2
= FP_TO_INT64_OVERFLOW
;
2938 update_fcr31(env
, GETPC());
2942 uint64_t helper_float_cvtps_pw(CPUMIPSState
*env
, uint64_t dt0
)
2947 fst2
= int32_to_float32(dt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2948 fsth2
= int32_to_float32(dt0
>> 32, &env
->active_fpu
.fp_status
);
2949 update_fcr31(env
, GETPC());
2950 return ((uint64_t)fsth2
<< 32) | fst2
;
2953 uint64_t helper_float_cvtpw_ps(CPUMIPSState
*env
, uint64_t fdt0
)
2959 wt2
= float32_to_int32(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2960 excp
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2961 if (excp
& (float_flag_overflow
| float_flag_invalid
)) {
2962 wt2
= FP_TO_INT32_OVERFLOW
;
2965 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2966 wth2
= float32_to_int32(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2967 excph
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2968 if (excph
& (float_flag_overflow
| float_flag_invalid
)) {
2969 wth2
= FP_TO_INT32_OVERFLOW
;
2972 set_float_exception_flags(excp
| excph
, &env
->active_fpu
.fp_status
);
2973 update_fcr31(env
, GETPC());
2975 return ((uint64_t)wth2
<< 32) | wt2
;
2978 uint32_t helper_float_cvts_d(CPUMIPSState
*env
, uint64_t fdt0
)
2982 fst2
= float64_to_float32(fdt0
, &env
->active_fpu
.fp_status
);
2983 update_fcr31(env
, GETPC());
2987 uint32_t helper_float_cvts_w(CPUMIPSState
*env
, uint32_t wt0
)
2991 fst2
= int32_to_float32(wt0
, &env
->active_fpu
.fp_status
);
2992 update_fcr31(env
, GETPC());
2996 uint32_t helper_float_cvts_l(CPUMIPSState
*env
, uint64_t dt0
)
3000 fst2
= int64_to_float32(dt0
, &env
->active_fpu
.fp_status
);
3001 update_fcr31(env
, GETPC());
3005 uint32_t helper_float_cvts_pl(CPUMIPSState
*env
, uint32_t wt0
)
3010 update_fcr31(env
, GETPC());
3014 uint32_t helper_float_cvts_pu(CPUMIPSState
*env
, uint32_t wth0
)
3019 update_fcr31(env
, GETPC());
3023 uint32_t helper_float_cvt_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3027 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3028 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3029 & (float_flag_invalid
| float_flag_overflow
)) {
3030 wt2
= FP_TO_INT32_OVERFLOW
;
3032 update_fcr31(env
, GETPC());
3036 uint32_t helper_float_cvt_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3040 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3041 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3042 & (float_flag_invalid
| float_flag_overflow
)) {
3043 wt2
= FP_TO_INT32_OVERFLOW
;
3045 update_fcr31(env
, GETPC());
3049 uint64_t helper_float_round_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3053 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
3054 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3055 restore_rounding_mode(env
);
3056 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3057 & (float_flag_invalid
| float_flag_overflow
)) {
3058 dt2
= FP_TO_INT64_OVERFLOW
;
3060 update_fcr31(env
, GETPC());
3064 uint64_t helper_float_round_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3068 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
3069 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3070 restore_rounding_mode(env
);
3071 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3072 & (float_flag_invalid
| float_flag_overflow
)) {
3073 dt2
= FP_TO_INT64_OVERFLOW
;
3075 update_fcr31(env
, GETPC());
3079 uint32_t helper_float_round_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3083 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
3084 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3085 restore_rounding_mode(env
);
3086 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3087 & (float_flag_invalid
| float_flag_overflow
)) {
3088 wt2
= FP_TO_INT32_OVERFLOW
;
3090 update_fcr31(env
, GETPC());
3094 uint32_t helper_float_round_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3098 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
3099 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3100 restore_rounding_mode(env
);
3101 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3102 & (float_flag_invalid
| float_flag_overflow
)) {
3103 wt2
= FP_TO_INT32_OVERFLOW
;
3105 update_fcr31(env
, GETPC());
3109 uint64_t helper_float_trunc_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3113 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3114 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3115 & (float_flag_invalid
| float_flag_overflow
)) {
3116 dt2
= FP_TO_INT64_OVERFLOW
;
3118 update_fcr31(env
, GETPC());
3122 uint64_t helper_float_trunc_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3126 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3127 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3128 & (float_flag_invalid
| float_flag_overflow
)) {
3129 dt2
= FP_TO_INT64_OVERFLOW
;
3131 update_fcr31(env
, GETPC());
3135 uint32_t helper_float_trunc_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3139 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3140 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3141 & (float_flag_invalid
| float_flag_overflow
)) {
3142 wt2
= FP_TO_INT32_OVERFLOW
;
3144 update_fcr31(env
, GETPC());
3148 uint32_t helper_float_trunc_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3152 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3153 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3154 & (float_flag_invalid
| float_flag_overflow
)) {
3155 wt2
= FP_TO_INT32_OVERFLOW
;
3157 update_fcr31(env
, GETPC());
3161 uint64_t helper_float_ceil_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3165 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3166 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3167 restore_rounding_mode(env
);
3168 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3169 & (float_flag_invalid
| float_flag_overflow
)) {
3170 dt2
= FP_TO_INT64_OVERFLOW
;
3172 update_fcr31(env
, GETPC());
3176 uint64_t helper_float_ceil_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3180 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3181 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3182 restore_rounding_mode(env
);
3183 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3184 & (float_flag_invalid
| float_flag_overflow
)) {
3185 dt2
= FP_TO_INT64_OVERFLOW
;
3187 update_fcr31(env
, GETPC());
3191 uint32_t helper_float_ceil_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3195 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3196 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3197 restore_rounding_mode(env
);
3198 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3199 & (float_flag_invalid
| float_flag_overflow
)) {
3200 wt2
= FP_TO_INT32_OVERFLOW
;
3202 update_fcr31(env
, GETPC());
3206 uint32_t helper_float_ceil_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3210 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3211 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3212 restore_rounding_mode(env
);
3213 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3214 & (float_flag_invalid
| float_flag_overflow
)) {
3215 wt2
= FP_TO_INT32_OVERFLOW
;
3217 update_fcr31(env
, GETPC());
3221 uint64_t helper_float_floor_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3225 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3226 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3227 restore_rounding_mode(env
);
3228 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3229 & (float_flag_invalid
| float_flag_overflow
)) {
3230 dt2
= FP_TO_INT64_OVERFLOW
;
3232 update_fcr31(env
, GETPC());
3236 uint64_t helper_float_floor_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3240 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3241 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3242 restore_rounding_mode(env
);
3243 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3244 & (float_flag_invalid
| float_flag_overflow
)) {
3245 dt2
= FP_TO_INT64_OVERFLOW
;
3247 update_fcr31(env
, GETPC());
3251 uint32_t helper_float_floor_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3255 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3256 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3257 restore_rounding_mode(env
);
3258 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3259 & (float_flag_invalid
| float_flag_overflow
)) {
3260 wt2
= FP_TO_INT32_OVERFLOW
;
3262 update_fcr31(env
, GETPC());
3266 uint32_t helper_float_floor_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3270 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3271 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3272 restore_rounding_mode(env
);
3273 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3274 & (float_flag_invalid
| float_flag_overflow
)) {
3275 wt2
= FP_TO_INT32_OVERFLOW
;
3277 update_fcr31(env
, GETPC());
3281 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3285 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3286 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3287 & float_flag_invalid
) {
3288 if (float64_is_any_nan(fdt0
)) {
3292 update_fcr31(env
, GETPC());
3296 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3300 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3301 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3302 & float_flag_invalid
) {
3303 if (float32_is_any_nan(fst0
)) {
3307 update_fcr31(env
, GETPC());
3311 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3315 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3316 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3317 & float_flag_invalid
) {
3318 if (float64_is_any_nan(fdt0
)) {
3322 update_fcr31(env
, GETPC());
3326 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3330 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3331 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3332 & float_flag_invalid
) {
3333 if (float32_is_any_nan(fst0
)) {
3337 update_fcr31(env
, GETPC());
3341 uint64_t helper_float_round_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3345 set_float_rounding_mode(float_round_nearest_even
,
3346 &env
->active_fpu
.fp_status
);
3347 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3348 restore_rounding_mode(env
);
3349 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3350 & float_flag_invalid
) {
3351 if (float64_is_any_nan(fdt0
)) {
3355 update_fcr31(env
, GETPC());
3359 uint64_t helper_float_round_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3363 set_float_rounding_mode(float_round_nearest_even
,
3364 &env
->active_fpu
.fp_status
);
3365 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3366 restore_rounding_mode(env
);
3367 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3368 & float_flag_invalid
) {
3369 if (float32_is_any_nan(fst0
)) {
3373 update_fcr31(env
, GETPC());
3377 uint32_t helper_float_round_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3381 set_float_rounding_mode(float_round_nearest_even
,
3382 &env
->active_fpu
.fp_status
);
3383 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3384 restore_rounding_mode(env
);
3385 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3386 & float_flag_invalid
) {
3387 if (float64_is_any_nan(fdt0
)) {
3391 update_fcr31(env
, GETPC());
3395 uint32_t helper_float_round_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3399 set_float_rounding_mode(float_round_nearest_even
,
3400 &env
->active_fpu
.fp_status
);
3401 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3402 restore_rounding_mode(env
);
3403 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3404 & float_flag_invalid
) {
3405 if (float32_is_any_nan(fst0
)) {
3409 update_fcr31(env
, GETPC());
3413 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3417 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3418 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3419 & float_flag_invalid
) {
3420 if (float64_is_any_nan(fdt0
)) {
3424 update_fcr31(env
, GETPC());
3428 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3432 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3433 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3434 & float_flag_invalid
) {
3435 if (float32_is_any_nan(fst0
)) {
3439 update_fcr31(env
, GETPC());
3443 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3447 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3448 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3449 & float_flag_invalid
) {
3450 if (float64_is_any_nan(fdt0
)) {
3454 update_fcr31(env
, GETPC());
3458 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3462 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3463 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3464 & float_flag_invalid
) {
3465 if (float32_is_any_nan(fst0
)) {
3469 update_fcr31(env
, GETPC());
3473 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3477 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3478 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3479 restore_rounding_mode(env
);
3480 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3481 & float_flag_invalid
) {
3482 if (float64_is_any_nan(fdt0
)) {
3486 update_fcr31(env
, GETPC());
3490 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3494 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3495 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3496 restore_rounding_mode(env
);
3497 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3498 & float_flag_invalid
) {
3499 if (float32_is_any_nan(fst0
)) {
3503 update_fcr31(env
, GETPC());
3507 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3511 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3512 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3513 restore_rounding_mode(env
);
3514 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3515 & float_flag_invalid
) {
3516 if (float64_is_any_nan(fdt0
)) {
3520 update_fcr31(env
, GETPC());
3524 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3528 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3529 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3530 restore_rounding_mode(env
);
3531 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3532 & float_flag_invalid
) {
3533 if (float32_is_any_nan(fst0
)) {
3537 update_fcr31(env
, GETPC());
3541 uint64_t helper_float_floor_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3545 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3546 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3547 restore_rounding_mode(env
);
3548 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3549 & float_flag_invalid
) {
3550 if (float64_is_any_nan(fdt0
)) {
3554 update_fcr31(env
, GETPC());
3558 uint64_t helper_float_floor_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3562 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3563 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3564 restore_rounding_mode(env
);
3565 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3566 & float_flag_invalid
) {
3567 if (float32_is_any_nan(fst0
)) {
3571 update_fcr31(env
, GETPC());
3575 uint32_t helper_float_floor_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3579 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3580 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3581 restore_rounding_mode(env
);
3582 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3583 & float_flag_invalid
) {
3584 if (float64_is_any_nan(fdt0
)) {
3588 update_fcr31(env
, GETPC());
3592 uint32_t helper_float_floor_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3596 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3597 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3598 restore_rounding_mode(env
);
3599 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3600 & float_flag_invalid
) {
3601 if (float32_is_any_nan(fst0
)) {
3605 update_fcr31(env
, GETPC());
3609 /* unary operations, not modifying fp status */
3610 #define FLOAT_UNOP(name) \
3611 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3613 return float64_ ## name(fdt0); \
3615 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3617 return float32_ ## name(fst0); \
3619 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3624 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3625 wth0 = float32_ ## name(fdt0 >> 32); \
3626 return ((uint64_t)wth0 << 32) | wt0; \
3632 /* MIPS specific unary operations */
3633 uint64_t helper_float_recip_d(CPUMIPSState
*env
, uint64_t fdt0
)
3637 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3638 update_fcr31(env
, GETPC());
3642 uint32_t helper_float_recip_s(CPUMIPSState
*env
, uint32_t fst0
)
3646 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3647 update_fcr31(env
, GETPC());
3651 uint64_t helper_float_rsqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
3655 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3656 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3657 update_fcr31(env
, GETPC());
3661 uint32_t helper_float_rsqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
3665 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3666 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3667 update_fcr31(env
, GETPC());
3671 uint64_t helper_float_recip1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3675 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3676 update_fcr31(env
, GETPC());
3680 uint32_t helper_float_recip1_s(CPUMIPSState
*env
, uint32_t fst0
)
3684 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3685 update_fcr31(env
, GETPC());
3689 uint64_t helper_float_recip1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3694 fst2
= float32_div(float32_one
, fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3695 fsth2
= float32_div(float32_one
, fdt0
>> 32, &env
->active_fpu
.fp_status
);
3696 update_fcr31(env
, GETPC());
3697 return ((uint64_t)fsth2
<< 32) | fst2
;
3700 uint64_t helper_float_rsqrt1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3704 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3705 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3706 update_fcr31(env
, GETPC());
3710 uint32_t helper_float_rsqrt1_s(CPUMIPSState
*env
, uint32_t fst0
)
3714 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3715 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3716 update_fcr31(env
, GETPC());
3720 uint64_t helper_float_rsqrt1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3725 fst2
= float32_sqrt(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3726 fsth2
= float32_sqrt(fdt0
>> 32, &env
->active_fpu
.fp_status
);
3727 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3728 fsth2
= float32_div(float32_one
, fsth2
, &env
->active_fpu
.fp_status
);
3729 update_fcr31(env
, GETPC());
3730 return ((uint64_t)fsth2
<< 32) | fst2
;
3733 #define FLOAT_RINT(name, bits) \
3734 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3735 uint ## bits ## _t fs) \
3737 uint ## bits ## _t fdret; \
3739 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3740 update_fcr31(env, GETPC()); \
3744 FLOAT_RINT(rint_s
, 32)
3745 FLOAT_RINT(rint_d
, 64)
3748 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3749 #define FLOAT_CLASS_QUIET_NAN 0x002
3750 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3751 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3752 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3753 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3754 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3755 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3756 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3757 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3759 #define FLOAT_CLASS(name, bits) \
3760 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3761 float_status *status) \
3763 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3764 return FLOAT_CLASS_SIGNALING_NAN; \
3765 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3766 return FLOAT_CLASS_QUIET_NAN; \
3767 } else if (float ## bits ## _is_neg(arg)) { \
3768 if (float ## bits ## _is_infinity(arg)) { \
3769 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3770 } else if (float ## bits ## _is_zero(arg)) { \
3771 return FLOAT_CLASS_NEGATIVE_ZERO; \
3772 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3773 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3775 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3778 if (float ## bits ## _is_infinity(arg)) { \
3779 return FLOAT_CLASS_POSITIVE_INFINITY; \
3780 } else if (float ## bits ## _is_zero(arg)) { \
3781 return FLOAT_CLASS_POSITIVE_ZERO; \
3782 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3783 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3785 return FLOAT_CLASS_POSITIVE_NORMAL; \
3790 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3791 uint ## bits ## _t arg) \
3793 return float_ ## name(arg, &env->active_fpu.fp_status); \
3796 FLOAT_CLASS(class_s
, 32)
3797 FLOAT_CLASS(class_d
, 64)
3800 /* binary operations */
3801 #define FLOAT_BINOP(name) \
3802 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3803 uint64_t fdt0, uint64_t fdt1) \
3807 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3808 update_fcr31(env, GETPC()); \
3812 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3813 uint32_t fst0, uint32_t fst1) \
3817 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3818 update_fcr31(env, GETPC()); \
3822 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3826 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3827 uint32_t fsth0 = fdt0 >> 32; \
3828 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3829 uint32_t fsth1 = fdt1 >> 32; \
3833 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3834 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3835 update_fcr31(env, GETPC()); \
3836 return ((uint64_t)wth2 << 32) | wt2; \
3845 /* MIPS specific binary operations */
3846 uint64_t helper_float_recip2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3848 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3849 fdt2
= float64_chs(float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
));
3850 update_fcr31(env
, GETPC());
3854 uint32_t helper_float_recip2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3856 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3857 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3858 update_fcr31(env
, GETPC());
3862 uint64_t helper_float_recip2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3864 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3865 uint32_t fsth0
= fdt0
>> 32;
3866 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3867 uint32_t fsth2
= fdt2
>> 32;
3869 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3870 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3871 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3872 fsth2
= float32_chs(float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
));
3873 update_fcr31(env
, GETPC());
3874 return ((uint64_t)fsth2
<< 32) | fst2
;
3877 uint64_t helper_float_rsqrt2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3879 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3880 fdt2
= float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
);
3881 fdt2
= float64_chs(float64_div(fdt2
, FLOAT_TWO64
, &env
->active_fpu
.fp_status
));
3882 update_fcr31(env
, GETPC());
3886 uint32_t helper_float_rsqrt2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3888 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3889 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3890 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3891 update_fcr31(env
, GETPC());
3895 uint64_t helper_float_rsqrt2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3897 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3898 uint32_t fsth0
= fdt0
>> 32;
3899 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3900 uint32_t fsth2
= fdt2
>> 32;
3902 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3903 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3904 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3905 fsth2
= float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
);
3906 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3907 fsth2
= float32_chs(float32_div(fsth2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3908 update_fcr31(env
, GETPC());
3909 return ((uint64_t)fsth2
<< 32) | fst2
;
3912 uint64_t helper_float_addr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3914 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3915 uint32_t fsth0
= fdt0
>> 32;
3916 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3917 uint32_t fsth1
= fdt1
>> 32;
3921 fst2
= float32_add (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3922 fsth2
= float32_add (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3923 update_fcr31(env
, GETPC());
3924 return ((uint64_t)fsth2
<< 32) | fst2
;
3927 uint64_t helper_float_mulr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3929 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3930 uint32_t fsth0
= fdt0
>> 32;
3931 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3932 uint32_t fsth1
= fdt1
>> 32;
3936 fst2
= float32_mul (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3937 fsth2
= float32_mul (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3938 update_fcr31(env
, GETPC());
3939 return ((uint64_t)fsth2
<< 32) | fst2
;
3942 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3943 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3944 uint ## bits ## _t fs, \
3945 uint ## bits ## _t ft) \
3947 uint ## bits ## _t fdret; \
3949 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3950 &env->active_fpu.fp_status); \
3951 update_fcr31(env, GETPC()); \
3955 FLOAT_MINMAX(max_s
, 32, maxnum
)
3956 FLOAT_MINMAX(max_d
, 64, maxnum
)
3957 FLOAT_MINMAX(maxa_s
, 32, maxnummag
)
3958 FLOAT_MINMAX(maxa_d
, 64, maxnummag
)
3960 FLOAT_MINMAX(min_s
, 32, minnum
)
3961 FLOAT_MINMAX(min_d
, 64, minnum
)
3962 FLOAT_MINMAX(mina_s
, 32, minnummag
)
3963 FLOAT_MINMAX(mina_d
, 64, minnummag
)
3966 /* ternary operations */
3967 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3969 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3970 if ((flags) & float_muladd_negate_c) { \
3971 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3973 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3975 if ((flags) & float_muladd_negate_result) { \
3976 a = prefix##_chs(a); \
3980 /* FMA based operations */
3981 #define FLOAT_FMA(name, type) \
3982 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3983 uint64_t fdt0, uint64_t fdt1, \
3986 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3987 update_fcr31(env, GETPC()); \
3991 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3992 uint32_t fst0, uint32_t fst1, \
3995 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3996 update_fcr31(env, GETPC()); \
4000 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
4001 uint64_t fdt0, uint64_t fdt1, \
4004 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
4005 uint32_t fsth0 = fdt0 >> 32; \
4006 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
4007 uint32_t fsth1 = fdt1 >> 32; \
4008 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
4009 uint32_t fsth2 = fdt2 >> 32; \
4011 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4012 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
4013 update_fcr31(env, GETPC()); \
4014 return ((uint64_t)fsth0 << 32) | fst0; \
4017 FLOAT_FMA(msub
, float_muladd_negate_c
)
4018 FLOAT_FMA(nmadd
, float_muladd_negate_result
)
4019 FLOAT_FMA(nmsub
, float_muladd_negate_result
| float_muladd_negate_c
)
4022 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
4023 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
4024 uint ## bits ## _t fs, \
4025 uint ## bits ## _t ft, \
4026 uint ## bits ## _t fd) \
4028 uint ## bits ## _t fdret; \
4030 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
4031 &env->active_fpu.fp_status); \
4032 update_fcr31(env, GETPC()); \
4036 FLOAT_FMADDSUB(maddf_s
, 32, 0)
4037 FLOAT_FMADDSUB(maddf_d
, 64, 0)
4038 FLOAT_FMADDSUB(msubf_s
, 32, float_muladd_negate_product
)
4039 FLOAT_FMADDSUB(msubf_d
, 64, float_muladd_negate_product
)
4040 #undef FLOAT_FMADDSUB
4042 /* compare operations */
4043 #define FOP_COND_D(op, cond) \
4044 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4045 uint64_t fdt1, int cc) \
4049 update_fcr31(env, GETPC()); \
4051 SET_FP_COND(cc, env->active_fpu); \
4053 CLEAR_FP_COND(cc, env->active_fpu); \
4055 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4056 uint64_t fdt1, int cc) \
4059 fdt0 = float64_abs(fdt0); \
4060 fdt1 = float64_abs(fdt1); \
4062 update_fcr31(env, GETPC()); \
4064 SET_FP_COND(cc, env->active_fpu); \
4066 CLEAR_FP_COND(cc, env->active_fpu); \
4069 /* NOTE: the comma operator will make "cond" to eval to false,
4070 * but float64_unordered_quiet() is still called. */
4071 FOP_COND_D(f
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4072 FOP_COND_D(un
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
4073 FOP_COND_D(eq
, float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4074 FOP_COND_D(ueq
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4075 FOP_COND_D(olt
, float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4076 FOP_COND_D(ult
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4077 FOP_COND_D(ole
, float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4078 FOP_COND_D(ule
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4079 /* NOTE: the comma operator will make "cond" to eval to false,
4080 * but float64_unordered() is still called. */
4081 FOP_COND_D(sf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4082 FOP_COND_D(ngle
,float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
4083 FOP_COND_D(seq
, float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4084 FOP_COND_D(ngl
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4085 FOP_COND_D(lt
, float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4086 FOP_COND_D(nge
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4087 FOP_COND_D(le
, float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4088 FOP_COND_D(ngt
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4090 #define FOP_COND_S(op, cond) \
4091 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4092 uint32_t fst1, int cc) \
4096 update_fcr31(env, GETPC()); \
4098 SET_FP_COND(cc, env->active_fpu); \
4100 CLEAR_FP_COND(cc, env->active_fpu); \
4102 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4103 uint32_t fst1, int cc) \
4106 fst0 = float32_abs(fst0); \
4107 fst1 = float32_abs(fst1); \
4109 update_fcr31(env, GETPC()); \
4111 SET_FP_COND(cc, env->active_fpu); \
4113 CLEAR_FP_COND(cc, env->active_fpu); \
4116 /* NOTE: the comma operator will make "cond" to eval to false,
4117 * but float32_unordered_quiet() is still called. */
4118 FOP_COND_S(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4119 FOP_COND_S(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
))
4120 FOP_COND_S(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4121 FOP_COND_S(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4122 FOP_COND_S(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4123 FOP_COND_S(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4124 FOP_COND_S(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4125 FOP_COND_S(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4126 /* NOTE: the comma operator will make "cond" to eval to false,
4127 * but float32_unordered() is still called. */
4128 FOP_COND_S(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4129 FOP_COND_S(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
))
4130 FOP_COND_S(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4131 FOP_COND_S(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4132 FOP_COND_S(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4133 FOP_COND_S(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4134 FOP_COND_S(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4135 FOP_COND_S(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4137 #define FOP_COND_PS(op, condl, condh) \
4138 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4139 uint64_t fdt1, int cc) \
4141 uint32_t fst0, fsth0, fst1, fsth1; \
4143 fst0 = fdt0 & 0XFFFFFFFF; \
4144 fsth0 = fdt0 >> 32; \
4145 fst1 = fdt1 & 0XFFFFFFFF; \
4146 fsth1 = fdt1 >> 32; \
4149 update_fcr31(env, GETPC()); \
4151 SET_FP_COND(cc, env->active_fpu); \
4153 CLEAR_FP_COND(cc, env->active_fpu); \
4155 SET_FP_COND(cc + 1, env->active_fpu); \
4157 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4159 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4160 uint64_t fdt1, int cc) \
4162 uint32_t fst0, fsth0, fst1, fsth1; \
4164 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
4165 fsth0 = float32_abs(fdt0 >> 32); \
4166 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
4167 fsth1 = float32_abs(fdt1 >> 32); \
4170 update_fcr31(env, GETPC()); \
4172 SET_FP_COND(cc, env->active_fpu); \
4174 CLEAR_FP_COND(cc, env->active_fpu); \
4176 SET_FP_COND(cc + 1, env->active_fpu); \
4178 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4181 /* NOTE: the comma operator will make "cond" to eval to false,
4182 * but float32_unordered_quiet() is still called. */
4183 FOP_COND_PS(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
4184 (float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
4185 FOP_COND_PS(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
),
4186 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
4187 FOP_COND_PS(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4188 float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4189 FOP_COND_PS(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4190 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4191 FOP_COND_PS(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4192 float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4193 FOP_COND_PS(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4194 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4195 FOP_COND_PS(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4196 float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4197 FOP_COND_PS(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4198 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4199 /* NOTE: the comma operator will make "cond" to eval to false,
4200 * but float32_unordered() is still called. */
4201 FOP_COND_PS(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
4202 (float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
4203 FOP_COND_PS(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
),
4204 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
4205 FOP_COND_PS(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4206 float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4207 FOP_COND_PS(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4208 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4209 FOP_COND_PS(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4210 float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4211 FOP_COND_PS(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4212 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4213 FOP_COND_PS(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4214 float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4215 FOP_COND_PS(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4216 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4218 /* R6 compare operations */
4219 #define FOP_CONDN_D(op, cond) \
4220 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
4225 update_fcr31(env, GETPC()); \
4233 /* NOTE: the comma operator will make "cond" to eval to false,
4234 * but float64_unordered_quiet() is still called. */
4235 FOP_CONDN_D(af
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4236 FOP_CONDN_D(un
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
4237 FOP_CONDN_D(eq
, (float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4238 FOP_CONDN_D(ueq
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4239 || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4240 FOP_CONDN_D(lt
, (float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4241 FOP_CONDN_D(ult
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4242 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4243 FOP_CONDN_D(le
, (float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4244 FOP_CONDN_D(ule
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4245 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4246 /* NOTE: the comma operator will make "cond" to eval to false,
4247 * but float64_unordered() is still called. */
4248 FOP_CONDN_D(saf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4249 FOP_CONDN_D(sun
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
4250 FOP_CONDN_D(seq
, (float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4251 FOP_CONDN_D(sueq
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4252 || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4253 FOP_CONDN_D(slt
, (float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4254 FOP_CONDN_D(sult
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4255 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4256 FOP_CONDN_D(sle
, (float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4257 FOP_CONDN_D(sule
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4258 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4259 FOP_CONDN_D(or, (float64_le_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4260 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4261 FOP_CONDN_D(une
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4262 || float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4263 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4264 FOP_CONDN_D(ne
, (float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4265 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4266 FOP_CONDN_D(sor
, (float64_le(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4267 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4268 FOP_CONDN_D(sune
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4269 || float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4270 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4271 FOP_CONDN_D(sne
, (float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4272 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4274 #define FOP_CONDN_S(op, cond) \
4275 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4280 update_fcr31(env, GETPC()); \
4288 /* NOTE: the comma operator will make "cond" to eval to false,
4289 * but float32_unordered_quiet() is still called. */
4290 FOP_CONDN_S(af
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4291 FOP_CONDN_S(un
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
4292 FOP_CONDN_S(eq
, (float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4293 FOP_CONDN_S(ueq
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4294 || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4295 FOP_CONDN_S(lt
, (float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4296 FOP_CONDN_S(ult
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4297 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4298 FOP_CONDN_S(le
, (float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4299 FOP_CONDN_S(ule
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4300 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4301 /* NOTE: the comma operator will make "cond" to eval to false,
4302 * but float32_unordered() is still called. */
4303 FOP_CONDN_S(saf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4304 FOP_CONDN_S(sun
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
4305 FOP_CONDN_S(seq
, (float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4306 FOP_CONDN_S(sueq
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4307 || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4308 FOP_CONDN_S(slt
, (float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4309 FOP_CONDN_S(sult
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4310 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4311 FOP_CONDN_S(sle
, (float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4312 FOP_CONDN_S(sule
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4313 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4314 FOP_CONDN_S(or, (float32_le_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4315 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4316 FOP_CONDN_S(une
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4317 || float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4318 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4319 FOP_CONDN_S(ne
, (float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4320 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4321 FOP_CONDN_S(sor
, (float32_le(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4322 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4323 FOP_CONDN_S(sune
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4324 || float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4325 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4326 FOP_CONDN_S(sne
, (float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4327 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4330 /* Data format min and max values */
4331 #define DF_BITS(df) (1 << ((df) + 3))
4333 /* Element-by-element access macros */
4334 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4336 #if !defined(CONFIG_USER_ONLY)
4337 #define MEMOP_IDX(DF) \
4338 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4339 cpu_mmu_index(env, false));
4341 #define MEMOP_IDX(DF)
4344 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
4345 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4346 target_ulong addr) \
4348 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4352 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4353 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
4355 memcpy(pwd, &wx, sizeof(wr_t)); \
4358 #if !defined(CONFIG_USER_ONLY)
4359 MSA_LD_DF(DF_BYTE
, b
, helper_ret_ldub_mmu
, oi
, GETPC())
4360 MSA_LD_DF(DF_HALF
, h
, helper_ret_lduw_mmu
, oi
, GETPC())
4361 MSA_LD_DF(DF_WORD
, w
, helper_ret_ldul_mmu
, oi
, GETPC())
4362 MSA_LD_DF(DF_DOUBLE
, d
, helper_ret_ldq_mmu
, oi
, GETPC())
4364 MSA_LD_DF(DF_BYTE
, b
, cpu_ldub_data
)
4365 MSA_LD_DF(DF_HALF
, h
, cpu_lduw_data
)
4366 MSA_LD_DF(DF_WORD
, w
, cpu_ldl_data
)
4367 MSA_LD_DF(DF_DOUBLE
, d
, cpu_ldq_data
)
4370 #define MSA_PAGESPAN(x) \
4371 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4373 static inline void ensure_writable_pages(CPUMIPSState
*env
,
4378 #if !defined(CONFIG_USER_ONLY)
4379 target_ulong page_addr
;
4380 if (unlikely(MSA_PAGESPAN(addr
))) {
4382 probe_write(env
, addr
, 0, mmu_idx
, retaddr
);
4384 page_addr
= (addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
4385 probe_write(env
, page_addr
, 0, mmu_idx
, retaddr
);
4390 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
4391 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4392 target_ulong addr) \
4394 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4395 int mmu_idx = cpu_mmu_index(env, false); \
4398 ensure_writable_pages(env, addr, mmu_idx, GETPC()); \
4399 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4400 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
4404 #if !defined(CONFIG_USER_ONLY)
4405 MSA_ST_DF(DF_BYTE
, b
, helper_ret_stb_mmu
, oi
, GETPC())
4406 MSA_ST_DF(DF_HALF
, h
, helper_ret_stw_mmu
, oi
, GETPC())
4407 MSA_ST_DF(DF_WORD
, w
, helper_ret_stl_mmu
, oi
, GETPC())
4408 MSA_ST_DF(DF_DOUBLE
, d
, helper_ret_stq_mmu
, oi
, GETPC())
4410 MSA_ST_DF(DF_BYTE
, b
, cpu_stb_data
)
4411 MSA_ST_DF(DF_HALF
, h
, cpu_stw_data
)
4412 MSA_ST_DF(DF_WORD
, w
, cpu_stl_data
)
4413 MSA_ST_DF(DF_DOUBLE
, d
, cpu_stq_data
)
4416 void helper_cache(CPUMIPSState
*env
, target_ulong addr
, uint32_t op
)
4418 #ifndef CONFIG_USER_ONLY
4419 target_ulong index
= addr
& 0x1fffffff;
4421 /* Index Store Tag */
4422 memory_region_dispatch_write(env
->itc_tag
, index
, env
->CP0_TagLo
,
4423 8, MEMTXATTRS_UNSPECIFIED
);
4424 } else if (op
== 5) {
4425 /* Index Load Tag */
4426 memory_region_dispatch_read(env
->itc_tag
, index
, &env
->CP0_TagLo
,
4427 8, MEMTXATTRS_UNSPECIFIED
);