cpus: reset throttle_thread_scheduled after sleep
[qemu/ar7.git] / exec.c
bloba93e209625979fab355a59a22f931fee7da560fd
1 /*
2 * Virtual page mapping
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
21 #ifndef _WIN32
22 #endif
24 #include "qemu/cutils.h"
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "exec/target_page.h"
28 #include "tcg.h"
29 #include "hw/qdev-core.h"
30 #if !defined(CONFIG_USER_ONLY)
31 #include "hw/boards.h"
32 #include "hw/xen/xen.h"
33 #endif
34 #include "sysemu/kvm.h"
35 #include "sysemu/sysemu.h"
36 #include "qemu/timer.h"
37 #include "qemu/config-file.h"
38 #include "qemu/error-report.h"
39 #if defined(CONFIG_USER_ONLY)
40 #include "qemu.h"
41 #else /* !CONFIG_USER_ONLY */
42 #include "hw/hw.h"
43 #include "exec/memory.h"
44 #include "exec/ioport.h"
45 #include "sysemu/dma.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/hw_accel.h"
48 #include "exec/address-spaces.h"
49 #include "sysemu/xen-mapcache.h"
50 #include "trace-root.h"
52 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
53 #include <fcntl.h>
54 #include <linux/falloc.h>
55 #endif
57 #endif
58 #include "exec/cpu-all.h"
59 #include "qemu/rcu_queue.h"
60 #include "qemu/main-loop.h"
61 #include "translate-all.h"
62 #include "sysemu/replay.h"
64 #include "exec/memory-internal.h"
65 #include "exec/ram_addr.h"
66 #include "exec/log.h"
68 #include "migration/vmstate.h"
70 #include "qemu/range.h"
71 #ifndef _WIN32
72 #include "qemu/mmap-alloc.h"
73 #endif
75 #include "monitor/monitor.h"
77 //#define DEBUG_SUBPAGE
79 #if !defined(CONFIG_USER_ONLY)
80 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
81 * are protected by the ramlist lock.
83 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
85 static MemoryRegion *system_memory;
86 static MemoryRegion *system_io;
88 AddressSpace address_space_io;
89 AddressSpace address_space_memory;
91 MemoryRegion io_mem_rom, io_mem_notdirty;
92 static MemoryRegion io_mem_unassigned;
94 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
95 #define RAM_PREALLOC (1 << 0)
97 /* RAM is mmap-ed with MAP_SHARED */
98 #define RAM_SHARED (1 << 1)
100 /* Only a portion of RAM (used_length) is actually used, and migrated.
101 * This used_length size can change across reboots.
103 #define RAM_RESIZEABLE (1 << 2)
105 #endif
107 #ifdef TARGET_PAGE_BITS_VARY
108 int target_page_bits;
109 bool target_page_bits_decided;
110 #endif
112 struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
113 /* current CPU in the current thread. It is only valid inside
114 cpu_exec() */
115 __thread CPUState *current_cpu;
116 /* 0 = Do not count executed instructions.
117 1 = Precise instruction counting.
118 2 = Adaptive rate instruction counting. */
119 int use_icount;
121 bool set_preferred_target_page_bits(int bits)
123 /* The target page size is the lowest common denominator for all
124 * the CPUs in the system, so we can only make it smaller, never
125 * larger. And we can't make it smaller once we've committed to
126 * a particular size.
128 #ifdef TARGET_PAGE_BITS_VARY
129 assert(bits >= TARGET_PAGE_BITS_MIN);
130 if (target_page_bits == 0 || target_page_bits > bits) {
131 if (target_page_bits_decided) {
132 return false;
134 target_page_bits = bits;
136 #endif
137 return true;
140 #if !defined(CONFIG_USER_ONLY)
142 static void finalize_target_page_bits(void)
144 #ifdef TARGET_PAGE_BITS_VARY
145 if (target_page_bits == 0) {
146 target_page_bits = TARGET_PAGE_BITS_MIN;
148 target_page_bits_decided = true;
149 #endif
152 typedef struct PhysPageEntry PhysPageEntry;
154 struct PhysPageEntry {
155 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
156 uint32_t skip : 6;
157 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
158 uint32_t ptr : 26;
161 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
163 /* Size of the L2 (and L3, etc) page tables. */
164 #define ADDR_SPACE_BITS 64
166 #define P_L2_BITS 9
167 #define P_L2_SIZE (1 << P_L2_BITS)
169 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
171 typedef PhysPageEntry Node[P_L2_SIZE];
173 typedef struct PhysPageMap {
174 struct rcu_head rcu;
176 unsigned sections_nb;
177 unsigned sections_nb_alloc;
178 unsigned nodes_nb;
179 unsigned nodes_nb_alloc;
180 Node *nodes;
181 MemoryRegionSection *sections;
182 } PhysPageMap;
184 struct AddressSpaceDispatch {
185 struct rcu_head rcu;
187 MemoryRegionSection *mru_section;
188 /* This is a multi-level map on the physical address space.
189 * The bottom level has pointers to MemoryRegionSections.
191 PhysPageEntry phys_map;
192 PhysPageMap map;
193 AddressSpace *as;
196 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
197 typedef struct subpage_t {
198 MemoryRegion iomem;
199 AddressSpace *as;
200 hwaddr base;
201 uint16_t sub_section[];
202 } subpage_t;
204 #define PHYS_SECTION_UNASSIGNED 0
205 #define PHYS_SECTION_NOTDIRTY 1
206 #define PHYS_SECTION_ROM 2
207 #define PHYS_SECTION_WATCH 3
209 static void io_mem_init(void);
210 static void memory_map_init(void);
211 static void tcg_commit(MemoryListener *listener);
213 static MemoryRegion io_mem_watch;
216 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
217 * @cpu: the CPU whose AddressSpace this is
218 * @as: the AddressSpace itself
219 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
220 * @tcg_as_listener: listener for tracking changes to the AddressSpace
222 struct CPUAddressSpace {
223 CPUState *cpu;
224 AddressSpace *as;
225 struct AddressSpaceDispatch *memory_dispatch;
226 MemoryListener tcg_as_listener;
229 struct DirtyBitmapSnapshot {
230 ram_addr_t start;
231 ram_addr_t end;
232 unsigned long dirty[];
235 #endif
237 #if !defined(CONFIG_USER_ONLY)
239 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
241 static unsigned alloc_hint = 16;
242 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
243 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
244 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
245 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
246 alloc_hint = map->nodes_nb_alloc;
250 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
252 unsigned i;
253 uint32_t ret;
254 PhysPageEntry e;
255 PhysPageEntry *p;
257 ret = map->nodes_nb++;
258 p = map->nodes[ret];
259 assert(ret != PHYS_MAP_NODE_NIL);
260 assert(ret != map->nodes_nb_alloc);
262 e.skip = leaf ? 0 : 1;
263 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
264 for (i = 0; i < P_L2_SIZE; ++i) {
265 memcpy(&p[i], &e, sizeof(e));
267 return ret;
270 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
271 hwaddr *index, hwaddr *nb, uint16_t leaf,
272 int level)
274 PhysPageEntry *p;
275 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
277 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
278 lp->ptr = phys_map_node_alloc(map, level == 0);
280 p = map->nodes[lp->ptr];
281 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
283 while (*nb && lp < &p[P_L2_SIZE]) {
284 if ((*index & (step - 1)) == 0 && *nb >= step) {
285 lp->skip = 0;
286 lp->ptr = leaf;
287 *index += step;
288 *nb -= step;
289 } else {
290 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
292 ++lp;
296 static void phys_page_set(AddressSpaceDispatch *d,
297 hwaddr index, hwaddr nb,
298 uint16_t leaf)
300 /* Wildly overreserve - it doesn't matter much. */
301 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
303 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
306 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
307 * and update our entry so we can skip it and go directly to the destination.
309 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
311 unsigned valid_ptr = P_L2_SIZE;
312 int valid = 0;
313 PhysPageEntry *p;
314 int i;
316 if (lp->ptr == PHYS_MAP_NODE_NIL) {
317 return;
320 p = nodes[lp->ptr];
321 for (i = 0; i < P_L2_SIZE; i++) {
322 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
323 continue;
326 valid_ptr = i;
327 valid++;
328 if (p[i].skip) {
329 phys_page_compact(&p[i], nodes);
333 /* We can only compress if there's only one child. */
334 if (valid != 1) {
335 return;
338 assert(valid_ptr < P_L2_SIZE);
340 /* Don't compress if it won't fit in the # of bits we have. */
341 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
342 return;
345 lp->ptr = p[valid_ptr].ptr;
346 if (!p[valid_ptr].skip) {
347 /* If our only child is a leaf, make this a leaf. */
348 /* By design, we should have made this node a leaf to begin with so we
349 * should never reach here.
350 * But since it's so simple to handle this, let's do it just in case we
351 * change this rule.
353 lp->skip = 0;
354 } else {
355 lp->skip += p[valid_ptr].skip;
359 static void phys_page_compact_all(AddressSpaceDispatch *d, int nodes_nb)
361 if (d->phys_map.skip) {
362 phys_page_compact(&d->phys_map, d->map.nodes);
366 static inline bool section_covers_addr(const MemoryRegionSection *section,
367 hwaddr addr)
369 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
370 * the section must cover the entire address space.
372 return int128_gethi(section->size) ||
373 range_covers_byte(section->offset_within_address_space,
374 int128_getlo(section->size), addr);
377 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
379 PhysPageEntry lp = d->phys_map, *p;
380 Node *nodes = d->map.nodes;
381 MemoryRegionSection *sections = d->map.sections;
382 hwaddr index = addr >> TARGET_PAGE_BITS;
383 int i;
385 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
386 if (lp.ptr == PHYS_MAP_NODE_NIL) {
387 return &sections[PHYS_SECTION_UNASSIGNED];
389 p = nodes[lp.ptr];
390 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
393 if (section_covers_addr(&sections[lp.ptr], addr)) {
394 return &sections[lp.ptr];
395 } else {
396 return &sections[PHYS_SECTION_UNASSIGNED];
400 bool memory_region_is_unassigned(MemoryRegion *mr)
402 return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
403 && mr != &io_mem_watch;
406 /* Called from RCU critical section */
407 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
408 hwaddr addr,
409 bool resolve_subpage)
411 MemoryRegionSection *section = atomic_read(&d->mru_section);
412 subpage_t *subpage;
413 bool update;
415 if (section && section != &d->map.sections[PHYS_SECTION_UNASSIGNED] &&
416 section_covers_addr(section, addr)) {
417 update = false;
418 } else {
419 section = phys_page_find(d, addr);
420 update = true;
422 if (resolve_subpage && section->mr->subpage) {
423 subpage = container_of(section->mr, subpage_t, iomem);
424 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
426 if (update) {
427 atomic_set(&d->mru_section, section);
429 return section;
432 /* Called from RCU critical section */
433 static MemoryRegionSection *
434 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
435 hwaddr *plen, bool resolve_subpage)
437 MemoryRegionSection *section;
438 MemoryRegion *mr;
439 Int128 diff;
441 section = address_space_lookup_region(d, addr, resolve_subpage);
442 /* Compute offset within MemoryRegionSection */
443 addr -= section->offset_within_address_space;
445 /* Compute offset within MemoryRegion */
446 *xlat = addr + section->offset_within_region;
448 mr = section->mr;
450 /* MMIO registers can be expected to perform full-width accesses based only
451 * on their address, without considering adjacent registers that could
452 * decode to completely different MemoryRegions. When such registers
453 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
454 * regions overlap wildly. For this reason we cannot clamp the accesses
455 * here.
457 * If the length is small (as is the case for address_space_ldl/stl),
458 * everything works fine. If the incoming length is large, however,
459 * the caller really has to do the clamping through memory_access_size.
461 if (memory_region_is_ram(mr)) {
462 diff = int128_sub(section->size, int128_make64(addr));
463 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
465 return section;
468 /* Called from RCU critical section */
469 static MemoryRegionSection address_space_do_translate(AddressSpace *as,
470 hwaddr addr,
471 hwaddr *xlat,
472 hwaddr *plen,
473 bool is_write,
474 bool is_mmio)
476 IOMMUTLBEntry iotlb;
477 MemoryRegionSection *section;
478 MemoryRegion *mr;
480 for (;;) {
481 AddressSpaceDispatch *d = atomic_rcu_read(&as->dispatch);
482 section = address_space_translate_internal(d, addr, &addr, plen, is_mmio);
483 mr = section->mr;
485 if (!mr->iommu_ops) {
486 break;
489 iotlb = mr->iommu_ops->translate(mr, addr, is_write ?
490 IOMMU_WO : IOMMU_RO);
491 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
492 | (addr & iotlb.addr_mask));
493 *plen = MIN(*plen, (addr | iotlb.addr_mask) - addr + 1);
494 if (!(iotlb.perm & (1 << is_write))) {
495 goto translate_fail;
498 as = iotlb.target_as;
501 *xlat = addr;
503 return *section;
505 translate_fail:
506 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
509 /* Called from RCU critical section */
510 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
511 bool is_write)
513 MemoryRegionSection section;
514 hwaddr xlat, plen;
516 /* Try to get maximum page mask during translation. */
517 plen = (hwaddr)-1;
519 /* This can never be MMIO. */
520 section = address_space_do_translate(as, addr, &xlat, &plen,
521 is_write, false);
523 /* Illegal translation */
524 if (section.mr == &io_mem_unassigned) {
525 goto iotlb_fail;
528 /* Convert memory region offset into address space offset */
529 xlat += section.offset_within_address_space -
530 section.offset_within_region;
532 if (plen == (hwaddr)-1) {
534 * We use default page size here. Logically it only happens
535 * for identity mappings.
537 plen = TARGET_PAGE_SIZE;
540 /* Convert to address mask */
541 plen -= 1;
543 return (IOMMUTLBEntry) {
544 .target_as = section.address_space,
545 .iova = addr & ~plen,
546 .translated_addr = xlat & ~plen,
547 .addr_mask = plen,
548 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
549 .perm = IOMMU_RW,
552 iotlb_fail:
553 return (IOMMUTLBEntry) {0};
556 /* Called from RCU critical section */
557 MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
558 hwaddr *xlat, hwaddr *plen,
559 bool is_write)
561 MemoryRegion *mr;
562 MemoryRegionSection section;
564 /* This can be MMIO, so setup MMIO bit. */
565 section = address_space_do_translate(as, addr, xlat, plen, is_write, true);
566 mr = section.mr;
568 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
569 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
570 *plen = MIN(page, *plen);
573 return mr;
576 /* Called from RCU critical section */
577 MemoryRegionSection *
578 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
579 hwaddr *xlat, hwaddr *plen)
581 MemoryRegionSection *section;
582 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
584 section = address_space_translate_internal(d, addr, xlat, plen, false);
586 assert(!section->mr->iommu_ops);
587 return section;
589 #endif
591 #if !defined(CONFIG_USER_ONLY)
593 static int cpu_common_post_load(void *opaque, int version_id)
595 CPUState *cpu = opaque;
597 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
598 version_id is increased. */
599 cpu->interrupt_request &= ~0x01;
600 tlb_flush(cpu);
602 return 0;
605 static int cpu_common_pre_load(void *opaque)
607 CPUState *cpu = opaque;
609 cpu->exception_index = -1;
611 return 0;
614 static bool cpu_common_exception_index_needed(void *opaque)
616 CPUState *cpu = opaque;
618 return tcg_enabled() && cpu->exception_index != -1;
621 static const VMStateDescription vmstate_cpu_common_exception_index = {
622 .name = "cpu_common/exception_index",
623 .version_id = 1,
624 .minimum_version_id = 1,
625 .needed = cpu_common_exception_index_needed,
626 .fields = (VMStateField[]) {
627 VMSTATE_INT32(exception_index, CPUState),
628 VMSTATE_END_OF_LIST()
632 static bool cpu_common_crash_occurred_needed(void *opaque)
634 CPUState *cpu = opaque;
636 return cpu->crash_occurred;
639 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
640 .name = "cpu_common/crash_occurred",
641 .version_id = 1,
642 .minimum_version_id = 1,
643 .needed = cpu_common_crash_occurred_needed,
644 .fields = (VMStateField[]) {
645 VMSTATE_BOOL(crash_occurred, CPUState),
646 VMSTATE_END_OF_LIST()
650 const VMStateDescription vmstate_cpu_common = {
651 .name = "cpu_common",
652 .version_id = 1,
653 .minimum_version_id = 1,
654 .pre_load = cpu_common_pre_load,
655 .post_load = cpu_common_post_load,
656 .fields = (VMStateField[]) {
657 VMSTATE_UINT32(halted, CPUState),
658 VMSTATE_UINT32(interrupt_request, CPUState),
659 VMSTATE_END_OF_LIST()
661 .subsections = (const VMStateDescription*[]) {
662 &vmstate_cpu_common_exception_index,
663 &vmstate_cpu_common_crash_occurred,
664 NULL
668 #endif
670 CPUState *qemu_get_cpu(int index)
672 CPUState *cpu;
674 CPU_FOREACH(cpu) {
675 if (cpu->cpu_index == index) {
676 return cpu;
680 return NULL;
683 #if !defined(CONFIG_USER_ONLY)
684 void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx)
686 CPUAddressSpace *newas;
688 /* Target code should have set num_ases before calling us */
689 assert(asidx < cpu->num_ases);
691 if (asidx == 0) {
692 /* address space 0 gets the convenience alias */
693 cpu->as = as;
696 /* KVM cannot currently support multiple address spaces. */
697 assert(asidx == 0 || !kvm_enabled());
699 if (!cpu->cpu_ases) {
700 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
703 newas = &cpu->cpu_ases[asidx];
704 newas->cpu = cpu;
705 newas->as = as;
706 if (tcg_enabled()) {
707 newas->tcg_as_listener.commit = tcg_commit;
708 memory_listener_register(&newas->tcg_as_listener, as);
712 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
714 /* Return the AddressSpace corresponding to the specified index */
715 return cpu->cpu_ases[asidx].as;
717 #endif
719 void cpu_exec_unrealizefn(CPUState *cpu)
721 CPUClass *cc = CPU_GET_CLASS(cpu);
723 cpu_list_remove(cpu);
725 if (cc->vmsd != NULL) {
726 vmstate_unregister(NULL, cc->vmsd, cpu);
728 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
729 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
733 void cpu_exec_initfn(CPUState *cpu)
735 cpu->as = NULL;
736 cpu->num_ases = 0;
738 #ifndef CONFIG_USER_ONLY
739 cpu->thread_id = qemu_get_thread_id();
741 /* This is a softmmu CPU object, so create a property for it
742 * so users can wire up its memory. (This can't go in qom/cpu.c
743 * because that file is compiled only once for both user-mode
744 * and system builds.) The default if no link is set up is to use
745 * the system address space.
747 object_property_add_link(OBJECT(cpu), "memory", TYPE_MEMORY_REGION,
748 (Object **)&cpu->memory,
749 qdev_prop_allow_set_link_before_realize,
750 OBJ_PROP_LINK_UNREF_ON_RELEASE,
751 &error_abort);
752 cpu->memory = system_memory;
753 object_ref(OBJECT(cpu->memory));
754 #endif
757 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
759 CPUClass *cc ATTRIBUTE_UNUSED = CPU_GET_CLASS(cpu);
761 cpu_list_add(cpu);
763 #ifndef CONFIG_USER_ONLY
764 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
765 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
767 if (cc->vmsd != NULL) {
768 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
770 #endif
773 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
775 /* Flush the whole TB as this will not have race conditions
776 * even if we don't have proper locking yet.
777 * Ideally we would just invalidate the TBs for the
778 * specified PC.
780 tb_flush(cpu);
783 #if defined(CONFIG_USER_ONLY)
784 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
789 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
790 int flags)
792 return -ENOSYS;
795 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
799 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
800 int flags, CPUWatchpoint **watchpoint)
802 return -ENOSYS;
804 #else
805 /* Add a watchpoint. */
806 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
807 int flags, CPUWatchpoint **watchpoint)
809 CPUWatchpoint *wp;
811 /* forbid ranges which are empty or run off the end of the address space */
812 if (len == 0 || (addr + len - 1) < addr) {
813 error_report("tried to set invalid watchpoint at %"
814 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
815 return -EINVAL;
817 wp = g_malloc(sizeof(*wp));
819 wp->vaddr = addr;
820 wp->len = len;
821 wp->flags = flags;
823 /* keep all GDB-injected watchpoints in front */
824 if (flags & BP_GDB) {
825 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
826 } else {
827 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
830 tlb_flush_page(cpu, addr);
832 if (watchpoint)
833 *watchpoint = wp;
834 return 0;
837 /* Remove a specific watchpoint. */
838 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
839 int flags)
841 CPUWatchpoint *wp;
843 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
844 if (addr == wp->vaddr && len == wp->len
845 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
846 cpu_watchpoint_remove_by_ref(cpu, wp);
847 return 0;
850 return -ENOENT;
853 /* Remove a specific watchpoint by reference. */
854 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
856 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
858 tlb_flush_page(cpu, watchpoint->vaddr);
860 g_free(watchpoint);
863 /* Remove all matching watchpoints. */
864 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
866 CPUWatchpoint *wp, *next;
868 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
869 if (wp->flags & mask) {
870 cpu_watchpoint_remove_by_ref(cpu, wp);
875 /* Return true if this watchpoint address matches the specified
876 * access (ie the address range covered by the watchpoint overlaps
877 * partially or completely with the address range covered by the
878 * access).
880 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
881 vaddr addr,
882 vaddr len)
884 /* We know the lengths are non-zero, but a little caution is
885 * required to avoid errors in the case where the range ends
886 * exactly at the top of the address space and so addr + len
887 * wraps round to zero.
889 vaddr wpend = wp->vaddr + wp->len - 1;
890 vaddr addrend = addr + len - 1;
892 return !(addr > wpend || wp->vaddr > addrend);
895 #endif
897 /* Add a breakpoint. */
898 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
899 CPUBreakpoint **breakpoint)
901 CPUBreakpoint *bp;
903 bp = g_malloc(sizeof(*bp));
905 bp->pc = pc;
906 bp->flags = flags;
908 /* keep all GDB-injected breakpoints in front */
909 if (flags & BP_GDB) {
910 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
911 } else {
912 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
915 breakpoint_invalidate(cpu, pc);
917 if (breakpoint) {
918 *breakpoint = bp;
920 return 0;
923 /* Remove a specific breakpoint. */
924 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
926 CPUBreakpoint *bp;
928 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
929 if (bp->pc == pc && bp->flags == flags) {
930 cpu_breakpoint_remove_by_ref(cpu, bp);
931 return 0;
934 return -ENOENT;
937 /* Remove a specific breakpoint by reference. */
938 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
940 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
942 breakpoint_invalidate(cpu, breakpoint->pc);
944 g_free(breakpoint);
947 /* Remove all matching breakpoints. */
948 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
950 CPUBreakpoint *bp, *next;
952 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
953 if (bp->flags & mask) {
954 cpu_breakpoint_remove_by_ref(cpu, bp);
959 /* enable or disable single step mode. EXCP_DEBUG is returned by the
960 CPU loop after each instruction */
961 void cpu_single_step(CPUState *cpu, int enabled)
963 if (cpu->singlestep_enabled != enabled) {
964 cpu->singlestep_enabled = enabled;
965 if (kvm_enabled()) {
966 kvm_update_guest_debug(cpu, 0);
967 } else {
968 /* must flush all the translated code to avoid inconsistencies */
969 /* XXX: only flush what is necessary */
970 tb_flush(cpu);
975 void cpu_abort(CPUState *cpu, const char *fmt, ...)
977 va_list ap;
978 va_list ap2;
980 va_start(ap, fmt);
981 va_copy(ap2, ap);
982 fprintf(stderr, "qemu: fatal: ");
983 vfprintf(stderr, fmt, ap);
984 fprintf(stderr, "\n");
985 cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
986 if (qemu_log_separate()) {
987 qemu_log_lock();
988 qemu_log("qemu: fatal: ");
989 qemu_log_vprintf(fmt, ap2);
990 qemu_log("\n");
991 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
992 qemu_log_flush();
993 qemu_log_unlock();
994 qemu_log_close();
996 va_end(ap2);
997 va_end(ap);
998 replay_finish();
999 #if defined(CONFIG_USER_ONLY)
1001 struct sigaction act;
1002 sigfillset(&act.sa_mask);
1003 act.sa_handler = SIG_DFL;
1004 sigaction(SIGABRT, &act, NULL);
1006 #endif
1007 abort();
1010 #if !defined(CONFIG_USER_ONLY)
1011 /* Called from RCU critical section */
1012 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1014 RAMBlock *block;
1016 block = atomic_rcu_read(&ram_list.mru_block);
1017 if (block && addr - block->offset < block->max_length) {
1018 return block;
1020 RAMBLOCK_FOREACH(block) {
1021 if (addr - block->offset < block->max_length) {
1022 goto found;
1026 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1027 abort();
1029 found:
1030 /* It is safe to write mru_block outside the iothread lock. This
1031 * is what happens:
1033 * mru_block = xxx
1034 * rcu_read_unlock()
1035 * xxx removed from list
1036 * rcu_read_lock()
1037 * read mru_block
1038 * mru_block = NULL;
1039 * call_rcu(reclaim_ramblock, xxx);
1040 * rcu_read_unlock()
1042 * atomic_rcu_set is not needed here. The block was already published
1043 * when it was placed into the list. Here we're just making an extra
1044 * copy of the pointer.
1046 ram_list.mru_block = block;
1047 return block;
1050 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1052 CPUState *cpu;
1053 ram_addr_t start1;
1054 RAMBlock *block;
1055 ram_addr_t end;
1057 end = TARGET_PAGE_ALIGN(start + length);
1058 start &= TARGET_PAGE_MASK;
1060 rcu_read_lock();
1061 block = qemu_get_ram_block(start);
1062 assert(block == qemu_get_ram_block(end - 1));
1063 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1064 CPU_FOREACH(cpu) {
1065 tlb_reset_dirty(cpu, start1, length);
1067 rcu_read_unlock();
1070 /* Note: start and end must be within the same ram block. */
1071 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1072 ram_addr_t length,
1073 unsigned client)
1075 DirtyMemoryBlocks *blocks;
1076 unsigned long end, page;
1077 bool dirty = false;
1079 if (length == 0) {
1080 return false;
1083 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1084 page = start >> TARGET_PAGE_BITS;
1086 rcu_read_lock();
1088 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1090 while (page < end) {
1091 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1092 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1093 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1095 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1096 offset, num);
1097 page += num;
1100 rcu_read_unlock();
1102 if (dirty && tcg_enabled()) {
1103 tlb_reset_dirty_range_all(start, length);
1106 return dirty;
1109 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1110 (ram_addr_t start, ram_addr_t length, unsigned client)
1112 DirtyMemoryBlocks *blocks;
1113 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1114 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1115 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1116 DirtyBitmapSnapshot *snap;
1117 unsigned long page, end, dest;
1119 snap = g_malloc0(sizeof(*snap) +
1120 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1121 snap->start = first;
1122 snap->end = last;
1124 page = first >> TARGET_PAGE_BITS;
1125 end = last >> TARGET_PAGE_BITS;
1126 dest = 0;
1128 rcu_read_lock();
1130 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1132 while (page < end) {
1133 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1134 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1135 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1137 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1138 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1139 offset >>= BITS_PER_LEVEL;
1141 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1142 blocks->blocks[idx] + offset,
1143 num);
1144 page += num;
1145 dest += num >> BITS_PER_LEVEL;
1148 rcu_read_unlock();
1150 if (tcg_enabled()) {
1151 tlb_reset_dirty_range_all(start, length);
1154 return snap;
1157 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1158 ram_addr_t start,
1159 ram_addr_t length)
1161 unsigned long page, end;
1163 assert(start >= snap->start);
1164 assert(start + length <= snap->end);
1166 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1167 page = (start - snap->start) >> TARGET_PAGE_BITS;
1169 while (page < end) {
1170 if (test_bit(page, snap->dirty)) {
1171 return true;
1173 page++;
1175 return false;
1178 /* Called from RCU critical section */
1179 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1180 MemoryRegionSection *section,
1181 target_ulong vaddr,
1182 hwaddr paddr, hwaddr xlat,
1183 int prot,
1184 target_ulong *address)
1186 hwaddr iotlb;
1187 CPUWatchpoint *wp;
1189 if (memory_region_is_ram(section->mr)) {
1190 /* Normal RAM. */
1191 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1192 if (!section->readonly) {
1193 iotlb |= PHYS_SECTION_NOTDIRTY;
1194 } else {
1195 iotlb |= PHYS_SECTION_ROM;
1197 } else {
1198 AddressSpaceDispatch *d;
1200 d = atomic_rcu_read(&section->address_space->dispatch);
1201 iotlb = section - d->map.sections;
1202 iotlb += xlat;
1205 /* Make accesses to pages with watchpoints go via the
1206 watchpoint trap routines. */
1207 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1208 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1209 /* Avoid trapping reads of pages with a write breakpoint. */
1210 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1211 iotlb = PHYS_SECTION_WATCH + paddr;
1212 *address |= TLB_MMIO;
1213 break;
1218 return iotlb;
1220 #endif /* defined(CONFIG_USER_ONLY) */
1222 #if !defined(CONFIG_USER_ONLY)
1224 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1225 uint16_t section);
1226 static subpage_t *subpage_init(AddressSpace *as, hwaddr base);
1228 static void *(*phys_mem_alloc)(size_t size, uint64_t *align) =
1229 qemu_anon_ram_alloc;
1232 * Set a custom physical guest memory alloator.
1233 * Accelerators with unusual needs may need this. Hopefully, we can
1234 * get rid of it eventually.
1236 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align))
1238 phys_mem_alloc = alloc;
1241 static uint16_t phys_section_add(PhysPageMap *map,
1242 MemoryRegionSection *section)
1244 /* The physical section number is ORed with a page-aligned
1245 * pointer to produce the iotlb entries. Thus it should
1246 * never overflow into the page-aligned value.
1248 assert(map->sections_nb < TARGET_PAGE_SIZE);
1250 if (map->sections_nb == map->sections_nb_alloc) {
1251 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1252 map->sections = g_renew(MemoryRegionSection, map->sections,
1253 map->sections_nb_alloc);
1255 map->sections[map->sections_nb] = *section;
1256 memory_region_ref(section->mr);
1257 return map->sections_nb++;
1260 static void phys_section_destroy(MemoryRegion *mr)
1262 bool have_sub_page = mr->subpage;
1264 memory_region_unref(mr);
1266 if (have_sub_page) {
1267 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1268 object_unref(OBJECT(&subpage->iomem));
1269 g_free(subpage);
1273 static void phys_sections_free(PhysPageMap *map)
1275 while (map->sections_nb > 0) {
1276 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1277 phys_section_destroy(section->mr);
1279 g_free(map->sections);
1280 g_free(map->nodes);
1283 static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
1285 subpage_t *subpage;
1286 hwaddr base = section->offset_within_address_space
1287 & TARGET_PAGE_MASK;
1288 MemoryRegionSection *existing = phys_page_find(d, base);
1289 MemoryRegionSection subsection = {
1290 .offset_within_address_space = base,
1291 .size = int128_make64(TARGET_PAGE_SIZE),
1293 hwaddr start, end;
1295 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1297 if (!(existing->mr->subpage)) {
1298 subpage = subpage_init(d->as, base);
1299 subsection.address_space = d->as;
1300 subsection.mr = &subpage->iomem;
1301 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1302 phys_section_add(&d->map, &subsection));
1303 } else {
1304 subpage = container_of(existing->mr, subpage_t, iomem);
1306 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1307 end = start + int128_get64(section->size) - 1;
1308 subpage_register(subpage, start, end,
1309 phys_section_add(&d->map, section));
1313 static void register_multipage(AddressSpaceDispatch *d,
1314 MemoryRegionSection *section)
1316 hwaddr start_addr = section->offset_within_address_space;
1317 uint16_t section_index = phys_section_add(&d->map, section);
1318 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1319 TARGET_PAGE_BITS));
1321 assert(num_pages);
1322 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1325 static void mem_add(MemoryListener *listener, MemoryRegionSection *section)
1327 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
1328 AddressSpaceDispatch *d = as->next_dispatch;
1329 MemoryRegionSection now = *section, remain = *section;
1330 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1332 if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
1333 uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
1334 - now.offset_within_address_space;
1336 now.size = int128_min(int128_make64(left), now.size);
1337 register_subpage(d, &now);
1338 } else {
1339 now.size = int128_zero();
1341 while (int128_ne(remain.size, now.size)) {
1342 remain.size = int128_sub(remain.size, now.size);
1343 remain.offset_within_address_space += int128_get64(now.size);
1344 remain.offset_within_region += int128_get64(now.size);
1345 now = remain;
1346 if (int128_lt(remain.size, page_size)) {
1347 register_subpage(d, &now);
1348 } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1349 now.size = page_size;
1350 register_subpage(d, &now);
1351 } else {
1352 now.size = int128_and(now.size, int128_neg(page_size));
1353 register_multipage(d, &now);
1358 void qemu_flush_coalesced_mmio_buffer(void)
1360 if (kvm_enabled())
1361 kvm_flush_coalesced_mmio_buffer();
1364 void qemu_mutex_lock_ramlist(void)
1366 qemu_mutex_lock(&ram_list.mutex);
1369 void qemu_mutex_unlock_ramlist(void)
1371 qemu_mutex_unlock(&ram_list.mutex);
1374 void ram_block_dump(Monitor *mon)
1376 RAMBlock *block;
1377 char *psize;
1379 rcu_read_lock();
1380 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1381 "Block Name", "PSize", "Offset", "Used", "Total");
1382 RAMBLOCK_FOREACH(block) {
1383 psize = size_to_str(block->page_size);
1384 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1385 " 0x%016" PRIx64 "\n", block->idstr, psize,
1386 (uint64_t)block->offset,
1387 (uint64_t)block->used_length,
1388 (uint64_t)block->max_length);
1389 g_free(psize);
1391 rcu_read_unlock();
1394 #ifdef __linux__
1396 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1397 * may or may not name the same files / on the same filesystem now as
1398 * when we actually open and map them. Iterate over the file
1399 * descriptors instead, and use qemu_fd_getpagesize().
1401 static int find_max_supported_pagesize(Object *obj, void *opaque)
1403 char *mem_path;
1404 long *hpsize_min = opaque;
1406 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1407 mem_path = object_property_get_str(obj, "mem-path", NULL);
1408 if (mem_path) {
1409 long hpsize = qemu_mempath_getpagesize(mem_path);
1410 if (hpsize < *hpsize_min) {
1411 *hpsize_min = hpsize;
1413 } else {
1414 *hpsize_min = getpagesize();
1418 return 0;
1421 long qemu_getrampagesize(void)
1423 long hpsize = LONG_MAX;
1424 long mainrampagesize;
1425 Object *memdev_root;
1427 if (mem_path) {
1428 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1429 } else {
1430 mainrampagesize = getpagesize();
1433 /* it's possible we have memory-backend objects with
1434 * hugepage-backed RAM. these may get mapped into system
1435 * address space via -numa parameters or memory hotplug
1436 * hooks. we want to take these into account, but we
1437 * also want to make sure these supported hugepage
1438 * sizes are applicable across the entire range of memory
1439 * we may boot from, so we take the min across all
1440 * backends, and assume normal pages in cases where a
1441 * backend isn't backed by hugepages.
1443 memdev_root = object_resolve_path("/objects", NULL);
1444 if (memdev_root) {
1445 object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize);
1447 if (hpsize == LONG_MAX) {
1448 /* No additional memory regions found ==> Report main RAM page size */
1449 return mainrampagesize;
1452 /* If NUMA is disabled or the NUMA nodes are not backed with a
1453 * memory-backend, then there is at least one node using "normal" RAM,
1454 * so if its page size is smaller we have got to report that size instead.
1456 if (hpsize > mainrampagesize &&
1457 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1458 static bool warned;
1459 if (!warned) {
1460 error_report("Huge page support disabled (n/a for main memory).");
1461 warned = true;
1463 return mainrampagesize;
1466 return hpsize;
1468 #else
1469 long qemu_getrampagesize(void)
1471 return getpagesize();
1473 #endif
1475 #ifdef __linux__
1476 static int64_t get_file_size(int fd)
1478 int64_t size = lseek(fd, 0, SEEK_END);
1479 if (size < 0) {
1480 return -errno;
1482 return size;
1485 static void *file_ram_alloc(RAMBlock *block,
1486 ram_addr_t memory,
1487 const char *path,
1488 Error **errp)
1490 bool unlink_on_error = false;
1491 char *filename;
1492 char *sanitized_name;
1493 char *c;
1494 void *area = MAP_FAILED;
1495 int fd = -1;
1496 int64_t file_size;
1498 if (kvm_enabled() && !kvm_has_sync_mmu()) {
1499 error_setg(errp,
1500 "host lacks kvm mmu notifiers, -mem-path unsupported");
1501 return NULL;
1504 for (;;) {
1505 fd = open(path, O_RDWR);
1506 if (fd >= 0) {
1507 /* @path names an existing file, use it */
1508 break;
1510 if (errno == ENOENT) {
1511 /* @path names a file that doesn't exist, create it */
1512 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1513 if (fd >= 0) {
1514 unlink_on_error = true;
1515 break;
1517 } else if (errno == EISDIR) {
1518 /* @path names a directory, create a file there */
1519 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1520 sanitized_name = g_strdup(memory_region_name(block->mr));
1521 for (c = sanitized_name; *c != '\0'; c++) {
1522 if (*c == '/') {
1523 *c = '_';
1527 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1528 sanitized_name);
1529 g_free(sanitized_name);
1531 fd = mkstemp(filename);
1532 if (fd >= 0) {
1533 unlink(filename);
1534 g_free(filename);
1535 break;
1537 g_free(filename);
1539 if (errno != EEXIST && errno != EINTR) {
1540 error_setg_errno(errp, errno,
1541 "can't open backing store %s for guest RAM",
1542 path);
1543 goto error;
1546 * Try again on EINTR and EEXIST. The latter happens when
1547 * something else creates the file between our two open().
1551 block->page_size = qemu_fd_getpagesize(fd);
1552 block->mr->align = block->page_size;
1553 #if defined(__s390x__)
1554 if (kvm_enabled()) {
1555 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1557 #endif
1559 file_size = get_file_size(fd);
1561 if (memory < block->page_size) {
1562 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1563 "or larger than page size 0x%zx",
1564 memory, block->page_size);
1565 goto error;
1568 if (file_size > 0 && file_size < memory) {
1569 error_setg(errp, "backing store %s size 0x%" PRIx64
1570 " does not match 'size' option 0x" RAM_ADDR_FMT,
1571 path, file_size, memory);
1572 goto error;
1575 memory = ROUND_UP(memory, block->page_size);
1578 * ftruncate is not supported by hugetlbfs in older
1579 * hosts, so don't bother bailing out on errors.
1580 * If anything goes wrong with it under other filesystems,
1581 * mmap will fail.
1583 * Do not truncate the non-empty backend file to avoid corrupting
1584 * the existing data in the file. Disabling shrinking is not
1585 * enough. For example, the current vNVDIMM implementation stores
1586 * the guest NVDIMM labels at the end of the backend file. If the
1587 * backend file is later extended, QEMU will not be able to find
1588 * those labels. Therefore, extending the non-empty backend file
1589 * is disabled as well.
1591 if (!file_size && ftruncate(fd, memory)) {
1592 perror("ftruncate");
1595 area = qemu_ram_mmap(fd, memory, block->mr->align,
1596 block->flags & RAM_SHARED);
1597 if (area == MAP_FAILED) {
1598 error_setg_errno(errp, errno,
1599 "unable to map backing store for guest RAM");
1600 goto error;
1603 if (mem_prealloc) {
1604 os_mem_prealloc(fd, area, memory, smp_cpus, errp);
1605 if (errp && *errp) {
1606 goto error;
1610 block->fd = fd;
1611 return area;
1613 error:
1614 if (area != MAP_FAILED) {
1615 qemu_ram_munmap(area, memory);
1617 if (unlink_on_error) {
1618 unlink(path);
1620 if (fd != -1) {
1621 close(fd);
1623 return NULL;
1625 #endif
1627 /* Called with the ramlist lock held. */
1628 static ram_addr_t find_ram_offset(ram_addr_t size)
1630 RAMBlock *block, *next_block;
1631 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1633 assert(size != 0); /* it would hand out same offset multiple times */
1635 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1636 return 0;
1639 RAMBLOCK_FOREACH(block) {
1640 ram_addr_t end, next = RAM_ADDR_MAX;
1642 end = block->offset + block->max_length;
1644 RAMBLOCK_FOREACH(next_block) {
1645 if (next_block->offset >= end) {
1646 next = MIN(next, next_block->offset);
1649 if (next - end >= size && next - end < mingap) {
1650 offset = end;
1651 mingap = next - end;
1655 if (offset == RAM_ADDR_MAX) {
1656 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1657 (uint64_t)size);
1658 abort();
1661 return offset;
1664 unsigned long last_ram_page(void)
1666 RAMBlock *block;
1667 ram_addr_t last = 0;
1669 rcu_read_lock();
1670 RAMBLOCK_FOREACH(block) {
1671 last = MAX(last, block->offset + block->max_length);
1673 rcu_read_unlock();
1674 return last >> TARGET_PAGE_BITS;
1677 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1679 int ret;
1681 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1682 if (!machine_dump_guest_core(current_machine)) {
1683 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1684 if (ret) {
1685 perror("qemu_madvise");
1686 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1687 "but dump_guest_core=off specified\n");
1692 const char *qemu_ram_get_idstr(RAMBlock *rb)
1694 return rb->idstr;
1697 bool qemu_ram_is_shared(RAMBlock *rb)
1699 return rb->flags & RAM_SHARED;
1702 /* Called with iothread lock held. */
1703 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
1705 RAMBlock *block;
1707 assert(new_block);
1708 assert(!new_block->idstr[0]);
1710 if (dev) {
1711 char *id = qdev_get_dev_path(dev);
1712 if (id) {
1713 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1714 g_free(id);
1717 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1719 rcu_read_lock();
1720 RAMBLOCK_FOREACH(block) {
1721 if (block != new_block &&
1722 !strcmp(block->idstr, new_block->idstr)) {
1723 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1724 new_block->idstr);
1725 abort();
1728 rcu_read_unlock();
1731 /* Called with iothread lock held. */
1732 void qemu_ram_unset_idstr(RAMBlock *block)
1734 /* FIXME: arch_init.c assumes that this is not called throughout
1735 * migration. Ignore the problem since hot-unplug during migration
1736 * does not work anyway.
1738 if (block) {
1739 memset(block->idstr, 0, sizeof(block->idstr));
1743 size_t qemu_ram_pagesize(RAMBlock *rb)
1745 return rb->page_size;
1748 /* Returns the largest size of page in use */
1749 size_t qemu_ram_pagesize_largest(void)
1751 RAMBlock *block;
1752 size_t largest = 0;
1754 RAMBLOCK_FOREACH(block) {
1755 largest = MAX(largest, qemu_ram_pagesize(block));
1758 return largest;
1761 static int memory_try_enable_merging(void *addr, size_t len)
1763 if (!machine_mem_merge(current_machine)) {
1764 /* disabled by the user */
1765 return 0;
1768 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1771 /* Only legal before guest might have detected the memory size: e.g. on
1772 * incoming migration, or right after reset.
1774 * As memory core doesn't know how is memory accessed, it is up to
1775 * resize callback to update device state and/or add assertions to detect
1776 * misuse, if necessary.
1778 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
1780 assert(block);
1782 newsize = HOST_PAGE_ALIGN(newsize);
1784 if (block->used_length == newsize) {
1785 return 0;
1788 if (!(block->flags & RAM_RESIZEABLE)) {
1789 error_setg_errno(errp, EINVAL,
1790 "Length mismatch: %s: 0x" RAM_ADDR_FMT
1791 " in != 0x" RAM_ADDR_FMT, block->idstr,
1792 newsize, block->used_length);
1793 return -EINVAL;
1796 if (block->max_length < newsize) {
1797 error_setg_errno(errp, EINVAL,
1798 "Length too large: %s: 0x" RAM_ADDR_FMT
1799 " > 0x" RAM_ADDR_FMT, block->idstr,
1800 newsize, block->max_length);
1801 return -EINVAL;
1804 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
1805 block->used_length = newsize;
1806 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
1807 DIRTY_CLIENTS_ALL);
1808 memory_region_set_size(block->mr, newsize);
1809 if (block->resized) {
1810 block->resized(block->idstr, newsize, block->host);
1812 return 0;
1815 /* Called with ram_list.mutex held */
1816 static void dirty_memory_extend(ram_addr_t old_ram_size,
1817 ram_addr_t new_ram_size)
1819 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
1820 DIRTY_MEMORY_BLOCK_SIZE);
1821 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
1822 DIRTY_MEMORY_BLOCK_SIZE);
1823 int i;
1825 /* Only need to extend if block count increased */
1826 if (new_num_blocks <= old_num_blocks) {
1827 return;
1830 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
1831 DirtyMemoryBlocks *old_blocks;
1832 DirtyMemoryBlocks *new_blocks;
1833 int j;
1835 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
1836 new_blocks = g_malloc(sizeof(*new_blocks) +
1837 sizeof(new_blocks->blocks[0]) * new_num_blocks);
1839 if (old_num_blocks) {
1840 memcpy(new_blocks->blocks, old_blocks->blocks,
1841 old_num_blocks * sizeof(old_blocks->blocks[0]));
1844 for (j = old_num_blocks; j < new_num_blocks; j++) {
1845 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
1848 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
1850 if (old_blocks) {
1851 g_free_rcu(old_blocks, rcu);
1856 static void ram_block_add(RAMBlock *new_block, Error **errp)
1858 RAMBlock *block;
1859 RAMBlock *last_block = NULL;
1860 ram_addr_t old_ram_size, new_ram_size;
1861 Error *err = NULL;
1863 old_ram_size = last_ram_page();
1865 qemu_mutex_lock_ramlist();
1866 new_block->offset = find_ram_offset(new_block->max_length);
1868 if (!new_block->host) {
1869 if (xen_enabled()) {
1870 xen_ram_alloc(new_block->offset, new_block->max_length,
1871 new_block->mr, &err);
1872 if (err) {
1873 error_propagate(errp, err);
1874 qemu_mutex_unlock_ramlist();
1875 return;
1877 } else {
1878 new_block->host = phys_mem_alloc(new_block->max_length,
1879 &new_block->mr->align);
1880 if (!new_block->host) {
1881 error_setg_errno(errp, errno,
1882 "cannot set up guest memory '%s'",
1883 memory_region_name(new_block->mr));
1884 qemu_mutex_unlock_ramlist();
1885 return;
1887 memory_try_enable_merging(new_block->host, new_block->max_length);
1891 new_ram_size = MAX(old_ram_size,
1892 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
1893 if (new_ram_size > old_ram_size) {
1894 dirty_memory_extend(old_ram_size, new_ram_size);
1896 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
1897 * QLIST (which has an RCU-friendly variant) does not have insertion at
1898 * tail, so save the last element in last_block.
1900 RAMBLOCK_FOREACH(block) {
1901 last_block = block;
1902 if (block->max_length < new_block->max_length) {
1903 break;
1906 if (block) {
1907 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
1908 } else if (last_block) {
1909 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
1910 } else { /* list is empty */
1911 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
1913 ram_list.mru_block = NULL;
1915 /* Write list before version */
1916 smp_wmb();
1917 ram_list.version++;
1918 qemu_mutex_unlock_ramlist();
1920 cpu_physical_memory_set_dirty_range(new_block->offset,
1921 new_block->used_length,
1922 DIRTY_CLIENTS_ALL);
1924 if (new_block->host) {
1925 qemu_ram_setup_dump(new_block->host, new_block->max_length);
1926 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
1927 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
1928 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
1929 ram_block_notify_add(new_block->host, new_block->max_length);
1933 #ifdef __linux__
1934 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
1935 bool share, const char *mem_path,
1936 Error **errp)
1938 RAMBlock *new_block;
1939 Error *local_err = NULL;
1941 if (xen_enabled()) {
1942 error_setg(errp, "-mem-path not supported with Xen");
1943 return NULL;
1946 if (phys_mem_alloc != qemu_anon_ram_alloc) {
1948 * file_ram_alloc() needs to allocate just like
1949 * phys_mem_alloc, but we haven't bothered to provide
1950 * a hook there.
1952 error_setg(errp,
1953 "-mem-path not supported with this accelerator");
1954 return NULL;
1957 size = HOST_PAGE_ALIGN(size);
1958 new_block = g_malloc0(sizeof(*new_block));
1959 new_block->mr = mr;
1960 new_block->used_length = size;
1961 new_block->max_length = size;
1962 new_block->flags = share ? RAM_SHARED : 0;
1963 new_block->host = file_ram_alloc(new_block, size,
1964 mem_path, errp);
1965 if (!new_block->host) {
1966 g_free(new_block);
1967 return NULL;
1970 ram_block_add(new_block, &local_err);
1971 if (local_err) {
1972 g_free(new_block);
1973 error_propagate(errp, local_err);
1974 return NULL;
1976 return new_block;
1978 #endif
1980 static
1981 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
1982 void (*resized)(const char*,
1983 uint64_t length,
1984 void *host),
1985 void *host, bool resizeable,
1986 MemoryRegion *mr, Error **errp)
1988 RAMBlock *new_block;
1989 Error *local_err = NULL;
1991 size = HOST_PAGE_ALIGN(size);
1992 max_size = HOST_PAGE_ALIGN(max_size);
1993 new_block = g_malloc0(sizeof(*new_block));
1994 new_block->mr = mr;
1995 new_block->resized = resized;
1996 new_block->used_length = size;
1997 new_block->max_length = max_size;
1998 assert(max_size >= size);
1999 new_block->fd = -1;
2000 new_block->page_size = getpagesize();
2001 new_block->host = host;
2002 if (host) {
2003 new_block->flags |= RAM_PREALLOC;
2005 if (resizeable) {
2006 new_block->flags |= RAM_RESIZEABLE;
2008 ram_block_add(new_block, &local_err);
2009 if (local_err) {
2010 g_free(new_block);
2011 error_propagate(errp, local_err);
2012 return NULL;
2014 return new_block;
2017 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2018 MemoryRegion *mr, Error **errp)
2020 return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp);
2023 RAMBlock *qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp)
2025 return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp);
2028 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2029 void (*resized)(const char*,
2030 uint64_t length,
2031 void *host),
2032 MemoryRegion *mr, Error **errp)
2034 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp);
2037 static void reclaim_ramblock(RAMBlock *block)
2039 if (block->flags & RAM_PREALLOC) {
2041 } else if (xen_enabled()) {
2042 xen_invalidate_map_cache_entry(block->host);
2043 #ifndef _WIN32
2044 } else if (block->fd >= 0) {
2045 qemu_ram_munmap(block->host, block->max_length);
2046 close(block->fd);
2047 #endif
2048 } else {
2049 qemu_anon_ram_free(block->host, block->max_length);
2051 g_free(block);
2054 void qemu_ram_free(RAMBlock *block)
2056 if (!block) {
2057 return;
2060 if (block->host) {
2061 ram_block_notify_remove(block->host, block->max_length);
2064 qemu_mutex_lock_ramlist();
2065 QLIST_REMOVE_RCU(block, next);
2066 ram_list.mru_block = NULL;
2067 /* Write list before version */
2068 smp_wmb();
2069 ram_list.version++;
2070 call_rcu(block, reclaim_ramblock, rcu);
2071 qemu_mutex_unlock_ramlist();
2074 #ifndef _WIN32
2075 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2077 RAMBlock *block;
2078 ram_addr_t offset;
2079 int flags;
2080 void *area, *vaddr;
2082 RAMBLOCK_FOREACH(block) {
2083 offset = addr - block->offset;
2084 if (offset < block->max_length) {
2085 vaddr = ramblock_ptr(block, offset);
2086 if (block->flags & RAM_PREALLOC) {
2088 } else if (xen_enabled()) {
2089 abort();
2090 } else {
2091 flags = MAP_FIXED;
2092 if (block->fd >= 0) {
2093 flags |= (block->flags & RAM_SHARED ?
2094 MAP_SHARED : MAP_PRIVATE);
2095 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2096 flags, block->fd, offset);
2097 } else {
2099 * Remap needs to match alloc. Accelerators that
2100 * set phys_mem_alloc never remap. If they did,
2101 * we'd need a remap hook here.
2103 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2105 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2106 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2107 flags, -1, 0);
2109 if (area != vaddr) {
2110 fprintf(stderr, "Could not remap addr: "
2111 RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n",
2112 length, addr);
2113 exit(1);
2115 memory_try_enable_merging(vaddr, length);
2116 qemu_ram_setup_dump(vaddr, length);
2121 #endif /* !_WIN32 */
2123 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2124 * This should not be used for general purpose DMA. Use address_space_map
2125 * or address_space_rw instead. For local memory (e.g. video ram) that the
2126 * device owns, use memory_region_get_ram_ptr.
2128 * Called within RCU critical section.
2130 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2132 RAMBlock *block = ram_block;
2134 if (block == NULL) {
2135 block = qemu_get_ram_block(addr);
2136 addr -= block->offset;
2139 if (xen_enabled() && block->host == NULL) {
2140 /* We need to check if the requested address is in the RAM
2141 * because we don't want to map the entire memory in QEMU.
2142 * In that case just map until the end of the page.
2144 if (block->offset == 0) {
2145 return xen_map_cache(addr, 0, 0, false);
2148 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2150 return ramblock_ptr(block, addr);
2153 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2154 * but takes a size argument.
2156 * Called within RCU critical section.
2158 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2159 hwaddr *size)
2161 RAMBlock *block = ram_block;
2162 if (*size == 0) {
2163 return NULL;
2166 if (block == NULL) {
2167 block = qemu_get_ram_block(addr);
2168 addr -= block->offset;
2170 *size = MIN(*size, block->max_length - addr);
2172 if (xen_enabled() && block->host == NULL) {
2173 /* We need to check if the requested address is in the RAM
2174 * because we don't want to map the entire memory in QEMU.
2175 * In that case just map the requested area.
2177 if (block->offset == 0) {
2178 return xen_map_cache(addr, *size, 1, true);
2181 block->host = xen_map_cache(block->offset, block->max_length, 1, true);
2184 return ramblock_ptr(block, addr);
2188 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2189 * in that RAMBlock.
2191 * ptr: Host pointer to look up
2192 * round_offset: If true round the result offset down to a page boundary
2193 * *ram_addr: set to result ram_addr
2194 * *offset: set to result offset within the RAMBlock
2196 * Returns: RAMBlock (or NULL if not found)
2198 * By the time this function returns, the returned pointer is not protected
2199 * by RCU anymore. If the caller is not within an RCU critical section and
2200 * does not hold the iothread lock, it must have other means of protecting the
2201 * pointer, such as a reference to the region that includes the incoming
2202 * ram_addr_t.
2204 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2205 ram_addr_t *offset)
2207 RAMBlock *block;
2208 uint8_t *host = ptr;
2210 if (xen_enabled()) {
2211 ram_addr_t ram_addr;
2212 rcu_read_lock();
2213 ram_addr = xen_ram_addr_from_mapcache(ptr);
2214 block = qemu_get_ram_block(ram_addr);
2215 if (block) {
2216 *offset = ram_addr - block->offset;
2218 rcu_read_unlock();
2219 return block;
2222 rcu_read_lock();
2223 block = atomic_rcu_read(&ram_list.mru_block);
2224 if (block && block->host && host - block->host < block->max_length) {
2225 goto found;
2228 RAMBLOCK_FOREACH(block) {
2229 /* This case append when the block is not mapped. */
2230 if (block->host == NULL) {
2231 continue;
2233 if (host - block->host < block->max_length) {
2234 goto found;
2238 rcu_read_unlock();
2239 return NULL;
2241 found:
2242 *offset = (host - block->host);
2243 if (round_offset) {
2244 *offset &= TARGET_PAGE_MASK;
2246 rcu_read_unlock();
2247 return block;
2251 * Finds the named RAMBlock
2253 * name: The name of RAMBlock to find
2255 * Returns: RAMBlock (or NULL if not found)
2257 RAMBlock *qemu_ram_block_by_name(const char *name)
2259 RAMBlock *block;
2261 RAMBLOCK_FOREACH(block) {
2262 if (!strcmp(name, block->idstr)) {
2263 return block;
2267 return NULL;
2270 /* Some of the softmmu routines need to translate from a host pointer
2271 (typically a TLB entry) back to a ram offset. */
2272 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2274 RAMBlock *block;
2275 ram_addr_t offset;
2277 block = qemu_ram_block_from_host(ptr, false, &offset);
2278 if (!block) {
2279 return RAM_ADDR_INVALID;
2282 return block->offset + offset;
2285 /* Called within RCU critical section. */
2286 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2287 uint64_t val, unsigned size)
2289 bool locked = false;
2291 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2292 locked = true;
2293 tb_lock();
2294 tb_invalidate_phys_page_fast(ram_addr, size);
2296 switch (size) {
2297 case 1:
2298 stb_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2299 break;
2300 case 2:
2301 stw_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2302 break;
2303 case 4:
2304 stl_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2305 break;
2306 default:
2307 abort();
2310 if (locked) {
2311 tb_unlock();
2314 /* Set both VGA and migration bits for simplicity and to remove
2315 * the notdirty callback faster.
2317 cpu_physical_memory_set_dirty_range(ram_addr, size,
2318 DIRTY_CLIENTS_NOCODE);
2319 /* we remove the notdirty callback only if the code has been
2320 flushed */
2321 if (!cpu_physical_memory_is_clean(ram_addr)) {
2322 tlb_set_dirty(current_cpu, current_cpu->mem_io_vaddr);
2326 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2327 unsigned size, bool is_write)
2329 return is_write;
2332 static const MemoryRegionOps notdirty_mem_ops = {
2333 .write = notdirty_mem_write,
2334 .valid.accepts = notdirty_mem_accepts,
2335 .endianness = DEVICE_NATIVE_ENDIAN,
2338 /* Generate a debug exception if a watchpoint has been hit. */
2339 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2341 CPUState *cpu = current_cpu;
2342 CPUClass *cc = CPU_GET_CLASS(cpu);
2343 CPUArchState *env = cpu->env_ptr;
2344 target_ulong pc, cs_base;
2345 target_ulong vaddr;
2346 CPUWatchpoint *wp;
2347 uint32_t cpu_flags;
2349 if (cpu->watchpoint_hit) {
2350 /* We re-entered the check after replacing the TB. Now raise
2351 * the debug interrupt so that is will trigger after the
2352 * current instruction. */
2353 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2354 return;
2356 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2357 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2358 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2359 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2360 && (wp->flags & flags)) {
2361 if (flags == BP_MEM_READ) {
2362 wp->flags |= BP_WATCHPOINT_HIT_READ;
2363 } else {
2364 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2366 wp->hitaddr = vaddr;
2367 wp->hitattrs = attrs;
2368 if (!cpu->watchpoint_hit) {
2369 if (wp->flags & BP_CPU &&
2370 !cc->debug_check_watchpoint(cpu, wp)) {
2371 wp->flags &= ~BP_WATCHPOINT_HIT;
2372 continue;
2374 cpu->watchpoint_hit = wp;
2376 /* Both tb_lock and iothread_mutex will be reset when
2377 * cpu_loop_exit or cpu_loop_exit_noexc longjmp
2378 * back into the cpu_exec main loop.
2380 tb_lock();
2381 tb_check_watchpoint(cpu);
2382 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2383 cpu->exception_index = EXCP_DEBUG;
2384 cpu_loop_exit(cpu);
2385 } else {
2386 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
2387 tb_gen_code(cpu, pc, cs_base, cpu_flags, 1);
2388 cpu_loop_exit_noexc(cpu);
2391 } else {
2392 wp->flags &= ~BP_WATCHPOINT_HIT;
2397 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2398 so these check for a hit then pass through to the normal out-of-line
2399 phys routines. */
2400 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2401 unsigned size, MemTxAttrs attrs)
2403 MemTxResult res;
2404 uint64_t data;
2405 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2406 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2408 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2409 switch (size) {
2410 case 1:
2411 data = address_space_ldub(as, addr, attrs, &res);
2412 break;
2413 case 2:
2414 data = address_space_lduw(as, addr, attrs, &res);
2415 break;
2416 case 4:
2417 data = address_space_ldl(as, addr, attrs, &res);
2418 break;
2419 default: abort();
2421 *pdata = data;
2422 return res;
2425 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2426 uint64_t val, unsigned size,
2427 MemTxAttrs attrs)
2429 MemTxResult res;
2430 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2431 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2433 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2434 switch (size) {
2435 case 1:
2436 address_space_stb(as, addr, val, attrs, &res);
2437 break;
2438 case 2:
2439 address_space_stw(as, addr, val, attrs, &res);
2440 break;
2441 case 4:
2442 address_space_stl(as, addr, val, attrs, &res);
2443 break;
2444 default: abort();
2446 return res;
2449 static const MemoryRegionOps watch_mem_ops = {
2450 .read_with_attrs = watch_mem_read,
2451 .write_with_attrs = watch_mem_write,
2452 .endianness = DEVICE_NATIVE_ENDIAN,
2455 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2456 unsigned len, MemTxAttrs attrs)
2458 subpage_t *subpage = opaque;
2459 uint8_t buf[8];
2460 MemTxResult res;
2462 #if defined(DEBUG_SUBPAGE)
2463 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2464 subpage, len, addr);
2465 #endif
2466 res = address_space_read(subpage->as, addr + subpage->base,
2467 attrs, buf, len);
2468 if (res) {
2469 return res;
2471 switch (len) {
2472 case 1:
2473 *data = ldub_p(buf);
2474 return MEMTX_OK;
2475 case 2:
2476 *data = lduw_p(buf);
2477 return MEMTX_OK;
2478 case 4:
2479 *data = ldl_p(buf);
2480 return MEMTX_OK;
2481 case 8:
2482 *data = ldq_p(buf);
2483 return MEMTX_OK;
2484 default:
2485 abort();
2489 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2490 uint64_t value, unsigned len, MemTxAttrs attrs)
2492 subpage_t *subpage = opaque;
2493 uint8_t buf[8];
2495 #if defined(DEBUG_SUBPAGE)
2496 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2497 " value %"PRIx64"\n",
2498 __func__, subpage, len, addr, value);
2499 #endif
2500 switch (len) {
2501 case 1:
2502 stb_p(buf, value);
2503 break;
2504 case 2:
2505 stw_p(buf, value);
2506 break;
2507 case 4:
2508 stl_p(buf, value);
2509 break;
2510 case 8:
2511 stq_p(buf, value);
2512 break;
2513 default:
2514 abort();
2516 return address_space_write(subpage->as, addr + subpage->base,
2517 attrs, buf, len);
2520 static bool subpage_accepts(void *opaque, hwaddr addr,
2521 unsigned len, bool is_write)
2523 subpage_t *subpage = opaque;
2524 #if defined(DEBUG_SUBPAGE)
2525 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2526 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2527 #endif
2529 return address_space_access_valid(subpage->as, addr + subpage->base,
2530 len, is_write);
2533 static const MemoryRegionOps subpage_ops = {
2534 .read_with_attrs = subpage_read,
2535 .write_with_attrs = subpage_write,
2536 .impl.min_access_size = 1,
2537 .impl.max_access_size = 8,
2538 .valid.min_access_size = 1,
2539 .valid.max_access_size = 8,
2540 .valid.accepts = subpage_accepts,
2541 .endianness = DEVICE_NATIVE_ENDIAN,
2544 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2545 uint16_t section)
2547 int idx, eidx;
2549 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2550 return -1;
2551 idx = SUBPAGE_IDX(start);
2552 eidx = SUBPAGE_IDX(end);
2553 #if defined(DEBUG_SUBPAGE)
2554 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2555 __func__, mmio, start, end, idx, eidx, section);
2556 #endif
2557 for (; idx <= eidx; idx++) {
2558 mmio->sub_section[idx] = section;
2561 return 0;
2564 static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
2566 subpage_t *mmio;
2568 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2569 mmio->as = as;
2570 mmio->base = base;
2571 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2572 NULL, TARGET_PAGE_SIZE);
2573 mmio->iomem.subpage = true;
2574 #if defined(DEBUG_SUBPAGE)
2575 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2576 mmio, base, TARGET_PAGE_SIZE);
2577 #endif
2578 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
2580 return mmio;
2583 static uint16_t dummy_section(PhysPageMap *map, AddressSpace *as,
2584 MemoryRegion *mr)
2586 assert(as);
2587 MemoryRegionSection section = {
2588 .address_space = as,
2589 .mr = mr,
2590 .offset_within_address_space = 0,
2591 .offset_within_region = 0,
2592 .size = int128_2_64(),
2595 return phys_section_add(map, &section);
2598 MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs)
2600 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2601 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2602 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
2603 MemoryRegionSection *sections = d->map.sections;
2605 return sections[index & ~TARGET_PAGE_MASK].mr;
2608 static void io_mem_init(void)
2610 memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX);
2611 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2612 NULL, UINT64_MAX);
2614 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
2615 * which can be called without the iothread mutex.
2617 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
2618 NULL, UINT64_MAX);
2619 memory_region_clear_global_locking(&io_mem_notdirty);
2621 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
2622 NULL, UINT64_MAX);
2625 static void mem_begin(MemoryListener *listener)
2627 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2628 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2629 uint16_t n;
2631 n = dummy_section(&d->map, as, &io_mem_unassigned);
2632 assert(n == PHYS_SECTION_UNASSIGNED);
2633 n = dummy_section(&d->map, as, &io_mem_notdirty);
2634 assert(n == PHYS_SECTION_NOTDIRTY);
2635 n = dummy_section(&d->map, as, &io_mem_rom);
2636 assert(n == PHYS_SECTION_ROM);
2637 n = dummy_section(&d->map, as, &io_mem_watch);
2638 assert(n == PHYS_SECTION_WATCH);
2640 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2641 d->as = as;
2642 as->next_dispatch = d;
2645 static void address_space_dispatch_free(AddressSpaceDispatch *d)
2647 phys_sections_free(&d->map);
2648 g_free(d);
2651 static void mem_commit(MemoryListener *listener)
2653 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2654 AddressSpaceDispatch *cur = as->dispatch;
2655 AddressSpaceDispatch *next = as->next_dispatch;
2657 phys_page_compact_all(next, next->map.nodes_nb);
2659 atomic_rcu_set(&as->dispatch, next);
2660 if (cur) {
2661 call_rcu(cur, address_space_dispatch_free, rcu);
2665 static void tcg_commit(MemoryListener *listener)
2667 CPUAddressSpace *cpuas;
2668 AddressSpaceDispatch *d;
2670 /* since each CPU stores ram addresses in its TLB cache, we must
2671 reset the modified entries */
2672 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2673 cpu_reloading_memory_map();
2674 /* The CPU and TLB are protected by the iothread lock.
2675 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2676 * may have split the RCU critical section.
2678 d = atomic_rcu_read(&cpuas->as->dispatch);
2679 atomic_rcu_set(&cpuas->memory_dispatch, d);
2680 tlb_flush(cpuas->cpu);
2683 void address_space_init_dispatch(AddressSpace *as)
2685 as->dispatch = NULL;
2686 as->dispatch_listener = (MemoryListener) {
2687 .begin = mem_begin,
2688 .commit = mem_commit,
2689 .region_add = mem_add,
2690 .region_nop = mem_add,
2691 .priority = 0,
2693 memory_listener_register(&as->dispatch_listener, as);
2696 void address_space_unregister(AddressSpace *as)
2698 memory_listener_unregister(&as->dispatch_listener);
2701 void address_space_destroy_dispatch(AddressSpace *as)
2703 AddressSpaceDispatch *d = as->dispatch;
2705 atomic_rcu_set(&as->dispatch, NULL);
2706 if (d) {
2707 call_rcu(d, address_space_dispatch_free, rcu);
2711 static void memory_map_init(void)
2713 system_memory = g_malloc(sizeof(*system_memory));
2715 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2716 address_space_init(&address_space_memory, system_memory, "memory");
2718 system_io = g_malloc(sizeof(*system_io));
2719 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2720 65536);
2721 address_space_init(&address_space_io, system_io, "I/O");
2724 MemoryRegion *get_system_memory(void)
2726 return system_memory;
2729 MemoryRegion *get_system_io(void)
2731 return system_io;
2734 #endif /* !defined(CONFIG_USER_ONLY) */
2736 /* physical memory access (slow version, mainly for debug) */
2737 #if defined(CONFIG_USER_ONLY)
2738 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2739 uint8_t *buf, int len, int is_write)
2741 int l, flags;
2742 target_ulong page;
2743 void * p;
2745 while (len > 0) {
2746 page = addr & TARGET_PAGE_MASK;
2747 l = (page + TARGET_PAGE_SIZE) - addr;
2748 if (l > len)
2749 l = len;
2750 flags = page_get_flags(page);
2751 if (!(flags & PAGE_VALID))
2752 return -1;
2753 if (is_write) {
2754 if (!(flags & PAGE_WRITE))
2755 return -1;
2756 /* XXX: this code should not depend on lock_user */
2757 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2758 return -1;
2759 memcpy(p, buf, l);
2760 unlock_user(p, addr, l);
2761 } else {
2762 if (!(flags & PAGE_READ))
2763 return -1;
2764 /* XXX: this code should not depend on lock_user */
2765 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
2766 return -1;
2767 memcpy(buf, p, l);
2768 unlock_user(p, addr, 0);
2770 len -= l;
2771 buf += l;
2772 addr += l;
2774 return 0;
2777 #else
2779 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
2780 hwaddr length)
2782 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
2783 addr += memory_region_get_ram_addr(mr);
2785 /* No early return if dirty_log_mask is or becomes 0, because
2786 * cpu_physical_memory_set_dirty_range will still call
2787 * xen_modified_memory.
2789 if (dirty_log_mask) {
2790 dirty_log_mask =
2791 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
2793 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
2794 tb_lock();
2795 tb_invalidate_phys_range(addr, addr + length);
2796 tb_unlock();
2797 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
2799 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
2802 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
2804 unsigned access_size_max = mr->ops->valid.max_access_size;
2806 /* Regions are assumed to support 1-4 byte accesses unless
2807 otherwise specified. */
2808 if (access_size_max == 0) {
2809 access_size_max = 4;
2812 /* Bound the maximum access by the alignment of the address. */
2813 if (!mr->ops->impl.unaligned) {
2814 unsigned align_size_max = addr & -addr;
2815 if (align_size_max != 0 && align_size_max < access_size_max) {
2816 access_size_max = align_size_max;
2820 /* Don't attempt accesses larger than the maximum. */
2821 if (l > access_size_max) {
2822 l = access_size_max;
2824 l = pow2floor(l);
2826 return l;
2829 static bool prepare_mmio_access(MemoryRegion *mr)
2831 bool unlocked = !qemu_mutex_iothread_locked();
2832 bool release_lock = false;
2834 if (unlocked && mr->global_locking) {
2835 qemu_mutex_lock_iothread();
2836 unlocked = false;
2837 release_lock = true;
2839 if (mr->flush_coalesced_mmio) {
2840 if (unlocked) {
2841 qemu_mutex_lock_iothread();
2843 qemu_flush_coalesced_mmio_buffer();
2844 if (unlocked) {
2845 qemu_mutex_unlock_iothread();
2849 return release_lock;
2852 /* Called within RCU critical section. */
2853 static MemTxResult address_space_write_continue(AddressSpace *as, hwaddr addr,
2854 MemTxAttrs attrs,
2855 const uint8_t *buf,
2856 int len, hwaddr addr1,
2857 hwaddr l, MemoryRegion *mr)
2859 uint8_t *ptr;
2860 uint64_t val;
2861 MemTxResult result = MEMTX_OK;
2862 bool release_lock = false;
2864 for (;;) {
2865 if (!memory_access_is_direct(mr, true)) {
2866 release_lock |= prepare_mmio_access(mr);
2867 l = memory_access_size(mr, l, addr1);
2868 /* XXX: could force current_cpu to NULL to avoid
2869 potential bugs */
2870 switch (l) {
2871 case 8:
2872 /* 64 bit write access */
2873 val = ldq_p(buf);
2874 result |= memory_region_dispatch_write(mr, addr1, val, 8,
2875 attrs);
2876 break;
2877 case 4:
2878 /* 32 bit write access */
2879 val = (uint32_t)ldl_p(buf);
2880 result |= memory_region_dispatch_write(mr, addr1, val, 4,
2881 attrs);
2882 break;
2883 case 2:
2884 /* 16 bit write access */
2885 val = lduw_p(buf);
2886 result |= memory_region_dispatch_write(mr, addr1, val, 2,
2887 attrs);
2888 break;
2889 case 1:
2890 /* 8 bit write access */
2891 val = ldub_p(buf);
2892 result |= memory_region_dispatch_write(mr, addr1, val, 1,
2893 attrs);
2894 break;
2895 default:
2896 abort();
2898 } else {
2899 /* RAM case */
2900 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2901 memcpy(ptr, buf, l);
2902 invalidate_and_set_dirty(mr, addr1, l);
2905 if (release_lock) {
2906 qemu_mutex_unlock_iothread();
2907 release_lock = false;
2910 len -= l;
2911 buf += l;
2912 addr += l;
2914 if (!len) {
2915 break;
2918 l = len;
2919 mr = address_space_translate(as, addr, &addr1, &l, true);
2922 return result;
2925 MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
2926 const uint8_t *buf, int len)
2928 hwaddr l;
2929 hwaddr addr1;
2930 MemoryRegion *mr;
2931 MemTxResult result = MEMTX_OK;
2933 if (len > 0) {
2934 rcu_read_lock();
2935 l = len;
2936 mr = address_space_translate(as, addr, &addr1, &l, true);
2937 result = address_space_write_continue(as, addr, attrs, buf, len,
2938 addr1, l, mr);
2939 rcu_read_unlock();
2942 return result;
2945 /* Called within RCU critical section. */
2946 MemTxResult address_space_read_continue(AddressSpace *as, hwaddr addr,
2947 MemTxAttrs attrs, uint8_t *buf,
2948 int len, hwaddr addr1, hwaddr l,
2949 MemoryRegion *mr)
2951 uint8_t *ptr;
2952 uint64_t val;
2953 MemTxResult result = MEMTX_OK;
2954 bool release_lock = false;
2956 for (;;) {
2957 if (!memory_access_is_direct(mr, false)) {
2958 /* I/O case */
2959 release_lock |= prepare_mmio_access(mr);
2960 l = memory_access_size(mr, l, addr1);
2961 switch (l) {
2962 case 8:
2963 /* 64 bit read access */
2964 result |= memory_region_dispatch_read(mr, addr1, &val, 8,
2965 attrs);
2966 stq_p(buf, val);
2967 break;
2968 case 4:
2969 /* 32 bit read access */
2970 result |= memory_region_dispatch_read(mr, addr1, &val, 4,
2971 attrs);
2972 stl_p(buf, val);
2973 break;
2974 case 2:
2975 /* 16 bit read access */
2976 result |= memory_region_dispatch_read(mr, addr1, &val, 2,
2977 attrs);
2978 stw_p(buf, val);
2979 break;
2980 case 1:
2981 /* 8 bit read access */
2982 result |= memory_region_dispatch_read(mr, addr1, &val, 1,
2983 attrs);
2984 stb_p(buf, val);
2985 break;
2986 default:
2987 abort();
2989 } else {
2990 /* RAM case */
2991 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2992 memcpy(buf, ptr, l);
2995 if (release_lock) {
2996 qemu_mutex_unlock_iothread();
2997 release_lock = false;
3000 len -= l;
3001 buf += l;
3002 addr += l;
3004 if (!len) {
3005 break;
3008 l = len;
3009 mr = address_space_translate(as, addr, &addr1, &l, false);
3012 return result;
3015 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3016 MemTxAttrs attrs, uint8_t *buf, int len)
3018 hwaddr l;
3019 hwaddr addr1;
3020 MemoryRegion *mr;
3021 MemTxResult result = MEMTX_OK;
3023 if (len > 0) {
3024 rcu_read_lock();
3025 l = len;
3026 mr = address_space_translate(as, addr, &addr1, &l, false);
3027 result = address_space_read_continue(as, addr, attrs, buf, len,
3028 addr1, l, mr);
3029 rcu_read_unlock();
3032 return result;
3035 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3036 uint8_t *buf, int len, bool is_write)
3038 if (is_write) {
3039 return address_space_write(as, addr, attrs, (uint8_t *)buf, len);
3040 } else {
3041 return address_space_read(as, addr, attrs, (uint8_t *)buf, len);
3045 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
3046 int len, int is_write)
3048 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3049 buf, len, is_write);
3052 enum write_rom_type {
3053 WRITE_DATA,
3054 FLUSH_CACHE,
3057 static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
3058 hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
3060 hwaddr l;
3061 uint8_t *ptr;
3062 hwaddr addr1;
3063 MemoryRegion *mr;
3065 rcu_read_lock();
3066 while (len > 0) {
3067 l = len;
3068 mr = address_space_translate(as, addr, &addr1, &l, true);
3070 if (!(memory_region_is_ram(mr) ||
3071 memory_region_is_romd(mr))) {
3072 l = memory_access_size(mr, l, addr1);
3073 } else {
3074 /* ROM/RAM case */
3075 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3076 switch (type) {
3077 case WRITE_DATA:
3078 memcpy(ptr, buf, l);
3079 invalidate_and_set_dirty(mr, addr1, l);
3080 break;
3081 case FLUSH_CACHE:
3082 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
3083 break;
3086 len -= l;
3087 buf += l;
3088 addr += l;
3090 rcu_read_unlock();
3093 /* used for ROM loading : can write in RAM and ROM */
3094 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
3095 const uint8_t *buf, int len)
3097 cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
3100 void cpu_flush_icache_range(hwaddr start, int len)
3103 * This function should do the same thing as an icache flush that was
3104 * triggered from within the guest. For TCG we are always cache coherent,
3105 * so there is no need to flush anything. For KVM / Xen we need to flush
3106 * the host's instruction cache at least.
3108 if (tcg_enabled()) {
3109 return;
3112 cpu_physical_memory_write_rom_internal(&address_space_memory,
3113 start, NULL, len, FLUSH_CACHE);
3116 typedef struct {
3117 MemoryRegion *mr;
3118 void *buffer;
3119 hwaddr addr;
3120 hwaddr len;
3121 bool in_use;
3122 } BounceBuffer;
3124 static BounceBuffer bounce;
3126 typedef struct MapClient {
3127 QEMUBH *bh;
3128 QLIST_ENTRY(MapClient) link;
3129 } MapClient;
3131 QemuMutex map_client_list_lock;
3132 static QLIST_HEAD(map_client_list, MapClient) map_client_list
3133 = QLIST_HEAD_INITIALIZER(map_client_list);
3135 static void cpu_unregister_map_client_do(MapClient *client)
3137 QLIST_REMOVE(client, link);
3138 g_free(client);
3141 static void cpu_notify_map_clients_locked(void)
3143 MapClient *client;
3145 while (!QLIST_EMPTY(&map_client_list)) {
3146 client = QLIST_FIRST(&map_client_list);
3147 qemu_bh_schedule(client->bh);
3148 cpu_unregister_map_client_do(client);
3152 void cpu_register_map_client(QEMUBH *bh)
3154 MapClient *client = g_malloc(sizeof(*client));
3156 qemu_mutex_lock(&map_client_list_lock);
3157 client->bh = bh;
3158 QLIST_INSERT_HEAD(&map_client_list, client, link);
3159 if (!atomic_read(&bounce.in_use)) {
3160 cpu_notify_map_clients_locked();
3162 qemu_mutex_unlock(&map_client_list_lock);
3165 void cpu_exec_init_all(void)
3167 qemu_mutex_init(&ram_list.mutex);
3168 /* The data structures we set up here depend on knowing the page size,
3169 * so no more changes can be made after this point.
3170 * In an ideal world, nothing we did before we had finished the
3171 * machine setup would care about the target page size, and we could
3172 * do this much later, rather than requiring board models to state
3173 * up front what their requirements are.
3175 finalize_target_page_bits();
3176 io_mem_init();
3177 memory_map_init();
3178 qemu_mutex_init(&map_client_list_lock);
3181 void cpu_unregister_map_client(QEMUBH *bh)
3183 MapClient *client;
3185 qemu_mutex_lock(&map_client_list_lock);
3186 QLIST_FOREACH(client, &map_client_list, link) {
3187 if (client->bh == bh) {
3188 cpu_unregister_map_client_do(client);
3189 break;
3192 qemu_mutex_unlock(&map_client_list_lock);
3195 static void cpu_notify_map_clients(void)
3197 qemu_mutex_lock(&map_client_list_lock);
3198 cpu_notify_map_clients_locked();
3199 qemu_mutex_unlock(&map_client_list_lock);
3202 bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write)
3204 MemoryRegion *mr;
3205 hwaddr l, xlat;
3207 rcu_read_lock();
3208 while (len > 0) {
3209 l = len;
3210 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3211 if (!memory_access_is_direct(mr, is_write)) {
3212 l = memory_access_size(mr, l, addr);
3213 if (!memory_region_access_valid(mr, xlat, l, is_write)) {
3214 rcu_read_unlock();
3215 return false;
3219 len -= l;
3220 addr += l;
3222 rcu_read_unlock();
3223 return true;
3226 static hwaddr
3227 address_space_extend_translation(AddressSpace *as, hwaddr addr, hwaddr target_len,
3228 MemoryRegion *mr, hwaddr base, hwaddr len,
3229 bool is_write)
3231 hwaddr done = 0;
3232 hwaddr xlat;
3233 MemoryRegion *this_mr;
3235 for (;;) {
3236 target_len -= len;
3237 addr += len;
3238 done += len;
3239 if (target_len == 0) {
3240 return done;
3243 len = target_len;
3244 this_mr = address_space_translate(as, addr, &xlat, &len, is_write);
3245 if (this_mr != mr || xlat != base + done) {
3246 return done;
3251 /* Map a physical memory region into a host virtual address.
3252 * May map a subset of the requested range, given by and returned in *plen.
3253 * May return NULL if resources needed to perform the mapping are exhausted.
3254 * Use only for reads OR writes - not for read-modify-write operations.
3255 * Use cpu_register_map_client() to know when retrying the map operation is
3256 * likely to succeed.
3258 void *address_space_map(AddressSpace *as,
3259 hwaddr addr,
3260 hwaddr *plen,
3261 bool is_write)
3263 hwaddr len = *plen;
3264 hwaddr l, xlat;
3265 MemoryRegion *mr;
3266 void *ptr;
3268 if (len == 0) {
3269 return NULL;
3272 l = len;
3273 rcu_read_lock();
3274 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3276 if (!memory_access_is_direct(mr, is_write)) {
3277 if (atomic_xchg(&bounce.in_use, true)) {
3278 rcu_read_unlock();
3279 return NULL;
3281 /* Avoid unbounded allocations */
3282 l = MIN(l, TARGET_PAGE_SIZE);
3283 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3284 bounce.addr = addr;
3285 bounce.len = l;
3287 memory_region_ref(mr);
3288 bounce.mr = mr;
3289 if (!is_write) {
3290 address_space_read(as, addr, MEMTXATTRS_UNSPECIFIED,
3291 bounce.buffer, l);
3294 rcu_read_unlock();
3295 *plen = l;
3296 return bounce.buffer;
3300 memory_region_ref(mr);
3301 *plen = address_space_extend_translation(as, addr, len, mr, xlat, l, is_write);
3302 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen);
3303 rcu_read_unlock();
3305 return ptr;
3308 /* Unmaps a memory region previously mapped by address_space_map().
3309 * Will also mark the memory as dirty if is_write == 1. access_len gives
3310 * the amount of memory that was actually read or written by the caller.
3312 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3313 int is_write, hwaddr access_len)
3315 if (buffer != bounce.buffer) {
3316 MemoryRegion *mr;
3317 ram_addr_t addr1;
3319 mr = memory_region_from_host(buffer, &addr1);
3320 assert(mr != NULL);
3321 if (is_write) {
3322 invalidate_and_set_dirty(mr, addr1, access_len);
3324 if (xen_enabled()) {
3325 xen_invalidate_map_cache_entry(buffer);
3327 memory_region_unref(mr);
3328 return;
3330 if (is_write) {
3331 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3332 bounce.buffer, access_len);
3334 qemu_vfree(bounce.buffer);
3335 bounce.buffer = NULL;
3336 memory_region_unref(bounce.mr);
3337 atomic_mb_set(&bounce.in_use, false);
3338 cpu_notify_map_clients();
3341 void *cpu_physical_memory_map(hwaddr addr,
3342 hwaddr *plen,
3343 int is_write)
3345 return address_space_map(&address_space_memory, addr, plen, is_write);
3348 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3349 int is_write, hwaddr access_len)
3351 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3354 #define ARG1_DECL AddressSpace *as
3355 #define ARG1 as
3356 #define SUFFIX
3357 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3358 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3359 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3360 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3361 #define RCU_READ_LOCK(...) rcu_read_lock()
3362 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3363 #include "memory_ldst.inc.c"
3365 int64_t address_space_cache_init(MemoryRegionCache *cache,
3366 AddressSpace *as,
3367 hwaddr addr,
3368 hwaddr len,
3369 bool is_write)
3371 cache->len = len;
3372 cache->as = as;
3373 cache->xlat = addr;
3374 return len;
3377 void address_space_cache_invalidate(MemoryRegionCache *cache,
3378 hwaddr addr,
3379 hwaddr access_len)
3383 void address_space_cache_destroy(MemoryRegionCache *cache)
3385 cache->as = NULL;
3388 #define ARG1_DECL MemoryRegionCache *cache
3389 #define ARG1 cache
3390 #define SUFFIX _cached
3391 #define TRANSLATE(addr, ...) \
3392 address_space_translate(cache->as, cache->xlat + (addr), __VA_ARGS__)
3393 #define IS_DIRECT(mr, is_write) true
3394 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3395 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3396 #define RCU_READ_LOCK() rcu_read_lock()
3397 #define RCU_READ_UNLOCK() rcu_read_unlock()
3398 #include "memory_ldst.inc.c"
3400 /* virtual memory access for debug (includes writing to ROM) */
3401 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3402 uint8_t *buf, int len, int is_write)
3404 int l;
3405 hwaddr phys_addr;
3406 target_ulong page;
3408 cpu_synchronize_state(cpu);
3409 while (len > 0) {
3410 int asidx;
3411 MemTxAttrs attrs;
3413 page = addr & TARGET_PAGE_MASK;
3414 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3415 asidx = cpu_asidx_from_attrs(cpu, attrs);
3416 /* if no physical page mapped, return an error */
3417 if (phys_addr == -1)
3418 return -1;
3419 l = (page + TARGET_PAGE_SIZE) - addr;
3420 if (l > len)
3421 l = len;
3422 phys_addr += (addr & ~TARGET_PAGE_MASK);
3423 if (is_write) {
3424 cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
3425 phys_addr, buf, l);
3426 } else {
3427 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3428 MEMTXATTRS_UNSPECIFIED,
3429 buf, l, 0);
3431 len -= l;
3432 buf += l;
3433 addr += l;
3435 return 0;
3439 * Allows code that needs to deal with migration bitmaps etc to still be built
3440 * target independent.
3442 size_t qemu_target_page_size(void)
3444 return TARGET_PAGE_SIZE;
3447 int qemu_target_page_bits(void)
3449 return TARGET_PAGE_BITS;
3452 int qemu_target_page_bits_min(void)
3454 return TARGET_PAGE_BITS_MIN;
3456 #endif
3459 * A helper function for the _utterly broken_ virtio device model to find out if
3460 * it's running on a big endian machine. Don't do this at home kids!
3462 bool target_words_bigendian(void);
3463 bool target_words_bigendian(void)
3465 #if defined(TARGET_WORDS_BIGENDIAN)
3466 return true;
3467 #else
3468 return false;
3469 #endif
3472 #ifndef CONFIG_USER_ONLY
3473 bool cpu_physical_memory_is_io(hwaddr phys_addr)
3475 MemoryRegion*mr;
3476 hwaddr l = 1;
3477 bool res;
3479 rcu_read_lock();
3480 mr = address_space_translate(&address_space_memory,
3481 phys_addr, &phys_addr, &l, false);
3483 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
3484 rcu_read_unlock();
3485 return res;
3488 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
3490 RAMBlock *block;
3491 int ret = 0;
3493 rcu_read_lock();
3494 RAMBLOCK_FOREACH(block) {
3495 ret = func(block->idstr, block->host, block->offset,
3496 block->used_length, opaque);
3497 if (ret) {
3498 break;
3501 rcu_read_unlock();
3502 return ret;
3506 * Unmap pages of memory from start to start+length such that
3507 * they a) read as 0, b) Trigger whatever fault mechanism
3508 * the OS provides for postcopy.
3509 * The pages must be unmapped by the end of the function.
3510 * Returns: 0 on success, none-0 on failure
3513 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
3515 int ret = -1;
3517 uint8_t *host_startaddr = rb->host + start;
3519 if ((uintptr_t)host_startaddr & (rb->page_size - 1)) {
3520 error_report("ram_block_discard_range: Unaligned start address: %p",
3521 host_startaddr);
3522 goto err;
3525 if ((start + length) <= rb->used_length) {
3526 uint8_t *host_endaddr = host_startaddr + length;
3527 if ((uintptr_t)host_endaddr & (rb->page_size - 1)) {
3528 error_report("ram_block_discard_range: Unaligned end address: %p",
3529 host_endaddr);
3530 goto err;
3533 errno = ENOTSUP; /* If we are missing MADVISE etc */
3535 if (rb->page_size == qemu_host_page_size) {
3536 #if defined(CONFIG_MADVISE)
3537 /* Note: We need the madvise MADV_DONTNEED behaviour of definitely
3538 * freeing the page.
3540 ret = madvise(host_startaddr, length, MADV_DONTNEED);
3541 #endif
3542 } else {
3543 /* Huge page case - unfortunately it can't do DONTNEED, but
3544 * it can do the equivalent by FALLOC_FL_PUNCH_HOLE in the
3545 * huge page file.
3547 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
3548 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
3549 start, length);
3550 #endif
3552 if (ret) {
3553 ret = -errno;
3554 error_report("ram_block_discard_range: Failed to discard range "
3555 "%s:%" PRIx64 " +%zx (%d)",
3556 rb->idstr, start, length, ret);
3558 } else {
3559 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
3560 "/%zx/" RAM_ADDR_FMT")",
3561 rb->idstr, start, length, rb->used_length);
3564 err:
3565 return ret;
3568 #endif