hw/arm/mps2.c

   1 /*
   2  * ARM V2M MPS2 board emulation.
   3  *
   4  * Copyright (c) 2017 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
  13  * FPGA but is otherwise the same as the 2). Since the CPU itself
  14  * and most of the devices are in the FPGA, the details of the board
  15  * as seen by the guest depend significantly on the FPGA image.
  16  * We model the following FPGA images:
  17  *  "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
  18  *  "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
  19  *
  20  * Links to the TRM for the board itself and to the various Application
  21  * Notes which document the FPGA images can be found here:
  22  *   https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "qemu/cutils.h"
  28 #include "qapi/error.h"
  29 #include "qemu/error-report.h"
  30 #include "hw/arm/boot.h"
  31 #include "hw/arm/armv7m.h"
  32 #include "hw/or-irq.h"
  33 #include "hw/boards.h"
  34 #include "exec/address-spaces.h"
  35 #include "sysemu/sysemu.h"
  36 #include "hw/misc/unimp.h"
  37 #include "hw/char/cmsdk-apb-uart.h"
  38 #include "hw/timer/cmsdk-apb-timer.h"
  39 #include "hw/timer/cmsdk-apb-dualtimer.h"
  40 #include "hw/misc/mps2-scc.h"
  41 #include "hw/net/lan9118.h"
  42 #include "net/net.h"
  43
  44 typedef enum MPS2FPGAType {
  45     FPGA_AN385,
  46     FPGA_AN511,
  47 } MPS2FPGAType;
  48
  49 typedef struct {
  50     MachineClass parent;
  51     MPS2FPGAType fpga_type;
  52     uint32_t scc_id;
  53 } MPS2MachineClass;
  54
  55 typedef struct {
  56     MachineState parent;
  57
  58     ARMv7MState armv7m;
  59     MemoryRegion ssram1;
  60     MemoryRegion ssram1_m;
  61     MemoryRegion ssram23;
  62     MemoryRegion ssram23_m;
  63     MemoryRegion blockram;
  64     MemoryRegion blockram_m1;
  65     MemoryRegion blockram_m2;
  66     MemoryRegion blockram_m3;
  67     MemoryRegion sram;
  68     /* FPGA APB subsystem */
  69     MPS2SCC scc;
  70     /* CMSDK APB subsystem */
  71     CMSDKAPBDualTimer dualtimer;
  72 } MPS2MachineState;
  73
  74 #define TYPE_MPS2_MACHINE "mps2"
  75 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
  76 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
  77
  78 #define MPS2_MACHINE(obj)                                       \
  79     OBJECT_CHECK(MPS2MachineState, obj, TYPE_MPS2_MACHINE)
  80 #define MPS2_MACHINE_GET_CLASS(obj) \
  81     OBJECT_GET_CLASS(MPS2MachineClass, obj, TYPE_MPS2_MACHINE)
  82 #define MPS2_MACHINE_CLASS(klass) \
  83     OBJECT_CLASS_CHECK(MPS2MachineClass, klass, TYPE_MPS2_MACHINE)
  84
  85 /* Main SYSCLK frequency in Hz */
  86 #define SYSCLK_FRQ 25000000
  87
  88 /* Initialize the auxiliary RAM region @mr and map it into
  89  * the memory map at @base.
  90  */
  91 static void make_ram(MemoryRegion *mr, const char *name,
  92                      hwaddr base, hwaddr size)
  93 {
  94     memory_region_init_ram(mr, NULL, name, size, &error_fatal);
  95     memory_region_add_subregion(get_system_memory(), base, mr);
  96 }
  97
  98 /* Create an alias of an entire original MemoryRegion @orig
  99  * located at @base in the memory map.
 100  */
 101 static void make_ram_alias(MemoryRegion *mr, const char *name,
 102                            MemoryRegion *orig, hwaddr base)
 103 {
 104     memory_region_init_alias(mr, NULL, name, orig, 0,
 105                              memory_region_size(orig));
 106     memory_region_add_subregion(get_system_memory(), base, mr);
 107 }
 108
 109 static void mps2_common_init(MachineState *machine)
 110 {
 111     MPS2MachineState *mms = MPS2_MACHINE(machine);
 112     MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
 113     MemoryRegion *system_memory = get_system_memory();
 114     MachineClass *mc = MACHINE_GET_CLASS(machine);
 115     DeviceState *armv7m, *sccdev;
 116
 117     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
 118         error_report("This board can only be used with CPU %s",
 119                      mc->default_cpu_type);
 120         exit(1);
 121     }
 122
 123     if (machine->ram_size != mc->default_ram_size) {
 124         char *sz = size_to_str(mc->default_ram_size);
 125         error_report("Invalid RAM size, should be %s", sz);
 126         g_free(sz);
 127         exit(EXIT_FAILURE);
 128     }
 129
 130     /* The FPGA images have an odd combination of different RAMs,
 131      * because in hardware they are different implementations and
 132      * connected to different buses, giving varying performance/size
 133      * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
 134      * call the 16MB our "system memory", as it's the largest lump.
 135      *
 136      * Common to both boards:
 137      *  0x21000000..0x21ffffff : PSRAM (16MB)
 138      * AN385 only:
 139      *  0x00000000 .. 0x003fffff : ZBT SSRAM1
 140      *  0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
 141      *  0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
 142      *  0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
 143      *  0x01000000 .. 0x01003fff : block RAM (16K)
 144      *  0x01004000 .. 0x01007fff : mirror of above
 145      *  0x01008000 .. 0x0100bfff : mirror of above
 146      *  0x0100c000 .. 0x0100ffff : mirror of above
 147      * AN511 only:
 148      *  0x00000000 .. 0x0003ffff : FPGA block RAM
 149      *  0x00400000 .. 0x007fffff : ZBT SSRAM1
 150      *  0x20000000 .. 0x2001ffff : SRAM
 151      *  0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
 152      *
 153      * The AN385 has a feature where the lowest 16K can be mapped
 154      * either to the bottom of the ZBT SSRAM1 or to the block RAM.
 155      * This is of no use for QEMU so we don't implement it (as if
 156      * zbt_boot_ctrl is always zero).
 157      */
 158     memory_region_add_subregion(system_memory, 0x21000000, machine->ram);
 159
 160     switch (mmc->fpga_type) {
 161     case FPGA_AN385:
 162         make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
 163         make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
 164         make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
 165         make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
 166                        &mms->ssram23, 0x20400000);
 167         make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
 168         make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
 169                        &mms->blockram, 0x01004000);
 170         make_ram_alias(&mms->blockram_m2, "mps.blockram_m2",
 171                        &mms->blockram, 0x01008000);
 172         make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
 173                        &mms->blockram, 0x0100c000);
 174         break;
 175     case FPGA_AN511:
 176         make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
 177         make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000);
 178         make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000);
 179         make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000);
 180         break;
 181     default:
 182         g_assert_not_reached();
 183     }
 184
 185     object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M);
 186     armv7m = DEVICE(&mms->armv7m);
 187     switch (mmc->fpga_type) {
 188     case FPGA_AN385:
 189         qdev_prop_set_uint32(armv7m, "num-irq", 32);
 190         break;
 191     case FPGA_AN511:
 192         qdev_prop_set_uint32(armv7m, "num-irq", 64);
 193         break;
 194     default:
 195         g_assert_not_reached();
 196     }
 197     qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
 198     qdev_prop_set_bit(armv7m, "enable-bitband", true);
 199     object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
 200                              "memory", &error_abort);
 201     sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal);
 202
 203     create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
 204     create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
 205     create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
 206     create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
 207     create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
 208     create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
 209     /* These three ranges all cover multiple devices; we may implement
 210      * some of them below (in which case the real device takes precedence
 211      * over the unimplemented-region mapping).
 212      */
 213     create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
 214                                 0x40000000, 0x00010000);
 215     create_unimplemented_device("CMSDK AHB peripheral region @0x40010000",
 216                                 0x40010000, 0x00010000);
 217     create_unimplemented_device("Extra peripheral region @0x40020000",
 218                                 0x40020000, 0x00010000);
 219
 220     create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
 221     create_unimplemented_device("VGA", 0x41000000, 0x0200000);
 222
 223     switch (mmc->fpga_type) {
 224     case FPGA_AN385:
 225     {
 226         /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
 227          * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
 228          */
 229         Object *orgate;
 230         DeviceState *orgate_dev;
 231         int i;
 232
 233         orgate = object_new(TYPE_OR_IRQ);
 234         object_property_set_int(orgate, 6, "num-lines", &error_fatal);
 235         qdev_realize(DEVICE(orgate), NULL, &error_fatal);
 236         orgate_dev = DEVICE(orgate);
 237         qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
 238
 239         for (i = 0; i < 5; i++) {
 240             static const hwaddr uartbase[] = {0x40004000, 0x40005000,
 241                                               0x40006000, 0x40007000,
 242                                               0x40009000};
 243             /* RX irq number; TX irq is always one greater */
 244             static const int uartirq[] = {0, 2, 4, 18, 20};
 245             qemu_irq txovrint = NULL, rxovrint = NULL;
 246
 247             if (i < 3) {
 248                 txovrint = qdev_get_gpio_in(orgate_dev, i * 2);
 249                 rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
 250             }
 251
 252             cmsdk_apb_uart_create(uartbase[i],
 253                                   qdev_get_gpio_in(armv7m, uartirq[i] + 1),
 254                                   qdev_get_gpio_in(armv7m, uartirq[i]),
 255                                   txovrint, rxovrint,
 256                                   NULL,
 257                                   serial_hd(i), SYSCLK_FRQ);
 258         }
 259         break;
 260     }
 261     case FPGA_AN511:
 262     {
 263         /* The overflow IRQs for all UARTs are ORed together.
 264          * Tx and Rx IRQs for each UART are ORed together.
 265          */
 266         Object *orgate;
 267         DeviceState *orgate_dev;
 268         int i;
 269
 270         orgate = object_new(TYPE_OR_IRQ);
 271         object_property_set_int(orgate, 10, "num-lines", &error_fatal);
 272         qdev_realize(DEVICE(orgate), NULL, &error_fatal);
 273         orgate_dev = DEVICE(orgate);
 274         qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
 275
 276         for (i = 0; i < 5; i++) {
 277             /* system irq numbers for the combined tx/rx for each UART */
 278             static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56};
 279             static const hwaddr uartbase[] = {0x40004000, 0x40005000,
 280                                               0x4002c000, 0x4002d000,
 281                                               0x4002e000};
 282             Object *txrx_orgate;
 283             DeviceState *txrx_orgate_dev;
 284
 285             txrx_orgate = object_new(TYPE_OR_IRQ);
 286             object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal);
 287             qdev_realize(DEVICE(txrx_orgate), NULL, &error_fatal);
 288             txrx_orgate_dev = DEVICE(txrx_orgate);
 289             qdev_connect_gpio_out(txrx_orgate_dev, 0,
 290                                   qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
 291             cmsdk_apb_uart_create(uartbase[i],
 292                                   qdev_get_gpio_in(txrx_orgate_dev, 0),
 293                                   qdev_get_gpio_in(txrx_orgate_dev, 1),
 294                                   qdev_get_gpio_in(orgate_dev, i * 2),
 295                                   qdev_get_gpio_in(orgate_dev, i * 2 + 1),
 296                                   NULL,
 297                                   serial_hd(i), SYSCLK_FRQ);
 298         }
 299         break;
 300     }
 301     default:
 302         g_assert_not_reached();
 303     }
 304
 305     /* CMSDK APB subsystem */
 306     cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
 307     cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
 308     object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
 309                             TYPE_CMSDK_APB_DUALTIMER);
 310     qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
 311     sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
 312     sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
 313                        qdev_get_gpio_in(armv7m, 10));
 314     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
 315
 316     /* FPGA APB subsystem */
 317     object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
 318     sccdev = DEVICE(&mms->scc);
 319     qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
 320     qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
 321     qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
 322     sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
 323     sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
 324
 325     /* In hardware this is a LAN9220; the LAN9118 is software compatible
 326      * except that it doesn't support the checksum-offload feature.
 327      */
 328     lan9118_init(&nd_table[0], 0x40200000,
 329                  qdev_get_gpio_in(armv7m,
 330                                   mmc->fpga_type == FPGA_AN385 ? 13 : 47));
 331
 332     system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
 333
 334     armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
 335                        0x400000);
 336 }
 337
 338 static void mps2_class_init(ObjectClass *oc, void *data)
 339 {
 340     MachineClass *mc = MACHINE_CLASS(oc);
 341
 342     mc->init = mps2_common_init;
 343     mc->max_cpus = 1;
 344     mc->default_ram_size = 16 * MiB;
 345     mc->default_ram_id = "mps.ram";
 346 }
 347
 348 static void mps2_an385_class_init(ObjectClass *oc, void *data)
 349 {
 350     MachineClass *mc = MACHINE_CLASS(oc);
 351     MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
 352
 353     mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
 354     mmc->fpga_type = FPGA_AN385;
 355     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
 356     mmc->scc_id = 0x41043850;
 357 }
 358
 359 static void mps2_an511_class_init(ObjectClass *oc, void *data)
 360 {
 361     MachineClass *mc = MACHINE_CLASS(oc);
 362     MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
 363
 364     mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
 365     mmc->fpga_type = FPGA_AN511;
 366     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
 367     mmc->scc_id = 0x41045110;
 368 }
 369
 370 static const TypeInfo mps2_info = {
 371     .name = TYPE_MPS2_MACHINE,
 372     .parent = TYPE_MACHINE,
 373     .abstract = true,
 374     .instance_size = sizeof(MPS2MachineState),
 375     .class_size = sizeof(MPS2MachineClass),
 376     .class_init = mps2_class_init,
 377 };
 378
 379 static const TypeInfo mps2_an385_info = {
 380     .name = TYPE_MPS2_AN385_MACHINE,
 381     .parent = TYPE_MPS2_MACHINE,
 382     .class_init = mps2_an385_class_init,
 383 };
 384
 385 static const TypeInfo mps2_an511_info = {
 386     .name = TYPE_MPS2_AN511_MACHINE,
 387     .parent = TYPE_MPS2_MACHINE,
 388     .class_init = mps2_an511_class_init,
 389 };
 390
 391 static void mps2_machine_init(void)
 392 {
 393     type_register_static(&mps2_info);
 394     type_register_static(&mps2_an385_info);
 395     type_register_static(&mps2_an511_info);
 396 }
 397
 398 type_init(mps2_machine_init);