4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/osdep.h"
27 #include "qemu-common.h"
28 #define NO_CPU_IO_DEFS
31 #include "disas/disas.h"
33 #if defined(CONFIG_USER_ONLY)
35 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
36 #include <sys/param.h>
37 #if __FreeBSD_version >= 700104
38 #define HAVE_KINFO_GETVMMAP
39 #define sigqueue sigqueue_freebsd /* avoid redefinition */
41 #include <machine/profile.h>
50 #include "exec/address-spaces.h"
53 #include "exec/cputlb.h"
54 #include "exec/tb-hash.h"
55 #include "translate-all.h"
56 #include "qemu/bitmap.h"
57 #include "qemu/timer.h"
60 //#define DEBUG_TB_INVALIDATE
62 /* make various TB consistency checks */
63 //#define DEBUG_TB_CHECK
65 #if !defined(CONFIG_USER_ONLY)
66 /* TB consistency checks only implemented for usermode emulation. */
70 #define SMC_BITMAP_USE_THRESHOLD 10
72 typedef struct PageDesc
{
73 /* list of TBs intersecting this ram page */
74 TranslationBlock
*first_tb
;
75 /* in order to optimize self modifying code, we count the number
76 of lookups we do to a given page to use a bitmap */
77 unsigned int code_write_count
;
78 unsigned long *code_bitmap
;
79 #if defined(CONFIG_USER_ONLY)
84 /* In system mode we want L1_MAP to be based on ram offsets,
85 while in user mode we want it to be based on virtual addresses. */
86 #if !defined(CONFIG_USER_ONLY)
87 #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS
88 # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS
90 # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS
93 # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS
96 /* Size of the L2 (and L3, etc) page tables. */
98 #define V_L2_SIZE (1 << V_L2_BITS)
100 /* The bits remaining after N lower levels of page tables. */
101 #define V_L1_BITS_REM \
102 ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % V_L2_BITS)
104 #if V_L1_BITS_REM < 4
105 #define V_L1_BITS (V_L1_BITS_REM + V_L2_BITS)
107 #define V_L1_BITS V_L1_BITS_REM
110 #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS)
112 #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS)
114 uintptr_t qemu_host_page_size
;
115 intptr_t qemu_host_page_mask
;
117 /* The bottom level has pointers to PageDesc */
118 static void *l1_map
[V_L1_SIZE
];
120 /* code generation context */
123 /* translation block context */
124 #ifdef CONFIG_USER_ONLY
125 __thread
int have_tb_lock
;
130 #ifdef CONFIG_USER_ONLY
131 assert(!have_tb_lock
);
132 qemu_mutex_lock(&tcg_ctx
.tb_ctx
.tb_lock
);
139 #ifdef CONFIG_USER_ONLY
140 assert(have_tb_lock
);
142 qemu_mutex_unlock(&tcg_ctx
.tb_ctx
.tb_lock
);
146 void tb_lock_reset(void)
148 #ifdef CONFIG_USER_ONLY
150 qemu_mutex_unlock(&tcg_ctx
.tb_ctx
.tb_lock
);
156 static TranslationBlock
*tb_find_pc(uintptr_t tc_ptr
);
158 void cpu_gen_init(void)
160 tcg_context_init(&tcg_ctx
);
163 /* Encode VAL as a signed leb128 sequence at P.
164 Return P incremented past the encoded value. */
165 static uint8_t *encode_sleb128(uint8_t *p
, target_long val
)
172 more
= !((val
== 0 && (byte
& 0x40) == 0)
173 || (val
== -1 && (byte
& 0x40) != 0));
183 /* Decode a signed leb128 sequence at *PP; increment *PP past the
184 decoded value. Return the decoded value. */
185 static target_long
decode_sleb128(uint8_t **pp
)
193 val
|= (target_ulong
)(byte
& 0x7f) << shift
;
195 } while (byte
& 0x80);
196 if (shift
< TARGET_LONG_BITS
&& (byte
& 0x40)) {
197 val
|= -(target_ulong
)1 << shift
;
204 /* Encode the data collected about the instructions while compiling TB.
205 Place the data at BLOCK, and return the number of bytes consumed.
207 The logical table consisits of TARGET_INSN_START_WORDS target_ulong's,
208 which come from the target's insn_start data, followed by a uintptr_t
209 which comes from the host pc of the end of the code implementing the insn.
211 Each line of the table is encoded as sleb128 deltas from the previous
212 line. The seed for the first line is { tb->pc, 0..., tb->tc_ptr }.
213 That is, the first column is seeded with the guest pc, the last column
214 with the host pc, and the middle columns with zeros. */
216 static int encode_search(TranslationBlock
*tb
, uint8_t *block
)
218 uint8_t *highwater
= tcg_ctx
.code_gen_highwater
;
222 tb
->tc_search
= block
;
224 for (i
= 0, n
= tb
->icount
; i
< n
; ++i
) {
227 for (j
= 0; j
< TARGET_INSN_START_WORDS
; ++j
) {
229 prev
= (j
== 0 ? tb
->pc
: 0);
231 prev
= tcg_ctx
.gen_insn_data
[i
- 1][j
];
233 p
= encode_sleb128(p
, tcg_ctx
.gen_insn_data
[i
][j
] - prev
);
235 prev
= (i
== 0 ? 0 : tcg_ctx
.gen_insn_end_off
[i
- 1]);
236 p
= encode_sleb128(p
, tcg_ctx
.gen_insn_end_off
[i
] - prev
);
238 /* Test for (pending) buffer overflow. The assumption is that any
239 one row beginning below the high water mark cannot overrun
240 the buffer completely. Thus we can test for overflow after
241 encoding a row without having to check during encoding. */
242 if (unlikely(p
> highwater
)) {
250 /* The cpu state corresponding to 'searched_pc' is restored. */
251 static int cpu_restore_state_from_tb(CPUState
*cpu
, TranslationBlock
*tb
,
252 uintptr_t searched_pc
)
254 target_ulong data
[TARGET_INSN_START_WORDS
] = { tb
->pc
};
255 uintptr_t host_pc
= (uintptr_t)tb
->tc_ptr
;
256 CPUArchState
*env
= cpu
->env_ptr
;
257 uint8_t *p
= tb
->tc_search
;
258 int i
, j
, num_insns
= tb
->icount
;
259 #ifdef CONFIG_PROFILER
260 int64_t ti
= profile_getclock();
263 if (searched_pc
< host_pc
) {
267 /* Reconstruct the stored insn data while looking for the point at
268 which the end of the insn exceeds the searched_pc. */
269 for (i
= 0; i
< num_insns
; ++i
) {
270 for (j
= 0; j
< TARGET_INSN_START_WORDS
; ++j
) {
271 data
[j
] += decode_sleb128(&p
);
273 host_pc
+= decode_sleb128(&p
);
274 if (host_pc
> searched_pc
) {
281 if (tb
->cflags
& CF_USE_ICOUNT
) {
283 /* Reset the cycle counter to the start of the block. */
284 cpu
->icount_decr
.u16
.low
+= num_insns
;
285 /* Clear the IO flag. */
288 cpu
->icount_decr
.u16
.low
-= i
;
289 restore_state_to_opc(env
, tb
, data
);
291 #ifdef CONFIG_PROFILER
292 tcg_ctx
.restore_time
+= profile_getclock() - ti
;
293 tcg_ctx
.restore_count
++;
298 bool cpu_restore_state(CPUState
*cpu
, uintptr_t retaddr
)
300 TranslationBlock
*tb
;
302 tb
= tb_find_pc(retaddr
);
304 cpu_restore_state_from_tb(cpu
, tb
, retaddr
);
305 if (tb
->cflags
& CF_NOCACHE
) {
306 /* one-shot translation, invalidate it immediately */
307 cpu
->current_tb
= NULL
;
308 tb_phys_invalidate(tb
, -1);
316 void page_size_init(void)
318 /* NOTE: we can always suppose that qemu_host_page_size >=
320 qemu_real_host_page_size
= getpagesize();
321 qemu_real_host_page_mask
= -(intptr_t)qemu_real_host_page_size
;
322 if (qemu_host_page_size
== 0) {
323 qemu_host_page_size
= qemu_real_host_page_size
;
325 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
326 qemu_host_page_size
= TARGET_PAGE_SIZE
;
328 qemu_host_page_mask
= -(intptr_t)qemu_host_page_size
;
331 static void page_init(void)
334 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
336 #ifdef HAVE_KINFO_GETVMMAP
337 struct kinfo_vmentry
*freep
;
340 freep
= kinfo_getvmmap(getpid(), &cnt
);
343 for (i
= 0; i
< cnt
; i
++) {
344 unsigned long startaddr
, endaddr
;
346 startaddr
= freep
[i
].kve_start
;
347 endaddr
= freep
[i
].kve_end
;
348 if (h2g_valid(startaddr
)) {
349 startaddr
= h2g(startaddr
) & TARGET_PAGE_MASK
;
351 if (h2g_valid(endaddr
)) {
352 endaddr
= h2g(endaddr
);
353 page_set_flags(startaddr
, endaddr
, PAGE_RESERVED
);
355 #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS
357 page_set_flags(startaddr
, endaddr
, PAGE_RESERVED
);
368 last_brk
= (unsigned long)sbrk(0);
370 f
= fopen("/compat/linux/proc/self/maps", "r");
375 unsigned long startaddr
, endaddr
;
378 n
= fscanf(f
, "%lx-%lx %*[^\n]\n", &startaddr
, &endaddr
);
380 if (n
== 2 && h2g_valid(startaddr
)) {
381 startaddr
= h2g(startaddr
) & TARGET_PAGE_MASK
;
383 if (h2g_valid(endaddr
)) {
384 endaddr
= h2g(endaddr
);
388 page_set_flags(startaddr
, endaddr
, PAGE_RESERVED
);
401 * Called with mmap_lock held for user-mode emulation.
403 static PageDesc
*page_find_alloc(tb_page_addr_t index
, int alloc
)
409 /* Level 1. Always allocated. */
410 lp
= l1_map
+ ((index
>> V_L1_SHIFT
) & (V_L1_SIZE
- 1));
413 for (i
= V_L1_SHIFT
/ V_L2_BITS
- 1; i
> 0; i
--) {
414 void **p
= atomic_rcu_read(lp
);
420 p
= g_new0(void *, V_L2_SIZE
);
421 atomic_rcu_set(lp
, p
);
424 lp
= p
+ ((index
>> (i
* V_L2_BITS
)) & (V_L2_SIZE
- 1));
427 pd
= atomic_rcu_read(lp
);
432 pd
= g_new0(PageDesc
, V_L2_SIZE
);
433 atomic_rcu_set(lp
, pd
);
436 return pd
+ (index
& (V_L2_SIZE
- 1));
439 static inline PageDesc
*page_find(tb_page_addr_t index
)
441 return page_find_alloc(index
, 0);
444 #if defined(CONFIG_USER_ONLY)
445 /* Currently it is not recommended to allocate big chunks of data in
446 user mode. It will change when a dedicated libc will be used. */
447 /* ??? 64-bit hosts ought to have no problem mmaping data outside the
448 region in which the guest needs to run. Revisit this. */
449 #define USE_STATIC_CODE_GEN_BUFFER
452 /* Minimum size of the code gen buffer. This number is randomly chosen,
453 but not so small that we can't have a fair number of TB's live. */
454 #define MIN_CODE_GEN_BUFFER_SIZE (1024u * 1024)
456 /* Maximum size of the code gen buffer we'd like to use. Unless otherwise
457 indicated, this is constrained by the range of direct branches on the
458 host cpu, as used by the TCG implementation of goto_tb. */
459 #if defined(__x86_64__)
460 # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024)
461 #elif defined(__sparc__)
462 # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024)
463 #elif defined(__powerpc64__)
464 # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024)
465 #elif defined(__powerpc__)
466 # define MAX_CODE_GEN_BUFFER_SIZE (32u * 1024 * 1024)
467 #elif defined(__aarch64__)
468 # define MAX_CODE_GEN_BUFFER_SIZE (128ul * 1024 * 1024)
469 #elif defined(__arm__)
470 # define MAX_CODE_GEN_BUFFER_SIZE (16u * 1024 * 1024)
471 #elif defined(__s390x__)
472 /* We have a +- 4GB range on the branches; leave some slop. */
473 # define MAX_CODE_GEN_BUFFER_SIZE (3ul * 1024 * 1024 * 1024)
474 #elif defined(__mips__)
475 /* We have a 256MB branch region, but leave room to make sure the
476 main executable is also within that region. */
477 # define MAX_CODE_GEN_BUFFER_SIZE (128ul * 1024 * 1024)
479 # define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
482 #define DEFAULT_CODE_GEN_BUFFER_SIZE_1 (32u * 1024 * 1024)
484 #define DEFAULT_CODE_GEN_BUFFER_SIZE \
485 (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \
486 ? DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE)
488 static inline size_t size_code_gen_buffer(size_t tb_size
)
490 /* Size the buffer. */
492 #ifdef USE_STATIC_CODE_GEN_BUFFER
493 tb_size
= DEFAULT_CODE_GEN_BUFFER_SIZE
;
495 /* ??? Needs adjustments. */
496 /* ??? If we relax the requirement that CONFIG_USER_ONLY use the
497 static buffer, we could size this on RESERVED_VA, on the text
498 segment size of the executable, or continue to use the default. */
499 tb_size
= (unsigned long)(ram_size
/ 4);
502 if (tb_size
< MIN_CODE_GEN_BUFFER_SIZE
) {
503 tb_size
= MIN_CODE_GEN_BUFFER_SIZE
;
505 if (tb_size
> MAX_CODE_GEN_BUFFER_SIZE
) {
506 tb_size
= MAX_CODE_GEN_BUFFER_SIZE
;
512 /* In order to use J and JAL within the code_gen_buffer, we require
513 that the buffer not cross a 256MB boundary. */
514 static inline bool cross_256mb(void *addr
, size_t size
)
516 return ((uintptr_t)addr
^ ((uintptr_t)addr
+ size
)) & ~0x0ffffffful
;
519 /* We weren't able to allocate a buffer without crossing that boundary,
520 so make do with the larger portion of the buffer that doesn't cross.
521 Returns the new base of the buffer, and adjusts code_gen_buffer_size. */
522 static inline void *split_cross_256mb(void *buf1
, size_t size1
)
524 void *buf2
= (void *)(((uintptr_t)buf1
+ size1
) & ~0x0ffffffful
);
525 size_t size2
= buf1
+ size1
- buf2
;
533 tcg_ctx
.code_gen_buffer_size
= size1
;
538 #ifdef USE_STATIC_CODE_GEN_BUFFER
539 static uint8_t static_code_gen_buffer
[DEFAULT_CODE_GEN_BUFFER_SIZE
]
540 __attribute__((aligned(CODE_GEN_ALIGN
)));
543 static inline void do_protect(void *addr
, long size
, int prot
)
546 VirtualProtect(addr
, size
, prot
, &old_protect
);
549 static inline void map_exec(void *addr
, long size
)
551 do_protect(addr
, size
, PAGE_EXECUTE_READWRITE
);
554 static inline void map_none(void *addr
, long size
)
556 do_protect(addr
, size
, PAGE_NOACCESS
);
559 static inline void do_protect(void *addr
, long size
, int prot
)
561 uintptr_t start
, end
;
563 start
= (uintptr_t)addr
;
564 start
&= qemu_real_host_page_mask
;
566 end
= (uintptr_t)addr
+ size
;
567 end
= ROUND_UP(end
, qemu_real_host_page_size
);
569 mprotect((void *)start
, end
- start
, prot
);
572 static inline void map_exec(void *addr
, long size
)
574 do_protect(addr
, size
, PROT_READ
| PROT_WRITE
| PROT_EXEC
);
577 static inline void map_none(void *addr
, long size
)
579 do_protect(addr
, size
, PROT_NONE
);
583 static inline void *alloc_code_gen_buffer(void)
585 void *buf
= static_code_gen_buffer
;
586 size_t full_size
, size
;
588 /* The size of the buffer, rounded down to end on a page boundary. */
589 full_size
= (((uintptr_t)buf
+ sizeof(static_code_gen_buffer
))
590 & qemu_real_host_page_mask
) - (uintptr_t)buf
;
592 /* Reserve a guard page. */
593 size
= full_size
- qemu_real_host_page_size
;
595 /* Honor a command-line option limiting the size of the buffer. */
596 if (size
> tcg_ctx
.code_gen_buffer_size
) {
597 size
= (((uintptr_t)buf
+ tcg_ctx
.code_gen_buffer_size
)
598 & qemu_real_host_page_mask
) - (uintptr_t)buf
;
600 tcg_ctx
.code_gen_buffer_size
= size
;
603 if (cross_256mb(buf
, size
)) {
604 buf
= split_cross_256mb(buf
, size
);
605 size
= tcg_ctx
.code_gen_buffer_size
;
610 map_none(buf
+ size
, qemu_real_host_page_size
);
611 qemu_madvise(buf
, size
, QEMU_MADV_HUGEPAGE
);
615 #elif defined(_WIN32)
616 static inline void *alloc_code_gen_buffer(void)
618 size_t size
= tcg_ctx
.code_gen_buffer_size
;
621 /* Perform the allocation in two steps, so that the guard page
622 is reserved but uncommitted. */
623 buf1
= VirtualAlloc(NULL
, size
+ qemu_real_host_page_size
,
624 MEM_RESERVE
, PAGE_NOACCESS
);
626 buf2
= VirtualAlloc(buf1
, size
, MEM_COMMIT
, PAGE_EXECUTE_READWRITE
);
627 assert(buf1
== buf2
);
633 static inline void *alloc_code_gen_buffer(void)
635 int flags
= MAP_PRIVATE
| MAP_ANONYMOUS
;
637 size_t size
= tcg_ctx
.code_gen_buffer_size
;
640 /* Constrain the position of the buffer based on the host cpu.
641 Note that these addresses are chosen in concert with the
642 addresses assigned in the relevant linker script file. */
643 # if defined(__PIE__) || defined(__PIC__)
644 /* Don't bother setting a preferred location if we're building
645 a position-independent executable. We're more likely to get
646 an address near the main executable if we let the kernel
647 choose the address. */
648 # elif defined(__x86_64__) && defined(MAP_32BIT)
649 /* Force the memory down into low memory with the executable.
650 Leave the choice of exact location with the kernel. */
652 /* Cannot expect to map more than 800MB in low memory. */
653 if (size
> 800u * 1024 * 1024) {
654 tcg_ctx
.code_gen_buffer_size
= size
= 800u * 1024 * 1024;
656 # elif defined(__sparc__)
657 start
= 0x40000000ul
;
658 # elif defined(__s390x__)
659 start
= 0x90000000ul
;
660 # elif defined(__mips__)
661 # if _MIPS_SIM == _ABI64
662 start
= 0x128000000ul
;
664 start
= 0x08000000ul
;
668 buf
= mmap((void *)start
, size
+ qemu_real_host_page_size
,
669 PROT_NONE
, flags
, -1, 0);
670 if (buf
== MAP_FAILED
) {
675 if (cross_256mb(buf
, size
)) {
676 /* Try again, with the original still mapped, to avoid re-acquiring
677 that 256mb crossing. This time don't specify an address. */
679 void *buf2
= mmap(NULL
, size
+ qemu_real_host_page_size
,
680 PROT_NONE
, flags
, -1, 0);
681 switch (buf2
!= MAP_FAILED
) {
683 if (!cross_256mb(buf2
, size
)) {
684 /* Success! Use the new buffer. */
685 munmap(buf
, size
+ qemu_real_host_page_size
);
688 /* Failure. Work with what we had. */
689 munmap(buf2
, size
+ qemu_real_host_page_size
);
692 /* Split the original buffer. Free the smaller half. */
693 buf2
= split_cross_256mb(buf
, size
);
694 size2
= tcg_ctx
.code_gen_buffer_size
;
696 munmap(buf
+ size2
+ qemu_real_host_page_size
, size
- size2
);
698 munmap(buf
, size
- size2
);
707 /* Make the final buffer accessible. The guard page at the end
708 will remain inaccessible with PROT_NONE. */
709 mprotect(buf
, size
, PROT_WRITE
| PROT_READ
| PROT_EXEC
);
711 /* Request large pages for the buffer. */
712 qemu_madvise(buf
, size
, QEMU_MADV_HUGEPAGE
);
716 #endif /* USE_STATIC_CODE_GEN_BUFFER, WIN32, POSIX */
718 static inline void code_gen_alloc(size_t tb_size
)
720 tcg_ctx
.code_gen_buffer_size
= size_code_gen_buffer(tb_size
);
721 tcg_ctx
.code_gen_buffer
= alloc_code_gen_buffer();
722 if (tcg_ctx
.code_gen_buffer
== NULL
) {
723 fprintf(stderr
, "Could not allocate dynamic translator buffer\n");
727 /* Estimate a good size for the number of TBs we can support. We
728 still haven't deducted the prologue from the buffer size here,
729 but that's minimal and won't affect the estimate much. */
730 tcg_ctx
.code_gen_max_blocks
731 = tcg_ctx
.code_gen_buffer_size
/ CODE_GEN_AVG_BLOCK_SIZE
;
732 tcg_ctx
.tb_ctx
.tbs
= g_new(TranslationBlock
, tcg_ctx
.code_gen_max_blocks
);
734 qemu_mutex_init(&tcg_ctx
.tb_ctx
.tb_lock
);
737 /* Must be called before using the QEMU cpus. 'tb_size' is the size
738 (in bytes) allocated to the translation buffer. Zero means default
740 void tcg_exec_init(unsigned long tb_size
)
744 code_gen_alloc(tb_size
);
745 #if defined(CONFIG_SOFTMMU)
746 /* There's no guest base to take into account, so go ahead and
747 initialize the prologue now. */
748 tcg_prologue_init(&tcg_ctx
);
752 bool tcg_enabled(void)
754 return tcg_ctx
.code_gen_buffer
!= NULL
;
757 /* Allocate a new translation block. Flush the translation buffer if
758 too many translation blocks or too much generated code. */
759 static TranslationBlock
*tb_alloc(target_ulong pc
)
761 TranslationBlock
*tb
;
763 if (tcg_ctx
.tb_ctx
.nb_tbs
>= tcg_ctx
.code_gen_max_blocks
) {
766 tb
= &tcg_ctx
.tb_ctx
.tbs
[tcg_ctx
.tb_ctx
.nb_tbs
++];
772 void tb_free(TranslationBlock
*tb
)
774 /* In practice this is mostly used for single use temporary TB
775 Ignore the hard cases and just back up if this TB happens to
776 be the last one generated. */
777 if (tcg_ctx
.tb_ctx
.nb_tbs
> 0 &&
778 tb
== &tcg_ctx
.tb_ctx
.tbs
[tcg_ctx
.tb_ctx
.nb_tbs
- 1]) {
779 tcg_ctx
.code_gen_ptr
= tb
->tc_ptr
;
780 tcg_ctx
.tb_ctx
.nb_tbs
--;
784 static inline void invalidate_page_bitmap(PageDesc
*p
)
786 g_free(p
->code_bitmap
);
787 p
->code_bitmap
= NULL
;
788 p
->code_write_count
= 0;
791 /* Set to NULL all the 'first_tb' fields in all PageDescs. */
792 static void page_flush_tb_1(int level
, void **lp
)
802 for (i
= 0; i
< V_L2_SIZE
; ++i
) {
803 pd
[i
].first_tb
= NULL
;
804 invalidate_page_bitmap(pd
+ i
);
809 for (i
= 0; i
< V_L2_SIZE
; ++i
) {
810 page_flush_tb_1(level
- 1, pp
+ i
);
815 static void page_flush_tb(void)
819 for (i
= 0; i
< V_L1_SIZE
; i
++) {
820 page_flush_tb_1(V_L1_SHIFT
/ V_L2_BITS
- 1, l1_map
+ i
);
824 /* flush all the translation blocks */
825 /* XXX: tb_flush is currently not thread safe */
826 void tb_flush(CPUState
*cpu
)
828 #if defined(DEBUG_FLUSH)
829 printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
830 (unsigned long)(tcg_ctx
.code_gen_ptr
- tcg_ctx
.code_gen_buffer
),
831 tcg_ctx
.tb_ctx
.nb_tbs
, tcg_ctx
.tb_ctx
.nb_tbs
> 0 ?
832 ((unsigned long)(tcg_ctx
.code_gen_ptr
- tcg_ctx
.code_gen_buffer
)) /
833 tcg_ctx
.tb_ctx
.nb_tbs
: 0);
835 if ((unsigned long)(tcg_ctx
.code_gen_ptr
- tcg_ctx
.code_gen_buffer
)
836 > tcg_ctx
.code_gen_buffer_size
) {
837 cpu_abort(cpu
, "Internal error: code buffer overflow\n");
839 tcg_ctx
.tb_ctx
.nb_tbs
= 0;
842 memset(cpu
->tb_jmp_cache
, 0, sizeof(cpu
->tb_jmp_cache
));
845 memset(tcg_ctx
.tb_ctx
.tb_phys_hash
, 0, sizeof(tcg_ctx
.tb_ctx
.tb_phys_hash
));
848 tcg_ctx
.code_gen_ptr
= tcg_ctx
.code_gen_buffer
;
849 /* XXX: flush processor icache at this point if cache flush is
851 tcg_ctx
.tb_ctx
.tb_flush_count
++;
854 #ifdef DEBUG_TB_CHECK
856 static void tb_invalidate_check(target_ulong address
)
858 TranslationBlock
*tb
;
861 address
&= TARGET_PAGE_MASK
;
862 for (i
= 0; i
< CODE_GEN_PHYS_HASH_SIZE
; i
++) {
863 for (tb
= tcg_ctx
.tb_ctx
.tb_phys_hash
[i
]; tb
!= NULL
;
864 tb
= tb
->phys_hash_next
) {
865 if (!(address
+ TARGET_PAGE_SIZE
<= tb
->pc
||
866 address
>= tb
->pc
+ tb
->size
)) {
867 printf("ERROR invalidate: address=" TARGET_FMT_lx
868 " PC=%08lx size=%04x\n",
869 address
, (long)tb
->pc
, tb
->size
);
875 /* verify that all the pages have correct rights for code */
876 static void tb_page_check(void)
878 TranslationBlock
*tb
;
879 int i
, flags1
, flags2
;
881 for (i
= 0; i
< CODE_GEN_PHYS_HASH_SIZE
; i
++) {
882 for (tb
= tcg_ctx
.tb_ctx
.tb_phys_hash
[i
]; tb
!= NULL
;
883 tb
= tb
->phys_hash_next
) {
884 flags1
= page_get_flags(tb
->pc
);
885 flags2
= page_get_flags(tb
->pc
+ tb
->size
- 1);
886 if ((flags1
& PAGE_WRITE
) || (flags2
& PAGE_WRITE
)) {
887 printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
888 (long)tb
->pc
, tb
->size
, flags1
, flags2
);
896 static inline void tb_hash_remove(TranslationBlock
**ptb
, TranslationBlock
*tb
)
898 TranslationBlock
*tb1
;
903 *ptb
= tb1
->phys_hash_next
;
906 ptb
= &tb1
->phys_hash_next
;
910 static inline void tb_page_remove(TranslationBlock
**ptb
, TranslationBlock
*tb
)
912 TranslationBlock
*tb1
;
917 n1
= (uintptr_t)tb1
& 3;
918 tb1
= (TranslationBlock
*)((uintptr_t)tb1
& ~3);
920 *ptb
= tb1
->page_next
[n1
];
923 ptb
= &tb1
->page_next
[n1
];
927 /* remove the TB from a list of TBs jumping to the n-th jump target of the TB */
928 static inline void tb_remove_from_jmp_list(TranslationBlock
*tb
, int n
)
930 TranslationBlock
*tb1
;
934 ptb
= &tb
->jmp_list_next
[n
];
936 /* find tb(n) in circular list */
940 tb1
= (TranslationBlock
*)(ntb
& ~3);
941 if (n1
== n
&& tb1
== tb
) {
945 ptb
= &tb1
->jmp_list_first
;
947 ptb
= &tb1
->jmp_list_next
[n1
];
950 /* now we can suppress tb(n) from the list */
951 *ptb
= tb
->jmp_list_next
[n
];
953 tb
->jmp_list_next
[n
] = (uintptr_t)NULL
;
957 /* reset the jump entry 'n' of a TB so that it is not chained to
959 static inline void tb_reset_jump(TranslationBlock
*tb
, int n
)
961 uintptr_t addr
= (uintptr_t)(tb
->tc_ptr
+ tb
->jmp_reset_offset
[n
]);
962 tb_set_jmp_target(tb
, n
, addr
);
965 /* remove any jumps to the TB */
966 static inline void tb_jmp_unlink(TranslationBlock
*tb
)
968 TranslationBlock
*tb1
;
972 ptb
= &tb
->jmp_list_first
;
976 tb1
= (TranslationBlock
*)(ntb
& ~3);
980 tb_reset_jump(tb1
, n1
);
981 *ptb
= tb1
->jmp_list_next
[n1
];
982 tb1
->jmp_list_next
[n1
] = (uintptr_t)NULL
;
986 /* invalidate one TB */
987 void tb_phys_invalidate(TranslationBlock
*tb
, tb_page_addr_t page_addr
)
992 tb_page_addr_t phys_pc
;
994 /* remove the TB from the hash list */
995 phys_pc
= tb
->page_addr
[0] + (tb
->pc
& ~TARGET_PAGE_MASK
);
996 h
= tb_phys_hash_func(phys_pc
);
997 tb_hash_remove(&tcg_ctx
.tb_ctx
.tb_phys_hash
[h
], tb
);
999 /* remove the TB from the page list */
1000 if (tb
->page_addr
[0] != page_addr
) {
1001 p
= page_find(tb
->page_addr
[0] >> TARGET_PAGE_BITS
);
1002 tb_page_remove(&p
->first_tb
, tb
);
1003 invalidate_page_bitmap(p
);
1005 if (tb
->page_addr
[1] != -1 && tb
->page_addr
[1] != page_addr
) {
1006 p
= page_find(tb
->page_addr
[1] >> TARGET_PAGE_BITS
);
1007 tb_page_remove(&p
->first_tb
, tb
);
1008 invalidate_page_bitmap(p
);
1011 tcg_ctx
.tb_ctx
.tb_invalidated_flag
= 1;
1013 /* remove the TB from the hash list */
1014 h
= tb_jmp_cache_hash_func(tb
->pc
);
1016 if (cpu
->tb_jmp_cache
[h
] == tb
) {
1017 cpu
->tb_jmp_cache
[h
] = NULL
;
1021 /* suppress this TB from the two jump lists */
1022 tb_remove_from_jmp_list(tb
, 0);
1023 tb_remove_from_jmp_list(tb
, 1);
1025 /* suppress any remaining jumps to this TB */
1028 tcg_ctx
.tb_ctx
.tb_phys_invalidate_count
++;
1031 static void build_page_bitmap(PageDesc
*p
)
1033 int n
, tb_start
, tb_end
;
1034 TranslationBlock
*tb
;
1036 p
->code_bitmap
= bitmap_new(TARGET_PAGE_SIZE
);
1039 while (tb
!= NULL
) {
1040 n
= (uintptr_t)tb
& 3;
1041 tb
= (TranslationBlock
*)((uintptr_t)tb
& ~3);
1042 /* NOTE: this is subtle as a TB may span two physical pages */
1044 /* NOTE: tb_end may be after the end of the page, but
1045 it is not a problem */
1046 tb_start
= tb
->pc
& ~TARGET_PAGE_MASK
;
1047 tb_end
= tb_start
+ tb
->size
;
1048 if (tb_end
> TARGET_PAGE_SIZE
) {
1049 tb_end
= TARGET_PAGE_SIZE
;
1053 tb_end
= ((tb
->pc
+ tb
->size
) & ~TARGET_PAGE_MASK
);
1055 bitmap_set(p
->code_bitmap
, tb_start
, tb_end
- tb_start
);
1056 tb
= tb
->page_next
[n
];
1060 /* add the tb in the target page and protect it if necessary
1062 * Called with mmap_lock held for user-mode emulation.
1064 static inline void tb_alloc_page(TranslationBlock
*tb
,
1065 unsigned int n
, tb_page_addr_t page_addr
)
1068 #ifndef CONFIG_USER_ONLY
1069 bool page_already_protected
;
1072 tb
->page_addr
[n
] = page_addr
;
1073 p
= page_find_alloc(page_addr
>> TARGET_PAGE_BITS
, 1);
1074 tb
->page_next
[n
] = p
->first_tb
;
1075 #ifndef CONFIG_USER_ONLY
1076 page_already_protected
= p
->first_tb
!= NULL
;
1078 p
->first_tb
= (TranslationBlock
*)((uintptr_t)tb
| n
);
1079 invalidate_page_bitmap(p
);
1081 #if defined(CONFIG_USER_ONLY)
1082 if (p
->flags
& PAGE_WRITE
) {
1087 /* force the host page as non writable (writes will have a
1088 page fault + mprotect overhead) */
1089 page_addr
&= qemu_host_page_mask
;
1091 for (addr
= page_addr
; addr
< page_addr
+ qemu_host_page_size
;
1092 addr
+= TARGET_PAGE_SIZE
) {
1094 p2
= page_find(addr
>> TARGET_PAGE_BITS
);
1099 p2
->flags
&= ~PAGE_WRITE
;
1101 mprotect(g2h(page_addr
), qemu_host_page_size
,
1102 (prot
& PAGE_BITS
) & ~PAGE_WRITE
);
1103 #ifdef DEBUG_TB_INVALIDATE
1104 printf("protecting code page: 0x" TARGET_FMT_lx
"\n",
1109 /* if some code is already present, then the pages are already
1110 protected. So we handle the case where only the first TB is
1111 allocated in a physical page */
1112 if (!page_already_protected
) {
1113 tlb_protect_code(page_addr
);
1118 /* add a new TB and link it to the physical page tables. phys_page2 is
1119 * (-1) to indicate that only one page contains the TB.
1121 * Called with mmap_lock held for user-mode emulation.
1123 static void tb_link_page(TranslationBlock
*tb
, tb_page_addr_t phys_pc
,
1124 tb_page_addr_t phys_page2
)
1127 TranslationBlock
**ptb
;
1129 /* add in the physical hash table */
1130 h
= tb_phys_hash_func(phys_pc
);
1131 ptb
= &tcg_ctx
.tb_ctx
.tb_phys_hash
[h
];
1132 tb
->phys_hash_next
= *ptb
;
1135 /* add in the page list */
1136 tb_alloc_page(tb
, 0, phys_pc
& TARGET_PAGE_MASK
);
1137 if (phys_page2
!= -1) {
1138 tb_alloc_page(tb
, 1, phys_page2
);
1140 tb
->page_addr
[1] = -1;
1143 #ifdef DEBUG_TB_CHECK
1148 /* Called with mmap_lock held for user mode emulation. */
1149 TranslationBlock
*tb_gen_code(CPUState
*cpu
,
1150 target_ulong pc
, target_ulong cs_base
,
1151 uint32_t flags
, int cflags
)
1153 CPUArchState
*env
= cpu
->env_ptr
;
1154 TranslationBlock
*tb
;
1155 tb_page_addr_t phys_pc
, phys_page2
;
1156 target_ulong virt_page2
;
1157 tcg_insn_unit
*gen_code_buf
;
1158 int gen_code_size
, search_size
;
1159 #ifdef CONFIG_PROFILER
1163 phys_pc
= get_page_addr_code(env
, pc
);
1164 if (use_icount
&& !(cflags
& CF_IGNORE_ICOUNT
)) {
1165 cflags
|= CF_USE_ICOUNT
;
1169 if (unlikely(!tb
)) {
1171 /* flush must be done */
1173 /* cannot fail at this point */
1176 /* Don't forget to invalidate previous TB info. */
1177 tcg_ctx
.tb_ctx
.tb_invalidated_flag
= 1;
1180 gen_code_buf
= tcg_ctx
.code_gen_ptr
;
1181 tb
->tc_ptr
= gen_code_buf
;
1182 tb
->cs_base
= cs_base
;
1184 tb
->cflags
= cflags
;
1186 #ifdef CONFIG_PROFILER
1187 tcg_ctx
.tb_count1
++; /* includes aborted translations because of
1189 ti
= profile_getclock();
1192 tcg_func_start(&tcg_ctx
);
1194 gen_intermediate_code(env
, tb
);
1196 trace_translate_block(tb
, tb
->pc
, tb
->tc_ptr
);
1198 /* generate machine code */
1199 tb
->jmp_reset_offset
[0] = TB_JMP_RESET_OFFSET_INVALID
;
1200 tb
->jmp_reset_offset
[1] = TB_JMP_RESET_OFFSET_INVALID
;
1201 tcg_ctx
.tb_jmp_reset_offset
= tb
->jmp_reset_offset
;
1202 #ifdef USE_DIRECT_JUMP
1203 tcg_ctx
.tb_jmp_insn_offset
= tb
->jmp_insn_offset
;
1204 tcg_ctx
.tb_jmp_target_addr
= NULL
;
1206 tcg_ctx
.tb_jmp_insn_offset
= NULL
;
1207 tcg_ctx
.tb_jmp_target_addr
= tb
->jmp_target_addr
;
1210 #ifdef CONFIG_PROFILER
1212 tcg_ctx
.interm_time
+= profile_getclock() - ti
;
1213 tcg_ctx
.code_time
-= profile_getclock();
1216 /* ??? Overflow could be handled better here. In particular, we
1217 don't need to re-do gen_intermediate_code, nor should we re-do
1218 the tcg optimization currently hidden inside tcg_gen_code. All
1219 that should be required is to flush the TBs, allocate a new TB,
1220 re-initialize it per above, and re-do the actual code generation. */
1221 gen_code_size
= tcg_gen_code(&tcg_ctx
, tb
);
1222 if (unlikely(gen_code_size
< 0)) {
1223 goto buffer_overflow
;
1225 search_size
= encode_search(tb
, (void *)gen_code_buf
+ gen_code_size
);
1226 if (unlikely(search_size
< 0)) {
1227 goto buffer_overflow
;
1230 #ifdef CONFIG_PROFILER
1231 tcg_ctx
.code_time
+= profile_getclock();
1232 tcg_ctx
.code_in_len
+= tb
->size
;
1233 tcg_ctx
.code_out_len
+= gen_code_size
;
1234 tcg_ctx
.search_out_len
+= search_size
;
1238 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM
) &&
1239 qemu_log_in_addr_range(tb
->pc
)) {
1240 qemu_log("OUT: [size=%d]\n", gen_code_size
);
1241 log_disas(tb
->tc_ptr
, gen_code_size
);
1247 tcg_ctx
.code_gen_ptr
= (void *)
1248 ROUND_UP((uintptr_t)gen_code_buf
+ gen_code_size
+ search_size
,
1251 /* init jump list */
1252 assert(((uintptr_t)tb
& 3) == 0);
1253 tb
->jmp_list_first
= (uintptr_t)tb
| 2;
1254 tb
->jmp_list_next
[0] = (uintptr_t)NULL
;
1255 tb
->jmp_list_next
[1] = (uintptr_t)NULL
;
1257 /* init original jump addresses wich has been set during tcg_gen_code() */
1258 if (tb
->jmp_reset_offset
[0] != TB_JMP_RESET_OFFSET_INVALID
) {
1259 tb_reset_jump(tb
, 0);
1261 if (tb
->jmp_reset_offset
[1] != TB_JMP_RESET_OFFSET_INVALID
) {
1262 tb_reset_jump(tb
, 1);
1265 /* check next page if needed */
1266 virt_page2
= (pc
+ tb
->size
- 1) & TARGET_PAGE_MASK
;
1268 if ((pc
& TARGET_PAGE_MASK
) != virt_page2
) {
1269 phys_page2
= get_page_addr_code(env
, virt_page2
);
1271 /* As long as consistency of the TB stuff is provided by tb_lock in user
1272 * mode and is implicit in single-threaded softmmu emulation, no explicit
1273 * memory barrier is required before tb_link_page() makes the TB visible
1274 * through the physical hash table and physical page list.
1276 tb_link_page(tb
, phys_pc
, phys_page2
);
1281 * Invalidate all TBs which intersect with the target physical address range
1282 * [start;end[. NOTE: start and end may refer to *different* physical pages.
1283 * 'is_cpu_write_access' should be true if called from a real cpu write
1284 * access: the virtual CPU will exit the current TB if code is modified inside
1287 * Called with mmap_lock held for user-mode emulation
1289 void tb_invalidate_phys_range(tb_page_addr_t start
, tb_page_addr_t end
)
1291 while (start
< end
) {
1292 tb_invalidate_phys_page_range(start
, end
, 0);
1293 start
&= TARGET_PAGE_MASK
;
1294 start
+= TARGET_PAGE_SIZE
;
1299 * Invalidate all TBs which intersect with the target physical address range
1300 * [start;end[. NOTE: start and end must refer to the *same* physical page.
1301 * 'is_cpu_write_access' should be true if called from a real cpu write
1302 * access: the virtual CPU will exit the current TB if code is modified inside
1305 * Called with mmap_lock held for user-mode emulation
1307 void tb_invalidate_phys_page_range(tb_page_addr_t start
, tb_page_addr_t end
,
1308 int is_cpu_write_access
)
1310 TranslationBlock
*tb
, *tb_next
, *saved_tb
;
1311 CPUState
*cpu
= current_cpu
;
1312 #if defined(TARGET_HAS_PRECISE_SMC)
1313 CPUArchState
*env
= NULL
;
1315 tb_page_addr_t tb_start
, tb_end
;
1318 #ifdef TARGET_HAS_PRECISE_SMC
1319 int current_tb_not_found
= is_cpu_write_access
;
1320 TranslationBlock
*current_tb
= NULL
;
1321 int current_tb_modified
= 0;
1322 target_ulong current_pc
= 0;
1323 target_ulong current_cs_base
= 0;
1324 uint32_t current_flags
= 0;
1325 #endif /* TARGET_HAS_PRECISE_SMC */
1327 p
= page_find(start
>> TARGET_PAGE_BITS
);
1331 #if defined(TARGET_HAS_PRECISE_SMC)
1337 /* we remove all the TBs in the range [start, end[ */
1338 /* XXX: see if in some cases it could be faster to invalidate all
1341 while (tb
!= NULL
) {
1342 n
= (uintptr_t)tb
& 3;
1343 tb
= (TranslationBlock
*)((uintptr_t)tb
& ~3);
1344 tb_next
= tb
->page_next
[n
];
1345 /* NOTE: this is subtle as a TB may span two physical pages */
1347 /* NOTE: tb_end may be after the end of the page, but
1348 it is not a problem */
1349 tb_start
= tb
->page_addr
[0] + (tb
->pc
& ~TARGET_PAGE_MASK
);
1350 tb_end
= tb_start
+ tb
->size
;
1352 tb_start
= tb
->page_addr
[1];
1353 tb_end
= tb_start
+ ((tb
->pc
+ tb
->size
) & ~TARGET_PAGE_MASK
);
1355 if (!(tb_end
<= start
|| tb_start
>= end
)) {
1356 #ifdef TARGET_HAS_PRECISE_SMC
1357 if (current_tb_not_found
) {
1358 current_tb_not_found
= 0;
1360 if (cpu
->mem_io_pc
) {
1361 /* now we have a real cpu fault */
1362 current_tb
= tb_find_pc(cpu
->mem_io_pc
);
1365 if (current_tb
== tb
&&
1366 (current_tb
->cflags
& CF_COUNT_MASK
) != 1) {
1367 /* If we are modifying the current TB, we must stop
1368 its execution. We could be more precise by checking
1369 that the modification is after the current PC, but it
1370 would require a specialized function to partially
1371 restore the CPU state */
1373 current_tb_modified
= 1;
1374 cpu_restore_state_from_tb(cpu
, current_tb
, cpu
->mem_io_pc
);
1375 cpu_get_tb_cpu_state(env
, ¤t_pc
, ¤t_cs_base
,
1378 #endif /* TARGET_HAS_PRECISE_SMC */
1379 /* we need to do that to handle the case where a signal
1380 occurs while doing tb_phys_invalidate() */
1383 saved_tb
= cpu
->current_tb
;
1384 cpu
->current_tb
= NULL
;
1386 tb_phys_invalidate(tb
, -1);
1388 cpu
->current_tb
= saved_tb
;
1389 if (cpu
->interrupt_request
&& cpu
->current_tb
) {
1390 cpu_interrupt(cpu
, cpu
->interrupt_request
);
1396 #if !defined(CONFIG_USER_ONLY)
1397 /* if no code remaining, no need to continue to use slow writes */
1399 invalidate_page_bitmap(p
);
1400 tlb_unprotect_code(start
);
1403 #ifdef TARGET_HAS_PRECISE_SMC
1404 if (current_tb_modified
) {
1405 /* we generate a block containing just the instruction
1406 modifying the memory. It will ensure that it cannot modify
1408 cpu
->current_tb
= NULL
;
1409 tb_gen_code(cpu
, current_pc
, current_cs_base
, current_flags
, 1);
1410 cpu_resume_from_signal(cpu
, NULL
);
1415 /* len must be <= 8 and start must be a multiple of len */
1416 void tb_invalidate_phys_page_fast(tb_page_addr_t start
, int len
)
1422 qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
1423 cpu_single_env
->mem_io_vaddr
, len
,
1424 cpu_single_env
->eip
,
1425 cpu_single_env
->eip
+
1426 (intptr_t)cpu_single_env
->segs
[R_CS
].base
);
1429 p
= page_find(start
>> TARGET_PAGE_BITS
);
1433 if (!p
->code_bitmap
&&
1434 ++p
->code_write_count
>= SMC_BITMAP_USE_THRESHOLD
) {
1435 /* build code bitmap */
1436 build_page_bitmap(p
);
1438 if (p
->code_bitmap
) {
1442 nr
= start
& ~TARGET_PAGE_MASK
;
1443 b
= p
->code_bitmap
[BIT_WORD(nr
)] >> (nr
& (BITS_PER_LONG
- 1));
1444 if (b
& ((1 << len
) - 1)) {
1449 tb_invalidate_phys_page_range(start
, start
+ len
, 1);
1453 #if !defined(CONFIG_SOFTMMU)
1454 /* Called with mmap_lock held. */
1455 static void tb_invalidate_phys_page(tb_page_addr_t addr
,
1456 uintptr_t pc
, void *puc
,
1459 TranslationBlock
*tb
;
1462 #ifdef TARGET_HAS_PRECISE_SMC
1463 TranslationBlock
*current_tb
= NULL
;
1464 CPUState
*cpu
= current_cpu
;
1465 CPUArchState
*env
= NULL
;
1466 int current_tb_modified
= 0;
1467 target_ulong current_pc
= 0;
1468 target_ulong current_cs_base
= 0;
1469 uint32_t current_flags
= 0;
1472 addr
&= TARGET_PAGE_MASK
;
1473 p
= page_find(addr
>> TARGET_PAGE_BITS
);
1478 #ifdef TARGET_HAS_PRECISE_SMC
1479 if (tb
&& pc
!= 0) {
1480 current_tb
= tb_find_pc(pc
);
1486 while (tb
!= NULL
) {
1487 n
= (uintptr_t)tb
& 3;
1488 tb
= (TranslationBlock
*)((uintptr_t)tb
& ~3);
1489 #ifdef TARGET_HAS_PRECISE_SMC
1490 if (current_tb
== tb
&&
1491 (current_tb
->cflags
& CF_COUNT_MASK
) != 1) {
1492 /* If we are modifying the current TB, we must stop
1493 its execution. We could be more precise by checking
1494 that the modification is after the current PC, but it
1495 would require a specialized function to partially
1496 restore the CPU state */
1498 current_tb_modified
= 1;
1499 cpu_restore_state_from_tb(cpu
, current_tb
, pc
);
1500 cpu_get_tb_cpu_state(env
, ¤t_pc
, ¤t_cs_base
,
1503 #endif /* TARGET_HAS_PRECISE_SMC */
1504 tb_phys_invalidate(tb
, addr
);
1505 tb
= tb
->page_next
[n
];
1508 #ifdef TARGET_HAS_PRECISE_SMC
1509 if (current_tb_modified
) {
1510 /* we generate a block containing just the instruction
1511 modifying the memory. It will ensure that it cannot modify
1513 cpu
->current_tb
= NULL
;
1514 tb_gen_code(cpu
, current_pc
, current_cs_base
, current_flags
, 1);
1518 cpu_resume_from_signal(cpu
, puc
);
1524 /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
1525 tb[1].tc_ptr. Return NULL if not found */
1526 static TranslationBlock
*tb_find_pc(uintptr_t tc_ptr
)
1528 int m_min
, m_max
, m
;
1530 TranslationBlock
*tb
;
1532 if (tcg_ctx
.tb_ctx
.nb_tbs
<= 0) {
1535 if (tc_ptr
< (uintptr_t)tcg_ctx
.code_gen_buffer
||
1536 tc_ptr
>= (uintptr_t)tcg_ctx
.code_gen_ptr
) {
1539 /* binary search (cf Knuth) */
1541 m_max
= tcg_ctx
.tb_ctx
.nb_tbs
- 1;
1542 while (m_min
<= m_max
) {
1543 m
= (m_min
+ m_max
) >> 1;
1544 tb
= &tcg_ctx
.tb_ctx
.tbs
[m
];
1545 v
= (uintptr_t)tb
->tc_ptr
;
1548 } else if (tc_ptr
< v
) {
1554 return &tcg_ctx
.tb_ctx
.tbs
[m_max
];
1557 #if !defined(CONFIG_USER_ONLY)
1558 void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
)
1560 ram_addr_t ram_addr
;
1565 mr
= address_space_translate(as
, addr
, &addr
, &l
, false);
1566 if (!(memory_region_is_ram(mr
)
1567 || memory_region_is_romd(mr
))) {
1571 ram_addr
= (memory_region_get_ram_addr(mr
) & TARGET_PAGE_MASK
)
1573 tb_invalidate_phys_page_range(ram_addr
, ram_addr
+ 1, 0);
1576 #endif /* !defined(CONFIG_USER_ONLY) */
1578 void tb_check_watchpoint(CPUState
*cpu
)
1580 TranslationBlock
*tb
;
1582 tb
= tb_find_pc(cpu
->mem_io_pc
);
1584 /* We can use retranslation to find the PC. */
1585 cpu_restore_state_from_tb(cpu
, tb
, cpu
->mem_io_pc
);
1586 tb_phys_invalidate(tb
, -1);
1588 /* The exception probably happened in a helper. The CPU state should
1589 have been saved before calling it. Fetch the PC from there. */
1590 CPUArchState
*env
= cpu
->env_ptr
;
1591 target_ulong pc
, cs_base
;
1592 tb_page_addr_t addr
;
1595 cpu_get_tb_cpu_state(env
, &pc
, &cs_base
, &flags
);
1596 addr
= get_page_addr_code(env
, pc
);
1597 tb_invalidate_phys_range(addr
, addr
+ 1);
1601 #ifndef CONFIG_USER_ONLY
1602 /* in deterministic execution mode, instructions doing device I/Os
1603 must be at the end of the TB */
1604 void cpu_io_recompile(CPUState
*cpu
, uintptr_t retaddr
)
1606 #if defined(TARGET_MIPS) || defined(TARGET_SH4)
1607 CPUArchState
*env
= cpu
->env_ptr
;
1609 TranslationBlock
*tb
;
1611 target_ulong pc
, cs_base
;
1614 tb
= tb_find_pc(retaddr
);
1616 cpu_abort(cpu
, "cpu_io_recompile: could not find TB for pc=%p",
1619 n
= cpu
->icount_decr
.u16
.low
+ tb
->icount
;
1620 cpu_restore_state_from_tb(cpu
, tb
, retaddr
);
1621 /* Calculate how many instructions had been executed before the fault
1623 n
= n
- cpu
->icount_decr
.u16
.low
;
1624 /* Generate a new TB ending on the I/O insn. */
1626 /* On MIPS and SH, delay slot instructions can only be restarted if
1627 they were already the first instruction in the TB. If this is not
1628 the first instruction in a TB then re-execute the preceding
1630 #if defined(TARGET_MIPS)
1631 if ((env
->hflags
& MIPS_HFLAG_BMASK
) != 0 && n
> 1) {
1632 env
->active_tc
.PC
-= (env
->hflags
& MIPS_HFLAG_B16
? 2 : 4);
1633 cpu
->icount_decr
.u16
.low
++;
1634 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
1636 #elif defined(TARGET_SH4)
1637 if ((env
->flags
& ((DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
))) != 0
1640 cpu
->icount_decr
.u16
.low
++;
1641 env
->flags
&= ~(DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
);
1644 /* This should never happen. */
1645 if (n
> CF_COUNT_MASK
) {
1646 cpu_abort(cpu
, "TB too big during recompile");
1649 cflags
= n
| CF_LAST_IO
;
1651 cs_base
= tb
->cs_base
;
1653 tb_phys_invalidate(tb
, -1);
1654 if (tb
->cflags
& CF_NOCACHE
) {
1656 /* Invalidate original TB if this TB was generated in
1657 * cpu_exec_nocache() */
1658 tb_phys_invalidate(tb
->orig_tb
, -1);
1662 /* FIXME: In theory this could raise an exception. In practice
1663 we have already translated the block once so it's probably ok. */
1664 tb_gen_code(cpu
, pc
, cs_base
, flags
, cflags
);
1665 /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
1666 the first in the TB) then we end up generating a whole new TB and
1667 repeating the fault, which is horribly inefficient.
1668 Better would be to execute just this insn uncached, or generate a
1670 cpu_resume_from_signal(cpu
, NULL
);
1673 void tb_flush_jmp_cache(CPUState
*cpu
, target_ulong addr
)
1677 /* Discard jump cache entries for any tb which might potentially
1678 overlap the flushed page. */
1679 i
= tb_jmp_cache_hash_page(addr
- TARGET_PAGE_SIZE
);
1680 memset(&cpu
->tb_jmp_cache
[i
], 0,
1681 TB_JMP_PAGE_SIZE
* sizeof(TranslationBlock
*));
1683 i
= tb_jmp_cache_hash_page(addr
);
1684 memset(&cpu
->tb_jmp_cache
[i
], 0,
1685 TB_JMP_PAGE_SIZE
* sizeof(TranslationBlock
*));
1688 void dump_exec_info(FILE *f
, fprintf_function cpu_fprintf
)
1690 int i
, target_code_size
, max_target_code_size
;
1691 int direct_jmp_count
, direct_jmp2_count
, cross_page
;
1692 TranslationBlock
*tb
;
1694 target_code_size
= 0;
1695 max_target_code_size
= 0;
1697 direct_jmp_count
= 0;
1698 direct_jmp2_count
= 0;
1699 for (i
= 0; i
< tcg_ctx
.tb_ctx
.nb_tbs
; i
++) {
1700 tb
= &tcg_ctx
.tb_ctx
.tbs
[i
];
1701 target_code_size
+= tb
->size
;
1702 if (tb
->size
> max_target_code_size
) {
1703 max_target_code_size
= tb
->size
;
1705 if (tb
->page_addr
[1] != -1) {
1708 if (tb
->jmp_reset_offset
[0] != TB_JMP_RESET_OFFSET_INVALID
) {
1710 if (tb
->jmp_reset_offset
[1] != TB_JMP_RESET_OFFSET_INVALID
) {
1711 direct_jmp2_count
++;
1715 /* XXX: avoid using doubles ? */
1716 cpu_fprintf(f
, "Translation buffer state:\n");
1717 cpu_fprintf(f
, "gen code size %td/%zd\n",
1718 tcg_ctx
.code_gen_ptr
- tcg_ctx
.code_gen_buffer
,
1719 tcg_ctx
.code_gen_highwater
- tcg_ctx
.code_gen_buffer
);
1720 cpu_fprintf(f
, "TB count %d/%d\n",
1721 tcg_ctx
.tb_ctx
.nb_tbs
, tcg_ctx
.code_gen_max_blocks
);
1722 cpu_fprintf(f
, "TB avg target size %d max=%d bytes\n",
1723 tcg_ctx
.tb_ctx
.nb_tbs
? target_code_size
/
1724 tcg_ctx
.tb_ctx
.nb_tbs
: 0,
1725 max_target_code_size
);
1726 cpu_fprintf(f
, "TB avg host size %td bytes (expansion ratio: %0.1f)\n",
1727 tcg_ctx
.tb_ctx
.nb_tbs
? (tcg_ctx
.code_gen_ptr
-
1728 tcg_ctx
.code_gen_buffer
) /
1729 tcg_ctx
.tb_ctx
.nb_tbs
: 0,
1730 target_code_size
? (double) (tcg_ctx
.code_gen_ptr
-
1731 tcg_ctx
.code_gen_buffer
) /
1732 target_code_size
: 0);
1733 cpu_fprintf(f
, "cross page TB count %d (%d%%)\n", cross_page
,
1734 tcg_ctx
.tb_ctx
.nb_tbs
? (cross_page
* 100) /
1735 tcg_ctx
.tb_ctx
.nb_tbs
: 0);
1736 cpu_fprintf(f
, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
1738 tcg_ctx
.tb_ctx
.nb_tbs
? (direct_jmp_count
* 100) /
1739 tcg_ctx
.tb_ctx
.nb_tbs
: 0,
1741 tcg_ctx
.tb_ctx
.nb_tbs
? (direct_jmp2_count
* 100) /
1742 tcg_ctx
.tb_ctx
.nb_tbs
: 0);
1743 cpu_fprintf(f
, "\nStatistics:\n");
1744 cpu_fprintf(f
, "TB flush count %d\n", tcg_ctx
.tb_ctx
.tb_flush_count
);
1745 cpu_fprintf(f
, "TB invalidate count %d\n",
1746 tcg_ctx
.tb_ctx
.tb_phys_invalidate_count
);
1747 cpu_fprintf(f
, "TLB flush count %d\n", tlb_flush_count
);
1748 tcg_dump_info(f
, cpu_fprintf
);
1751 void dump_opcount_info(FILE *f
, fprintf_function cpu_fprintf
)
1753 tcg_dump_op_count(f
, cpu_fprintf
);
1756 #else /* CONFIG_USER_ONLY */
1758 void cpu_interrupt(CPUState
*cpu
, int mask
)
1760 cpu
->interrupt_request
|= mask
;
1761 cpu
->tcg_exit_req
= 1;
1765 * Walks guest process memory "regions" one by one
1766 * and calls callback function 'fn' for each region.
1768 struct walk_memory_regions_data
{
1769 walk_memory_regions_fn fn
;
1775 static int walk_memory_regions_end(struct walk_memory_regions_data
*data
,
1776 target_ulong end
, int new_prot
)
1778 if (data
->start
!= -1u) {
1779 int rc
= data
->fn(data
->priv
, data
->start
, end
, data
->prot
);
1785 data
->start
= (new_prot
? end
: -1u);
1786 data
->prot
= new_prot
;
1791 static int walk_memory_regions_1(struct walk_memory_regions_data
*data
,
1792 target_ulong base
, int level
, void **lp
)
1798 return walk_memory_regions_end(data
, base
, 0);
1804 for (i
= 0; i
< V_L2_SIZE
; ++i
) {
1805 int prot
= pd
[i
].flags
;
1807 pa
= base
| (i
<< TARGET_PAGE_BITS
);
1808 if (prot
!= data
->prot
) {
1809 rc
= walk_memory_regions_end(data
, pa
, prot
);
1818 for (i
= 0; i
< V_L2_SIZE
; ++i
) {
1819 pa
= base
| ((target_ulong
)i
<<
1820 (TARGET_PAGE_BITS
+ V_L2_BITS
* level
));
1821 rc
= walk_memory_regions_1(data
, pa
, level
- 1, pp
+ i
);
1831 int walk_memory_regions(void *priv
, walk_memory_regions_fn fn
)
1833 struct walk_memory_regions_data data
;
1841 for (i
= 0; i
< V_L1_SIZE
; i
++) {
1842 int rc
= walk_memory_regions_1(&data
, (target_ulong
)i
<< (V_L1_SHIFT
+ TARGET_PAGE_BITS
),
1843 V_L1_SHIFT
/ V_L2_BITS
- 1, l1_map
+ i
);
1849 return walk_memory_regions_end(&data
, 0, 0);
1852 static int dump_region(void *priv
, target_ulong start
,
1853 target_ulong end
, unsigned long prot
)
1855 FILE *f
= (FILE *)priv
;
1857 (void) fprintf(f
, TARGET_FMT_lx
"-"TARGET_FMT_lx
1858 " "TARGET_FMT_lx
" %c%c%c\n",
1859 start
, end
, end
- start
,
1860 ((prot
& PAGE_READ
) ? 'r' : '-'),
1861 ((prot
& PAGE_WRITE
) ? 'w' : '-'),
1862 ((prot
& PAGE_EXEC
) ? 'x' : '-'));
1867 /* dump memory mappings */
1868 void page_dump(FILE *f
)
1870 const int length
= sizeof(target_ulong
) * 2;
1871 (void) fprintf(f
, "%-*s %-*s %-*s %s\n",
1872 length
, "start", length
, "end", length
, "size", "prot");
1873 walk_memory_regions(f
, dump_region
);
1876 int page_get_flags(target_ulong address
)
1880 p
= page_find(address
>> TARGET_PAGE_BITS
);
1887 /* Modify the flags of a page and invalidate the code if necessary.
1888 The flag PAGE_WRITE_ORG is positioned automatically depending
1889 on PAGE_WRITE. The mmap_lock should already be held. */
1890 void page_set_flags(target_ulong start
, target_ulong end
, int flags
)
1892 target_ulong addr
, len
;
1894 /* This function should never be called with addresses outside the
1895 guest address space. If this assert fires, it probably indicates
1896 a missing call to h2g_valid. */
1897 #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS
1898 assert(end
< ((target_ulong
)1 << L1_MAP_ADDR_SPACE_BITS
));
1900 assert(start
< end
);
1902 start
= start
& TARGET_PAGE_MASK
;
1903 end
= TARGET_PAGE_ALIGN(end
);
1905 if (flags
& PAGE_WRITE
) {
1906 flags
|= PAGE_WRITE_ORG
;
1909 for (addr
= start
, len
= end
- start
;
1911 len
-= TARGET_PAGE_SIZE
, addr
+= TARGET_PAGE_SIZE
) {
1912 PageDesc
*p
= page_find_alloc(addr
>> TARGET_PAGE_BITS
, 1);
1914 /* If the write protection bit is set, then we invalidate
1916 if (!(p
->flags
& PAGE_WRITE
) &&
1917 (flags
& PAGE_WRITE
) &&
1919 tb_invalidate_phys_page(addr
, 0, NULL
, false);
1925 int page_check_range(target_ulong start
, target_ulong len
, int flags
)
1931 /* This function should never be called with addresses outside the
1932 guest address space. If this assert fires, it probably indicates
1933 a missing call to h2g_valid. */
1934 #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS
1935 assert(start
< ((target_ulong
)1 << L1_MAP_ADDR_SPACE_BITS
));
1941 if (start
+ len
- 1 < start
) {
1942 /* We've wrapped around. */
1946 /* must do before we loose bits in the next step */
1947 end
= TARGET_PAGE_ALIGN(start
+ len
);
1948 start
= start
& TARGET_PAGE_MASK
;
1950 for (addr
= start
, len
= end
- start
;
1952 len
-= TARGET_PAGE_SIZE
, addr
+= TARGET_PAGE_SIZE
) {
1953 p
= page_find(addr
>> TARGET_PAGE_BITS
);
1957 if (!(p
->flags
& PAGE_VALID
)) {
1961 if ((flags
& PAGE_READ
) && !(p
->flags
& PAGE_READ
)) {
1964 if (flags
& PAGE_WRITE
) {
1965 if (!(p
->flags
& PAGE_WRITE_ORG
)) {
1968 /* unprotect the page if it was put read-only because it
1969 contains translated code */
1970 if (!(p
->flags
& PAGE_WRITE
)) {
1971 if (!page_unprotect(addr
, 0, NULL
)) {
1980 /* called from signal handler: invalidate the code and unprotect the
1981 page. Return TRUE if the fault was successfully handled. */
1982 int page_unprotect(target_ulong address
, uintptr_t pc
, void *puc
)
1986 target_ulong host_start
, host_end
, addr
;
1988 /* Technically this isn't safe inside a signal handler. However we
1989 know this only ever happens in a synchronous SEGV handler, so in
1990 practice it seems to be ok. */
1993 p
= page_find(address
>> TARGET_PAGE_BITS
);
1999 /* if the page was really writable, then we change its
2000 protection back to writable */
2001 if ((p
->flags
& PAGE_WRITE_ORG
) && !(p
->flags
& PAGE_WRITE
)) {
2002 host_start
= address
& qemu_host_page_mask
;
2003 host_end
= host_start
+ qemu_host_page_size
;
2006 for (addr
= host_start
; addr
< host_end
; addr
+= TARGET_PAGE_SIZE
) {
2007 p
= page_find(addr
>> TARGET_PAGE_BITS
);
2008 p
->flags
|= PAGE_WRITE
;
2011 /* and since the content will be modified, we must invalidate
2012 the corresponding translated code. */
2013 tb_invalidate_phys_page(addr
, pc
, puc
, true);
2014 #ifdef DEBUG_TB_CHECK
2015 tb_invalidate_check(addr
);
2018 mprotect((void *)g2h(host_start
), qemu_host_page_size
,
2027 #endif /* CONFIG_USER_ONLY */