util/cacheinfo.c

   1 /*
   2  * cacheinfo.c - helpers to query the host about its caches
   3  *
   4  * Copyright (C) 2017, Emilio G. Cota <cota@braap.org>
   5  * License: GNU GPL, version 2 or later.
   6  *   See the COPYING file in the top-level directory.
   7  */
   8
   9 #include "qemu/osdep.h"
  10
  11 int qemu_icache_linesize = 0;
  12 int qemu_dcache_linesize = 0;
  13
  14 /*
  15  * Operating system specific detection mechanisms.
  16  */
  17
  18 #if defined(_AIX)
  19 # include <sys/systemcfg.h>
  20
  21 static void sys_cache_info(int *isize, int *dsize)
  22 {
  23     *isize = _system_configuration.icache_line;
  24     *dsize = _system_configuration.dcache_line;
  25 }
  26
  27 #elif defined(_WIN32)
  28
  29 static void sys_cache_info(int *isize, int *dsize)
  30 {
  31     SYSTEM_LOGICAL_PROCESSOR_INFORMATION *buf;
  32     DWORD size = 0;
  33     BOOL success;
  34     size_t i, n;
  35
  36     /* Check for the required buffer size first.  Note that if the zero
  37        size we use for the probe results in success, then there is no
  38        data available; fail in that case.  */
  39     success = GetLogicalProcessorInformation(0, &size);
  40     if (success || GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
  41         return;
  42     }
  43
  44     n = size / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
  45     size = n * sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
  46     buf = g_new0(SYSTEM_LOGICAL_PROCESSOR_INFORMATION, n);
  47     if (!GetLogicalProcessorInformation(buf, &size)) {
  48         goto fail;
  49     }
  50
  51     for (i = 0; i < n; i++) {
  52         if (buf[i].Relationship == RelationCache
  53             && buf[i].Cache.Level == 1) {
  54             switch (buf[i].Cache.Type) {
  55             case CacheUnified:
  56                 *isize = *dsize = buf[i].Cache.LineSize;
  57                 break;
  58             case CacheInstruction:
  59                 *isize = buf[i].Cache.LineSize;
  60                 break;
  61             case CacheData:
  62                 *dsize = buf[i].Cache.LineSize;
  63                 break;
  64             default:
  65                 break;
  66             }
  67         }
  68     }
  69  fail:
  70     g_free(buf);
  71 }
  72
  73 #elif defined(__APPLE__) \
  74       || defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
  75 # include <sys/sysctl.h>
  76 # if defined(__APPLE__)
  77 #  define SYSCTL_CACHELINE_NAME "hw.cachelinesize"
  78 # else
  79 #  define SYSCTL_CACHELINE_NAME "machdep.cacheline_size"
  80 # endif
  81
  82 static void sys_cache_info(int *isize, int *dsize)
  83 {
  84     /* There's only a single sysctl for both I/D cache line sizes.  */
  85     long size;
  86     size_t len = sizeof(size);
  87     if (!sysctlbyname(SYSCTL_CACHELINE_NAME, &size, &len, NULL, 0)) {
  88         *isize = *dsize = size;
  89     }
  90 }
  91
  92 #else
  93 /* POSIX */
  94
  95 static void sys_cache_info(int *isize, int *dsize)
  96 {
  97 # ifdef _SC_LEVEL1_ICACHE_LINESIZE
  98     *isize = sysconf(_SC_LEVEL1_ICACHE_LINESIZE);
  99 # endif
 100 # ifdef _SC_LEVEL1_DCACHE_LINESIZE
 101     *dsize = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
 102 # endif
 103 }
 104 #endif /* sys_cache_info */
 105
 106 /*
 107  * Architecture (+ OS) specific detection mechanisms.
 108  */
 109
 110 #if defined(__aarch64__)
 111
 112 static void arch_cache_info(int *isize, int *dsize)
 113 {
 114     if (*isize == 0 || *dsize == 0) {
 115         unsigned long ctr;
 116
 117         /* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,
 118            but (at least under Linux) these are marked protected by the
 119            kernel.  However, CTR_EL0 contains the minimum linesize in the
 120            entire hierarchy, and is used by userspace cache flushing.  */
 121         asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
 122         if (*isize == 0) {
 123             *isize = 4 << (ctr & 0xf);
 124         }
 125         if (*dsize == 0) {
 126             *dsize = 4 << ((ctr >> 16) & 0xf);
 127         }
 128     }
 129 }
 130
 131 #elif defined(_ARCH_PPC) && defined(__linux__)
 132
 133 static void arch_cache_info(int *isize, int *dsize)
 134 {
 135     if (*isize == 0) {
 136         *isize = qemu_getauxval(AT_ICACHEBSIZE);
 137     }
 138     if (*dsize == 0) {
 139         *dsize = qemu_getauxval(AT_DCACHEBSIZE);
 140     }
 141 }
 142
 143 #else
 144 static void arch_cache_info(int *isize, int *dsize) { }
 145 #endif /* arch_cache_info */
 146
 147 /*
 148  * ... and if all else fails ...
 149  */
 150
 151 static void fallback_cache_info(int *isize, int *dsize)
 152 {
 153     /* If we can only find one of the two, assume they're the same.  */
 154     if (*isize) {
 155         if (*dsize) {
 156             /* Success! */
 157         } else {
 158             *dsize = *isize;
 159         }
 160     } else if (*dsize) {
 161         *isize = *dsize;
 162     } else {
 163 #if defined(_ARCH_PPC)
 164         /* For PPC, we're going to use the icache size computed for
 165            flush_icache_range.  Which means that we must use the
 166            architecture minimum.  */
 167         *isize = *dsize = 16;
 168 #else
 169         /* Otherwise, 64 bytes is not uncommon.  */
 170         *isize = *dsize = 64;
 171 #endif
 172     }
 173 }
 174
 175 static void __attribute__((constructor)) init_cache_info(void)
 176 {
 177     int isize = 0, dsize = 0;
 178
 179     sys_cache_info(&isize, &dsize);
 180     arch_cache_info(&isize, &dsize);
 181     fallback_cache_info(&isize, &dsize);
 182
 183     qemu_icache_linesize = isize;
 184     qemu_dcache_linesize = dsize;
 185 }