target-tilegx/translate.c

   1 /*
   2  * QEMU TILE-Gx CPU
   3  *
   4  *  Copyright (c) 2015 Chen Gang
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu/log.h"
  23 #include "disas/disas.h"
  24 #include "tcg-op.h"
  25 #include "exec/cpu_ldst.h"
  26 #include "opcode_tilegx.h"
  27
  28 #define FMT64X                          "%016" PRIx64
  29
  30 static TCGv_ptr cpu_env;
  31 static TCGv cpu_pc;
  32 static TCGv cpu_regs[TILEGX_R_COUNT];
  33
  34 static const char * const reg_names[64] = {
  35      "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
  36      "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  37     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  38     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
  39     "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  40     "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
  41     "r48", "r49", "r50", "r51",  "bp",  "tp",  "sp",  "lr",
  42     "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero"
  43 };
  44
  45 /* Modified registers are cached in temporaries until the end of the bundle. */
  46 typedef struct {
  47     unsigned reg;
  48     TCGv val;
  49 } DisasContextTemp;
  50
  51 #define MAX_WRITEBACK 4
  52
  53 /* This is the state at translation time.  */
  54 typedef struct {
  55     uint64_t pc;                /* Current pc */
  56
  57     TCGv zero;                  /* For zero register */
  58
  59     DisasContextTemp wb[MAX_WRITEBACK];
  60     int num_wb;
  61     int mmuidx;
  62     bool exit_tb;
  63
  64     struct {
  65         TCGCond cond;    /* branch condition */
  66         TCGv dest;       /* branch destination */
  67         TCGv val1;       /* value to be compared against zero, for cond */
  68     } jmp;               /* Jump object, only once in each TB block */
  69 } DisasContext;
  70
  71 #include "exec/gen-icount.h"
  72
  73 /* Differentiate the various pipe encodings.  */
  74 #define TY_X0  0
  75 #define TY_X1  1
  76 #define TY_Y0  2
  77 #define TY_Y1  3
  78
  79 /* Remerge the base opcode and extension fields for switching.
  80    The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits;
  81    Y2 opcode field is 2 bits.  */
  82 #define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64)
  83
  84 /* Similar, but for Y2 only.  */
  85 #define OEY2(OP, MODE) (OP + MODE * 4)
  86
  87 /* Similar, but make sure opcode names match up.  */
  88 #define OE_RR_X0(E)    OE(RRR_0_OPCODE_X0, E##_UNARY_OPCODE_X0, X0)
  89 #define OE_RR_X1(E)    OE(RRR_0_OPCODE_X1, E##_UNARY_OPCODE_X1, X1)
  90 #define OE_RR_Y0(E)    OE(RRR_1_OPCODE_Y0, E##_UNARY_OPCODE_Y0, Y0)
  91 #define OE_RR_Y1(E)    OE(RRR_1_OPCODE_Y1, E##_UNARY_OPCODE_Y1, Y1)
  92 #define OE_RRR(E,N,XY) OE(RRR_##N##_OPCODE_##XY, E##_RRR_##N##_OPCODE_##XY, XY)
  93 #define OE_IM(E,XY)    OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY)
  94 #define OE_SH(E,XY)    OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
  95
  96
  97 static void gen_exception(DisasContext *dc, TileExcp num)
  98 {
  99     TCGv_i32 tmp;
 100
 101     tcg_gen_movi_tl(cpu_pc, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
 102
 103     tmp = tcg_const_i32(num);
 104     gen_helper_exception(cpu_env, tmp);
 105     tcg_temp_free_i32(tmp);
 106     dc->exit_tb = true;
 107 }
 108
 109 static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
 110                               unsigned dest, unsigned srca)
 111 {
 112     const char *mnemonic;
 113
 114     /* Eliminate nops before doing anything else.  */
 115     switch (opext) {
 116     case OE_RR_Y0(NOP):
 117     case OE_RR_Y1(NOP):
 118     case OE_RR_X0(NOP):
 119     case OE_RR_X1(NOP):
 120         mnemonic = "nop";
 121         goto do_nop;
 122     case OE_RR_Y0(FNOP):
 123     case OE_RR_Y1(FNOP):
 124     case OE_RR_X0(FNOP):
 125     case OE_RR_X1(FNOP):
 126         mnemonic = "fnop";
 127     do_nop:
 128         if (srca || dest) {
 129             return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
 130         }
 131         qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
 132         return TILEGX_EXCP_NONE;
 133     }
 134
 135     switch (opext) {
 136     case OE_RR_X0(CNTLZ):
 137     case OE_RR_Y0(CNTLZ):
 138     case OE_RR_X0(CNTTZ):
 139     case OE_RR_Y0(CNTTZ):
 140     case OE_RR_X1(DRAIN):
 141     case OE_RR_X1(DTLBPR):
 142     case OE_RR_X1(FINV):
 143     case OE_RR_X1(FLUSHWB):
 144     case OE_RR_X1(FLUSH):
 145     case OE_RR_X0(FSINGLE_PACK1):
 146     case OE_RR_Y0(FSINGLE_PACK1):
 147     case OE_RR_X1(ICOH):
 148     case OE_RR_X1(ILL):
 149     case OE_RR_Y1(ILL):
 150     case OE_RR_X1(INV):
 151     case OE_RR_X1(IRET):
 152     case OE_RR_X1(JALRP):
 153     case OE_RR_Y1(JALRP):
 154     case OE_RR_X1(JALR):
 155     case OE_RR_Y1(JALR):
 156     case OE_RR_X1(JRP):
 157     case OE_RR_Y1(JRP):
 158     case OE_RR_X1(JR):
 159     case OE_RR_Y1(JR):
 160     case OE_RR_X1(LD1S):
 161     case OE_RR_X1(LD1U):
 162     case OE_RR_X1(LD2S):
 163     case OE_RR_X1(LD2U):
 164     case OE_RR_X1(LD4S):
 165     case OE_RR_X1(LD4U):
 166     case OE_RR_X1(LDNA):
 167     case OE_RR_X1(LDNT1S):
 168     case OE_RR_X1(LDNT1U):
 169     case OE_RR_X1(LDNT2S):
 170     case OE_RR_X1(LDNT2U):
 171     case OE_RR_X1(LDNT4S):
 172     case OE_RR_X1(LDNT4U):
 173     case OE_RR_X1(LDNT):
 174     case OE_RR_X1(LD):
 175     case OE_RR_X1(LNK):
 176     case OE_RR_Y1(LNK):
 177     case OE_RR_X1(MF):
 178     case OE_RR_X1(NAP):
 179     case OE_RR_X0(PCNT):
 180     case OE_RR_Y0(PCNT):
 181     case OE_RR_X0(REVBITS):
 182     case OE_RR_Y0(REVBITS):
 183     case OE_RR_X0(REVBYTES):
 184     case OE_RR_Y0(REVBYTES):
 185     case OE_RR_X1(SWINT0):
 186     case OE_RR_X1(SWINT1):
 187     case OE_RR_X1(SWINT2):
 188     case OE_RR_X1(SWINT3):
 189     case OE_RR_X0(TBLIDXB0):
 190     case OE_RR_Y0(TBLIDXB0):
 191     case OE_RR_X0(TBLIDXB1):
 192     case OE_RR_Y0(TBLIDXB1):
 193     case OE_RR_X0(TBLIDXB2):
 194     case OE_RR_Y0(TBLIDXB2):
 195     case OE_RR_X0(TBLIDXB3):
 196     case OE_RR_Y0(TBLIDXB3):
 197     case OE_RR_X1(WH64):
 198     default:
 199         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
 200     }
 201
 202     qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
 203                   reg_names[dest], reg_names[srca]);
 204     return TILEGX_EXCP_NONE;
 205 }
 206
 207 static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
 208                                unsigned dest, unsigned srca, unsigned srcb)
 209 {
 210     const char *mnemonic;
 211
 212     switch (opext) {
 213     case OE_RRR(ADDXSC, 0, X0):
 214     case OE_RRR(ADDXSC, 0, X1):
 215     case OE_RRR(ADDX, 0, X0):
 216     case OE_RRR(ADDX, 0, X1):
 217     case OE_RRR(ADDX, 0, Y0):
 218     case OE_RRR(ADDX, 0, Y1):
 219     case OE_RRR(ADD, 0, X0):
 220     case OE_RRR(ADD, 0, X1):
 221     case OE_RRR(ADD, 0, Y0):
 222     case OE_RRR(ADD, 0, Y1):
 223     case OE_RRR(AND, 0, X0):
 224     case OE_RRR(AND, 0, X1):
 225     case OE_RRR(AND, 5, Y0):
 226     case OE_RRR(AND, 5, Y1):
 227     case OE_RRR(CMOVEQZ, 0, X0):
 228     case OE_RRR(CMOVEQZ, 4, Y0):
 229     case OE_RRR(CMOVNEZ, 0, X0):
 230     case OE_RRR(CMOVNEZ, 4, Y0):
 231     case OE_RRR(CMPEQ, 0, X0):
 232     case OE_RRR(CMPEQ, 0, X1):
 233     case OE_RRR(CMPEQ, 3, Y0):
 234     case OE_RRR(CMPEQ, 3, Y1):
 235     case OE_RRR(CMPEXCH4, 0, X1):
 236     case OE_RRR(CMPEXCH, 0, X1):
 237     case OE_RRR(CMPLES, 0, X0):
 238     case OE_RRR(CMPLES, 0, X1):
 239     case OE_RRR(CMPLES, 2, Y0):
 240     case OE_RRR(CMPLES, 2, Y1):
 241     case OE_RRR(CMPLEU, 0, X0):
 242     case OE_RRR(CMPLEU, 0, X1):
 243     case OE_RRR(CMPLEU, 2, Y0):
 244     case OE_RRR(CMPLEU, 2, Y1):
 245     case OE_RRR(CMPLTS, 0, X0):
 246     case OE_RRR(CMPLTS, 0, X1):
 247     case OE_RRR(CMPLTS, 2, Y0):
 248     case OE_RRR(CMPLTS, 2, Y1):
 249     case OE_RRR(CMPLTU, 0, X0):
 250     case OE_RRR(CMPLTU, 0, X1):
 251     case OE_RRR(CMPLTU, 2, Y0):
 252     case OE_RRR(CMPLTU, 2, Y1):
 253     case OE_RRR(CMPNE, 0, X0):
 254     case OE_RRR(CMPNE, 0, X1):
 255     case OE_RRR(CMPNE, 3, Y0):
 256     case OE_RRR(CMPNE, 3, Y1):
 257     case OE_RRR(CMULAF, 0, X0):
 258     case OE_RRR(CMULA, 0, X0):
 259     case OE_RRR(CMULFR, 0, X0):
 260     case OE_RRR(CMULF, 0, X0):
 261     case OE_RRR(CMULHR, 0, X0):
 262     case OE_RRR(CMULH, 0, X0):
 263     case OE_RRR(CMUL, 0, X0):
 264     case OE_RRR(CRC32_32, 0, X0):
 265     case OE_RRR(CRC32_8, 0, X0):
 266     case OE_RRR(DBLALIGN2, 0, X0):
 267     case OE_RRR(DBLALIGN2, 0, X1):
 268     case OE_RRR(DBLALIGN4, 0, X0):
 269     case OE_RRR(DBLALIGN4, 0, X1):
 270     case OE_RRR(DBLALIGN6, 0, X0):
 271     case OE_RRR(DBLALIGN6, 0, X1):
 272     case OE_RRR(DBLALIGN, 0, X0):
 273     case OE_RRR(EXCH4, 0, X1):
 274     case OE_RRR(EXCH, 0, X1):
 275     case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
 276     case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0):
 277     case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0):
 278     case OE_RRR(FDOUBLE_PACK1, 0, X0):
 279     case OE_RRR(FDOUBLE_PACK2, 0, X0):
 280     case OE_RRR(FDOUBLE_SUB_FLAGS, 0, X0):
 281     case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0):
 282     case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0):
 283     case OE_RRR(FETCHADD4, 0, X1):
 284     case OE_RRR(FETCHADDGEZ4, 0, X1):
 285     case OE_RRR(FETCHADDGEZ, 0, X1):
 286     case OE_RRR(FETCHADD, 0, X1):
 287     case OE_RRR(FETCHAND4, 0, X1):
 288     case OE_RRR(FETCHAND, 0, X1):
 289     case OE_RRR(FETCHOR4, 0, X1):
 290     case OE_RRR(FETCHOR, 0, X1):
 291     case OE_RRR(FSINGLE_ADD1, 0, X0):
 292     case OE_RRR(FSINGLE_ADDSUB2, 0, X0):
 293     case OE_RRR(FSINGLE_MUL1, 0, X0):
 294     case OE_RRR(FSINGLE_MUL2, 0, X0):
 295     case OE_RRR(FSINGLE_PACK2, 0, X0):
 296     case OE_RRR(FSINGLE_SUB1, 0, X0):
 297     case OE_RRR(MNZ, 0, X0):
 298     case OE_RRR(MNZ, 0, X1):
 299     case OE_RRR(MNZ, 4, Y0):
 300     case OE_RRR(MNZ, 4, Y1):
 301     case OE_RRR(MULAX, 0, X0):
 302     case OE_RRR(MULAX, 3, Y0):
 303     case OE_RRR(MULA_HS_HS, 0, X0):
 304     case OE_RRR(MULA_HS_HS, 9, Y0):
 305     case OE_RRR(MULA_HS_HU, 0, X0):
 306     case OE_RRR(MULA_HS_LS, 0, X0):
 307     case OE_RRR(MULA_HS_LU, 0, X0):
 308     case OE_RRR(MULA_HU_HU, 0, X0):
 309     case OE_RRR(MULA_HU_HU, 9, Y0):
 310     case OE_RRR(MULA_HU_LS, 0, X0):
 311     case OE_RRR(MULA_HU_LU, 0, X0):
 312     case OE_RRR(MULA_LS_LS, 0, X0):
 313     case OE_RRR(MULA_LS_LS, 9, Y0):
 314     case OE_RRR(MULA_LS_LU, 0, X0):
 315     case OE_RRR(MULA_LU_LU, 0, X0):
 316     case OE_RRR(MULA_LU_LU, 9, Y0):
 317     case OE_RRR(MULX, 0, X0):
 318     case OE_RRR(MULX, 3, Y0):
 319     case OE_RRR(MUL_HS_HS, 0, X0):
 320     case OE_RRR(MUL_HS_HS, 8, Y0):
 321     case OE_RRR(MUL_HS_HU, 0, X0):
 322     case OE_RRR(MUL_HS_LS, 0, X0):
 323     case OE_RRR(MUL_HS_LU, 0, X0):
 324     case OE_RRR(MUL_HU_HU, 0, X0):
 325     case OE_RRR(MUL_HU_HU, 8, Y0):
 326     case OE_RRR(MUL_HU_LS, 0, X0):
 327     case OE_RRR(MUL_HU_LU, 0, X0):
 328     case OE_RRR(MUL_LS_LS, 0, X0):
 329     case OE_RRR(MUL_LS_LS, 8, Y0):
 330     case OE_RRR(MUL_LS_LU, 0, X0):
 331     case OE_RRR(MUL_LU_LU, 0, X0):
 332     case OE_RRR(MUL_LU_LU, 8, Y0):
 333     case OE_RRR(MZ, 0, X0):
 334     case OE_RRR(MZ, 0, X1):
 335     case OE_RRR(MZ, 4, Y0):
 336     case OE_RRR(MZ, 4, Y1):
 337     case OE_RRR(NOR, 0, X0):
 338     case OE_RRR(NOR, 0, X1):
 339     case OE_RRR(NOR, 5, Y0):
 340     case OE_RRR(NOR, 5, Y1):
 341     case OE_RRR(OR, 0, X0):
 342     case OE_RRR(OR, 0, X1):
 343     case OE_RRR(OR, 5, Y0):
 344     case OE_RRR(OR, 5, Y1):
 345     case OE_RRR(ROTL, 0, X0):
 346     case OE_RRR(ROTL, 0, X1):
 347     case OE_RRR(ROTL, 6, Y0):
 348     case OE_RRR(ROTL, 6, Y1):
 349     case OE_RRR(SHL1ADDX, 0, X0):
 350     case OE_RRR(SHL1ADDX, 0, X1):
 351     case OE_RRR(SHL1ADDX, 7, Y0):
 352     case OE_RRR(SHL1ADDX, 7, Y1):
 353     case OE_RRR(SHL1ADD, 0, X0):
 354     case OE_RRR(SHL1ADD, 0, X1):
 355     case OE_RRR(SHL1ADD, 1, Y0):
 356     case OE_RRR(SHL1ADD, 1, Y1):
 357     case OE_RRR(SHL2ADDX, 0, X0):
 358     case OE_RRR(SHL2ADDX, 0, X1):
 359     case OE_RRR(SHL2ADDX, 7, Y0):
 360     case OE_RRR(SHL2ADDX, 7, Y1):
 361     case OE_RRR(SHL2ADD, 0, X0):
 362     case OE_RRR(SHL2ADD, 0, X1):
 363     case OE_RRR(SHL2ADD, 1, Y0):
 364     case OE_RRR(SHL2ADD, 1, Y1):
 365     case OE_RRR(SHL3ADDX, 0, X0):
 366     case OE_RRR(SHL3ADDX, 0, X1):
 367     case OE_RRR(SHL3ADDX, 7, Y0):
 368     case OE_RRR(SHL3ADDX, 7, Y1):
 369     case OE_RRR(SHL3ADD, 0, X0):
 370     case OE_RRR(SHL3ADD, 0, X1):
 371     case OE_RRR(SHL3ADD, 1, Y0):
 372     case OE_RRR(SHL3ADD, 1, Y1):
 373     case OE_RRR(SHLX, 0, X0):
 374     case OE_RRR(SHLX, 0, X1):
 375     case OE_RRR(SHL, 0, X0):
 376     case OE_RRR(SHL, 0, X1):
 377     case OE_RRR(SHL, 6, Y0):
 378     case OE_RRR(SHL, 6, Y1):
 379     case OE_RRR(SHRS, 0, X0):
 380     case OE_RRR(SHRS, 0, X1):
 381     case OE_RRR(SHRS, 6, Y0):
 382     case OE_RRR(SHRS, 6, Y1):
 383     case OE_RRR(SHRUX, 0, X0):
 384     case OE_RRR(SHRUX, 0, X1):
 385     case OE_RRR(SHRU, 0, X0):
 386     case OE_RRR(SHRU, 0, X1):
 387     case OE_RRR(SHRU, 6, Y0):
 388     case OE_RRR(SHRU, 6, Y1):
 389     case OE_RRR(SHUFFLEBYTES, 0, X0):
 390     case OE_RRR(ST1, 0, X1):
 391     case OE_RRR(ST2, 0, X1):
 392     case OE_RRR(ST4, 0, X1):
 393     case OE_RRR(STNT1, 0, X1):
 394     case OE_RRR(STNT2, 0, X1):
 395     case OE_RRR(STNT4, 0, X1):
 396     case OE_RRR(STNT, 0, X1):
 397     case OE_RRR(ST, 0, X1):
 398     case OE_RRR(SUBXSC, 0, X0):
 399     case OE_RRR(SUBXSC, 0, X1):
 400     case OE_RRR(SUBX, 0, X0):
 401     case OE_RRR(SUBX, 0, X1):
 402     case OE_RRR(SUBX, 0, Y0):
 403     case OE_RRR(SUBX, 0, Y1):
 404     case OE_RRR(SUB, 0, X0):
 405     case OE_RRR(SUB, 0, X1):
 406     case OE_RRR(SUB, 0, Y0):
 407     case OE_RRR(SUB, 0, Y1):
 408     case OE_RRR(V1ADDUC, 0, X0):
 409     case OE_RRR(V1ADDUC, 0, X1):
 410     case OE_RRR(V1ADD, 0, X0):
 411     case OE_RRR(V1ADD, 0, X1):
 412     case OE_RRR(V1ADIFFU, 0, X0):
 413     case OE_RRR(V1AVGU, 0, X0):
 414     case OE_RRR(V1CMPEQ, 0, X0):
 415     case OE_RRR(V1CMPEQ, 0, X1):
 416     case OE_RRR(V1CMPLES, 0, X0):
 417     case OE_RRR(V1CMPLES, 0, X1):
 418     case OE_RRR(V1CMPLEU, 0, X0):
 419     case OE_RRR(V1CMPLEU, 0, X1):
 420     case OE_RRR(V1CMPLTS, 0, X0):
 421     case OE_RRR(V1CMPLTS, 0, X1):
 422     case OE_RRR(V1CMPLTU, 0, X0):
 423     case OE_RRR(V1CMPLTU, 0, X1):
 424     case OE_RRR(V1CMPNE, 0, X0):
 425     case OE_RRR(V1CMPNE, 0, X1):
 426     case OE_RRR(V1DDOTPUA, 0, X0):
 427     case OE_RRR(V1DDOTPUSA, 0, X0):
 428     case OE_RRR(V1DDOTPUS, 0, X0):
 429     case OE_RRR(V1DDOTPU, 0, X0):
 430     case OE_RRR(V1DOTPA, 0, X0):
 431     case OE_RRR(V1DOTPUA, 0, X0):
 432     case OE_RRR(V1DOTPUSA, 0, X0):
 433     case OE_RRR(V1DOTPUS, 0, X0):
 434     case OE_RRR(V1DOTPU, 0, X0):
 435     case OE_RRR(V1DOTP, 0, X0):
 436     case OE_RRR(V1INT_H, 0, X0):
 437     case OE_RRR(V1INT_H, 0, X1):
 438     case OE_RRR(V1INT_L, 0, X0):
 439     case OE_RRR(V1INT_L, 0, X1):
 440     case OE_RRR(V1MAXU, 0, X0):
 441     case OE_RRR(V1MAXU, 0, X1):
 442     case OE_RRR(V1MINU, 0, X0):
 443     case OE_RRR(V1MINU, 0, X1):
 444     case OE_RRR(V1MNZ, 0, X0):
 445     case OE_RRR(V1MNZ, 0, X1):
 446     case OE_RRR(V1MULTU, 0, X0):
 447     case OE_RRR(V1MULUS, 0, X0):
 448     case OE_RRR(V1MULU, 0, X0):
 449     case OE_RRR(V1MZ, 0, X0):
 450     case OE_RRR(V1MZ, 0, X1):
 451     case OE_RRR(V1SADAU, 0, X0):
 452     case OE_RRR(V1SADU, 0, X0):
 453     case OE_RRR(V1SHL, 0, X0):
 454     case OE_RRR(V1SHL, 0, X1):
 455     case OE_RRR(V1SHRS, 0, X0):
 456     case OE_RRR(V1SHRS, 0, X1):
 457     case OE_RRR(V1SHRU, 0, X0):
 458     case OE_RRR(V1SHRU, 0, X1):
 459     case OE_RRR(V1SUBUC, 0, X0):
 460     case OE_RRR(V1SUBUC, 0, X1):
 461     case OE_RRR(V1SUB, 0, X0):
 462     case OE_RRR(V1SUB, 0, X1):
 463     case OE_RRR(V2ADDSC, 0, X0):
 464     case OE_RRR(V2ADDSC, 0, X1):
 465     case OE_RRR(V2ADD, 0, X0):
 466     case OE_RRR(V2ADD, 0, X1):
 467     case OE_RRR(V2ADIFFS, 0, X0):
 468     case OE_RRR(V2AVGS, 0, X0):
 469     case OE_RRR(V2CMPEQ, 0, X0):
 470     case OE_RRR(V2CMPEQ, 0, X1):
 471     case OE_RRR(V2CMPLES, 0, X0):
 472     case OE_RRR(V2CMPLES, 0, X1):
 473     case OE_RRR(V2CMPLEU, 0, X0):
 474     case OE_RRR(V2CMPLEU, 0, X1):
 475     case OE_RRR(V2CMPLTS, 0, X0):
 476     case OE_RRR(V2CMPLTS, 0, X1):
 477     case OE_RRR(V2CMPLTU, 0, X0):
 478     case OE_RRR(V2CMPLTU, 0, X1):
 479     case OE_RRR(V2CMPNE, 0, X0):
 480     case OE_RRR(V2CMPNE, 0, X1):
 481     case OE_RRR(V2DOTPA, 0, X0):
 482     case OE_RRR(V2DOTP, 0, X0):
 483     case OE_RRR(V2INT_H, 0, X0):
 484     case OE_RRR(V2INT_H, 0, X1):
 485     case OE_RRR(V2INT_L, 0, X0):
 486     case OE_RRR(V2INT_L, 0, X1):
 487     case OE_RRR(V2MAXS, 0, X0):
 488     case OE_RRR(V2MAXS, 0, X1):
 489     case OE_RRR(V2MINS, 0, X0):
 490     case OE_RRR(V2MINS, 0, X1):
 491     case OE_RRR(V2MNZ, 0, X0):
 492     case OE_RRR(V2MNZ, 0, X1):
 493     case OE_RRR(V2MULFSC, 0, X0):
 494     case OE_RRR(V2MULS, 0, X0):
 495     case OE_RRR(V2MULTS, 0, X0):
 496     case OE_RRR(V2MZ, 0, X0):
 497     case OE_RRR(V2MZ, 0, X1):
 498     case OE_RRR(V2PACKH, 0, X0):
 499     case OE_RRR(V2PACKH, 0, X1):
 500     case OE_RRR(V2PACKL, 0, X0):
 501     case OE_RRR(V2PACKL, 0, X1):
 502     case OE_RRR(V2PACKUC, 0, X0):
 503     case OE_RRR(V2PACKUC, 0, X1):
 504     case OE_RRR(V2SADAS, 0, X0):
 505     case OE_RRR(V2SADAU, 0, X0):
 506     case OE_RRR(V2SADS, 0, X0):
 507     case OE_RRR(V2SADU, 0, X0):
 508     case OE_RRR(V2SHLSC, 0, X0):
 509     case OE_RRR(V2SHLSC, 0, X1):
 510     case OE_RRR(V2SHL, 0, X0):
 511     case OE_RRR(V2SHL, 0, X1):
 512     case OE_RRR(V2SHRS, 0, X0):
 513     case OE_RRR(V2SHRS, 0, X1):
 514     case OE_RRR(V2SHRU, 0, X0):
 515     case OE_RRR(V2SHRU, 0, X1):
 516     case OE_RRR(V2SUBSC, 0, X0):
 517     case OE_RRR(V2SUBSC, 0, X1):
 518     case OE_RRR(V2SUB, 0, X0):
 519     case OE_RRR(V2SUB, 0, X1):
 520     case OE_RRR(V4ADDSC, 0, X0):
 521     case OE_RRR(V4ADDSC, 0, X1):
 522     case OE_RRR(V4ADD, 0, X0):
 523     case OE_RRR(V4ADD, 0, X1):
 524     case OE_RRR(V4INT_H, 0, X0):
 525     case OE_RRR(V4INT_H, 0, X1):
 526     case OE_RRR(V4INT_L, 0, X0):
 527     case OE_RRR(V4INT_L, 0, X1):
 528     case OE_RRR(V4PACKSC, 0, X0):
 529     case OE_RRR(V4PACKSC, 0, X1):
 530     case OE_RRR(V4SHLSC, 0, X0):
 531     case OE_RRR(V4SHLSC, 0, X1):
 532     case OE_RRR(V4SHL, 0, X0):
 533     case OE_RRR(V4SHL, 0, X1):
 534     case OE_RRR(V4SHRS, 0, X0):
 535     case OE_RRR(V4SHRS, 0, X1):
 536     case OE_RRR(V4SHRU, 0, X0):
 537     case OE_RRR(V4SHRU, 0, X1):
 538     case OE_RRR(V4SUBSC, 0, X0):
 539     case OE_RRR(V4SUBSC, 0, X1):
 540     case OE_RRR(V4SUB, 0, X0):
 541     case OE_RRR(V4SUB, 0, X1):
 542     case OE_RRR(XOR, 0, X0):
 543     case OE_RRR(XOR, 0, X1):
 544     case OE_RRR(XOR, 5, Y0):
 545     case OE_RRR(XOR, 5, Y1):
 546     default:
 547         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
 548     }
 549
 550     qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %s", mnemonic,
 551                   reg_names[dest], reg_names[srca], reg_names[srcb]);
 552     return TILEGX_EXCP_NONE;
 553 }
 554
 555 static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
 556                                unsigned dest, unsigned srca, int imm)
 557 {
 558     const char *mnemonic;
 559
 560     switch (opext) {
 561     case OE_IM(ADDI, X0):
 562     case OE_IM(ADDI, X1):
 563     case OE_IM(ADDXI, X0):
 564     case OE_IM(ADDXI, X1):
 565     case OE_IM(ANDI, X0):
 566     case OE_IM(ANDI, X1):
 567     case OE_IM(CMPEQI, X0):
 568     case OE_IM(CMPEQI, X1):
 569     case OE_IM(CMPLTSI, X0):
 570     case OE_IM(CMPLTSI, X1):
 571     case OE_IM(CMPLTUI, X0):
 572     case OE_IM(CMPLTUI, X1):
 573     case OE_IM(LD1S_ADD, X1):
 574     case OE_IM(LD1U_ADD, X1):
 575     case OE_IM(LD2S_ADD, X1):
 576     case OE_IM(LD2U_ADD, X1):
 577     case OE_IM(LD4S_ADD, X1):
 578     case OE_IM(LD4U_ADD, X1):
 579     case OE_IM(LDNT1S_ADD, X1):
 580     case OE_IM(LDNT1U_ADD, X1):
 581     case OE_IM(LDNT2S_ADD, X1):
 582     case OE_IM(LDNT2U_ADD, X1):
 583     case OE_IM(LDNT4S_ADD, X1):
 584     case OE_IM(LDNT4U_ADD, X1):
 585     case OE_IM(LDNT_ADD, X1):
 586     case OE_IM(LD_ADD, X1):
 587     case OE_IM(LDNA_ADD, X1):
 588     case OE_IM(MFSPR, X1):
 589     case OE_IM(MTSPR, X1):
 590     case OE_IM(ORI, X0):
 591     case OE_IM(ORI, X1):
 592     case OE_IM(ST1_ADD, X1):
 593     case OE_IM(ST2_ADD, X1):
 594     case OE_IM(ST4_ADD, X1):
 595     case OE_IM(STNT1_ADD, X1):
 596     case OE_IM(STNT2_ADD, X1):
 597     case OE_IM(STNT4_ADD, X1):
 598     case OE_IM(STNT_ADD, X1):
 599     case OE_IM(ST_ADD, X1):
 600     case OE_IM(V1ADDI, X0):
 601     case OE_IM(V1ADDI, X1):
 602     case OE_IM(V1CMPEQI, X0):
 603     case OE_IM(V1CMPEQI, X1):
 604     case OE_IM(V1CMPLTSI, X0):
 605     case OE_IM(V1CMPLTSI, X1):
 606     case OE_IM(V1CMPLTUI, X0):
 607     case OE_IM(V1CMPLTUI, X1):
 608     case OE_IM(V1MAXUI, X0):
 609     case OE_IM(V1MAXUI, X1):
 610     case OE_IM(V1MINUI, X0):
 611     case OE_IM(V1MINUI, X1):
 612     case OE_IM(V2ADDI, X0):
 613     case OE_IM(V2ADDI, X1):
 614     case OE_IM(V2CMPEQI, X0):
 615     case OE_IM(V2CMPEQI, X1):
 616     case OE_IM(V2CMPLTSI, X0):
 617     case OE_IM(V2CMPLTSI, X1):
 618     case OE_IM(V2CMPLTUI, X0):
 619     case OE_IM(V2CMPLTUI, X1):
 620     case OE_IM(V2MAXSI, X0):
 621     case OE_IM(V2MAXSI, X1):
 622     case OE_IM(V2MINSI, X0):
 623     case OE_IM(V2MINSI, X1):
 624     case OE_IM(XORI, X0):
 625     case OE_IM(XORI, X1):
 626
 627     case OE_SH(ROTLI, X0):
 628     case OE_SH(ROTLI, X1):
 629     case OE_SH(ROTLI, Y0):
 630     case OE_SH(ROTLI, Y1):
 631     case OE_SH(SHLI, X0):
 632     case OE_SH(SHLI, X1):
 633     case OE_SH(SHLI, Y0):
 634     case OE_SH(SHLI, Y1):
 635     case OE_SH(SHLXI, X0):
 636     case OE_SH(SHLXI, X1):
 637     case OE_SH(SHRSI, X0):
 638     case OE_SH(SHRSI, X1):
 639     case OE_SH(SHRSI, Y0):
 640     case OE_SH(SHRSI, Y1):
 641     case OE_SH(SHRUI, X0):
 642     case OE_SH(SHRUI, X1):
 643     case OE_SH(SHRUI, Y0):
 644     case OE_SH(SHRUI, Y1):
 645     case OE_SH(SHRUXI, X0):
 646     case OE_SH(SHRUXI, X1):
 647     case OE_SH(V1SHLI, X0):
 648     case OE_SH(V1SHLI, X1):
 649     case OE_SH(V1SHRSI, X0):
 650     case OE_SH(V1SHRSI, X1):
 651     case OE_SH(V1SHRUI, X0):
 652     case OE_SH(V1SHRUI, X1):
 653     case OE_SH(V2SHLI, X0):
 654     case OE_SH(V2SHLI, X1):
 655     case OE_SH(V2SHRSI, X0):
 656     case OE_SH(V2SHRSI, X1):
 657     case OE_SH(V2SHRUI, X0):
 658     case OE_SH(V2SHRUI, X1):
 659
 660     case OE(ADDI_OPCODE_Y0, 0, Y0):
 661     case OE(ADDI_OPCODE_Y1, 0, Y1):
 662     case OE(ADDLI_OPCODE_X0, 0, X0):
 663     case OE(ADDLI_OPCODE_X1, 0, X1):
 664     case OE(ADDXI_OPCODE_Y0, 0, Y0):
 665     case OE(ADDXI_OPCODE_Y1, 0, Y1):
 666     case OE(ADDXLI_OPCODE_X0, 0, X0):
 667     case OE(ADDXLI_OPCODE_X1, 0, X1):
 668     case OE(ANDI_OPCODE_Y0, 0, Y0):
 669     case OE(ANDI_OPCODE_Y1, 0, Y1):
 670     case OE(CMPEQI_OPCODE_Y0, 0, Y0):
 671     case OE(CMPEQI_OPCODE_Y1, 0, Y1):
 672     case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
 673     case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
 674     case OE(SHL16INSLI_OPCODE_X0, 0, X0):
 675     case OE(SHL16INSLI_OPCODE_X1, 0, X1):
 676
 677     default:
 678         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
 679     }
 680
 681     qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,
 682                   reg_names[dest], reg_names[srca], imm);
 683     return TILEGX_EXCP_NONE;
 684 }
 685
 686 static TileExcp gen_bf_opcode_x0(DisasContext *dc, unsigned ext,
 687                                  unsigned dest, unsigned srca,
 688                                  unsigned bfs, unsigned bfe)
 689 {
 690     const char *mnemonic;
 691
 692     switch (ext) {
 693     case BFEXTU_BF_OPCODE_X0:
 694     case BFEXTS_BF_OPCODE_X0:
 695     case BFINS_BF_OPCODE_X0:
 696     case MM_BF_OPCODE_X0:
 697     default:
 698         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
 699     }
 700
 701     qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %u, %u", mnemonic,
 702                   reg_names[dest], reg_names[srca], bfs, bfe);
 703     return TILEGX_EXCP_NONE;
 704 }
 705
 706 static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext,
 707                                      unsigned srca, int off)
 708 {
 709     target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
 710     const char *mnemonic;
 711
 712     switch (ext) {
 713     case BEQZT_BRANCH_OPCODE_X1:
 714     case BEQZ_BRANCH_OPCODE_X1:
 715     case BNEZT_BRANCH_OPCODE_X1:
 716     case BNEZ_BRANCH_OPCODE_X1:
 717     case BLBC_BRANCH_OPCODE_X1:
 718     case BGEZT_BRANCH_OPCODE_X1:
 719     case BGEZ_BRANCH_OPCODE_X1:
 720     case BGTZT_BRANCH_OPCODE_X1:
 721     case BGTZ_BRANCH_OPCODE_X1:
 722     case BLBCT_BRANCH_OPCODE_X1:
 723     case BLBST_BRANCH_OPCODE_X1:
 724     case BLBS_BRANCH_OPCODE_X1:
 725     case BLEZT_BRANCH_OPCODE_X1:
 726     case BLEZ_BRANCH_OPCODE_X1:
 727     case BLTZT_BRANCH_OPCODE_X1:
 728     case BLTZ_BRANCH_OPCODE_X1:
 729     default:
 730         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
 731     }
 732
 733     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
 734         qemu_log("%s %s, " TARGET_FMT_lx " <%s>",
 735                  mnemonic, reg_names[srca], tgt, lookup_symbol(tgt));
 736     }
 737     return TILEGX_EXCP_NONE;
 738 }
 739
 740 static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext,
 741                                    int off)
 742 {
 743     target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
 744     const char *mnemonic;
 745
 746     switch (ext) {
 747     case JAL_JUMP_OPCODE_X1:
 748     case J_JUMP_OPCODE_X1:
 749     default:
 750         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
 751     }
 752
 753     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
 754         qemu_log("%s " TARGET_FMT_lx " <%s>",
 755                  mnemonic, tgt, lookup_symbol(tgt));
 756     }
 757     return TILEGX_EXCP_NONE;
 758 }
 759
 760 static TileExcp decode_y0(DisasContext *dc, tilegx_bundle_bits bundle)
 761 {
 762     unsigned opc = get_Opcode_Y0(bundle);
 763     unsigned ext = get_RRROpcodeExtension_Y0(bundle);
 764     unsigned dest = get_Dest_Y0(bundle);
 765     unsigned srca = get_SrcA_Y0(bundle);
 766     unsigned srcb;
 767     int imm;
 768
 769     switch (opc) {
 770     case RRR_1_OPCODE_Y0:
 771         if (ext == UNARY_RRR_1_OPCODE_Y0) {
 772             ext = get_UnaryOpcodeExtension_Y0(bundle);
 773             return gen_rr_opcode(dc, OE(opc, ext, Y0), dest, srca);
 774         }
 775         /* fallthru */
 776     case RRR_0_OPCODE_Y0:
 777     case RRR_2_OPCODE_Y0:
 778     case RRR_3_OPCODE_Y0:
 779     case RRR_4_OPCODE_Y0:
 780     case RRR_5_OPCODE_Y0:
 781     case RRR_6_OPCODE_Y0:
 782     case RRR_7_OPCODE_Y0:
 783     case RRR_8_OPCODE_Y0:
 784     case RRR_9_OPCODE_Y0:
 785         srcb = get_SrcB_Y0(bundle);
 786         return gen_rrr_opcode(dc, OE(opc, ext, Y0), dest, srca, srcb);
 787
 788     case SHIFT_OPCODE_Y0:
 789         ext = get_ShiftOpcodeExtension_Y0(bundle);
 790         imm = get_ShAmt_Y0(bundle);
 791         return gen_rri_opcode(dc, OE(opc, ext, Y0), dest, srca, imm);
 792
 793     case ADDI_OPCODE_Y0:
 794     case ADDXI_OPCODE_Y0:
 795     case ANDI_OPCODE_Y0:
 796     case CMPEQI_OPCODE_Y0:
 797     case CMPLTSI_OPCODE_Y0:
 798         imm = (int8_t)get_Imm8_Y0(bundle);
 799         return gen_rri_opcode(dc, OE(opc, 0, Y0), dest, srca, imm);
 800
 801     default:
 802         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
 803     }
 804 }
 805
 806 static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle)
 807 {
 808     unsigned opc = get_Opcode_Y1(bundle);
 809     unsigned ext = get_RRROpcodeExtension_Y1(bundle);
 810     unsigned dest = get_Dest_Y1(bundle);
 811     unsigned srca = get_SrcA_Y1(bundle);
 812     unsigned srcb;
 813     int imm;
 814
 815     switch (get_Opcode_Y1(bundle)) {
 816     case RRR_1_OPCODE_Y1:
 817         if (ext == UNARY_RRR_1_OPCODE_Y0) {
 818             ext = get_UnaryOpcodeExtension_Y1(bundle);
 819             return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca);
 820         }
 821         /* fallthru */
 822     case RRR_0_OPCODE_Y1:
 823     case RRR_2_OPCODE_Y1:
 824     case RRR_3_OPCODE_Y1:
 825     case RRR_4_OPCODE_Y1:
 826     case RRR_5_OPCODE_Y1:
 827     case RRR_6_OPCODE_Y1:
 828     case RRR_7_OPCODE_Y1:
 829         srcb = get_SrcB_Y1(bundle);
 830         return gen_rrr_opcode(dc, OE(opc, ext, Y1), dest, srca, srcb);
 831
 832     case SHIFT_OPCODE_Y1:
 833         ext = get_ShiftOpcodeExtension_Y1(bundle);
 834         imm = get_ShAmt_Y1(bundle);
 835         return gen_rri_opcode(dc, OE(opc, ext, Y1), dest, srca, imm);
 836
 837     case ADDI_OPCODE_Y1:
 838     case ADDXI_OPCODE_Y1:
 839     case ANDI_OPCODE_Y1:
 840     case CMPEQI_OPCODE_Y1:
 841     case CMPLTSI_OPCODE_Y1:
 842         imm = (int8_t)get_Imm8_Y1(bundle);
 843         return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm);
 844
 845     default:
 846         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
 847     }
 848 }
 849
 850 static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
 851 {
 852     unsigned mode = get_Mode(bundle);
 853     unsigned opc = get_Opcode_Y2(bundle);
 854     unsigned srca = get_SrcA_Y2(bundle);
 855     unsigned srcbdest = get_SrcBDest_Y2(bundle);
 856     const char *mnemonic;
 857
 858     switch (OEY2(opc, mode)) {
 859     case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
 860     case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
 861     case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
 862     case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
 863     case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
 864     case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
 865     case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
 866
 867     case OEY2(ST1_OPCODE_Y2, MODE_OPCODE_YC2):
 868     case OEY2(ST2_OPCODE_Y2, MODE_OPCODE_YC2):
 869     case OEY2(ST4_OPCODE_Y2, MODE_OPCODE_YC2):
 870     case OEY2(ST_OPCODE_Y2, MODE_OPCODE_YC2):
 871
 872     default:
 873         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
 874     }
 875     qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
 876                   reg_names[srca], reg_names[srcbdest]);
 877     return TILEGX_EXCP_NONE;
 878 }
 879
 880 static TileExcp decode_x0(DisasContext *dc, tilegx_bundle_bits bundle)
 881 {
 882     unsigned opc = get_Opcode_X0(bundle);
 883     unsigned dest = get_Dest_X0(bundle);
 884     unsigned srca = get_SrcA_X0(bundle);
 885     unsigned ext, srcb, bfs, bfe;
 886     int imm;
 887
 888     switch (opc) {
 889     case RRR_0_OPCODE_X0:
 890         ext = get_RRROpcodeExtension_X0(bundle);
 891         if (ext == UNARY_RRR_0_OPCODE_X0) {
 892             ext = get_UnaryOpcodeExtension_X0(bundle);
 893             return gen_rr_opcode(dc, OE(opc, ext, X0), dest, srca);
 894         }
 895         srcb = get_SrcB_X0(bundle);
 896         return gen_rrr_opcode(dc, OE(opc, ext, X0), dest, srca, srcb);
 897
 898     case SHIFT_OPCODE_X0:
 899         ext = get_ShiftOpcodeExtension_X0(bundle);
 900         imm = get_ShAmt_X0(bundle);
 901         return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
 902
 903     case IMM8_OPCODE_X0:
 904         ext = get_Imm8OpcodeExtension_X0(bundle);
 905         imm = (int8_t)get_Imm8_X0(bundle);
 906         return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
 907
 908     case BF_OPCODE_X0:
 909         ext = get_BFOpcodeExtension_X0(bundle);
 910         bfs = get_BFStart_X0(bundle);
 911         bfe = get_BFEnd_X0(bundle);
 912         return gen_bf_opcode_x0(dc, ext, dest, srca, bfs, bfe);
 913
 914     case ADDLI_OPCODE_X0:
 915     case SHL16INSLI_OPCODE_X0:
 916     case ADDXLI_OPCODE_X0:
 917         imm = (int16_t)get_Imm16_X0(bundle);
 918         return gen_rri_opcode(dc, OE(opc, 0, X0), dest, srca, imm);
 919
 920     default:
 921         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
 922     }
 923 }
 924
 925 static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
 926 {
 927     unsigned opc = get_Opcode_X1(bundle);
 928     unsigned dest = get_Dest_X1(bundle);
 929     unsigned srca = get_SrcA_X1(bundle);
 930     unsigned ext, srcb;
 931     int imm;
 932
 933     switch (opc) {
 934     case RRR_0_OPCODE_X1:
 935         ext = get_RRROpcodeExtension_X1(bundle);
 936         if (ext == UNARY_RRR_0_OPCODE_X1) {
 937             ext = get_UnaryOpcodeExtension_X1(bundle);
 938             return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca);
 939         }
 940         srcb = get_SrcB_X1(bundle);
 941         return gen_rrr_opcode(dc, OE(opc, ext, X1), dest, srca, srcb);
 942
 943     case SHIFT_OPCODE_X1:
 944         ext = get_ShiftOpcodeExtension_X1(bundle);
 945         imm = get_ShAmt_X1(bundle);
 946         return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
 947
 948     case IMM8_OPCODE_X1:
 949         ext = get_Imm8OpcodeExtension_X1(bundle);
 950         imm = (int8_t)get_Imm8_X1(bundle);
 951         return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
 952
 953     case BRANCH_OPCODE_X1:
 954         ext = get_BrType_X1(bundle);
 955         imm = sextract32(get_BrOff_X1(bundle), 0, 17);
 956         return gen_branch_opcode_x1(dc, ext, srca, imm);
 957
 958     case JUMP_OPCODE_X1:
 959         ext = get_JumpOpcodeExtension_X1(bundle);
 960         imm = sextract32(get_JumpOff_X1(bundle), 0, 27);
 961         return gen_jump_opcode_x1(dc, ext, imm);
 962
 963     case ADDLI_OPCODE_X1:
 964     case SHL16INSLI_OPCODE_X1:
 965     case ADDXLI_OPCODE_X1:
 966         imm = (int16_t)get_Imm16_X1(bundle);
 967         return gen_rri_opcode(dc, OE(opc, 0, X1), dest, srca, imm);
 968
 969     default:
 970         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
 971     }
 972 }
 973
 974 static void notice_excp(DisasContext *dc, uint64_t bundle,
 975                         const char *type, TileExcp excp)
 976 {
 977     if (likely(excp == TILEGX_EXCP_NONE)) {
 978         return;
 979     }
 980     gen_exception(dc, excp);
 981     if (excp == TILEGX_EXCP_OPCODE_UNIMPLEMENTED) {
 982         qemu_log_mask(LOG_UNIMP, "UNIMP %s, [" FMT64X "]\n", type, bundle);
 983     }
 984 }
 985
 986 static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
 987 {
 988     int i;
 989
 990     for (i = 0; i < ARRAY_SIZE(dc->wb); i++) {
 991         DisasContextTemp *wb = &dc->wb[i];
 992         wb->reg = TILEGX_R_NOREG;
 993         TCGV_UNUSED_I64(wb->val);
 994     }
 995     dc->num_wb = 0;
 996
 997     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
 998         tcg_gen_debug_insn_start(dc->pc);
 999     }
1000
1001     qemu_log_mask(CPU_LOG_TB_IN_ASM, "  %" PRIx64 ":  { ", dc->pc);
1002     if (get_Mode(bundle)) {
1003         notice_excp(dc, bundle, "y0", decode_y0(dc, bundle));
1004         qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1005         notice_excp(dc, bundle, "y1", decode_y1(dc, bundle));
1006         qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1007         notice_excp(dc, bundle, "y2", decode_y2(dc, bundle));
1008     } else {
1009         notice_excp(dc, bundle, "x0", decode_x0(dc, bundle));
1010         qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1011         notice_excp(dc, bundle, "x1", decode_x1(dc, bundle));
1012     }
1013     qemu_log_mask(CPU_LOG_TB_IN_ASM, " }\n");
1014
1015     for (i = dc->num_wb - 1; i >= 0; --i) {
1016         DisasContextTemp *wb = &dc->wb[i];
1017         if (wb->reg < TILEGX_R_COUNT) {
1018             tcg_gen_mov_i64(cpu_regs[wb->reg], wb->val);
1019         }
1020         tcg_temp_free_i64(wb->val);
1021     }
1022
1023     if (dc->jmp.cond != TCG_COND_NEVER) {
1024         if (dc->jmp.cond == TCG_COND_ALWAYS) {
1025             tcg_gen_mov_i64(cpu_pc, dc->jmp.dest);
1026         } else {
1027             TCGv next = tcg_const_i64(dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
1028             tcg_gen_movcond_i64(dc->jmp.cond, cpu_pc,
1029                                 dc->jmp.val1, load_zero(dc),
1030                                 dc->jmp.dest, next);
1031             tcg_temp_free_i64(dc->jmp.val1);
1032             tcg_temp_free_i64(next);
1033         }
1034         tcg_temp_free_i64(dc->jmp.dest);
1035         tcg_gen_exit_tb(0);
1036         dc->exit_tb = true;
1037     }
1038 }
1039
1040 static inline void gen_intermediate_code_internal(TileGXCPU *cpu,
1041                                                   TranslationBlock *tb,
1042                                                   bool search_pc)
1043 {
1044     DisasContext ctx;
1045     DisasContext *dc = &ctx;
1046     CPUState *cs = CPU(cpu);
1047     CPUTLGState *env = &cpu->env;
1048     uint64_t pc_start = tb->pc;
1049     uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1050     int j, lj = -1;
1051     int num_insns = 0;
1052     int max_insns = tb->cflags & CF_COUNT_MASK;
1053
1054     dc->pc = pc_start;
1055     dc->mmuidx = 0;
1056     dc->exit_tb = false;
1057     dc->jmp.cond = TCG_COND_NEVER;
1058     TCGV_UNUSED_I64(dc->jmp.dest);
1059     TCGV_UNUSED_I64(dc->jmp.val1);
1060     TCGV_UNUSED_I64(dc->jmp.val2);
1061     TCGV_UNUSED_I64(dc->zero);
1062
1063     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1064         qemu_log("IN: %s\n", lookup_symbol(pc_start));
1065     }
1066     if (!max_insns) {
1067         max_insns = CF_COUNT_MASK;
1068     }
1069     if (cs->singlestep_enabled || singlestep) {
1070         max_insns = 1;
1071     }
1072     gen_tb_start(tb);
1073
1074     while (1) {
1075         if (search_pc) {
1076             j = tcg_op_buf_count();
1077             if (lj < j) {
1078                 lj++;
1079                 while (lj < j) {
1080                     tcg_ctx.gen_opc_instr_start[lj++] = 0;
1081                 }
1082             }
1083             tcg_ctx.gen_opc_pc[lj] = dc->pc;
1084             tcg_ctx.gen_opc_instr_start[lj] = 1;
1085             tcg_ctx.gen_opc_icount[lj] = num_insns;
1086         }
1087         translate_one_bundle(dc, cpu_ldq_data(env, dc->pc));
1088
1089         if (dc->exit_tb) {
1090             /* PC updated and EXIT_TB/GOTO_TB/exception emitted.  */
1091             break;
1092         }
1093         dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES;
1094         if (++num_insns >= max_insns
1095             || dc->pc >= next_page_start
1096             || tcg_op_buf_full()) {
1097             /* Ending the TB due to TB size or page boundary.  Set PC.  */
1098             tcg_gen_movi_tl(cpu_pc, dc->pc);
1099             tcg_gen_exit_tb(0);
1100             break;
1101         }
1102     }
1103
1104     gen_tb_end(tb, num_insns);
1105     if (search_pc) {
1106         j = tcg_op_buf_count();
1107         lj++;
1108         while (lj <= j) {
1109             tcg_ctx.gen_opc_instr_start[lj++] = 0;
1110         }
1111     } else {
1112         tb->size = dc->pc - pc_start;
1113         tb->icount = num_insns;
1114     }
1115
1116     qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
1117 }
1118
1119 void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
1120 {
1121     gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, false);
1122 }
1123
1124 void gen_intermediate_code_pc(CPUTLGState *env, struct TranslationBlock *tb)
1125 {
1126     gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, true);
1127 }
1128
1129 void restore_state_to_opc(CPUTLGState *env, TranslationBlock *tb, int pc_pos)
1130 {
1131     env->pc = tcg_ctx.gen_opc_pc[pc_pos];
1132 }
1133
1134 void tilegx_tcg_init(void)
1135 {
1136     int i;
1137
1138     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1139     cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUTLGState, pc), "pc");
1140     for (i = 0; i < TILEGX_R_COUNT; i++) {
1141         cpu_regs[i] = tcg_global_mem_new_i64(TCG_AREG0,
1142                                              offsetof(CPUTLGState, regs[i]),
1143                                              reg_names[i]);
1144     }
1145 }