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pc_q35: remove unnecessary m->alias assignment
[qemu/ar7.git] / hw / riscv / virt.c
blobd171e74f7b81a98d4430ba51ba4dad29fa35e26c
1 /*
2 * QEMU RISC-V VirtIO Board
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * RISC-V machine with 16550a UART and VirtIO MMIO
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
25 #include "qapi/error.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/sysbus.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial.h"
31 #include "target/riscv/cpu.h"
32 #include "hw/core/sysbus-fdt.h"
33 #include "target/riscv/pmu.h"
34 #include "hw/riscv/riscv_hart.h"
35 #include "hw/riscv/virt.h"
36 #include "hw/riscv/boot.h"
37 #include "hw/riscv/numa.h"
38 #include "kvm/kvm_riscv.h"
39 #include "hw/firmware/smbios.h"
40 #include "hw/intc/riscv_aclint.h"
41 #include "hw/intc/riscv_aplic.h"
42 #include "hw/intc/sifive_plic.h"
43 #include "hw/misc/sifive_test.h"
44 #include "hw/platform-bus.h"
45 #include "chardev/char.h"
46 #include "sysemu/device_tree.h"
47 #include "sysemu/sysemu.h"
48 #include "sysemu/tcg.h"
49 #include "sysemu/kvm.h"
50 #include "sysemu/tpm.h"
51 #include "sysemu/qtest.h"
52 #include "hw/pci/pci.h"
53 #include "hw/pci-host/gpex.h"
54 #include "hw/display/ramfb.h"
55 #include "hw/acpi/aml-build.h"
56 #include "qapi/qapi-visit-common.h"
57 #include "hw/virtio/virtio-iommu.h"
58
59 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
60 static bool virt_use_kvm_aia(RISCVVirtState *s)
61 {
62 return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
63 }
64
65 static bool virt_aclint_allowed(void)
66 {
67 return tcg_enabled() || qtest_enabled();
68 }
69
70 static const MemMapEntry virt_memmap[] = {
71 [VIRT_DEBUG] = { 0x0, 0x100 },
72 [VIRT_MROM] = { 0x1000, 0xf000 },
73 [VIRT_TEST] = { 0x100000, 0x1000 },
74 [VIRT_RTC] = { 0x101000, 0x1000 },
75 [VIRT_CLINT] = { 0x2000000, 0x10000 },
76 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
77 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
78 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 },
79 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
80 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
81 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
82 [VIRT_UART0] = { 0x10000000, 0x100 },
83 [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
84 [VIRT_FW_CFG] = { 0x10100000, 0x18 },
85 [VIRT_FLASH] = { 0x20000000, 0x4000000 },
86 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
87 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE },
88 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
89 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
90 [VIRT_DRAM] = { 0x80000000, 0x0 },
91 };
92
93 /* PCIe high mmio is fixed for RV32 */
94 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
95 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
96
97 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
98 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
99
100 static MemMapEntry virt_high_pcie_memmap;
101
102 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
103
104 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
105 const char *name,
106 const char *alias_prop_name)
107 {
108 /*
109 * Create a single flash device. We use the same parameters as
110 * the flash devices on the ARM virt board.
111 */
112 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
113
114 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
115 qdev_prop_set_uint8(dev, "width", 4);
116 qdev_prop_set_uint8(dev, "device-width", 2);
117 qdev_prop_set_bit(dev, "big-endian", false);
118 qdev_prop_set_uint16(dev, "id0", 0x89);
119 qdev_prop_set_uint16(dev, "id1", 0x18);
120 qdev_prop_set_uint16(dev, "id2", 0x00);
121 qdev_prop_set_uint16(dev, "id3", 0x00);
122 qdev_prop_set_string(dev, "name", name);
123
124 object_property_add_child(OBJECT(s), name, OBJECT(dev));
125 object_property_add_alias(OBJECT(s), alias_prop_name,
126 OBJECT(dev), "drive");
127
128 return PFLASH_CFI01(dev);
129 }
130
131 static void virt_flash_create(RISCVVirtState *s)
132 {
133 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
134 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
135 }
136
137 static void virt_flash_map1(PFlashCFI01 *flash,
138 hwaddr base, hwaddr size,
139 MemoryRegion *sysmem)
140 {
141 DeviceState *dev = DEVICE(flash);
142
143 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
144 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
145 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
146 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
147
148 memory_region_add_subregion(sysmem, base,
149 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
150 0));
151 }
152
153 static void virt_flash_map(RISCVVirtState *s,
154 MemoryRegion *sysmem)
155 {
156 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
157 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
158
159 virt_flash_map1(s->flash[0], flashbase, flashsize,
160 sysmem);
161 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
162 sysmem);
163 }
164
165 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
166 uint32_t irqchip_phandle)
167 {
168 int pin, dev;
169 uint32_t irq_map_stride = 0;
170 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS *
171 FDT_MAX_INT_MAP_WIDTH] = {};
172 uint32_t *irq_map = full_irq_map;
173
174 /* This code creates a standard swizzle of interrupts such that
175 * each device's first interrupt is based on it's PCI_SLOT number.
176 * (See pci_swizzle_map_irq_fn())
177 *
178 * We only need one entry per interrupt in the table (not one per
179 * possible slot) seeing the interrupt-map-mask will allow the table
180 * to wrap to any number of devices.
181 */
182 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
183 int devfn = dev * 0x8;
184
185 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
186 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
187 int i = 0;
188
189 /* Fill PCI address cells */
190 irq_map[i] = cpu_to_be32(devfn << 8);
191 i += FDT_PCI_ADDR_CELLS;
192
193 /* Fill PCI Interrupt cells */
194 irq_map[i] = cpu_to_be32(pin + 1);
195 i += FDT_PCI_INT_CELLS;
196
197 /* Fill interrupt controller phandle and cells */
198 irq_map[i++] = cpu_to_be32(irqchip_phandle);
199 irq_map[i++] = cpu_to_be32(irq_nr);
200 if (s->aia_type != VIRT_AIA_TYPE_NONE) {
201 irq_map[i++] = cpu_to_be32(0x4);
202 }
203
204 if (!irq_map_stride) {
205 irq_map_stride = i;
206 }
207 irq_map += irq_map_stride;
208 }
209 }
210
211 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
212 GPEX_NUM_IRQS * GPEX_NUM_IRQS *
213 irq_map_stride * sizeof(uint32_t));
214
215 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
216 0x1800, 0, 0, 0x7);
217 }
218
219 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
220 char *clust_name, uint32_t *phandle,
221 uint32_t *intc_phandles)
222 {
223 int cpu;
224 uint32_t cpu_phandle;
225 MachineState *ms = MACHINE(s);
226 bool is_32_bit = riscv_is_32bit(&s->soc[0]);
227 uint8_t satp_mode_max;
228
229 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
230 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];
231 g_autofree char *cpu_name = NULL;
232 g_autofree char *core_name = NULL;
233 g_autofree char *intc_name = NULL;
234 g_autofree char *sv_name = NULL;
235
236 cpu_phandle = (*phandle)++;
237
238 cpu_name = g_strdup_printf("/cpus/cpu@%d",
239 s->soc[socket].hartid_base + cpu);
240 qemu_fdt_add_subnode(ms->fdt, cpu_name);
241
242 if (cpu_ptr->cfg.satp_mode.supported != 0) {
243 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map);
244 sv_name = g_strdup_printf("riscv,%s",
245 satp_mode_str(satp_mode_max, is_32_bit));
246 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name);
247 }
248
249 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name);
250
251 if (cpu_ptr->cfg.ext_zicbom) {
252 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size",
253 cpu_ptr->cfg.cbom_blocksize);
254 }
255
256 if (cpu_ptr->cfg.ext_zicboz) {
257 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size",
258 cpu_ptr->cfg.cboz_blocksize);
259 }
260
261 if (cpu_ptr->cfg.ext_zicbop) {
262 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size",
263 cpu_ptr->cfg.cbop_blocksize);
264 }
265
266 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
267 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay");
268 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg",
269 s->soc[socket].hartid_base + cpu);
270 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu");
271 riscv_socket_fdt_write_id(ms, cpu_name, socket);
272 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle);
273
274 intc_phandles[cpu] = (*phandle)++;
275
276 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
277 qemu_fdt_add_subnode(ms->fdt, intc_name);
278 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle",
279 intc_phandles[cpu]);
280 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible",
281 "riscv,cpu-intc");
282 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0);
283 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1);
284
285 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
286 qemu_fdt_add_subnode(ms->fdt, core_name);
287 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle);
288 }
289 }
290
291 static void create_fdt_socket_memory(RISCVVirtState *s,
292 const MemMapEntry *memmap, int socket)
293 {
294 g_autofree char *mem_name = NULL;
295 uint64_t addr, size;
296 MachineState *ms = MACHINE(s);
297
298 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket);
299 size = riscv_socket_mem_size(ms, socket);
300 mem_name = g_strdup_printf("/memory@%lx", (long)addr);
301 qemu_fdt_add_subnode(ms->fdt, mem_name);
302 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg",
303 addr >> 32, addr, size >> 32, size);
304 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory");
305 riscv_socket_fdt_write_id(ms, mem_name, socket);
306 }
307
308 static void create_fdt_socket_clint(RISCVVirtState *s,
309 const MemMapEntry *memmap, int socket,
310 uint32_t *intc_phandles)
311 {
312 int cpu;
313 g_autofree char *clint_name = NULL;
314 g_autofree uint32_t *clint_cells = NULL;
315 unsigned long clint_addr;
316 MachineState *ms = MACHINE(s);
317 static const char * const clint_compat[2] = {
318 "sifive,clint0", "riscv,clint0"
319 };
320
321 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
322
323 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
324 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
325 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
326 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
327 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
328 }
329
330 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
331 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
332 qemu_fdt_add_subnode(ms->fdt, clint_name);
333 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
334 (char **)&clint_compat,
335 ARRAY_SIZE(clint_compat));
336 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg",
337 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
338 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended",
339 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
340 riscv_socket_fdt_write_id(ms, clint_name, socket);
341 }
342
343 static void create_fdt_socket_aclint(RISCVVirtState *s,
344 const MemMapEntry *memmap, int socket,
345 uint32_t *intc_phandles)
346 {
347 int cpu;
348 char *name;
349 unsigned long addr, size;
350 uint32_t aclint_cells_size;
351 g_autofree uint32_t *aclint_mswi_cells = NULL;
352 g_autofree uint32_t *aclint_sswi_cells = NULL;
353 g_autofree uint32_t *aclint_mtimer_cells = NULL;
354 MachineState *ms = MACHINE(s);
355
356 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
357 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
358 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
359
360 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
361 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
362 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT);
363 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
364 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER);
365 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
366 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT);
367 }
368 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
369
370 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
371 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
372 name = g_strdup_printf("/soc/mswi@%lx", addr);
373 qemu_fdt_add_subnode(ms->fdt, name);
374 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
375 "riscv,aclint-mswi");
376 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
377 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
378 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
379 aclint_mswi_cells, aclint_cells_size);
380 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
381 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
382 riscv_socket_fdt_write_id(ms, name, socket);
383 g_free(name);
384 }
385
386 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
387 addr = memmap[VIRT_CLINT].base +
388 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket);
389 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE;
390 } else {
391 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
392 (memmap[VIRT_CLINT].size * socket);
393 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
394 }
395 name = g_strdup_printf("/soc/mtimer@%lx", addr);
396 qemu_fdt_add_subnode(ms->fdt, name);
397 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
398 "riscv,aclint-mtimer");
399 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
400 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
401 0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
402 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
403 0x0, RISCV_ACLINT_DEFAULT_MTIME);
404 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
405 aclint_mtimer_cells, aclint_cells_size);
406 riscv_socket_fdt_write_id(ms, name, socket);
407 g_free(name);
408
409 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
410 addr = memmap[VIRT_ACLINT_SSWI].base +
411 (memmap[VIRT_ACLINT_SSWI].size * socket);
412 name = g_strdup_printf("/soc/sswi@%lx", addr);
413 qemu_fdt_add_subnode(ms->fdt, name);
414 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
415 "riscv,aclint-sswi");
416 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
417 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
418 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
419 aclint_sswi_cells, aclint_cells_size);
420 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
421 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
422 riscv_socket_fdt_write_id(ms, name, socket);
423 g_free(name);
424 }
425 }
426
427 static void create_fdt_socket_plic(RISCVVirtState *s,
428 const MemMapEntry *memmap, int socket,
429 uint32_t *phandle, uint32_t *intc_phandles,
430 uint32_t *plic_phandles)
431 {
432 int cpu;
433 g_autofree char *plic_name = NULL;
434 g_autofree uint32_t *plic_cells;
435 unsigned long plic_addr;
436 MachineState *ms = MACHINE(s);
437 static const char * const plic_compat[2] = {
438 "sifive,plic-1.0.0", "riscv,plic0"
439 };
440
441 plic_phandles[socket] = (*phandle)++;
442 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
443 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
444 qemu_fdt_add_subnode(ms->fdt, plic_name);
445 qemu_fdt_setprop_cell(ms->fdt, plic_name,
446 "#interrupt-cells", FDT_PLIC_INT_CELLS);
447 qemu_fdt_setprop_cell(ms->fdt, plic_name,
448 "#address-cells", FDT_PLIC_ADDR_CELLS);
449 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible",
450 (char **)&plic_compat,
451 ARRAY_SIZE(plic_compat));
452 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0);
453
454 if (kvm_enabled()) {
455 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
456
457 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
458 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
459 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
460 }
461
462 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
463 plic_cells,
464 s->soc[socket].num_harts * sizeof(uint32_t) * 2);
465 } else {
466 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
467
468 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
469 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
470 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
471 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
472 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
473 }
474
475 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
476 plic_cells,
477 s->soc[socket].num_harts * sizeof(uint32_t) * 4);
478 }
479
480 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg",
481 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
482 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev",
483 VIRT_IRQCHIP_NUM_SOURCES - 1);
484 riscv_socket_fdt_write_id(ms, plic_name, socket);
485 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle",
486 plic_phandles[socket]);
487
488 if (!socket) {
489 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name,
490 memmap[VIRT_PLATFORM_BUS].base,
491 memmap[VIRT_PLATFORM_BUS].size,
492 VIRT_PLATFORM_BUS_IRQ);
493 }
494 }
495
496 uint32_t imsic_num_bits(uint32_t count)
497 {
498 uint32_t ret = 0;
499
500 while (BIT(ret) < count) {
501 ret++;
502 }
503
504 return ret;
505 }
506
507 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr,
508 uint32_t *intc_phandles, uint32_t msi_phandle,
509 bool m_mode, uint32_t imsic_guest_bits)
510 {
511 int cpu, socket;
512 g_autofree char *imsic_name = NULL;
513 MachineState *ms = MACHINE(s);
514 int socket_count = riscv_socket_count(ms);
515 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size;
516 g_autofree uint32_t *imsic_cells = NULL;
517 g_autofree uint32_t *imsic_regs = NULL;
518
519 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);
520 imsic_regs = g_new0(uint32_t, socket_count * 4);
521
522 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
523 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
524 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
525 }
526
527 imsic_max_hart_per_socket = 0;
528 for (socket = 0; socket < socket_count; socket++) {
529 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
530 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
531 s->soc[socket].num_harts;
532 imsic_regs[socket * 4 + 0] = 0;
533 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
534 imsic_regs[socket * 4 + 2] = 0;
535 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
536 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
537 imsic_max_hart_per_socket = s->soc[socket].num_harts;
538 }
539 }
540
541 imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_addr);
542 qemu_fdt_add_subnode(ms->fdt, imsic_name);
543 qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics");
544 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
545 FDT_IMSIC_INT_CELLS);
546 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0);
547 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0);
548 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
549 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
550 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
551 socket_count * sizeof(uint32_t) * 4);
552 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
553 VIRT_IRQCHIP_NUM_MSIS);
554
555 if (imsic_guest_bits) {
556 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits",
557 imsic_guest_bits);
558 }
559
560 if (socket_count > 1) {
561 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
562 imsic_num_bits(imsic_max_hart_per_socket));
563 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
564 imsic_num_bits(socket_count));
565 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
566 IMSIC_MMIO_GROUP_MIN_SHIFT);
567 }
568 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle);
569 }
570
571 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
572 uint32_t *phandle, uint32_t *intc_phandles,
573 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
574 {
575 *msi_m_phandle = (*phandle)++;
576 *msi_s_phandle = (*phandle)++;
577
578 if (!kvm_enabled()) {
579 /* M-level IMSIC node */
580 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles,
581 *msi_m_phandle, true, 0);
582 }
583
584 /* S-level IMSIC node */
585 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles,
586 *msi_s_phandle, false,
587 imsic_num_bits(s->aia_guests + 1));
588
589 }
590
591 static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
592 unsigned long aplic_addr, uint32_t aplic_size,
593 uint32_t msi_phandle,
594 uint32_t *intc_phandles,
595 uint32_t aplic_phandle,
596 uint32_t aplic_child_phandle,
597 bool m_mode, int num_harts)
598 {
599 int cpu;
600 g_autofree char *aplic_name = NULL;
601 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2);
602 MachineState *ms = MACHINE(s);
603
604 for (cpu = 0; cpu < num_harts; cpu++) {
605 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
606 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
607 }
608
609 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
610 qemu_fdt_add_subnode(ms->fdt, aplic_name);
611 qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
612 qemu_fdt_setprop_cell(ms->fdt, aplic_name,
613 "#interrupt-cells", FDT_APLIC_INT_CELLS);
614 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
615
616 if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
617 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
618 aplic_cells, num_harts * sizeof(uint32_t) * 2);
619 } else {
620 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle);
621 }
622
623 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
624 0x0, aplic_addr, 0x0, aplic_size);
625 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
626 VIRT_IRQCHIP_NUM_SOURCES);
627
628 if (aplic_child_phandle) {
629 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
630 aplic_child_phandle);
631 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
632 aplic_child_phandle, 0x1,
633 VIRT_IRQCHIP_NUM_SOURCES);
634 }
635
636 riscv_socket_fdt_write_id(ms, aplic_name, socket);
637 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle);
638 }
639
640 static void create_fdt_socket_aplic(RISCVVirtState *s,
641 const MemMapEntry *memmap, int socket,
642 uint32_t msi_m_phandle,
643 uint32_t msi_s_phandle,
644 uint32_t *phandle,
645 uint32_t *intc_phandles,
646 uint32_t *aplic_phandles,
647 int num_harts)
648 {
649 g_autofree char *aplic_name = NULL;
650 unsigned long aplic_addr;
651 MachineState *ms = MACHINE(s);
652 uint32_t aplic_m_phandle, aplic_s_phandle;
653
654 aplic_m_phandle = (*phandle)++;
655 aplic_s_phandle = (*phandle)++;
656
657 if (!kvm_enabled()) {
658 /* M-level APLIC node */
659 aplic_addr = memmap[VIRT_APLIC_M].base +
660 (memmap[VIRT_APLIC_M].size * socket);
661 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size,
662 msi_m_phandle, intc_phandles,
663 aplic_m_phandle, aplic_s_phandle,
664 true, num_harts);
665 }
666
667 /* S-level APLIC node */
668 aplic_addr = memmap[VIRT_APLIC_S].base +
669 (memmap[VIRT_APLIC_S].size * socket);
670 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size,
671 msi_s_phandle, intc_phandles,
672 aplic_s_phandle, 0,
673 false, num_harts);
674
675 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
676
677 if (!socket) {
678 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name,
679 memmap[VIRT_PLATFORM_BUS].base,
680 memmap[VIRT_PLATFORM_BUS].size,
681 VIRT_PLATFORM_BUS_IRQ);
682 }
683
684 aplic_phandles[socket] = aplic_s_phandle;
685 }
686
687 static void create_fdt_pmu(RISCVVirtState *s)
688 {
689 g_autofree char *pmu_name = g_strdup_printf("/pmu");
690 MachineState *ms = MACHINE(s);
691 RISCVCPU hart = s->soc[0].harts[0];
692
693 qemu_fdt_add_subnode(ms->fdt, pmu_name);
694 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
695 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name);
696 }
697
698 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
699 uint32_t *phandle,
700 uint32_t *irq_mmio_phandle,
701 uint32_t *irq_pcie_phandle,
702 uint32_t *irq_virtio_phandle,
703 uint32_t *msi_pcie_phandle)
704 {
705 int socket, phandle_pos;
706 MachineState *ms = MACHINE(s);
707 uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
708 uint32_t xplic_phandles[MAX_NODES];
709 g_autofree uint32_t *intc_phandles = NULL;
710 int socket_count = riscv_socket_count(ms);
711
712 qemu_fdt_add_subnode(ms->fdt, "/cpus");
713 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency",
714 kvm_enabled() ?
715 kvm_riscv_get_timebase_frequency(first_cpu) :
716 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
717 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
718 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
719 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
720
721 intc_phandles = g_new0(uint32_t, ms->smp.cpus);
722
723 phandle_pos = ms->smp.cpus;
724 for (socket = (socket_count - 1); socket >= 0; socket--) {
725 g_autofree char *clust_name = NULL;
726 phandle_pos -= s->soc[socket].num_harts;
727
728 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
729 qemu_fdt_add_subnode(ms->fdt, clust_name);
730
731 create_fdt_socket_cpus(s, socket, clust_name, phandle,
732 &intc_phandles[phandle_pos]);
733
734 create_fdt_socket_memory(s, memmap, socket);
735
736 if (virt_aclint_allowed() && s->have_aclint) {
737 create_fdt_socket_aclint(s, memmap, socket,
738 &intc_phandles[phandle_pos]);
739 } else if (tcg_enabled()) {
740 create_fdt_socket_clint(s, memmap, socket,
741 &intc_phandles[phandle_pos]);
742 }
743 }
744
745 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
746 create_fdt_imsic(s, memmap, phandle, intc_phandles,
747 &msi_m_phandle, &msi_s_phandle);
748 *msi_pcie_phandle = msi_s_phandle;
749 }
750
751 /* KVM AIA only has one APLIC instance */
752 if (kvm_enabled() && virt_use_kvm_aia(s)) {
753 create_fdt_socket_aplic(s, memmap, 0,
754 msi_m_phandle, msi_s_phandle, phandle,
755 &intc_phandles[0], xplic_phandles,
756 ms->smp.cpus);
757 } else {
758 phandle_pos = ms->smp.cpus;
759 for (socket = (socket_count - 1); socket >= 0; socket--) {
760 phandle_pos -= s->soc[socket].num_harts;
761
762 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
763 create_fdt_socket_plic(s, memmap, socket, phandle,
764 &intc_phandles[phandle_pos],
765 xplic_phandles);
766 } else {
767 create_fdt_socket_aplic(s, memmap, socket,
768 msi_m_phandle, msi_s_phandle, phandle,
769 &intc_phandles[phandle_pos],
770 xplic_phandles,
771 s->soc[socket].num_harts);
772 }
773 }
774 }
775
776 if (kvm_enabled() && virt_use_kvm_aia(s)) {
777 *irq_mmio_phandle = xplic_phandles[0];
778 *irq_virtio_phandle = xplic_phandles[0];
779 *irq_pcie_phandle = xplic_phandles[0];
780 } else {
781 for (socket = 0; socket < socket_count; socket++) {
782 if (socket == 0) {
783 *irq_mmio_phandle = xplic_phandles[socket];
784 *irq_virtio_phandle = xplic_phandles[socket];
785 *irq_pcie_phandle = xplic_phandles[socket];
786 }
787 if (socket == 1) {
788 *irq_virtio_phandle = xplic_phandles[socket];
789 *irq_pcie_phandle = xplic_phandles[socket];
790 }
791 if (socket == 2) {
792 *irq_pcie_phandle = xplic_phandles[socket];
793 }
794 }
795 }
796
797 riscv_socket_fdt_write_distance_matrix(ms);
798 }
799
800 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
801 uint32_t irq_virtio_phandle)
802 {
803 int i;
804 MachineState *ms = MACHINE(s);
805
806 for (i = 0; i < VIRTIO_COUNT; i++) {
807 g_autofree char *name = g_strdup_printf("/soc/virtio_mmio@%lx",
808 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
809
810 qemu_fdt_add_subnode(ms->fdt, name);
811 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio");
812 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
813 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
814 0x0, memmap[VIRT_VIRTIO].size);
815 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
816 irq_virtio_phandle);
817 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
818 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts",
819 VIRTIO_IRQ + i);
820 } else {
821 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts",
822 VIRTIO_IRQ + i, 0x4);
823 }
824 }
825 }
826
827 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
828 uint32_t irq_pcie_phandle,
829 uint32_t msi_pcie_phandle)
830 {
831 g_autofree char *name = NULL;
832 MachineState *ms = MACHINE(s);
833
834 name = g_strdup_printf("/soc/pci@%lx",
835 (long) memmap[VIRT_PCIE_ECAM].base);
836 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells",
837 FDT_PCI_ADDR_CELLS);
838 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells",
839 FDT_PCI_INT_CELLS);
840 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2);
841 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
842 "pci-host-ecam-generic");
843 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci");
844 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0);
845 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0,
846 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
847 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0);
848 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
849 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle);
850 }
851 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0,
852 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
853 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges",
854 1, FDT_PCI_RANGE_IOPORT, 2, 0,
855 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
856 1, FDT_PCI_RANGE_MMIO,
857 2, memmap[VIRT_PCIE_MMIO].base,
858 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
859 1, FDT_PCI_RANGE_MMIO_64BIT,
860 2, virt_high_pcie_memmap.base,
861 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
862
863 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle);
864 }
865
866 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap,
867 uint32_t *phandle)
868 {
869 char *name;
870 uint32_t test_phandle;
871 MachineState *ms = MACHINE(s);
872
873 test_phandle = (*phandle)++;
874 name = g_strdup_printf("/soc/test@%lx",
875 (long)memmap[VIRT_TEST].base);
876 qemu_fdt_add_subnode(ms->fdt, name);
877 {
878 static const char * const compat[3] = {
879 "sifive,test1", "sifive,test0", "syscon"
880 };
881 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible",
882 (char **)&compat, ARRAY_SIZE(compat));
883 }
884 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
885 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size);
886 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle);
887 test_phandle = qemu_fdt_get_phandle(ms->fdt, name);
888 g_free(name);
889
890 name = g_strdup_printf("/reboot");
891 qemu_fdt_add_subnode(ms->fdt, name);
892 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot");
893 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
894 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
895 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET);
896 g_free(name);
897
898 name = g_strdup_printf("/poweroff");
899 qemu_fdt_add_subnode(ms->fdt, name);
900 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff");
901 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
902 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
903 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS);
904 g_free(name);
905 }
906
907 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
908 uint32_t irq_mmio_phandle)
909 {
910 g_autofree char *name = NULL;
911 MachineState *ms = MACHINE(s);
912
913 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base);
914 qemu_fdt_add_subnode(ms->fdt, name);
915 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a");
916 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
917 0x0, memmap[VIRT_UART0].base,
918 0x0, memmap[VIRT_UART0].size);
919 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400);
920 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle);
921 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
922 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ);
923 } else {
924 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4);
925 }
926
927 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name);
928 }
929
930 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
931 uint32_t irq_mmio_phandle)
932 {
933 g_autofree char *name = NULL;
934 MachineState *ms = MACHINE(s);
935
936 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
937 qemu_fdt_add_subnode(ms->fdt, name);
938 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
939 "google,goldfish-rtc");
940 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
941 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
942 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
943 irq_mmio_phandle);
944 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
945 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ);
946 } else {
947 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4);
948 }
949 }
950
951 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
952 {
953 MachineState *ms = MACHINE(s);
954 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
955 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
956 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase);
957
958 qemu_fdt_add_subnode(ms->fdt, name);
959 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash");
960 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
961 2, flashbase, 2, flashsize,
962 2, flashbase + flashsize, 2, flashsize);
963 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4);
964 }
965
966 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
967 {
968 MachineState *ms = MACHINE(s);
969 hwaddr base = memmap[VIRT_FW_CFG].base;
970 hwaddr size = memmap[VIRT_FW_CFG].size;
971 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
972
973 qemu_fdt_add_subnode(ms->fdt, nodename);
974 qemu_fdt_setprop_string(ms->fdt, nodename,
975 "compatible", "qemu,fw-cfg-mmio");
976 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
977 2, base, 2, size);
978 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
979 }
980
981 static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf)
982 {
983 const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
984 void *fdt = MACHINE(s)->fdt;
985 uint32_t iommu_phandle;
986 g_autofree char *iommu_node = NULL;
987 g_autofree char *pci_node = NULL;
988
989 pci_node = g_strdup_printf("/soc/pci@%lx",
990 (long) virt_memmap[VIRT_PCIE_ECAM].base);
991 iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node,
992 PCI_SLOT(bdf), PCI_FUNC(bdf));
993 iommu_phandle = qemu_fdt_alloc_phandle(fdt);
994
995 qemu_fdt_add_subnode(fdt, iommu_node);
996
997 qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat));
998 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg",
999 1, bdf << 8, 1, 0, 1, 0,
1000 1, 0, 1, 0);
1001 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
1002 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
1003
1004 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map",
1005 0, iommu_phandle, 0, bdf,
1006 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
1007 }
1008
1009 static void finalize_fdt(RISCVVirtState *s)
1010 {
1011 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
1012 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
1013
1014 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle,
1015 &irq_pcie_phandle, &irq_virtio_phandle,
1016 &msi_pcie_phandle);
1017
1018 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle);
1019
1020 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle);
1021
1022 create_fdt_reset(s, virt_memmap, &phandle);
1023
1024 create_fdt_uart(s, virt_memmap, irq_mmio_phandle);
1025
1026 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle);
1027 }
1028
1029 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
1030 {
1031 MachineState *ms = MACHINE(s);
1032 uint8_t rng_seed[32];
1033 g_autofree char *name = NULL;
1034
1035 ms->fdt = create_device_tree(&s->fdt_size);
1036 if (!ms->fdt) {
1037 error_report("create_device_tree() failed");
1038 exit(1);
1039 }
1040
1041 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu");
1042 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio");
1043 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2);
1044 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2);
1045
1046 qemu_fdt_add_subnode(ms->fdt, "/soc");
1047 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0);
1048 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus");
1049 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2);
1050 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2);
1051
1052 /*
1053 * The "/soc/pci@..." node is needed for PCIE hotplugs
1054 * that might happen before finalize_fdt().
1055 */
1056 name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base);
1057 qemu_fdt_add_subnode(ms->fdt, name);
1058
1059 qemu_fdt_add_subnode(ms->fdt, "/chosen");
1060
1061 /* Pass seed to RNG */
1062 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
1063 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed",
1064 rng_seed, sizeof(rng_seed));
1065
1066 create_fdt_flash(s, memmap);
1067 create_fdt_fw_cfg(s, memmap);
1068 create_fdt_pmu(s);
1069 }
1070
1071 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
1072 DeviceState *irqchip,
1073 RISCVVirtState *s)
1074 {
1075 DeviceState *dev;
1076 MemoryRegion *ecam_alias, *ecam_reg;
1077 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
1078 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base;
1079 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size;
1080 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base;
1081 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size;
1082 hwaddr high_mmio_base = virt_high_pcie_memmap.base;
1083 hwaddr high_mmio_size = virt_high_pcie_memmap.size;
1084 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base;
1085 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size;
1086 qemu_irq irq;
1087 int i;
1088
1089 dev = qdev_new(TYPE_GPEX_HOST);
1090
1091 /* Set GPEX object properties for the virt machine */
1092 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE,
1093 ecam_base, NULL);
1094 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE,
1095 ecam_size, NULL);
1096 object_property_set_uint(OBJECT(GPEX_HOST(dev)),
1097 PCI_HOST_BELOW_4G_MMIO_BASE,
1098 mmio_base, NULL);
1099 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE,
1100 mmio_size, NULL);
1101 object_property_set_uint(OBJECT(GPEX_HOST(dev)),
1102 PCI_HOST_ABOVE_4G_MMIO_BASE,
1103 high_mmio_base, NULL);
1104 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE,
1105 high_mmio_size, NULL);
1106 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE,
1107 pio_base, NULL);
1108 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE,
1109 pio_size, NULL);
1110
1111 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1112
1113 ecam_alias = g_new0(MemoryRegion, 1);
1114 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1115 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1116 ecam_reg, 0, ecam_size);
1117 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
1118
1119 mmio_alias = g_new0(MemoryRegion, 1);
1120 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1121 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1122 mmio_reg, mmio_base, mmio_size);
1123 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
1124
1125 /* Map high MMIO space */
1126 high_mmio_alias = g_new0(MemoryRegion, 1);
1127 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1128 mmio_reg, high_mmio_base, high_mmio_size);
1129 memory_region_add_subregion(get_system_memory(), high_mmio_base,
1130 high_mmio_alias);
1131
1132 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
1133
1134 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1135 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i);
1136
1137 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
1138 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
1139 }
1140
1141 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus;
1142 return dev;
1143 }
1144
1145 static FWCfgState *create_fw_cfg(const MachineState *ms)
1146 {
1147 hwaddr base = virt_memmap[VIRT_FW_CFG].base;
1148 FWCfgState *fw_cfg;
1149
1150 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
1151 &address_space_memory);
1152 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1153
1154 return fw_cfg;
1155 }
1156
1157 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
1158 int base_hartid, int hart_count)
1159 {
1160 DeviceState *ret;
1161 g_autofree char *plic_hart_config = NULL;
1162
1163 /* Per-socket PLIC hart topology configuration string */
1164 plic_hart_config = riscv_plic_hart_config_string(hart_count);
1165
1166 /* Per-socket PLIC */
1167 ret = sifive_plic_create(
1168 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size,
1169 plic_hart_config, hart_count, base_hartid,
1170 VIRT_IRQCHIP_NUM_SOURCES,
1171 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1),
1172 VIRT_PLIC_PRIORITY_BASE,
1173 VIRT_PLIC_PENDING_BASE,
1174 VIRT_PLIC_ENABLE_BASE,
1175 VIRT_PLIC_ENABLE_STRIDE,
1176 VIRT_PLIC_CONTEXT_BASE,
1177 VIRT_PLIC_CONTEXT_STRIDE,
1178 memmap[VIRT_PLIC].size);
1179
1180 return ret;
1181 }
1182
1183 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
1184 const MemMapEntry *memmap, int socket,
1185 int base_hartid, int hart_count)
1186 {
1187 int i;
1188 hwaddr addr;
1189 uint32_t guest_bits;
1190 DeviceState *aplic_s = NULL;
1191 DeviceState *aplic_m = NULL;
1192 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
1193
1194 if (msimode) {
1195 if (!kvm_enabled()) {
1196 /* Per-socket M-level IMSICs */
1197 addr = memmap[VIRT_IMSIC_M].base +
1198 socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1199 for (i = 0; i < hart_count; i++) {
1200 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
1201 base_hartid + i, true, 1,
1202 VIRT_IRQCHIP_NUM_MSIS);
1203 }
1204 }
1205
1206 /* Per-socket S-level IMSICs */
1207 guest_bits = imsic_num_bits(aia_guests + 1);
1208 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1209 for (i = 0; i < hart_count; i++) {
1210 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),
1211 base_hartid + i, false, 1 + aia_guests,
1212 VIRT_IRQCHIP_NUM_MSIS);
1213 }
1214 }
1215
1216 if (!kvm_enabled()) {
1217 /* Per-socket M-level APLIC */
1218 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base +
1219 socket * memmap[VIRT_APLIC_M].size,
1220 memmap[VIRT_APLIC_M].size,
1221 (msimode) ? 0 : base_hartid,
1222 (msimode) ? 0 : hart_count,
1223 VIRT_IRQCHIP_NUM_SOURCES,
1224 VIRT_IRQCHIP_NUM_PRIO_BITS,
1225 msimode, true, NULL);
1226 }
1227
1228 /* Per-socket S-level APLIC */
1229 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base +
1230 socket * memmap[VIRT_APLIC_S].size,
1231 memmap[VIRT_APLIC_S].size,
1232 (msimode) ? 0 : base_hartid,
1233 (msimode) ? 0 : hart_count,
1234 VIRT_IRQCHIP_NUM_SOURCES,
1235 VIRT_IRQCHIP_NUM_PRIO_BITS,
1236 msimode, false, aplic_m);
1237
1238 return kvm_enabled() ? aplic_s : aplic_m;
1239 }
1240
1241 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)
1242 {
1243 DeviceState *dev;
1244 SysBusDevice *sysbus;
1245 const MemMapEntry *memmap = virt_memmap;
1246 int i;
1247 MemoryRegion *sysmem = get_system_memory();
1248
1249 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1250 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1251 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS);
1252 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size);
1253 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1254 s->platform_bus_dev = dev;
1255
1256 sysbus = SYS_BUS_DEVICE(dev);
1257 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {
1258 int irq = VIRT_PLATFORM_BUS_IRQ + i;
1259 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq));
1260 }
1261
1262 memory_region_add_subregion(sysmem,
1263 memmap[VIRT_PLATFORM_BUS].base,
1264 sysbus_mmio_get_region(sysbus, 0));
1265 }
1266
1267 static void virt_build_smbios(RISCVVirtState *s)
1268 {
1269 MachineClass *mc = MACHINE_GET_CLASS(s);
1270 MachineState *ms = MACHINE(s);
1271 uint8_t *smbios_tables, *smbios_anchor;
1272 size_t smbios_tables_len, smbios_anchor_len;
1273 struct smbios_phys_mem_area mem_array;
1274 const char *product = "QEMU Virtual Machine";
1275
1276 if (kvm_enabled()) {
1277 product = "KVM Virtual Machine";
1278 }
1279
1280 smbios_set_defaults("QEMU", product, mc->name, true);
1281
1282 if (riscv_is_32bit(&s->soc[0])) {
1283 smbios_set_default_processor_family(0x200);
1284 } else {
1285 smbios_set_default_processor_family(0x201);
1286 }
1287
1288 /* build the array of physical mem area from base_memmap */
1289 mem_array.address = s->memmap[VIRT_DRAM].base;
1290 mem_array.length = ms->ram_size;
1291
1292 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64,
1293 &mem_array, 1,
1294 &smbios_tables, &smbios_tables_len,
1295 &smbios_anchor, &smbios_anchor_len,
1296 &error_fatal);
1297
1298 if (smbios_anchor) {
1299 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables",
1300 smbios_tables, smbios_tables_len);
1301 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor",
1302 smbios_anchor, smbios_anchor_len);
1303 }
1304 }
1305
1306 static void virt_machine_done(Notifier *notifier, void *data)
1307 {
1308 RISCVVirtState *s = container_of(notifier, RISCVVirtState,
1309 machine_done);
1310 const MemMapEntry *memmap = virt_memmap;
1311 MachineState *machine = MACHINE(s);
1312 target_ulong start_addr = memmap[VIRT_DRAM].base;
1313 target_ulong firmware_end_addr, kernel_start_addr;
1314 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
1315 uint64_t fdt_load_addr;
1316 uint64_t kernel_entry = 0;
1317 BlockBackend *pflash_blk0;
1318
1319 /*
1320 * An user provided dtb must include everything, including
1321 * dynamic sysbus devices. Our FDT needs to be finalized.
1322 */
1323 if (machine->dtb == NULL) {
1324 finalize_fdt(s);
1325 }
1326
1327 /*
1328 * Only direct boot kernel is currently supported for KVM VM,
1329 * so the "-bios" parameter is not supported when KVM is enabled.
1330 */
1331 if (kvm_enabled()) {
1332 if (machine->firmware) {
1333 if (strcmp(machine->firmware, "none")) {
1334 error_report("Machine mode firmware is not supported in "
1335 "combination with KVM.");
1336 exit(1);
1337 }
1338 } else {
1339 machine->firmware = g_strdup("none");
1340 }
1341 }
1342
1343 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
1344 start_addr, NULL);
1345
1346 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]);
1347 if (pflash_blk0) {
1348 if (machine->firmware && !strcmp(machine->firmware, "none") &&
1349 !kvm_enabled()) {
1350 /*
1351 * Pflash was supplied but bios is none and not KVM guest,
1352 * let's overwrite the address we jump to after reset to
1353 * the base of the flash.
1354 */
1355 start_addr = virt_memmap[VIRT_FLASH].base;
1356 } else {
1357 /*
1358 * Pflash was supplied but either KVM guest or bios is not none.
1359 * In this case, base of the flash would contain S-mode payload.
1360 */
1361 riscv_setup_firmware_boot(machine);
1362 kernel_entry = virt_memmap[VIRT_FLASH].base;
1363 }
1364 }
1365
1366 if (machine->kernel_filename && !kernel_entry) {
1367 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
1368 firmware_end_addr);
1369
1370 kernel_entry = riscv_load_kernel(machine, &s->soc[0],
1371 kernel_start_addr, true, NULL);
1372 }
1373
1374 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
1375 memmap[VIRT_DRAM].size,
1376 machine);
1377 riscv_load_fdt(fdt_load_addr, machine->fdt);
1378
1379 /* load the reset vector */
1380 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
1381 virt_memmap[VIRT_MROM].base,
1382 virt_memmap[VIRT_MROM].size, kernel_entry,
1383 fdt_load_addr);
1384
1385 /*
1386 * Only direct boot kernel is currently supported for KVM VM,
1387 * So here setup kernel start address and fdt address.
1388 * TODO:Support firmware loading and integrate to TCG start
1389 */
1390 if (kvm_enabled()) {
1391 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
1392 }
1393
1394 virt_build_smbios(s);
1395
1396 if (virt_is_acpi_enabled(s)) {
1397 virt_acpi_setup(s);
1398 }
1399 }
1400
1401 static void virt_machine_init(MachineState *machine)
1402 {
1403 const MemMapEntry *memmap = virt_memmap;
1404 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
1405 MemoryRegion *system_memory = get_system_memory();
1406 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
1407 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
1408 int i, base_hartid, hart_count;
1409 int socket_count = riscv_socket_count(machine);
1410
1411 /* Check socket count limit */
1412 if (VIRT_SOCKETS_MAX < socket_count) {
1413 error_report("number of sockets/nodes should be less than %d",
1414 VIRT_SOCKETS_MAX);
1415 exit(1);
1416 }
1417
1418 if (!virt_aclint_allowed() && s->have_aclint) {
1419 error_report("'aclint' is only available with TCG acceleration");
1420 exit(1);
1421 }
1422
1423 /* Initialize sockets */
1424 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
1425 for (i = 0; i < socket_count; i++) {
1426 g_autofree char *soc_name = g_strdup_printf("soc%d", i);
1427
1428 if (!riscv_socket_check_hartids(machine, i)) {
1429 error_report("discontinuous hartids in socket%d", i);
1430 exit(1);
1431 }
1432
1433 base_hartid = riscv_socket_first_hartid(machine, i);
1434 if (base_hartid < 0) {
1435 error_report("can't find hartid base for socket%d", i);
1436 exit(1);
1437 }
1438
1439 hart_count = riscv_socket_hart_count(machine, i);
1440 if (hart_count < 0) {
1441 error_report("can't find hart count for socket%d", i);
1442 exit(1);
1443 }
1444
1445 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
1446 TYPE_RISCV_HART_ARRAY);
1447 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
1448 machine->cpu_type, &error_abort);
1449 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
1450 base_hartid, &error_abort);
1451 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
1452 hart_count, &error_abort);
1453 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
1454
1455 if (virt_aclint_allowed() && s->have_aclint) {
1456 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
1457 /* Per-socket ACLINT MTIMER */
1458 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1459 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1460 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1461 base_hartid, hart_count,
1462 RISCV_ACLINT_DEFAULT_MTIMECMP,
1463 RISCV_ACLINT_DEFAULT_MTIME,
1464 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1465 } else {
1466 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
1467 riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
1468 i * memmap[VIRT_CLINT].size,
1469 base_hartid, hart_count, false);
1470 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1471 i * memmap[VIRT_CLINT].size +
1472 RISCV_ACLINT_SWI_SIZE,
1473 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1474 base_hartid, hart_count,
1475 RISCV_ACLINT_DEFAULT_MTIMECMP,
1476 RISCV_ACLINT_DEFAULT_MTIME,
1477 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1478 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
1479 i * memmap[VIRT_ACLINT_SSWI].size,
1480 base_hartid, hart_count, true);
1481 }
1482 } else if (tcg_enabled()) {
1483 /* Per-socket SiFive CLINT */
1484 riscv_aclint_swi_create(
1485 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
1486 base_hartid, hart_count, false);
1487 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1488 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
1489 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
1490 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
1491 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1492 }
1493
1494 /* Per-socket interrupt controller */
1495 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
1496 s->irqchip[i] = virt_create_plic(memmap, i,
1497 base_hartid, hart_count);
1498 } else {
1499 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests,
1500 memmap, i, base_hartid,
1501 hart_count);
1502 }
1503
1504 /* Try to use different IRQCHIP instance based device type */
1505 if (i == 0) {
1506 mmio_irqchip = s->irqchip[i];
1507 virtio_irqchip = s->irqchip[i];
1508 pcie_irqchip = s->irqchip[i];
1509 }
1510 if (i == 1) {
1511 virtio_irqchip = s->irqchip[i];
1512 pcie_irqchip = s->irqchip[i];
1513 }
1514 if (i == 2) {
1515 pcie_irqchip = s->irqchip[i];
1516 }
1517 }
1518
1519 if (kvm_enabled() && virt_use_kvm_aia(s)) {
1520 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT,
1521 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS,
1522 memmap[VIRT_APLIC_S].base,
1523 memmap[VIRT_IMSIC_S].base,
1524 s->aia_guests);
1525 }
1526
1527 if (riscv_is_32bit(&s->soc[0])) {
1528 #if HOST_LONG_BITS == 64
1529 /* limit RAM size in a 32-bit system */
1530 if (machine->ram_size > 10 * GiB) {
1531 machine->ram_size = 10 * GiB;
1532 error_report("Limiting RAM size to 10 GiB");
1533 }
1534 #endif
1535 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
1536 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
1537 } else {
1538 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
1539 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
1540 virt_high_pcie_memmap.base =
1541 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
1542 }
1543
1544 s->memmap = virt_memmap;
1545
1546 /* register system main memory (actual RAM) */
1547 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
1548 machine->ram);
1549
1550 /* boot rom */
1551 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
1552 memmap[VIRT_MROM].size, &error_fatal);
1553 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
1554 mask_rom);
1555
1556 /*
1557 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the
1558 * device tree cannot be altered and we get FDT_ERR_NOSPACE.
1559 */
1560 s->fw_cfg = create_fw_cfg(machine);
1561 rom_set_fw(s->fw_cfg);
1562
1563 /* SiFive Test MMIO device */
1564 sifive_test_create(memmap[VIRT_TEST].base);
1565
1566 /* VirtIO MMIO devices */
1567 for (i = 0; i < VIRTIO_COUNT; i++) {
1568 sysbus_create_simple("virtio-mmio",
1569 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
1570 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
1571 }
1572
1573 gpex_pcie_init(system_memory, pcie_irqchip, s);
1574
1575 create_platform_bus(s, mmio_irqchip);
1576
1577 serial_mm_init(system_memory, memmap[VIRT_UART0].base,
1578 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193,
1579 serial_hd(0), DEVICE_LITTLE_ENDIAN);
1580
1581 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
1582 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ));
1583
1584 for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
1585 /* Map legacy -drive if=pflash to machine properties */
1586 pflash_cfi01_legacy_drive(s->flash[i],
1587 drive_get(IF_PFLASH, 0, i));
1588 }
1589 virt_flash_map(s, system_memory);
1590
1591 /* load/create device tree */
1592 if (machine->dtb) {
1593 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size);
1594 if (!machine->fdt) {
1595 error_report("load_device_tree() failed");
1596 exit(1);
1597 }
1598 } else {
1599 create_fdt(s, memmap);
1600 }
1601
1602 s->machine_done.notify = virt_machine_done;
1603 qemu_add_machine_init_done_notifier(&s->machine_done);
1604 }
1605
1606 static void virt_machine_instance_init(Object *obj)
1607 {
1608 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1609
1610 virt_flash_create(s);
1611
1612 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
1613 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
1614 s->acpi = ON_OFF_AUTO_AUTO;
1615 }
1616
1617 static char *virt_get_aia_guests(Object *obj, Error **errp)
1618 {
1619 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1620 char val[32];
1621
1622 sprintf(val, "%d", s->aia_guests);
1623 return g_strdup(val);
1624 }
1625
1626 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp)
1627 {
1628 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1629
1630 s->aia_guests = atoi(val);
1631 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) {
1632 error_setg(errp, "Invalid number of AIA IMSIC guests");
1633 error_append_hint(errp, "Valid values be between 0 and %d.\n",
1634 VIRT_IRQCHIP_MAX_GUESTS);
1635 }
1636 }
1637
1638 static char *virt_get_aia(Object *obj, Error **errp)
1639 {
1640 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1641 const char *val;
1642
1643 switch (s->aia_type) {
1644 case VIRT_AIA_TYPE_APLIC:
1645 val = "aplic";
1646 break;
1647 case VIRT_AIA_TYPE_APLIC_IMSIC:
1648 val = "aplic-imsic";
1649 break;
1650 default:
1651 val = "none";
1652 break;
1653 };
1654
1655 return g_strdup(val);
1656 }
1657
1658 static void virt_set_aia(Object *obj, const char *val, Error **errp)
1659 {
1660 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1661
1662 if (!strcmp(val, "none")) {
1663 s->aia_type = VIRT_AIA_TYPE_NONE;
1664 } else if (!strcmp(val, "aplic")) {
1665 s->aia_type = VIRT_AIA_TYPE_APLIC;
1666 } else if (!strcmp(val, "aplic-imsic")) {
1667 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC;
1668 } else {
1669 error_setg(errp, "Invalid AIA interrupt controller type");
1670 error_append_hint(errp, "Valid values are none, aplic, and "
1671 "aplic-imsic.\n");
1672 }
1673 }
1674
1675 static bool virt_get_aclint(Object *obj, Error **errp)
1676 {
1677 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1678
1679 return s->have_aclint;
1680 }
1681
1682 static void virt_set_aclint(Object *obj, bool value, Error **errp)
1683 {
1684 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1685
1686 s->have_aclint = value;
1687 }
1688
1689 bool virt_is_acpi_enabled(RISCVVirtState *s)
1690 {
1691 return s->acpi != ON_OFF_AUTO_OFF;
1692 }
1693
1694 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
1695 void *opaque, Error **errp)
1696 {
1697 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1698 OnOffAuto acpi = s->acpi;
1699
1700 visit_type_OnOffAuto(v, name, &acpi, errp);
1701 }
1702
1703 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
1704 void *opaque, Error **errp)
1705 {
1706 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1707
1708 visit_type_OnOffAuto(v, name, &s->acpi, errp);
1709 }
1710
1711 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1712 DeviceState *dev)
1713 {
1714 MachineClass *mc = MACHINE_GET_CLASS(machine);
1715
1716 if (device_is_dynamic_sysbus(mc, dev) ||
1717 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1718 return HOTPLUG_HANDLER(machine);
1719 }
1720 return NULL;
1721 }
1722
1723 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1724 DeviceState *dev, Error **errp)
1725 {
1726 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev);
1727
1728 if (s->platform_bus_dev) {
1729 MachineClass *mc = MACHINE_GET_CLASS(s);
1730
1731 if (device_is_dynamic_sysbus(mc, dev)) {
1732 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev),
1733 SYS_BUS_DEVICE(dev));
1734 }
1735 }
1736
1737 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1738 create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev)));
1739 }
1740 }
1741
1742 static void virt_machine_class_init(ObjectClass *oc, void *data)
1743 {
1744 char str[128];
1745 MachineClass *mc = MACHINE_CLASS(oc);
1746 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1747
1748 mc->desc = "RISC-V VirtIO board";
1749 mc->init = virt_machine_init;
1750 mc->max_cpus = VIRT_CPUS_MAX;
1751 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
1752 mc->pci_allow_0_address = true;
1753 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
1754 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
1755 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
1756 mc->numa_mem_supported = true;
1757 /* platform instead of architectural choice */
1758 mc->cpu_cluster_has_numa_boundary = true;
1759 mc->default_ram_id = "riscv_virt_board.ram";
1760 assert(!mc->get_hotplug_handler);
1761 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1762
1763 hc->plug = virt_machine_device_plug_cb;
1764
1765 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1766 #ifdef CONFIG_TPM
1767 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
1768 #endif
1769
1770
1771 object_class_property_add_bool(oc, "aclint", virt_get_aclint,
1772 virt_set_aclint);
1773 object_class_property_set_description(oc, "aclint",
1774 "(TCG only) Set on/off to "
1775 "enable/disable emulating "
1776 "ACLINT devices");
1777
1778 object_class_property_add_str(oc, "aia", virt_get_aia,
1779 virt_set_aia);
1780 object_class_property_set_description(oc, "aia",
1781 "Set type of AIA interrupt "
1782 "controller. Valid values are "
1783 "none, aplic, and aplic-imsic.");
1784
1785 object_class_property_add_str(oc, "aia-guests",
1786 virt_get_aia_guests,
1787 virt_set_aia_guests);
1788 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value "
1789 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS);
1790 object_class_property_set_description(oc, "aia-guests", str);
1791 object_class_property_add(oc, "acpi", "OnOffAuto",
1792 virt_get_acpi, virt_set_acpi,
1793 NULL, NULL);
1794 object_class_property_set_description(oc, "acpi",
1795 "Enable ACPI");
1796 }
1797
1798 static const TypeInfo virt_machine_typeinfo = {
1799 .name = MACHINE_TYPE_NAME("virt"),
1800 .parent = TYPE_MACHINE,
1801 .class_init = virt_machine_class_init,
1802 .instance_init = virt_machine_instance_init,
1803 .instance_size = sizeof(RISCVVirtState),
1804 .interfaces = (InterfaceInfo[]) {
1805 { TYPE_HOTPLUG_HANDLER },
1806 { }
1807 },
1808 };
1809
1810 static void virt_machine_init_register_types(void)
1811 {
1812 type_register_static(&virt_machine_typeinfo);
1813 }
1814
1815 type_init(virt_machine_init_register_types)
AR7 emulation for QEMU