hw/misc/mchp_pfsoc_sysreg.c

   1 /*
   2  * Microchip PolarFire SoC SYSREG module emulation
   3  *
   4  * Copyright (c) 2020 Wind River Systems, Inc.
   5  *
   6  * Author:
   7  *   Bin Meng <bin.meng@windriver.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 or
  12  * (at your option) version 3 of the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "qemu/bitops.h"
  25 #include "qemu/log.h"
  26 #include "qapi/error.h"
  27 #include "hw/irq.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/misc/mchp_pfsoc_sysreg.h"
  30
  31 #define ENVM_CR         0xb8
  32 #define MESSAGE_INT     0x118c
  33
  34 static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
  35                                        unsigned size)
  36 {
  37     uint32_t val = 0;
  38
  39     switch (offset) {
  40     case ENVM_CR:
  41         /* Indicate the eNVM is running at the configured divider rate */
  42         val = BIT(6);
  43         break;
  44     default:
  45         qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
  46                       "(size %d, offset 0x%" HWADDR_PRIx ")\n",
  47                       __func__, size, offset);
  48         break;
  49     }
  50
  51     return val;
  52 }
  53
  54 static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
  55                                     uint64_t value, unsigned size)
  56 {
  57     MchpPfSoCSysregState *s = opaque;
  58     switch (offset) {
  59     case MESSAGE_INT:
  60         qemu_irq_lower(s->irq);
  61         break;
  62     default:
  63         qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
  64                       "(size %d, value 0x%" PRIx64
  65                       ", offset 0x%" HWADDR_PRIx ")\n",
  66                       __func__, size, value, offset);
  67     }
  68 }
  69
  70 static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
  71     .read = mchp_pfsoc_sysreg_read,
  72     .write = mchp_pfsoc_sysreg_write,
  73     .endianness = DEVICE_LITTLE_ENDIAN,
  74 };
  75
  76 static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
  77 {
  78     MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev);
  79
  80     memory_region_init_io(&s->sysreg, OBJECT(dev),
  81                           &mchp_pfsoc_sysreg_ops, s,
  82                           "mchp.pfsoc.sysreg",
  83                           MCHP_PFSOC_SYSREG_REG_SIZE);
  84     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
  85     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
  86 }
  87
  88 static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data)
  89 {
  90     DeviceClass *dc = DEVICE_CLASS(klass);
  91
  92     dc->desc = "Microchip PolarFire SoC SYSREG module";
  93     dc->realize = mchp_pfsoc_sysreg_realize;
  94 }
  95
  96 static const TypeInfo mchp_pfsoc_sysreg_info = {
  97     .name          = TYPE_MCHP_PFSOC_SYSREG,
  98     .parent        = TYPE_SYS_BUS_DEVICE,
  99     .instance_size = sizeof(MchpPfSoCSysregState),
 100     .class_init    = mchp_pfsoc_sysreg_class_init,
 101 };
 102
 103 static void mchp_pfsoc_sysreg_register_types(void)
 104 {
 105     type_register_static(&mchp_pfsoc_sysreg_info);
 106 }
 107
 108 type_init(mchp_pfsoc_sysreg_register_types)