2 * QEMU IDE Emulation: MacIO support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/ppc/mac.h"
28 #include "hw/ppc/mac_dbdma.h"
29 #include "sysemu/block-backend.h"
30 #include "sysemu/dma.h"
32 #include "hw/ide/internal.h"
35 // #define DEBUG_MACIO
38 static const int debug_macio
= 1;
40 static const int debug_macio
= 0;
43 #define MACIO_DPRINTF(fmt, ...) do { \
45 printf(fmt , ## __VA_ARGS__); \
50 /***********************************************************/
51 /* MacIO based PowerPC IDE */
53 #define MACIO_PAGE_SIZE 4096
55 static void pmac_ide_atapi_transfer_cb(void *opaque
, int ret
)
57 DBDMA_io
*io
= opaque
;
58 MACIOIDEState
*m
= io
->opaque
;
59 IDEState
*s
= idebus_active_if(&m
->bus
);
62 MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
65 MACIO_DPRINTF("DMA error: %d\n", ret
);
66 qemu_sglist_destroy(&s
->sg
);
67 ide_atapi_io_error(s
, ret
);
72 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
73 s
->nsector
, io
->len
, s
->status
);
74 /* data not ready yet, wait for the channel to get restarted */
75 io
->processing
= false;
79 if (s
->io_buffer_size
<= 0) {
80 MACIO_DPRINTF("End of IDE transfer\n");
81 qemu_sglist_destroy(&s
->sg
);
83 m
->dma_active
= false;
88 MACIO_DPRINTF("End of DMA transfer\n");
93 /* Non-block ATAPI transfer - just copy to RAM */
94 s
->io_buffer_size
= MIN(s
->io_buffer_size
, io
->len
);
95 dma_memory_write(&address_space_memory
, io
->addr
, s
->io_buffer
,
99 m
->dma_active
= false;
103 /* Calculate current offset */
104 offset
= ((int64_t)s
->lba
<< 11) + s
->io_buffer_index
;
106 qemu_sglist_init(&s
->sg
, DEVICE(m
), io
->len
/ MACIO_PAGE_SIZE
+ 1,
107 &address_space_memory
);
108 qemu_sglist_add(&s
->sg
, io
->addr
, io
->len
);
109 s
->io_buffer_size
-= io
->len
;
110 s
->io_buffer_index
+= io
->len
;
113 s
->bus
->dma
->aiocb
= dma_blk_read(s
->blk
, &s
->sg
, offset
, 0x1,
114 pmac_ide_atapi_transfer_cb
, io
);
118 dma_memory_unmap(&address_space_memory
, io
->dma_mem
, io
->dma_len
,
119 io
->dir
, io
->dma_len
);
122 block_acct_failed(blk_get_stats(s
->blk
), &s
->acct
);
124 block_acct_done(blk_get_stats(s
->blk
), &s
->acct
);
127 ide_set_inactive(s
, false);
131 static void pmac_ide_transfer_cb(void *opaque
, int ret
)
133 DBDMA_io
*io
= opaque
;
134 MACIOIDEState
*m
= io
->opaque
;
135 IDEState
*s
= idebus_active_if(&m
->bus
);
138 MACIO_DPRINTF("pmac_ide_transfer_cb\n");
141 MACIO_DPRINTF("DMA error: %d\n", ret
);
142 qemu_sglist_destroy(&s
->sg
);
147 if (!m
->dma_active
) {
148 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
149 s
->nsector
, io
->len
, s
->status
);
150 /* data not ready yet, wait for the channel to get restarted */
151 io
->processing
= false;
155 if (s
->io_buffer_size
<= 0) {
156 MACIO_DPRINTF("End of IDE transfer\n");
157 qemu_sglist_destroy(&s
->sg
);
158 s
->status
= READY_STAT
| SEEK_STAT
;
160 m
->dma_active
= false;
165 MACIO_DPRINTF("End of DMA transfer\n");
169 /* Calculate number of sectors */
170 offset
= (ide_get_sector(s
) << 9) + s
->io_buffer_index
;
172 qemu_sglist_init(&s
->sg
, DEVICE(m
), io
->len
/ MACIO_PAGE_SIZE
+ 1,
173 &address_space_memory
);
174 qemu_sglist_add(&s
->sg
, io
->addr
, io
->len
);
175 s
->io_buffer_size
-= io
->len
;
176 s
->io_buffer_index
+= io
->len
;
179 switch (s
->dma_cmd
) {
181 s
->bus
->dma
->aiocb
= dma_blk_read(s
->blk
, &s
->sg
, offset
, 0x1,
182 pmac_ide_atapi_transfer_cb
, io
);
185 s
->bus
->dma
->aiocb
= dma_blk_write(s
->blk
, &s
->sg
, offset
, 0x1,
186 pmac_ide_transfer_cb
, io
);
189 s
->bus
->dma
->aiocb
= dma_blk_io(blk_get_aio_context(s
->blk
), &s
->sg
,
190 offset
, 0x1, ide_issue_trim
, s
->blk
,
191 pmac_ide_transfer_cb
, io
,
192 DMA_DIRECTION_TO_DEVICE
);
201 dma_memory_unmap(&address_space_memory
, io
->dma_mem
, io
->dma_len
,
202 io
->dir
, io
->dma_len
);
204 if (s
->dma_cmd
== IDE_DMA_READ
|| s
->dma_cmd
== IDE_DMA_WRITE
) {
206 block_acct_failed(blk_get_stats(s
->blk
), &s
->acct
);
208 block_acct_done(blk_get_stats(s
->blk
), &s
->acct
);
212 ide_set_inactive(s
, false);
216 static void pmac_ide_transfer(DBDMA_io
*io
)
218 MACIOIDEState
*m
= io
->opaque
;
219 IDEState
*s
= idebus_active_if(&m
->bus
);
223 if (s
->drive_kind
== IDE_CD
) {
224 block_acct_start(blk_get_stats(s
->blk
), &s
->acct
, io
->len
,
227 pmac_ide_atapi_transfer_cb(io
, 0);
231 switch (s
->dma_cmd
) {
233 block_acct_start(blk_get_stats(s
->blk
), &s
->acct
, io
->len
,
237 block_acct_start(blk_get_stats(s
->blk
), &s
->acct
, io
->len
,
244 pmac_ide_transfer_cb(io
, 0);
247 static void pmac_ide_flush(DBDMA_io
*io
)
249 MACIOIDEState
*m
= io
->opaque
;
250 IDEState
*s
= idebus_active_if(&m
->bus
);
252 if (s
->bus
->dma
->aiocb
) {
257 /* PowerMac IDE memory IO */
258 static uint64_t pmac_ide_read(void *opaque
, hwaddr addr
, unsigned size
)
260 MACIOIDEState
*d
= opaque
;
261 uint64_t retval
= 0xffffffff;
267 retval
= ide_data_readw(&d
->bus
, 0);
268 } else if (size
== 4) {
269 retval
= ide_data_readl(&d
->bus
, 0);
274 retval
= ide_ioport_read(&d
->bus
, reg
);
280 retval
= ide_status_read(&d
->bus
, 0);
285 retval
= d
->timing_reg
;
289 /* This is an interrupt state register that only exists
290 * in the KeyLargo and later variants. Bit 0x8000_0000
291 * latches the DMA interrupt and has to be written to
292 * clear. Bit 0x4000_0000 is an image of the disk
293 * interrupt. MacOS X relies on this and will hang if
294 * we don't provide at least the disk interrupt
306 static void pmac_ide_write(void *opaque
, hwaddr addr
, uint64_t val
,
309 MACIOIDEState
*d
= opaque
;
315 ide_data_writew(&d
->bus
, 0, val
);
316 } else if (size
== 4) {
317 ide_data_writel(&d
->bus
, 0, val
);
322 ide_ioport_write(&d
->bus
, reg
, val
);
328 ide_cmd_write(&d
->bus
, 0, val
);
338 if (val
& 0x80000000u
) {
339 d
->irq_reg
&= 0x7fffffff;
346 static const MemoryRegionOps pmac_ide_ops
= {
347 .read
= pmac_ide_read
,
348 .write
= pmac_ide_write
,
349 .valid
.min_access_size
= 1,
350 .valid
.max_access_size
= 4,
351 .endianness
= DEVICE_LITTLE_ENDIAN
,
354 static const VMStateDescription vmstate_pmac
= {
357 .minimum_version_id
= 0,
358 .fields
= (VMStateField
[]) {
359 VMSTATE_IDE_BUS(bus
, MACIOIDEState
),
360 VMSTATE_IDE_DRIVES(bus
.ifs
, MACIOIDEState
),
361 VMSTATE_BOOL(dma_active
, MACIOIDEState
),
362 VMSTATE_UINT32(timing_reg
, MACIOIDEState
),
363 VMSTATE_UINT32(irq_reg
, MACIOIDEState
),
364 VMSTATE_END_OF_LIST()
368 static void macio_ide_reset(DeviceState
*dev
)
370 MACIOIDEState
*d
= MACIO_IDE(dev
);
372 ide_bus_reset(&d
->bus
);
375 static int ide_nop_int(IDEDMA
*dma
, int x
)
380 static int32_t ide_nop_int32(IDEDMA
*dma
, int32_t l
)
385 static void ide_dbdma_start(IDEDMA
*dma
, IDEState
*s
,
386 BlockCompletionFunc
*cb
)
388 MACIOIDEState
*m
= container_of(dma
, MACIOIDEState
, dma
);
390 s
->io_buffer_index
= 0;
391 if (s
->drive_kind
== IDE_CD
) {
392 s
->io_buffer_size
= s
->packet_transfer_size
;
394 s
->io_buffer_size
= s
->nsector
* BDRV_SECTOR_SIZE
;
397 MACIO_DPRINTF("\n\n------------ IDE transfer\n");
398 MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
399 s
->io_buffer_size
, s
->io_buffer_index
);
400 MACIO_DPRINTF("lba: %x size: %x\n", s
->lba
, s
->io_buffer_size
);
401 MACIO_DPRINTF("-------------------------\n");
403 m
->dma_active
= true;
404 DBDMA_kick(m
->dbdma
);
407 static const IDEDMAOps dbdma_ops
= {
408 .start_dma
= ide_dbdma_start
,
409 .prepare_buf
= ide_nop_int32
,
410 .rw_buf
= ide_nop_int
,
413 static void macio_ide_realizefn(DeviceState
*dev
, Error
**errp
)
415 MACIOIDEState
*s
= MACIO_IDE(dev
);
417 ide_init2(&s
->bus
, s
->ide_irq
);
419 /* Register DMA callbacks */
420 s
->dma
.ops
= &dbdma_ops
;
421 s
->bus
.dma
= &s
->dma
;
424 static void pmac_ide_irq(void *opaque
, int n
, int level
)
426 MACIOIDEState
*s
= opaque
;
427 uint32_t mask
= 0x80000000u
>> n
;
429 /* We need to reflect the IRQ state in the irq register */
437 qemu_set_irq(s
->real_ide_irq
, level
);
439 qemu_set_irq(s
->real_dma_irq
, level
);
443 static void macio_ide_initfn(Object
*obj
)
445 SysBusDevice
*d
= SYS_BUS_DEVICE(obj
);
446 MACIOIDEState
*s
= MACIO_IDE(obj
);
448 ide_bus_new(&s
->bus
, sizeof(s
->bus
), DEVICE(obj
), 0, 2);
449 memory_region_init_io(&s
->mem
, obj
, &pmac_ide_ops
, s
, "pmac-ide", 0x1000);
450 sysbus_init_mmio(d
, &s
->mem
);
451 sysbus_init_irq(d
, &s
->real_ide_irq
);
452 sysbus_init_irq(d
, &s
->real_dma_irq
);
453 s
->dma_irq
= qemu_allocate_irq(pmac_ide_irq
, s
, 0);
454 s
->ide_irq
= qemu_allocate_irq(pmac_ide_irq
, s
, 1);
456 object_property_add_link(obj
, "dbdma", TYPE_MAC_DBDMA
,
457 (Object
**) &s
->dbdma
,
458 qdev_prop_allow_set_link_before_realize
, 0, NULL
);
461 static Property macio_ide_properties
[] = {
462 DEFINE_PROP_UINT32("channel", MACIOIDEState
, channel
, 0),
463 DEFINE_PROP_END_OF_LIST(),
466 static void macio_ide_class_init(ObjectClass
*oc
, void *data
)
468 DeviceClass
*dc
= DEVICE_CLASS(oc
);
470 dc
->realize
= macio_ide_realizefn
;
471 dc
->reset
= macio_ide_reset
;
472 dc
->props
= macio_ide_properties
;
473 dc
->vmsd
= &vmstate_pmac
;
474 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
477 static const TypeInfo macio_ide_type_info
= {
478 .name
= TYPE_MACIO_IDE
,
479 .parent
= TYPE_SYS_BUS_DEVICE
,
480 .instance_size
= sizeof(MACIOIDEState
),
481 .instance_init
= macio_ide_initfn
,
482 .class_init
= macio_ide_class_init
,
485 static void macio_ide_register_types(void)
487 type_register_static(&macio_ide_type_info
);
490 /* hd_table must contain 2 block drivers */
491 void macio_ide_init_drives(MACIOIDEState
*s
, DriveInfo
**hd_table
)
495 for (i
= 0; i
< 2; i
++) {
497 ide_create_drive(&s
->bus
, i
, hd_table
[i
]);
502 void macio_ide_register_dma(MACIOIDEState
*s
)
504 DBDMA_register_channel(s
->dbdma
, s
->channel
, s
->dma_irq
,
505 pmac_ide_transfer
, pmac_ide_flush
, s
);
508 type_init(macio_ide_register_types
)