target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     return cs->interrupt_request &
  44         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
  45 }
  46
  47 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  48 {
  49     /* Reset a single ARMCPRegInfo register */
  50     ARMCPRegInfo *ri = value;
  51     ARMCPU *cpu = opaque;
  52
  53     if (ri->type & ARM_CP_SPECIAL) {
  54         return;
  55     }
  56
  57     if (ri->resetfn) {
  58         ri->resetfn(&cpu->env, ri);
  59         return;
  60     }
  61
  62     /* A zero offset is never possible as it would be regs[0]
  63      * so we use it to indicate that reset is being handled elsewhere.
  64      * This is basically only used for fields in non-core coprocessors
  65      * (like the pxa2xx ones).
  66      */
  67     if (!ri->fieldoffset) {
  68         return;
  69     }
  70
  71     if (cpreg_field_is_64bit(ri)) {
  72         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  73     } else {
  74         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  75     }
  76 }
  77
  78 /* CPUClass::reset() */
  79 static void arm_cpu_reset(CPUState *s)
  80 {
  81     ARMCPU *cpu = ARM_CPU(s);
  82     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  83     CPUARMState *env = &cpu->env;
  84
  85     acc->parent_reset(s);
  86
  87     memset(env, 0, offsetof(CPUARMState, features));
  88     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  89     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  90     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  91     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  92     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  93
  94     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  95         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  96     }
  97
  98     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
  99         /* 64 bit CPUs always start in 64 bit mode */
 100         env->aarch64 = 1;
 101 #if defined(CONFIG_USER_ONLY)
 102         env->pstate = PSTATE_MODE_EL0t;
 103         /* Userspace expects access to CTL_EL0 and the cache ops */
 104         env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
 105         /* and to the FP/Neon instructions */
 106         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 107 #else
 108         env->pstate = PSTATE_MODE_EL1h;
 109         env->pc = cpu->rvbar;
 110 #endif
 111     } else {
 112 #if defined(CONFIG_USER_ONLY)
 113         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 114         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 115 #endif
 116     }
 117
 118 #if defined(CONFIG_USER_ONLY)
 119     env->uncached_cpsr = ARM_CPU_MODE_USR;
 120     /* For user mode we must enable access to coprocessors */
 121     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 122     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 123         env->cp15.c15_cpar = 3;
 124     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 125         env->cp15.c15_cpar = 1;
 126     }
 127 #else
 128     /* SVC mode with interrupts disabled.  */
 129     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 130     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 131     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 132      * clear at reset. Initial SP and PC are loaded from ROM.
 133      */
 134     if (IS_M(env)) {
 135         uint32_t initial_msp; /* Loaded from 0x0 */
 136         uint32_t initial_pc; /* Loaded from 0x4 */
 137         uint8_t *rom;
 138
 139         env->daif &= ~PSTATE_I;
 140         rom = rom_ptr(0);
 141         if (rom) {
 142             /* Address zero is covered by ROM which hasn't yet been
 143              * copied into physical memory.
 144              */
 145             initial_msp = ldl_p(rom);
 146             initial_pc = ldl_p(rom + 4);
 147         } else {
 148             /* Address zero not covered by a ROM blob, or the ROM blob
 149              * is in non-modifiable memory and this is a second reset after
 150              * it got copied into memory. In the latter case, rom_ptr
 151              * will return a NULL pointer and we should use ldl_phys instead.
 152              */
 153             initial_msp = ldl_phys(s->as, 0);
 154             initial_pc = ldl_phys(s->as, 4);
 155         }
 156
 157         env->regs[13] = initial_msp & 0xFFFFFFFC;
 158         env->regs[15] = initial_pc & ~1;
 159         env->thumb = initial_pc & 1;
 160     }
 161
 162     if (env->cp15.c1_sys & SCTLR_V) {
 163         env->regs[15] = 0xFFFF0000;
 164     }
 165
 166     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 167 #endif
 168     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 169     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 170     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 171     set_float_detect_tininess(float_tininess_before_rounding,
 172                               &env->vfp.fp_status);
 173     set_float_detect_tininess(float_tininess_before_rounding,
 174                               &env->vfp.standard_fp_status);
 175     tlb_flush(s, 1);
 176     /* Reset is a state change for some CPUARMState fields which we
 177      * bake assumptions about into translated code, so we need to
 178      * tb_flush().
 179      */
 180     tb_flush(env);
 181
 182 #ifndef CONFIG_USER_ONLY
 183     if (kvm_enabled()) {
 184         kvm_arm_reset_vcpu(cpu);
 185     }
 186 #endif
 187
 188     hw_breakpoint_update_all(cpu);
 189     hw_watchpoint_update_all(cpu);
 190 }
 191
 192 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 193 {
 194     CPUClass *cc = CPU_GET_CLASS(cs);
 195     ARMCPU *cpu = ARM_CPU(cs);
 196     CPUARMState *env = &cpu->env;
 197     bool ret = false;
 198
 199     if (interrupt_request & CPU_INTERRUPT_FIQ
 200         && !(env->daif & PSTATE_F)) {
 201         cs->exception_index = EXCP_FIQ;
 202         cc->do_interrupt(cs);
 203         ret = true;
 204     }
 205     /* ARMv7-M interrupt return works by loading a magic value
 206        into the PC.  On real hardware the load causes the
 207        return to occur.  The qemu implementation performs the
 208        jump normally, then does the exception return when the
 209        CPU tries to execute code at the magic address.
 210        This will cause the magic PC value to be pushed to
 211        the stack if an interrupt occurred at the wrong time.
 212        We avoid this by disabling interrupts when
 213        pc contains a magic address.  */
 214     if (interrupt_request & CPU_INTERRUPT_HARD
 215         && !(env->daif & PSTATE_I)
 216         && (!IS_M(env) || env->regs[15] < 0xfffffff0)) {
 217         cs->exception_index = EXCP_IRQ;
 218         cc->do_interrupt(cs);
 219         ret = true;
 220     }
 221
 222     return ret;
 223 }
 224
 225 #ifndef CONFIG_USER_ONLY
 226 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 227 {
 228     ARMCPU *cpu = opaque;
 229     CPUState *cs = CPU(cpu);
 230
 231     switch (irq) {
 232     case ARM_CPU_IRQ:
 233         if (level) {
 234             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 235         } else {
 236             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 237         }
 238         break;
 239     case ARM_CPU_FIQ:
 240         if (level) {
 241             cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
 242         } else {
 243             cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
 244         }
 245         break;
 246     default:
 247         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 248     }
 249 }
 250
 251 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 252 {
 253 #ifdef CONFIG_KVM
 254     ARMCPU *cpu = opaque;
 255     CPUState *cs = CPU(cpu);
 256     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 257
 258     switch (irq) {
 259     case ARM_CPU_IRQ:
 260         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 261         break;
 262     case ARM_CPU_FIQ:
 263         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 264         break;
 265     default:
 266         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 267     }
 268     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 269     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 270 #endif
 271 }
 272 #endif
 273
 274 static inline void set_feature(CPUARMState *env, int feature)
 275 {
 276     env->features |= 1ULL << feature;
 277 }
 278
 279 static void arm_cpu_initfn(Object *obj)
 280 {
 281     CPUState *cs = CPU(obj);
 282     ARMCPU *cpu = ARM_CPU(obj);
 283     static bool inited;
 284
 285     cs->env_ptr = &cpu->env;
 286     cpu_exec_init(&cpu->env);
 287     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 288                                          g_free, g_free);
 289
 290 #ifndef CONFIG_USER_ONLY
 291     /* Our inbound IRQ and FIQ lines */
 292     if (kvm_enabled()) {
 293         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
 294     } else {
 295         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
 296     }
 297
 298     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 299                                                 arm_gt_ptimer_cb, cpu);
 300     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 301                                                 arm_gt_vtimer_cb, cpu);
 302     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 303                        ARRAY_SIZE(cpu->gt_timer_outputs));
 304 #endif
 305
 306     /* DTB consumers generally don't in fact care what the 'compatible'
 307      * string is, so always provide some string and trust that a hypothetical
 308      * picky DTB consumer will also provide a helpful error message.
 309      */
 310     cpu->dtb_compatible = "qemu,unknown";
 311     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 312     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 313
 314     if (tcg_enabled() && !inited) {
 315         inited = true;
 316         arm_translate_init();
 317     }
 318 }
 319
 320 static Property arm_cpu_reset_cbar_property =
 321             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 322
 323 static Property arm_cpu_reset_hivecs_property =
 324             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 325
 326 static Property arm_cpu_rvbar_property =
 327             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 328
 329 static void arm_cpu_post_init(Object *obj)
 330 {
 331     ARMCPU *cpu = ARM_CPU(obj);
 332
 333     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 334         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 335         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 336                                  &error_abort);
 337     }
 338
 339     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 340         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 341                                  &error_abort);
 342     }
 343
 344     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 345         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 346                                  &error_abort);
 347     }
 348 }
 349
 350 static void arm_cpu_finalizefn(Object *obj)
 351 {
 352     ARMCPU *cpu = ARM_CPU(obj);
 353     g_hash_table_destroy(cpu->cp_regs);
 354 }
 355
 356 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 357 {
 358     CPUState *cs = CPU(dev);
 359     ARMCPU *cpu = ARM_CPU(dev);
 360     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 361     CPUARMState *env = &cpu->env;
 362
 363     /* Some features automatically imply others: */
 364     if (arm_feature(env, ARM_FEATURE_V8)) {
 365         set_feature(env, ARM_FEATURE_V7);
 366         set_feature(env, ARM_FEATURE_ARM_DIV);
 367         set_feature(env, ARM_FEATURE_LPAE);
 368     }
 369     if (arm_feature(env, ARM_FEATURE_V7)) {
 370         set_feature(env, ARM_FEATURE_VAPA);
 371         set_feature(env, ARM_FEATURE_THUMB2);
 372         set_feature(env, ARM_FEATURE_MPIDR);
 373         if (!arm_feature(env, ARM_FEATURE_M)) {
 374             set_feature(env, ARM_FEATURE_V6K);
 375         } else {
 376             set_feature(env, ARM_FEATURE_V6);
 377         }
 378     }
 379     if (arm_feature(env, ARM_FEATURE_V6K)) {
 380         set_feature(env, ARM_FEATURE_V6);
 381         set_feature(env, ARM_FEATURE_MVFR);
 382     }
 383     if (arm_feature(env, ARM_FEATURE_V6)) {
 384         set_feature(env, ARM_FEATURE_V5);
 385         if (!arm_feature(env, ARM_FEATURE_M)) {
 386             set_feature(env, ARM_FEATURE_AUXCR);
 387         }
 388     }
 389     if (arm_feature(env, ARM_FEATURE_V5)) {
 390         set_feature(env, ARM_FEATURE_V4T);
 391     }
 392     if (arm_feature(env, ARM_FEATURE_M)) {
 393         set_feature(env, ARM_FEATURE_THUMB_DIV);
 394     }
 395     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 396         set_feature(env, ARM_FEATURE_THUMB_DIV);
 397     }
 398     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 399         set_feature(env, ARM_FEATURE_VFP3);
 400         set_feature(env, ARM_FEATURE_VFP_FP16);
 401     }
 402     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 403         set_feature(env, ARM_FEATURE_VFP);
 404     }
 405     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 406         set_feature(env, ARM_FEATURE_V7MP);
 407         set_feature(env, ARM_FEATURE_PXN);
 408     }
 409     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 410         set_feature(env, ARM_FEATURE_CBAR);
 411     }
 412
 413     if (cpu->reset_hivecs) {
 414             cpu->reset_sctlr |= (1 << 13);
 415     }
 416
 417     register_cp_regs_for_features(cpu);
 418     arm_cpu_register_gdb_regs_for_features(cpu);
 419
 420     init_cpreg_list(cpu);
 421
 422     qemu_init_vcpu(cs);
 423     cpu_reset(cs);
 424
 425     acc->parent_realize(dev, errp);
 426 }
 427
 428 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 429 {
 430     ObjectClass *oc;
 431     char *typename;
 432
 433     if (!cpu_model) {
 434         return NULL;
 435     }
 436
 437     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 438     oc = object_class_by_name(typename);
 439     g_free(typename);
 440     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 441         object_class_is_abstract(oc)) {
 442         return NULL;
 443     }
 444     return oc;
 445 }
 446
 447 /* CPU models. These are not needed for the AArch64 linux-user build. */
 448 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 449
 450 static void arm926_initfn(Object *obj)
 451 {
 452     ARMCPU *cpu = ARM_CPU(obj);
 453
 454     cpu->dtb_compatible = "arm,arm926";
 455     set_feature(&cpu->env, ARM_FEATURE_V5);
 456     set_feature(&cpu->env, ARM_FEATURE_VFP);
 457     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 458     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 459     cpu->midr = 0x41069265;
 460     cpu->reset_fpsid = 0x41011090;
 461     cpu->ctr = 0x1dd20d2;
 462     cpu->reset_sctlr = 0x00090078;
 463 }
 464
 465 static void arm946_initfn(Object *obj)
 466 {
 467     ARMCPU *cpu = ARM_CPU(obj);
 468
 469     cpu->dtb_compatible = "arm,arm946";
 470     set_feature(&cpu->env, ARM_FEATURE_V5);
 471     set_feature(&cpu->env, ARM_FEATURE_MPU);
 472     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 473     cpu->midr = 0x41059461;
 474     cpu->ctr = 0x0f004006;
 475     cpu->reset_sctlr = 0x00000078;
 476 }
 477
 478 static void arm1026_initfn(Object *obj)
 479 {
 480     ARMCPU *cpu = ARM_CPU(obj);
 481
 482     cpu->dtb_compatible = "arm,arm1026";
 483     set_feature(&cpu->env, ARM_FEATURE_V5);
 484     set_feature(&cpu->env, ARM_FEATURE_VFP);
 485     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 486     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 487     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 488     cpu->midr = 0x4106a262;
 489     cpu->reset_fpsid = 0x410110a0;
 490     cpu->ctr = 0x1dd20d2;
 491     cpu->reset_sctlr = 0x00090078;
 492     cpu->reset_auxcr = 1;
 493     {
 494         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 495         ARMCPRegInfo ifar = {
 496             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 497             .access = PL1_RW,
 498             .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 499             .resetvalue = 0
 500         };
 501         define_one_arm_cp_reg(cpu, &ifar);
 502     }
 503 }
 504
 505 static void arm1136_r2_initfn(Object *obj)
 506 {
 507     ARMCPU *cpu = ARM_CPU(obj);
 508     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 509      * older core than plain "arm1136". In particular this does not
 510      * have the v6K features.
 511      * These ID register values are correct for 1136 but may be wrong
 512      * for 1136_r2 (in particular r0p2 does not actually implement most
 513      * of the ID registers).
 514      */
 515
 516     cpu->dtb_compatible = "arm,arm1136";
 517     set_feature(&cpu->env, ARM_FEATURE_V6);
 518     set_feature(&cpu->env, ARM_FEATURE_VFP);
 519     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 520     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 521     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 522     cpu->midr = 0x4107b362;
 523     cpu->reset_fpsid = 0x410120b4;
 524     cpu->mvfr0 = 0x11111111;
 525     cpu->mvfr1 = 0x00000000;
 526     cpu->ctr = 0x1dd20d2;
 527     cpu->reset_sctlr = 0x00050078;
 528     cpu->id_pfr0 = 0x111;
 529     cpu->id_pfr1 = 0x1;
 530     cpu->id_dfr0 = 0x2;
 531     cpu->id_afr0 = 0x3;
 532     cpu->id_mmfr0 = 0x01130003;
 533     cpu->id_mmfr1 = 0x10030302;
 534     cpu->id_mmfr2 = 0x01222110;
 535     cpu->id_isar0 = 0x00140011;
 536     cpu->id_isar1 = 0x12002111;
 537     cpu->id_isar2 = 0x11231111;
 538     cpu->id_isar3 = 0x01102131;
 539     cpu->id_isar4 = 0x141;
 540     cpu->reset_auxcr = 7;
 541 }
 542
 543 static void arm1136_initfn(Object *obj)
 544 {
 545     ARMCPU *cpu = ARM_CPU(obj);
 546
 547     cpu->dtb_compatible = "arm,arm1136";
 548     set_feature(&cpu->env, ARM_FEATURE_V6K);
 549     set_feature(&cpu->env, ARM_FEATURE_V6);
 550     set_feature(&cpu->env, ARM_FEATURE_VFP);
 551     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 552     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 553     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 554     cpu->midr = 0x4117b363;
 555     cpu->reset_fpsid = 0x410120b4;
 556     cpu->mvfr0 = 0x11111111;
 557     cpu->mvfr1 = 0x00000000;
 558     cpu->ctr = 0x1dd20d2;
 559     cpu->reset_sctlr = 0x00050078;
 560     cpu->id_pfr0 = 0x111;
 561     cpu->id_pfr1 = 0x1;
 562     cpu->id_dfr0 = 0x2;
 563     cpu->id_afr0 = 0x3;
 564     cpu->id_mmfr0 = 0x01130003;
 565     cpu->id_mmfr1 = 0x10030302;
 566     cpu->id_mmfr2 = 0x01222110;
 567     cpu->id_isar0 = 0x00140011;
 568     cpu->id_isar1 = 0x12002111;
 569     cpu->id_isar2 = 0x11231111;
 570     cpu->id_isar3 = 0x01102131;
 571     cpu->id_isar4 = 0x141;
 572     cpu->reset_auxcr = 7;
 573 }
 574
 575 static void arm1176_initfn(Object *obj)
 576 {
 577     ARMCPU *cpu = ARM_CPU(obj);
 578
 579     cpu->dtb_compatible = "arm,arm1176";
 580     set_feature(&cpu->env, ARM_FEATURE_V6K);
 581     set_feature(&cpu->env, ARM_FEATURE_VFP);
 582     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 583     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 584     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 585     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 586     cpu->midr = 0x410fb767;
 587     cpu->reset_fpsid = 0x410120b5;
 588     cpu->mvfr0 = 0x11111111;
 589     cpu->mvfr1 = 0x00000000;
 590     cpu->ctr = 0x1dd20d2;
 591     cpu->reset_sctlr = 0x00050078;
 592     cpu->id_pfr0 = 0x111;
 593     cpu->id_pfr1 = 0x11;
 594     cpu->id_dfr0 = 0x33;
 595     cpu->id_afr0 = 0;
 596     cpu->id_mmfr0 = 0x01130003;
 597     cpu->id_mmfr1 = 0x10030302;
 598     cpu->id_mmfr2 = 0x01222100;
 599     cpu->id_isar0 = 0x0140011;
 600     cpu->id_isar1 = 0x12002111;
 601     cpu->id_isar2 = 0x11231121;
 602     cpu->id_isar3 = 0x01102131;
 603     cpu->id_isar4 = 0x01141;
 604     cpu->reset_auxcr = 7;
 605 }
 606
 607 static void arm11mpcore_initfn(Object *obj)
 608 {
 609     ARMCPU *cpu = ARM_CPU(obj);
 610
 611     cpu->dtb_compatible = "arm,arm11mpcore";
 612     set_feature(&cpu->env, ARM_FEATURE_V6K);
 613     set_feature(&cpu->env, ARM_FEATURE_VFP);
 614     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 615     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 616     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 617     cpu->midr = 0x410fb022;
 618     cpu->reset_fpsid = 0x410120b4;
 619     cpu->mvfr0 = 0x11111111;
 620     cpu->mvfr1 = 0x00000000;
 621     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 622     cpu->id_pfr0 = 0x111;
 623     cpu->id_pfr1 = 0x1;
 624     cpu->id_dfr0 = 0;
 625     cpu->id_afr0 = 0x2;
 626     cpu->id_mmfr0 = 0x01100103;
 627     cpu->id_mmfr1 = 0x10020302;
 628     cpu->id_mmfr2 = 0x01222000;
 629     cpu->id_isar0 = 0x00100011;
 630     cpu->id_isar1 = 0x12002111;
 631     cpu->id_isar2 = 0x11221011;
 632     cpu->id_isar3 = 0x01102131;
 633     cpu->id_isar4 = 0x141;
 634     cpu->reset_auxcr = 1;
 635 }
 636
 637 static void cortex_m3_initfn(Object *obj)
 638 {
 639     ARMCPU *cpu = ARM_CPU(obj);
 640     set_feature(&cpu->env, ARM_FEATURE_V7);
 641     set_feature(&cpu->env, ARM_FEATURE_M);
 642     cpu->midr = 0x410fc231;
 643 }
 644
 645 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 646 {
 647 #ifndef CONFIG_USER_ONLY
 648     CPUClass *cc = CPU_CLASS(oc);
 649
 650     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 651 #endif
 652 }
 653
 654 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 655     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 656       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 657     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 658       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 659     REGINFO_SENTINEL
 660 };
 661
 662 static void cortex_a8_initfn(Object *obj)
 663 {
 664     ARMCPU *cpu = ARM_CPU(obj);
 665
 666     cpu->dtb_compatible = "arm,cortex-a8";
 667     set_feature(&cpu->env, ARM_FEATURE_V7);
 668     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 669     set_feature(&cpu->env, ARM_FEATURE_NEON);
 670     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 671     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 672     cpu->midr = 0x410fc080;
 673     cpu->reset_fpsid = 0x410330c0;
 674     cpu->mvfr0 = 0x11110222;
 675     cpu->mvfr1 = 0x00011100;
 676     cpu->ctr = 0x82048004;
 677     cpu->reset_sctlr = 0x00c50078;
 678     cpu->id_pfr0 = 0x1031;
 679     cpu->id_pfr1 = 0x11;
 680     cpu->id_dfr0 = 0x400;
 681     cpu->id_afr0 = 0;
 682     cpu->id_mmfr0 = 0x31100003;
 683     cpu->id_mmfr1 = 0x20000000;
 684     cpu->id_mmfr2 = 0x01202000;
 685     cpu->id_mmfr3 = 0x11;
 686     cpu->id_isar0 = 0x00101111;
 687     cpu->id_isar1 = 0x12112111;
 688     cpu->id_isar2 = 0x21232031;
 689     cpu->id_isar3 = 0x11112131;
 690     cpu->id_isar4 = 0x00111142;
 691     cpu->dbgdidr = 0x15141000;
 692     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 693     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 694     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 695     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 696     cpu->reset_auxcr = 2;
 697     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 698 }
 699
 700 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 701     /* power_control should be set to maximum latency. Again,
 702      * default to 0 and set by private hook
 703      */
 704     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 705       .access = PL1_RW, .resetvalue = 0,
 706       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 707     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 708       .access = PL1_RW, .resetvalue = 0,
 709       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 710     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 711       .access = PL1_RW, .resetvalue = 0,
 712       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 713     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 714       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 715     /* TLB lockdown control */
 716     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 717       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 718     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 719       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 720     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 721       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 722     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 723       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 724     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 725       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 726     REGINFO_SENTINEL
 727 };
 728
 729 static void cortex_a9_initfn(Object *obj)
 730 {
 731     ARMCPU *cpu = ARM_CPU(obj);
 732
 733     cpu->dtb_compatible = "arm,cortex-a9";
 734     set_feature(&cpu->env, ARM_FEATURE_V7);
 735     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 736     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 737     set_feature(&cpu->env, ARM_FEATURE_NEON);
 738     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 739     /* Note that A9 supports the MP extensions even for
 740      * A9UP and single-core A9MP (which are both different
 741      * and valid configurations; we don't model A9UP).
 742      */
 743     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 744     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 745     cpu->midr = 0x410fc090;
 746     cpu->reset_fpsid = 0x41033090;
 747     cpu->mvfr0 = 0x11110222;
 748     cpu->mvfr1 = 0x01111111;
 749     cpu->ctr = 0x80038003;
 750     cpu->reset_sctlr = 0x00c50078;
 751     cpu->id_pfr0 = 0x1031;
 752     cpu->id_pfr1 = 0x11;
 753     cpu->id_dfr0 = 0x000;
 754     cpu->id_afr0 = 0;
 755     cpu->id_mmfr0 = 0x00100103;
 756     cpu->id_mmfr1 = 0x20000000;
 757     cpu->id_mmfr2 = 0x01230000;
 758     cpu->id_mmfr3 = 0x00002111;
 759     cpu->id_isar0 = 0x00101111;
 760     cpu->id_isar1 = 0x13112111;
 761     cpu->id_isar2 = 0x21232041;
 762     cpu->id_isar3 = 0x11112131;
 763     cpu->id_isar4 = 0x00111142;
 764     cpu->dbgdidr = 0x35141000;
 765     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 766     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 767     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 768     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 769 }
 770
 771 #ifndef CONFIG_USER_ONLY
 772 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 773 {
 774     /* Linux wants the number of processors from here.
 775      * Might as well set the interrupt-controller bit too.
 776      */
 777     return ((smp_cpus - 1) << 24) | (1 << 23);
 778 }
 779 #endif
 780
 781 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 782 #ifndef CONFIG_USER_ONLY
 783     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 784       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 785       .writefn = arm_cp_write_ignore, },
 786 #endif
 787     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 788       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 789     REGINFO_SENTINEL
 790 };
 791
 792 static void cortex_a15_initfn(Object *obj)
 793 {
 794     ARMCPU *cpu = ARM_CPU(obj);
 795
 796     cpu->dtb_compatible = "arm,cortex-a15";
 797     set_feature(&cpu->env, ARM_FEATURE_V7);
 798     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 799     set_feature(&cpu->env, ARM_FEATURE_NEON);
 800     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 801     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 802     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 803     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 804     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 805     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 806     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 807     cpu->midr = 0x412fc0f1;
 808     cpu->reset_fpsid = 0x410430f0;
 809     cpu->mvfr0 = 0x10110222;
 810     cpu->mvfr1 = 0x11111111;
 811     cpu->ctr = 0x8444c004;
 812     cpu->reset_sctlr = 0x00c50078;
 813     cpu->id_pfr0 = 0x00001131;
 814     cpu->id_pfr1 = 0x00011011;
 815     cpu->id_dfr0 = 0x02010555;
 816     cpu->id_afr0 = 0x00000000;
 817     cpu->id_mmfr0 = 0x10201105;
 818     cpu->id_mmfr1 = 0x20000000;
 819     cpu->id_mmfr2 = 0x01240000;
 820     cpu->id_mmfr3 = 0x02102211;
 821     cpu->id_isar0 = 0x02101110;
 822     cpu->id_isar1 = 0x13112111;
 823     cpu->id_isar2 = 0x21232041;
 824     cpu->id_isar3 = 0x11112131;
 825     cpu->id_isar4 = 0x10011142;
 826     cpu->dbgdidr = 0x3515f021;
 827     cpu->clidr = 0x0a200023;
 828     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 829     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 830     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 831     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 832 }
 833
 834 static void ti925t_initfn(Object *obj)
 835 {
 836     ARMCPU *cpu = ARM_CPU(obj);
 837     set_feature(&cpu->env, ARM_FEATURE_V4T);
 838     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 839     cpu->midr = ARM_CPUID_TI925T;
 840     cpu->ctr = 0x5109149;
 841     cpu->reset_sctlr = 0x00000070;
 842 }
 843
 844 static void sa1100_initfn(Object *obj)
 845 {
 846     ARMCPU *cpu = ARM_CPU(obj);
 847
 848     cpu->dtb_compatible = "intel,sa1100";
 849     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 850     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 851     cpu->midr = 0x4401A11B;
 852     cpu->reset_sctlr = 0x00000070;
 853 }
 854
 855 static void sa1110_initfn(Object *obj)
 856 {
 857     ARMCPU *cpu = ARM_CPU(obj);
 858     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 859     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 860     cpu->midr = 0x6901B119;
 861     cpu->reset_sctlr = 0x00000070;
 862 }
 863
 864 static void pxa250_initfn(Object *obj)
 865 {
 866     ARMCPU *cpu = ARM_CPU(obj);
 867
 868     cpu->dtb_compatible = "marvell,xscale";
 869     set_feature(&cpu->env, ARM_FEATURE_V5);
 870     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 871     cpu->midr = 0x69052100;
 872     cpu->ctr = 0xd172172;
 873     cpu->reset_sctlr = 0x00000078;
 874 }
 875
 876 static void pxa255_initfn(Object *obj)
 877 {
 878     ARMCPU *cpu = ARM_CPU(obj);
 879
 880     cpu->dtb_compatible = "marvell,xscale";
 881     set_feature(&cpu->env, ARM_FEATURE_V5);
 882     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 883     cpu->midr = 0x69052d00;
 884     cpu->ctr = 0xd172172;
 885     cpu->reset_sctlr = 0x00000078;
 886 }
 887
 888 static void pxa260_initfn(Object *obj)
 889 {
 890     ARMCPU *cpu = ARM_CPU(obj);
 891
 892     cpu->dtb_compatible = "marvell,xscale";
 893     set_feature(&cpu->env, ARM_FEATURE_V5);
 894     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 895     cpu->midr = 0x69052903;
 896     cpu->ctr = 0xd172172;
 897     cpu->reset_sctlr = 0x00000078;
 898 }
 899
 900 static void pxa261_initfn(Object *obj)
 901 {
 902     ARMCPU *cpu = ARM_CPU(obj);
 903
 904     cpu->dtb_compatible = "marvell,xscale";
 905     set_feature(&cpu->env, ARM_FEATURE_V5);
 906     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 907     cpu->midr = 0x69052d05;
 908     cpu->ctr = 0xd172172;
 909     cpu->reset_sctlr = 0x00000078;
 910 }
 911
 912 static void pxa262_initfn(Object *obj)
 913 {
 914     ARMCPU *cpu = ARM_CPU(obj);
 915
 916     cpu->dtb_compatible = "marvell,xscale";
 917     set_feature(&cpu->env, ARM_FEATURE_V5);
 918     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 919     cpu->midr = 0x69052d06;
 920     cpu->ctr = 0xd172172;
 921     cpu->reset_sctlr = 0x00000078;
 922 }
 923
 924 static void pxa270a0_initfn(Object *obj)
 925 {
 926     ARMCPU *cpu = ARM_CPU(obj);
 927
 928     cpu->dtb_compatible = "marvell,xscale";
 929     set_feature(&cpu->env, ARM_FEATURE_V5);
 930     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 931     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 932     cpu->midr = 0x69054110;
 933     cpu->ctr = 0xd172172;
 934     cpu->reset_sctlr = 0x00000078;
 935 }
 936
 937 static void pxa270a1_initfn(Object *obj)
 938 {
 939     ARMCPU *cpu = ARM_CPU(obj);
 940
 941     cpu->dtb_compatible = "marvell,xscale";
 942     set_feature(&cpu->env, ARM_FEATURE_V5);
 943     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 944     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 945     cpu->midr = 0x69054111;
 946     cpu->ctr = 0xd172172;
 947     cpu->reset_sctlr = 0x00000078;
 948 }
 949
 950 static void pxa270b0_initfn(Object *obj)
 951 {
 952     ARMCPU *cpu = ARM_CPU(obj);
 953
 954     cpu->dtb_compatible = "marvell,xscale";
 955     set_feature(&cpu->env, ARM_FEATURE_V5);
 956     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 957     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 958     cpu->midr = 0x69054112;
 959     cpu->ctr = 0xd172172;
 960     cpu->reset_sctlr = 0x00000078;
 961 }
 962
 963 static void pxa270b1_initfn(Object *obj)
 964 {
 965     ARMCPU *cpu = ARM_CPU(obj);
 966
 967     cpu->dtb_compatible = "marvell,xscale";
 968     set_feature(&cpu->env, ARM_FEATURE_V5);
 969     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 970     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 971     cpu->midr = 0x69054113;
 972     cpu->ctr = 0xd172172;
 973     cpu->reset_sctlr = 0x00000078;
 974 }
 975
 976 static void pxa270c0_initfn(Object *obj)
 977 {
 978     ARMCPU *cpu = ARM_CPU(obj);
 979
 980     cpu->dtb_compatible = "marvell,xscale";
 981     set_feature(&cpu->env, ARM_FEATURE_V5);
 982     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 983     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 984     cpu->midr = 0x69054114;
 985     cpu->ctr = 0xd172172;
 986     cpu->reset_sctlr = 0x00000078;
 987 }
 988
 989 static void pxa270c5_initfn(Object *obj)
 990 {
 991     ARMCPU *cpu = ARM_CPU(obj);
 992
 993     cpu->dtb_compatible = "marvell,xscale";
 994     set_feature(&cpu->env, ARM_FEATURE_V5);
 995     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 996     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 997     cpu->midr = 0x69054117;
 998     cpu->ctr = 0xd172172;
 999     cpu->reset_sctlr = 0x00000078;
1000 }
1001
1002 #ifdef CONFIG_USER_ONLY
1003 static void arm_any_initfn(Object *obj)
1004 {
1005     ARMCPU *cpu = ARM_CPU(obj);
1006     set_feature(&cpu->env, ARM_FEATURE_V8);
1007     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1008     set_feature(&cpu->env, ARM_FEATURE_NEON);
1009     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1010     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1011     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1012     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1013     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1014     set_feature(&cpu->env, ARM_FEATURE_CRC);
1015     cpu->midr = 0xffffffff;
1016 }
1017 #endif
1018
1019 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1020
1021 typedef struct ARMCPUInfo {
1022     const char *name;
1023     void (*initfn)(Object *obj);
1024     void (*class_init)(ObjectClass *oc, void *data);
1025 } ARMCPUInfo;
1026
1027 static const ARMCPUInfo arm_cpus[] = {
1028 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1029     { .name = "arm926",      .initfn = arm926_initfn },
1030     { .name = "arm946",      .initfn = arm946_initfn },
1031     { .name = "arm1026",     .initfn = arm1026_initfn },
1032     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1033      * older core than plain "arm1136". In particular this does not
1034      * have the v6K features.
1035      */
1036     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1037     { .name = "arm1136",     .initfn = arm1136_initfn },
1038     { .name = "arm1176",     .initfn = arm1176_initfn },
1039     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1040     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1041                              .class_init = arm_v7m_class_init },
1042     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1043     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1044     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1045     { .name = "ti925t",      .initfn = ti925t_initfn },
1046     { .name = "sa1100",      .initfn = sa1100_initfn },
1047     { .name = "sa1110",      .initfn = sa1110_initfn },
1048     { .name = "pxa250",      .initfn = pxa250_initfn },
1049     { .name = "pxa255",      .initfn = pxa255_initfn },
1050     { .name = "pxa260",      .initfn = pxa260_initfn },
1051     { .name = "pxa261",      .initfn = pxa261_initfn },
1052     { .name = "pxa262",      .initfn = pxa262_initfn },
1053     /* "pxa270" is an alias for "pxa270-a0" */
1054     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1055     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1056     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1057     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1058     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1059     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1060     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1061 #ifdef CONFIG_USER_ONLY
1062     { .name = "any",         .initfn = arm_any_initfn },
1063 #endif
1064 #endif
1065     { .name = NULL }
1066 };
1067
1068 static Property arm_cpu_properties[] = {
1069     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1070     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1071     DEFINE_PROP_END_OF_LIST()
1072 };
1073
1074 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1075 {
1076     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1077     CPUClass *cc = CPU_CLASS(acc);
1078     DeviceClass *dc = DEVICE_CLASS(oc);
1079
1080     acc->parent_realize = dc->realize;
1081     dc->realize = arm_cpu_realizefn;
1082     dc->props = arm_cpu_properties;
1083
1084     acc->parent_reset = cc->reset;
1085     cc->reset = arm_cpu_reset;
1086
1087     cc->class_by_name = arm_cpu_class_by_name;
1088     cc->has_work = arm_cpu_has_work;
1089     cc->do_interrupt = arm_cpu_do_interrupt;
1090     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1091     cc->dump_state = arm_cpu_dump_state;
1092     cc->set_pc = arm_cpu_set_pc;
1093     cc->gdb_read_register = arm_cpu_gdb_read_register;
1094     cc->gdb_write_register = arm_cpu_gdb_write_register;
1095 #ifdef CONFIG_USER_ONLY
1096     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1097 #else
1098     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1099     cc->vmsd = &vmstate_arm_cpu;
1100 #endif
1101     cc->gdb_num_core_regs = 26;
1102     cc->gdb_core_xml_file = "arm-core.xml";
1103     cc->debug_excp_handler = arm_debug_excp_handler;
1104 }
1105
1106 static void cpu_register(const ARMCPUInfo *info)
1107 {
1108     TypeInfo type_info = {
1109         .parent = TYPE_ARM_CPU,
1110         .instance_size = sizeof(ARMCPU),
1111         .instance_init = info->initfn,
1112         .class_size = sizeof(ARMCPUClass),
1113         .class_init = info->class_init,
1114     };
1115
1116     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1117     type_register(&type_info);
1118     g_free((void *)type_info.name);
1119 }
1120
1121 static const TypeInfo arm_cpu_type_info = {
1122     .name = TYPE_ARM_CPU,
1123     .parent = TYPE_CPU,
1124     .instance_size = sizeof(ARMCPU),
1125     .instance_init = arm_cpu_initfn,
1126     .instance_post_init = arm_cpu_post_init,
1127     .instance_finalize = arm_cpu_finalizefn,
1128     .abstract = true,
1129     .class_size = sizeof(ARMCPUClass),
1130     .class_init = arm_cpu_class_init,
1131 };
1132
1133 static void arm_cpu_register_types(void)
1134 {
1135     const ARMCPUInfo *info = arm_cpus;
1136
1137     type_register_static(&arm_cpu_type_info);
1138
1139     while (info->name) {
1140         cpu_register(info);
1141         info++;
1142     }
1143 }
1144
1145 type_init(arm_cpu_register_types)