3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 typedef struct DisasContext
{
45 const XtensaConfig
*config
;
55 int singlestep_enabled
;
59 bool sar_m32_allocated
;
62 uint32_t ccount_delta
;
66 static TCGv_ptr cpu_env
;
67 static TCGv_i32 cpu_pc
;
68 static TCGv_i32 cpu_R
[16];
69 static TCGv_i32 cpu_SR
[256];
70 static TCGv_i32 cpu_UR
[256];
72 #include "gen-icount.h"
74 static const char * const sregnames
[256] = {
80 [LITBASE
] = "LITBASE",
81 [SCOMPARE1
] = "SCOMPARE1",
82 [WINDOW_BASE
] = "WINDOW_BASE",
83 [WINDOW_START
] = "WINDOW_START",
84 [PTEVADDR
] = "PTEVADDR",
86 [ITLBCFG
] = "ITLBCFG",
87 [DTLBCFG
] = "DTLBCFG",
102 [EXCSAVE1
] = "EXCSAVE1",
103 [EXCSAVE1
+ 1] = "EXCSAVE2",
104 [EXCSAVE1
+ 2] = "EXCSAVE3",
105 [EXCSAVE1
+ 3] = "EXCSAVE4",
106 [EXCSAVE1
+ 4] = "EXCSAVE5",
107 [EXCSAVE1
+ 5] = "EXCSAVE6",
108 [EXCSAVE1
+ 6] = "EXCSAVE7",
109 [CPENABLE
] = "CPENABLE",
111 [INTCLEAR
] = "INTCLEAR",
112 [INTENABLE
] = "INTENABLE",
114 [VECBASE
] = "VECBASE",
115 [EXCCAUSE
] = "EXCCAUSE",
118 [EXCVADDR
] = "EXCVADDR",
119 [CCOMPARE
] = "CCOMPARE0",
120 [CCOMPARE
+ 1] = "CCOMPARE1",
121 [CCOMPARE
+ 2] = "CCOMPARE2",
124 static const char * const uregnames
[256] = {
125 [THREADPTR
] = "THREADPTR",
130 void xtensa_translate_init(void)
132 static const char * const regnames
[] = {
133 "ar0", "ar1", "ar2", "ar3",
134 "ar4", "ar5", "ar6", "ar7",
135 "ar8", "ar9", "ar10", "ar11",
136 "ar12", "ar13", "ar14", "ar15",
140 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
141 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
142 offsetof(CPUState
, pc
), "pc");
144 for (i
= 0; i
< 16; i
++) {
145 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
146 offsetof(CPUState
, regs
[i
]),
150 for (i
= 0; i
< 256; ++i
) {
152 cpu_SR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
153 offsetof(CPUState
, sregs
[i
]),
158 for (i
= 0; i
< 256; ++i
) {
160 cpu_UR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
161 offsetof(CPUState
, uregs
[i
]),
169 static inline bool option_bits_enabled(DisasContext
*dc
, uint64_t opt
)
171 return xtensa_option_bits_enabled(dc
->config
, opt
);
174 static inline bool option_enabled(DisasContext
*dc
, int opt
)
176 return xtensa_option_enabled(dc
->config
, opt
);
179 static void init_litbase(DisasContext
*dc
)
181 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
182 dc
->litbase
= tcg_temp_local_new_i32();
183 tcg_gen_andi_i32(dc
->litbase
, cpu_SR
[LITBASE
], 0xfffff000);
187 static void reset_litbase(DisasContext
*dc
)
189 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
190 tcg_temp_free(dc
->litbase
);
194 static void init_sar_tracker(DisasContext
*dc
)
196 dc
->sar_5bit
= false;
197 dc
->sar_m32_5bit
= false;
198 dc
->sar_m32_allocated
= false;
201 static void reset_sar_tracker(DisasContext
*dc
)
203 if (dc
->sar_m32_allocated
) {
204 tcg_temp_free(dc
->sar_m32
);
208 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
210 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
211 if (dc
->sar_m32_5bit
) {
212 tcg_gen_discard_i32(dc
->sar_m32
);
215 dc
->sar_m32_5bit
= false;
218 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
220 TCGv_i32 tmp
= tcg_const_i32(32);
221 if (!dc
->sar_m32_allocated
) {
222 dc
->sar_m32
= tcg_temp_local_new_i32();
223 dc
->sar_m32_allocated
= true;
225 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
226 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
227 dc
->sar_5bit
= false;
228 dc
->sar_m32_5bit
= true;
232 static void gen_advance_ccount(DisasContext
*dc
)
234 if (dc
->ccount_delta
> 0) {
235 TCGv_i32 tmp
= tcg_const_i32(dc
->ccount_delta
);
236 dc
->ccount_delta
= 0;
237 gen_helper_advance_ccount(tmp
);
242 static void reset_used_window(DisasContext
*dc
)
247 static void gen_exception(DisasContext
*dc
, int excp
)
249 TCGv_i32 tmp
= tcg_const_i32(excp
);
250 gen_advance_ccount(dc
);
251 gen_helper_exception(tmp
);
255 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
257 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
258 TCGv_i32 tcause
= tcg_const_i32(cause
);
259 gen_advance_ccount(dc
);
260 gen_helper_exception_cause(tpc
, tcause
);
262 tcg_temp_free(tcause
);
265 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
268 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
269 TCGv_i32 tcause
= tcg_const_i32(cause
);
270 gen_advance_ccount(dc
);
271 gen_helper_exception_cause_vaddr(tpc
, tcause
, vaddr
);
273 tcg_temp_free(tcause
);
276 static void gen_check_privilege(DisasContext
*dc
)
279 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
283 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
285 tcg_gen_mov_i32(cpu_pc
, dest
);
286 if (dc
->singlestep_enabled
) {
287 gen_exception(dc
, EXCP_DEBUG
);
289 gen_advance_ccount(dc
);
291 tcg_gen_goto_tb(slot
);
292 tcg_gen_exit_tb((tcg_target_long
)dc
->tb
+ slot
);
297 dc
->is_jmp
= DISAS_UPDATE
;
300 static void gen_jump(DisasContext
*dc
, TCGv dest
)
302 gen_jump_slot(dc
, dest
, -1);
305 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
307 TCGv_i32 tmp
= tcg_const_i32(dest
);
308 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
311 gen_jump_slot(dc
, tmp
, slot
);
315 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
318 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
320 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
321 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
322 tcg_temp_free(tcallinc
);
323 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
324 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
325 gen_jump_slot(dc
, dest
, slot
);
328 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
330 gen_callw_slot(dc
, callinc
, dest
, -1);
333 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
335 TCGv_i32 tmp
= tcg_const_i32(dest
);
336 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
339 gen_callw_slot(dc
, callinc
, tmp
, slot
);
343 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
345 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
346 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
347 dc
->next_pc
== dc
->lend
) {
348 int label
= gen_new_label();
350 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
351 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
352 gen_jumpi(dc
, dc
->lbeg
, slot
);
353 gen_set_label(label
);
354 gen_jumpi(dc
, dc
->next_pc
, -1);
360 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
362 if (!gen_check_loop_end(dc
, slot
)) {
363 gen_jumpi(dc
, dc
->next_pc
, slot
);
367 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
368 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t offset
)
370 int label
= gen_new_label();
372 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
373 gen_jumpi_check_loop_end(dc
, 0);
374 gen_set_label(label
);
375 gen_jumpi(dc
, dc
->pc
+ offset
, 1);
378 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
379 TCGv_i32 t0
, uint32_t t1
, uint32_t offset
)
381 TCGv_i32 tmp
= tcg_const_i32(t1
);
382 gen_brcond(dc
, cond
, t0
, tmp
, offset
);
386 static void gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
388 gen_advance_ccount(dc
);
389 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
392 static void gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
394 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
395 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
396 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
399 static void gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
401 static void (* const rsr_handler
[256])(DisasContext
*dc
,
402 TCGv_i32 d
, uint32_t sr
) = {
403 [CCOUNT
] = gen_rsr_ccount
,
404 [PTEVADDR
] = gen_rsr_ptevaddr
,
408 if (rsr_handler
[sr
]) {
409 rsr_handler
[sr
](dc
, d
, sr
);
411 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
414 qemu_log("RSR %d not implemented, ", sr
);
418 static void gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
420 gen_helper_wsr_lbeg(s
);
423 static void gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
425 gen_helper_wsr_lend(s
);
428 static void gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
430 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
431 if (dc
->sar_m32_5bit
) {
432 tcg_gen_discard_i32(dc
->sar_m32
);
434 dc
->sar_5bit
= false;
435 dc
->sar_m32_5bit
= false;
438 static void gen_wsr_br(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
440 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xffff);
443 static void gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
445 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
446 /* This can change tb->flags, so exit tb */
447 gen_jumpi_check_loop_end(dc
, -1);
450 static void gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
452 gen_helper_wsr_windowbase(v
);
453 reset_used_window(dc
);
456 static void gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
458 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
459 reset_used_window(dc
);
462 static void gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
464 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
467 static void gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
469 gen_helper_wsr_rasid(v
);
470 /* This can change tb->flags, so exit tb */
471 gen_jumpi_check_loop_end(dc
, -1);
474 static void gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
476 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
479 static void gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
481 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
482 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
483 gen_helper_check_interrupts(cpu_env
);
484 gen_jumpi_check_loop_end(dc
, 0);
487 static void gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
489 TCGv_i32 tmp
= tcg_temp_new_i32();
491 tcg_gen_andi_i32(tmp
, v
,
492 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
493 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
494 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
495 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
497 gen_helper_check_interrupts(cpu_env
);
500 static void gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
502 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
503 gen_helper_check_interrupts(cpu_env
);
504 gen_jumpi_check_loop_end(dc
, 0);
507 static void gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
509 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
510 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
512 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
515 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
516 reset_used_window(dc
);
517 gen_helper_check_interrupts(cpu_env
);
518 /* This can change mmu index and tb->flags, so exit tb */
519 gen_jumpi_check_loop_end(dc
, -1);
522 static void gen_wsr_prid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
526 static void gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
528 uint32_t id
= sr
- CCOMPARE
;
529 if (id
< dc
->config
->nccompare
) {
530 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
531 gen_advance_ccount(dc
);
532 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
533 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
534 gen_helper_check_interrupts(cpu_env
);
538 static void gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
540 static void (* const wsr_handler
[256])(DisasContext
*dc
,
541 uint32_t sr
, TCGv_i32 v
) = {
542 [LBEG
] = gen_wsr_lbeg
,
543 [LEND
] = gen_wsr_lend
,
546 [LITBASE
] = gen_wsr_litbase
,
547 [WINDOW_BASE
] = gen_wsr_windowbase
,
548 [WINDOW_START
] = gen_wsr_windowstart
,
549 [PTEVADDR
] = gen_wsr_ptevaddr
,
550 [RASID
] = gen_wsr_rasid
,
551 [ITLBCFG
] = gen_wsr_tlbcfg
,
552 [DTLBCFG
] = gen_wsr_tlbcfg
,
553 [INTSET
] = gen_wsr_intset
,
554 [INTCLEAR
] = gen_wsr_intclear
,
555 [INTENABLE
] = gen_wsr_intenable
,
557 [PRID
] = gen_wsr_prid
,
558 [CCOMPARE
] = gen_wsr_ccompare
,
559 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
560 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
564 if (wsr_handler
[sr
]) {
565 wsr_handler
[sr
](dc
, sr
, s
);
567 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
570 qemu_log("WSR %d not implemented, ", sr
);
574 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
575 TCGv_i32 addr
, bool no_hw_alignment
)
577 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
578 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
579 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
581 int label
= gen_new_label();
582 TCGv_i32 tmp
= tcg_temp_new_i32();
583 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
584 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
585 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
586 gen_set_label(label
);
591 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
593 TCGv_i32 pc
= tcg_const_i32(dc
->next_pc
);
594 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
595 gen_advance_ccount(dc
);
596 gen_helper_waiti(pc
, intlevel
);
598 tcg_temp_free(intlevel
);
601 static void gen_window_check1(DisasContext
*dc
, unsigned r1
)
603 if (dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) {
606 if (option_enabled(dc
, XTENSA_OPTION_WINDOWED_REGISTER
) &&
607 r1
/ 4 > dc
->used_window
) {
608 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
609 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
611 dc
->used_window
= r1
/ 4;
612 gen_advance_ccount(dc
);
613 gen_helper_window_check(pc
, w
);
620 static void gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
622 gen_window_check1(dc
, r1
> r2
? r1
: r2
);
625 static void gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
628 gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
631 static void disas_xtensa_insn(DisasContext
*dc
)
633 #define HAS_OPTION_BITS(opt) do { \
634 if (!option_bits_enabled(dc, opt)) { \
635 qemu_log("Option is not enabled %s:%d\n", \
636 __FILE__, __LINE__); \
637 goto invalid_opcode; \
641 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
643 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
644 #define RESERVED() do { \
645 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
646 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
647 goto invalid_opcode; \
651 #ifdef TARGET_WORDS_BIGENDIAN
652 #define OP0 (((b0) & 0xf0) >> 4)
653 #define OP1 (((b2) & 0xf0) >> 4)
654 #define OP2 ((b2) & 0xf)
655 #define RRR_R ((b1) & 0xf)
656 #define RRR_S (((b1) & 0xf0) >> 4)
657 #define RRR_T ((b0) & 0xf)
659 #define OP0 (((b0) & 0xf))
660 #define OP1 (((b2) & 0xf))
661 #define OP2 (((b2) & 0xf0) >> 4)
662 #define RRR_R (((b1) & 0xf0) >> 4)
663 #define RRR_S (((b1) & 0xf))
664 #define RRR_T (((b0) & 0xf0) >> 4)
674 #define RRI8_IMM8 (b2)
675 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
677 #ifdef TARGET_WORDS_BIGENDIAN
678 #define RI16_IMM16 (((b1) << 8) | (b2))
680 #define RI16_IMM16 (((b2) << 8) | (b1))
683 #ifdef TARGET_WORDS_BIGENDIAN
684 #define CALL_N (((b0) & 0xc) >> 2)
685 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
687 #define CALL_N (((b0) & 0x30) >> 4)
688 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
690 #define CALL_OFFSET_SE \
691 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
693 #define CALLX_N CALL_N
694 #ifdef TARGET_WORDS_BIGENDIAN
695 #define CALLX_M ((b0) & 0x3)
697 #define CALLX_M (((b0) & 0xc0) >> 6)
699 #define CALLX_S RRR_S
701 #define BRI12_M CALLX_M
702 #define BRI12_S RRR_S
703 #ifdef TARGET_WORDS_BIGENDIAN
704 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
706 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
708 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
710 #define BRI8_M BRI12_M
711 #define BRI8_R RRI8_R
712 #define BRI8_S RRI8_S
713 #define BRI8_IMM8 RRI8_IMM8
714 #define BRI8_IMM8_SE RRI8_IMM8_SE
718 uint8_t b0
= ldub_code(dc
->pc
);
719 uint8_t b1
= ldub_code(dc
->pc
+ 1);
720 uint8_t b2
= ldub_code(dc
->pc
+ 2);
722 static const uint32_t B4CONST
[] = {
723 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
726 static const uint32_t B4CONSTU
[] = {
727 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
731 dc
->next_pc
= dc
->pc
+ 2;
732 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY
);
734 dc
->next_pc
= dc
->pc
+ 3;
743 if ((RRR_R
& 0xc) == 0x8) {
744 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
751 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
762 gen_window_check1(dc
, CALLX_S
);
763 gen_jump(dc
, cpu_R
[CALLX_S
]);
767 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
769 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
770 gen_advance_ccount(dc
);
771 gen_helper_retw(tmp
, tmp
);
784 gen_window_check2(dc
, CALLX_S
, CALLX_N
<< 2);
788 TCGv_i32 tmp
= tcg_temp_new_i32();
789 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
790 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
799 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
801 TCGv_i32 tmp
= tcg_temp_new_i32();
803 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
804 gen_callw(dc
, CALLX_N
, tmp
);
814 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
815 gen_window_check2(dc
, RRR_T
, RRR_S
);
817 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
818 gen_advance_ccount(dc
);
819 gen_helper_movsp(pc
);
820 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
840 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
852 default: /*reserved*/
861 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
864 gen_check_privilege(dc
);
865 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
866 gen_helper_check_interrupts(cpu_env
);
867 gen_jump(dc
, cpu_SR
[EPC1
]);
875 gen_check_privilege(dc
);
877 dc
->config
->ndepc
? DEPC
: EPC1
]);
882 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
883 gen_check_privilege(dc
);
885 TCGv_i32 tmp
= tcg_const_i32(1);
888 cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
889 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
892 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
893 cpu_SR
[WINDOW_START
], tmp
);
895 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
896 cpu_SR
[WINDOW_START
], tmp
);
899 gen_helper_restore_owb();
900 gen_helper_check_interrupts(cpu_env
);
901 gen_jump(dc
, cpu_SR
[EPC1
]);
907 default: /*reserved*/
914 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
);
915 if (RRR_S
>= 2 && RRR_S
<= dc
->config
->nlevel
) {
916 gen_check_privilege(dc
);
917 tcg_gen_mov_i32(cpu_SR
[PS
],
918 cpu_SR
[EPS2
+ RRR_S
- 2]);
919 gen_helper_check_interrupts(cpu_env
);
920 gen_jump(dc
, cpu_SR
[EPC1
+ RRR_S
- 1]);
922 qemu_log("RFI %d is illegal\n", RRR_S
);
923 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
931 default: /*reserved*/
939 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
944 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
947 gen_exception_cause(dc
, SYSCALL_CAUSE
);
951 if (semihosting_enabled
) {
952 gen_check_privilege(dc
);
953 gen_helper_simcall(cpu_env
);
955 qemu_log("SIMCALL but semihosting is disabled\n");
956 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
967 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
968 gen_check_privilege(dc
);
969 gen_window_check1(dc
, RRR_T
);
970 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_SR
[PS
]);
971 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
972 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], RRR_S
);
973 gen_helper_check_interrupts(cpu_env
);
974 gen_jumpi_check_loop_end(dc
, 0);
978 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
979 gen_check_privilege(dc
);
980 gen_waiti(dc
, RRR_S
);
987 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
989 const unsigned shift
= (RRR_R
& 2) ? 8 : 4;
990 TCGv_i32 mask
= tcg_const_i32(
991 ((1 << shift
) - 1) << RRR_S
);
992 TCGv_i32 tmp
= tcg_temp_new_i32();
994 tcg_gen_and_i32(tmp
, cpu_SR
[BR
], mask
);
995 if (RRR_R
& 1) { /*ALL*/
996 tcg_gen_addi_i32(tmp
, tmp
, 1 << RRR_S
);
998 tcg_gen_add_i32(tmp
, tmp
, mask
);
1000 tcg_gen_shri_i32(tmp
, tmp
, RRR_S
+ shift
);
1001 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
],
1003 tcg_temp_free(mask
);
1008 default: /*reserved*/
1016 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1017 tcg_gen_and_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1021 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1022 tcg_gen_or_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1026 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1027 tcg_gen_xor_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1033 gen_window_check1(dc
, RRR_S
);
1034 gen_right_shift_sar(dc
, cpu_R
[RRR_S
]);
1038 gen_window_check1(dc
, RRR_S
);
1039 gen_left_shift_sar(dc
, cpu_R
[RRR_S
]);
1043 gen_window_check1(dc
, RRR_S
);
1045 TCGv_i32 tmp
= tcg_temp_new_i32();
1046 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1047 gen_right_shift_sar(dc
, tmp
);
1053 gen_window_check1(dc
, RRR_S
);
1055 TCGv_i32 tmp
= tcg_temp_new_i32();
1056 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1057 gen_left_shift_sar(dc
, tmp
);
1064 TCGv_i32 tmp
= tcg_const_i32(
1065 RRR_S
| ((RRR_T
& 1) << 4));
1066 gen_right_shift_sar(dc
, tmp
);
1080 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1081 gen_check_privilege(dc
);
1083 TCGv_i32 tmp
= tcg_const_i32(
1084 RRR_T
| ((RRR_T
& 8) ? 0xfffffff0 : 0));
1085 gen_helper_rotw(tmp
);
1087 reset_used_window(dc
);
1092 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
1093 gen_window_check2(dc
, RRR_S
, RRR_T
);
1094 gen_helper_nsa(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1098 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
1099 gen_window_check2(dc
, RRR_S
, RRR_T
);
1100 gen_helper_nsau(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1103 default: /*reserved*/
1111 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU
) |
1112 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION
) |
1113 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION
));
1114 gen_check_privilege(dc
);
1115 gen_window_check2(dc
, RRR_S
, RRR_T
);
1117 TCGv_i32 dtlb
= tcg_const_i32((RRR_R
& 8) != 0);
1119 switch (RRR_R
& 7) {
1120 case 3: /*RITLB0*/ /*RDTLB0*/
1121 gen_helper_rtlb0(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1124 case 4: /*IITLB*/ /*IDTLB*/
1125 gen_helper_itlb(cpu_R
[RRR_S
], dtlb
);
1126 /* This could change memory mapping, so exit tb */
1127 gen_jumpi_check_loop_end(dc
, -1);
1130 case 5: /*PITLB*/ /*PDTLB*/
1131 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1132 gen_helper_ptlb(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1135 case 6: /*WITLB*/ /*WDTLB*/
1136 gen_helper_wtlb(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1137 /* This could change memory mapping, so exit tb */
1138 gen_jumpi_check_loop_end(dc
, -1);
1141 case 7: /*RITLB1*/ /*RDTLB1*/
1142 gen_helper_rtlb1(cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1146 tcg_temp_free(dtlb
);
1150 tcg_temp_free(dtlb
);
1155 gen_window_check2(dc
, RRR_R
, RRR_T
);
1158 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1163 int label
= gen_new_label();
1164 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1165 tcg_gen_brcondi_i32(
1166 TCG_COND_GE
, cpu_R
[RRR_R
], 0, label
);
1167 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1168 gen_set_label(label
);
1172 default: /*reserved*/
1178 case 7: /*reserved*/
1183 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1184 tcg_gen_add_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1190 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1192 TCGv_i32 tmp
= tcg_temp_new_i32();
1193 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 8);
1194 tcg_gen_add_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1200 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1201 tcg_gen_sub_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1207 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1209 TCGv_i32 tmp
= tcg_temp_new_i32();
1210 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 12);
1211 tcg_gen_sub_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1222 gen_window_check2(dc
, RRR_R
, RRR_S
);
1223 tcg_gen_shli_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
],
1224 32 - (RRR_T
| ((OP2
& 1) << 4)));
1229 gen_window_check2(dc
, RRR_R
, RRR_T
);
1230 tcg_gen_sari_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
],
1231 RRR_S
| ((OP2
& 1) << 4));
1235 gen_window_check2(dc
, RRR_R
, RRR_T
);
1236 tcg_gen_shri_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], RRR_S
);
1241 TCGv_i32 tmp
= tcg_temp_new_i32();
1243 gen_check_privilege(dc
);
1245 gen_window_check1(dc
, RRR_T
);
1246 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
1247 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1248 gen_wsr(dc
, RSR_SR
, tmp
);
1250 if (!sregnames
[RSR_SR
]) {
1257 * Note: 64 bit ops are used here solely because SAR values
1260 #define gen_shift_reg(cmd, reg) do { \
1261 TCGv_i64 tmp = tcg_temp_new_i64(); \
1262 tcg_gen_extu_i32_i64(tmp, reg); \
1263 tcg_gen_##cmd##_i64(v, v, tmp); \
1264 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1265 tcg_temp_free_i64(v); \
1266 tcg_temp_free_i64(tmp); \
1269 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1272 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1274 TCGv_i64 v
= tcg_temp_new_i64();
1275 tcg_gen_concat_i32_i64(v
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1281 gen_window_check2(dc
, RRR_R
, RRR_T
);
1283 tcg_gen_shr_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1285 TCGv_i64 v
= tcg_temp_new_i64();
1286 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_T
]);
1292 gen_window_check2(dc
, RRR_R
, RRR_S
);
1293 if (dc
->sar_m32_5bit
) {
1294 tcg_gen_shl_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], dc
->sar_m32
);
1296 TCGv_i64 v
= tcg_temp_new_i64();
1297 TCGv_i32 s
= tcg_const_i32(32);
1298 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
1299 tcg_gen_andi_i32(s
, s
, 0x3f);
1300 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_S
]);
1301 gen_shift_reg(shl
, s
);
1307 gen_window_check2(dc
, RRR_R
, RRR_T
);
1309 tcg_gen_sar_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1311 TCGv_i64 v
= tcg_temp_new_i64();
1312 tcg_gen_ext_i32_i64(v
, cpu_R
[RRR_T
]);
1317 #undef gen_shift_reg
1320 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1321 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1323 TCGv_i32 v1
= tcg_temp_new_i32();
1324 TCGv_i32 v2
= tcg_temp_new_i32();
1325 tcg_gen_ext16u_i32(v1
, cpu_R
[RRR_S
]);
1326 tcg_gen_ext16u_i32(v2
, cpu_R
[RRR_T
]);
1327 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1334 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1335 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1337 TCGv_i32 v1
= tcg_temp_new_i32();
1338 TCGv_i32 v2
= tcg_temp_new_i32();
1339 tcg_gen_ext16s_i32(v1
, cpu_R
[RRR_S
]);
1340 tcg_gen_ext16s_i32(v2
, cpu_R
[RRR_T
]);
1341 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1347 default: /*reserved*/
1355 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1359 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV
);
1360 int label
= gen_new_label();
1361 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0, label
);
1362 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
1363 gen_set_label(label
);
1367 #define BOOLEAN_LOGIC(fn, r, s, t) \
1369 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1370 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1371 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1373 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1374 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1375 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1376 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1377 tcg_temp_free(tmp1); \
1378 tcg_temp_free(tmp2); \
1382 BOOLEAN_LOGIC(and, RRR_R
, RRR_S
, RRR_T
);
1386 BOOLEAN_LOGIC(andc
, RRR_R
, RRR_S
, RRR_T
);
1390 BOOLEAN_LOGIC(or, RRR_R
, RRR_S
, RRR_T
);
1394 BOOLEAN_LOGIC(orc
, RRR_R
, RRR_S
, RRR_T
);
1398 BOOLEAN_LOGIC(xor, RRR_R
, RRR_S
, RRR_T
);
1401 #undef BOOLEAN_LOGIC
1404 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1405 tcg_gen_mul_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1410 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1412 TCGv_i64 r
= tcg_temp_new_i64();
1413 TCGv_i64 s
= tcg_temp_new_i64();
1414 TCGv_i64 t
= tcg_temp_new_i64();
1417 tcg_gen_extu_i32_i64(s
, cpu_R
[RRR_S
]);
1418 tcg_gen_extu_i32_i64(t
, cpu_R
[RRR_T
]);
1420 tcg_gen_ext_i32_i64(s
, cpu_R
[RRR_S
]);
1421 tcg_gen_ext_i32_i64(t
, cpu_R
[RRR_T
]);
1423 tcg_gen_mul_i64(r
, s
, t
);
1424 tcg_gen_shri_i64(r
, r
, 32);
1425 tcg_gen_trunc_i64_i32(cpu_R
[RRR_R
], r
);
1427 tcg_temp_free_i64(r
);
1428 tcg_temp_free_i64(s
);
1429 tcg_temp_free_i64(t
);
1434 tcg_gen_divu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1440 int label1
= gen_new_label();
1441 int label2
= gen_new_label();
1443 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_S
], 0x80000000,
1445 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0xffffffff,
1447 tcg_gen_movi_i32(cpu_R
[RRR_R
],
1448 OP2
== 13 ? 0x80000000 : 0);
1450 gen_set_label(label1
);
1452 tcg_gen_div_i32(cpu_R
[RRR_R
],
1453 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1455 tcg_gen_rem_i32(cpu_R
[RRR_R
],
1456 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1458 gen_set_label(label2
);
1463 tcg_gen_remu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1466 default: /*reserved*/
1476 gen_check_privilege(dc
);
1478 gen_window_check1(dc
, RRR_T
);
1479 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1480 if (!sregnames
[RSR_SR
]) {
1487 gen_check_privilege(dc
);
1489 gen_window_check1(dc
, RRR_T
);
1490 gen_wsr(dc
, RSR_SR
, cpu_R
[RRR_T
]);
1491 if (!sregnames
[RSR_SR
]) {
1497 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
1498 gen_window_check2(dc
, RRR_R
, RRR_S
);
1500 int shift
= 24 - RRR_T
;
1503 tcg_gen_ext8s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1504 } else if (shift
== 16) {
1505 tcg_gen_ext16s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1507 TCGv_i32 tmp
= tcg_temp_new_i32();
1508 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], shift
);
1509 tcg_gen_sari_i32(cpu_R
[RRR_R
], tmp
, shift
);
1516 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
1517 gen_window_check2(dc
, RRR_R
, RRR_S
);
1519 TCGv_i32 tmp1
= tcg_temp_new_i32();
1520 TCGv_i32 tmp2
= tcg_temp_new_i32();
1521 int label
= gen_new_label();
1523 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 24 - RRR_T
);
1524 tcg_gen_xor_i32(tmp2
, tmp1
, cpu_R
[RRR_S
]);
1525 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffffffff << (RRR_T
+ 7));
1526 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1527 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp2
, 0, label
);
1529 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 31);
1530 tcg_gen_xori_i32(cpu_R
[RRR_R
], tmp1
,
1531 0xffffffff >> (25 - RRR_T
));
1533 gen_set_label(label
);
1535 tcg_temp_free(tmp1
);
1536 tcg_temp_free(tmp2
);
1544 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
1545 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1547 static const TCGCond cond
[] = {
1553 int label
= gen_new_label();
1555 if (RRR_R
!= RRR_T
) {
1556 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1557 tcg_gen_brcond_i32(cond
[OP2
- 4],
1558 cpu_R
[RRR_S
], cpu_R
[RRR_T
], label
);
1559 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1561 tcg_gen_brcond_i32(cond
[OP2
- 4],
1562 cpu_R
[RRR_T
], cpu_R
[RRR_S
], label
);
1563 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1565 gen_set_label(label
);
1573 gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
);
1575 static const TCGCond cond
[] = {
1581 int label
= gen_new_label();
1582 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
1583 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1584 gen_set_label(label
);
1590 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1591 gen_window_check2(dc
, RRR_R
, RRR_S
);
1593 int label
= gen_new_label();
1594 TCGv_i32 tmp
= tcg_temp_new_i32();
1596 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
1597 tcg_gen_brcondi_i32(
1598 OP2
& 1 ? TCG_COND_EQ
: TCG_COND_NE
,
1600 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1601 gen_set_label(label
);
1607 gen_window_check1(dc
, RRR_R
);
1609 int st
= (RRR_S
<< 4) + RRR_T
;
1610 if (uregnames
[st
]) {
1611 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_UR
[st
]);
1613 qemu_log("RUR %d not implemented, ", st
);
1620 gen_window_check1(dc
, RRR_T
);
1622 if (uregnames
[RSR_SR
]) {
1623 tcg_gen_mov_i32(cpu_UR
[RSR_SR
], cpu_R
[RRR_T
]);
1625 qemu_log("WUR %d not implemented, ", RSR_SR
);
1636 gen_window_check2(dc
, RRR_R
, RRR_T
);
1638 int shiftimm
= RRR_S
| (OP1
<< 4);
1639 int maskimm
= (1 << (OP2
+ 1)) - 1;
1641 TCGv_i32 tmp
= tcg_temp_new_i32();
1642 tcg_gen_shri_i32(tmp
, cpu_R
[RRR_T
], shiftimm
);
1643 tcg_gen_andi_i32(cpu_R
[RRR_R
], tmp
, maskimm
);
1657 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
1662 gen_window_check2(dc
, RRR_S
, RRR_T
);
1665 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1666 gen_check_privilege(dc
);
1668 TCGv_i32 addr
= tcg_temp_new_i32();
1669 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1670 (0xffffffc0 | (RRR_R
<< 2)));
1671 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], addr
, dc
->ring
);
1672 tcg_temp_free(addr
);
1677 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1678 gen_check_privilege(dc
);
1680 TCGv_i32 addr
= tcg_temp_new_i32();
1681 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1682 (0xffffffc0 | (RRR_R
<< 2)));
1683 tcg_gen_qemu_st32(cpu_R
[RRR_T
], addr
, dc
->ring
);
1684 tcg_temp_free(addr
);
1695 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1700 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1704 default: /*reserved*/
1711 gen_window_check1(dc
, RRR_T
);
1713 TCGv_i32 tmp
= tcg_const_i32(
1714 ((dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) ?
1715 0 : ((dc
->pc
+ 3) & ~3)) +
1716 (0xfffc0000 | (RI16_IMM16
<< 2)));
1718 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
1719 tcg_gen_add_i32(tmp
, tmp
, dc
->litbase
);
1721 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], tmp
, dc
->cring
);
1727 #define gen_load_store(type, shift) do { \
1728 TCGv_i32 addr = tcg_temp_new_i32(); \
1729 gen_window_check2(dc, RRI8_S, RRI8_T); \
1730 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
1732 gen_load_store_alignment(dc, shift, addr, false); \
1734 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1735 tcg_temp_free(addr); \
1740 gen_load_store(ld8u
, 0);
1744 gen_load_store(ld16u
, 1);
1748 gen_load_store(ld32u
, 2);
1752 gen_load_store(st8
, 0);
1756 gen_load_store(st16
, 1);
1760 gen_load_store(st32
, 2);
1765 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1796 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1800 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1804 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
1808 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1812 HAS_OPTION(XTENSA_OPTION_DCACHE
);
1815 default: /*reserved*/
1823 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1829 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1833 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1837 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
1840 default: /*reserved*/
1847 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1851 HAS_OPTION(XTENSA_OPTION_ICACHE
);
1854 default: /*reserved*/
1861 gen_load_store(ld16s
, 1);
1863 #undef gen_load_store
1866 gen_window_check1(dc
, RRI8_T
);
1867 tcg_gen_movi_i32(cpu_R
[RRI8_T
],
1868 RRI8_IMM8
| (RRI8_S
<< 8) |
1869 ((RRI8_S
& 0x8) ? 0xfffff000 : 0));
1872 #define gen_load_store_no_hw_align(type) do { \
1873 TCGv_i32 addr = tcg_temp_local_new_i32(); \
1874 gen_window_check2(dc, RRI8_S, RRI8_T); \
1875 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
1876 gen_load_store_alignment(dc, 2, addr, true); \
1877 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1878 tcg_temp_free(addr); \
1882 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
1883 gen_load_store_no_hw_align(ld32u
); /*TODO acquire?*/
1887 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
1888 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
);
1892 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
1893 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
<< 8);
1896 case 14: /*S32C1Iy*/
1897 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
1898 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
1900 int label
= gen_new_label();
1901 TCGv_i32 tmp
= tcg_temp_local_new_i32();
1902 TCGv_i32 addr
= tcg_temp_local_new_i32();
1904 tcg_gen_mov_i32(tmp
, cpu_R
[RRI8_T
]);
1905 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
1906 gen_load_store_alignment(dc
, 2, addr
, true);
1907 tcg_gen_qemu_ld32u(cpu_R
[RRI8_T
], addr
, dc
->cring
);
1908 tcg_gen_brcond_i32(TCG_COND_NE
, cpu_R
[RRI8_T
],
1909 cpu_SR
[SCOMPARE1
], label
);
1911 tcg_gen_qemu_st32(tmp
, addr
, dc
->cring
);
1913 gen_set_label(label
);
1914 tcg_temp_free(addr
);
1920 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
1921 gen_load_store_no_hw_align(st32
); /*TODO release?*/
1923 #undef gen_load_store_no_hw_align
1925 default: /*reserved*/
1932 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
1937 HAS_OPTION(XTENSA_OPTION_MAC16
);
1944 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
1945 gen_jumpi(dc
, (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
1951 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1952 gen_window_check1(dc
, CALL_N
<< 2);
1953 gen_callwi(dc
, CALL_N
,
1954 (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
1962 gen_jumpi(dc
, dc
->pc
+ 4 + CALL_OFFSET_SE
, 0);
1966 gen_window_check1(dc
, BRI12_S
);
1968 static const TCGCond cond
[] = {
1969 TCG_COND_EQ
, /*BEQZ*/
1970 TCG_COND_NE
, /*BNEZ*/
1971 TCG_COND_LT
, /*BLTZ*/
1972 TCG_COND_GE
, /*BGEZ*/
1975 gen_brcondi(dc
, cond
[BRI12_M
& 3], cpu_R
[BRI12_S
], 0,
1976 4 + BRI12_IMM12_SE
);
1981 gen_window_check1(dc
, BRI8_S
);
1983 static const TCGCond cond
[] = {
1984 TCG_COND_EQ
, /*BEQI*/
1985 TCG_COND_NE
, /*BNEI*/
1986 TCG_COND_LT
, /*BLTI*/
1987 TCG_COND_GE
, /*BGEI*/
1990 gen_brcondi(dc
, cond
[BRI8_M
& 3],
1991 cpu_R
[BRI8_S
], B4CONST
[BRI8_R
], 4 + BRI8_IMM8_SE
);
1998 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2000 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
2001 TCGv_i32 s
= tcg_const_i32(BRI12_S
);
2002 TCGv_i32 imm
= tcg_const_i32(BRI12_IMM12
);
2003 gen_advance_ccount(dc
);
2004 gen_helper_entry(pc
, s
, imm
);
2008 reset_used_window(dc
);
2016 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2018 TCGv_i32 tmp
= tcg_temp_new_i32();
2019 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRI8_S
);
2021 BRI8_R
== 1 ? TCG_COND_NE
: TCG_COND_EQ
,
2022 tmp
, 0, 4 + RRI8_IMM8_SE
);
2029 case 10: /*LOOPGTZ*/
2030 HAS_OPTION(XTENSA_OPTION_LOOP
);
2031 gen_window_check1(dc
, RRI8_S
);
2033 uint32_t lend
= dc
->pc
+ RRI8_IMM8
+ 4;
2034 TCGv_i32 tmp
= tcg_const_i32(lend
);
2036 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[RRI8_S
], 1);
2037 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
2038 gen_wsr_lend(dc
, LEND
, tmp
);
2042 int label
= gen_new_label();
2043 tcg_gen_brcondi_i32(
2044 BRI8_R
== 9 ? TCG_COND_NE
: TCG_COND_GT
,
2045 cpu_R
[RRI8_S
], 0, label
);
2046 gen_jumpi(dc
, lend
, 1);
2047 gen_set_label(label
);
2050 gen_jumpi(dc
, dc
->next_pc
, 0);
2054 default: /*reserved*/
2063 gen_window_check1(dc
, BRI8_S
);
2064 gen_brcondi(dc
, BRI8_M
== 2 ? TCG_COND_LTU
: TCG_COND_GEU
,
2065 cpu_R
[BRI8_S
], B4CONSTU
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2075 TCGCond eq_ne
= (RRI8_R
& 8) ? TCG_COND_NE
: TCG_COND_EQ
;
2077 switch (RRI8_R
& 7) {
2078 case 0: /*BNONE*/ /*BANY*/
2079 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2081 TCGv_i32 tmp
= tcg_temp_new_i32();
2082 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2083 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2088 case 1: /*BEQ*/ /*BNE*/
2089 case 2: /*BLT*/ /*BGE*/
2090 case 3: /*BLTU*/ /*BGEU*/
2091 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2093 static const TCGCond cond
[] = {
2099 [11] = TCG_COND_GEU
,
2101 gen_brcond(dc
, cond
[RRI8_R
], cpu_R
[RRI8_S
], cpu_R
[RRI8_T
],
2106 case 4: /*BALL*/ /*BNALL*/
2107 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2109 TCGv_i32 tmp
= tcg_temp_new_i32();
2110 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2111 gen_brcond(dc
, eq_ne
, tmp
, cpu_R
[RRI8_T
],
2117 case 5: /*BBC*/ /*BBS*/
2118 gen_window_check2(dc
, RRI8_S
, RRI8_T
);
2120 TCGv_i32 bit
= tcg_const_i32(1);
2121 TCGv_i32 tmp
= tcg_temp_new_i32();
2122 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_T
], 0x1f);
2123 tcg_gen_shl_i32(bit
, bit
, tmp
);
2124 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], bit
);
2125 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2131 case 6: /*BBCI*/ /*BBSI*/
2133 gen_window_check1(dc
, RRI8_S
);
2135 TCGv_i32 tmp
= tcg_temp_new_i32();
2136 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_S
],
2137 1 << (((RRI8_R
& 1) << 4) | RRI8_T
));
2138 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2147 #define gen_narrow_load_store(type) do { \
2148 TCGv_i32 addr = tcg_temp_new_i32(); \
2149 gen_window_check2(dc, RRRN_S, RRRN_T); \
2150 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2151 gen_load_store_alignment(dc, 2, addr, false); \
2152 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2153 tcg_temp_free(addr); \
2157 gen_narrow_load_store(ld32u
);
2161 gen_narrow_load_store(st32
);
2163 #undef gen_narrow_load_store
2166 gen_window_check3(dc
, RRRN_R
, RRRN_S
, RRRN_T
);
2167 tcg_gen_add_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], cpu_R
[RRRN_T
]);
2170 case 11: /*ADDI.Nn*/
2171 gen_window_check2(dc
, RRRN_R
, RRRN_S
);
2172 tcg_gen_addi_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], RRRN_T
? RRRN_T
: -1);
2176 gen_window_check1(dc
, RRRN_S
);
2177 if (RRRN_T
< 8) { /*MOVI.Nn*/
2178 tcg_gen_movi_i32(cpu_R
[RRRN_S
],
2179 RRRN_R
| (RRRN_T
<< 4) |
2180 ((RRRN_T
& 6) == 6 ? 0xffffff80 : 0));
2181 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2182 TCGCond eq_ne
= (RRRN_T
& 4) ? TCG_COND_NE
: TCG_COND_EQ
;
2184 gen_brcondi(dc
, eq_ne
, cpu_R
[RRRN_S
], 0,
2185 4 + (RRRN_R
| ((RRRN_T
& 3) << 4)));
2192 gen_window_check2(dc
, RRRN_S
, RRRN_T
);
2193 tcg_gen_mov_i32(cpu_R
[RRRN_T
], cpu_R
[RRRN_S
]);
2199 gen_jump(dc
, cpu_R
[0]);
2203 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2205 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2206 gen_advance_ccount(dc
);
2207 gen_helper_retw(tmp
, tmp
);
2213 case 2: /*BREAK.Nn*/
2221 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2224 default: /*reserved*/
2230 default: /*reserved*/
2236 default: /*reserved*/
2241 gen_check_loop_end(dc
, 0);
2242 dc
->pc
= dc
->next_pc
;
2247 qemu_log("INVALID(pc = %08x)\n", dc
->pc
);
2248 dc
->pc
= dc
->next_pc
;
2252 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
2256 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
2257 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
2258 if (bp
->pc
== dc
->pc
) {
2259 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
2260 gen_exception(dc
, EXCP_DEBUG
);
2261 dc
->is_jmp
= DISAS_UPDATE
;
2267 static void gen_intermediate_code_internal(
2268 CPUState
*env
, TranslationBlock
*tb
, int search_pc
)
2273 uint16_t *gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
2274 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
2275 uint32_t pc_start
= tb
->pc
;
2276 uint32_t next_page_start
=
2277 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
2279 if (max_insns
== 0) {
2280 max_insns
= CF_COUNT_MASK
;
2283 dc
.config
= env
->config
;
2284 dc
.singlestep_enabled
= env
->singlestep_enabled
;
2287 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
2288 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
2289 dc
.lbeg
= env
->sregs
[LBEG
];
2290 dc
.lend
= env
->sregs
[LEND
];
2291 dc
.is_jmp
= DISAS_NEXT
;
2292 dc
.ccount_delta
= 0;
2295 init_sar_tracker(&dc
);
2296 reset_used_window(&dc
);
2300 if (env
->singlestep_enabled
&& env
->exception_taken
) {
2301 env
->exception_taken
= 0;
2302 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2303 gen_exception(&dc
, EXCP_DEBUG
);
2307 check_breakpoint(env
, &dc
);
2310 j
= gen_opc_ptr
- gen_opc_buf
;
2314 gen_opc_instr_start
[lj
++] = 0;
2317 gen_opc_pc
[lj
] = dc
.pc
;
2318 gen_opc_instr_start
[lj
] = 1;
2319 gen_opc_icount
[lj
] = insn_count
;
2322 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
2323 tcg_gen_debug_insn_start(dc
.pc
);
2328 if (insn_count
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
2332 disas_xtensa_insn(&dc
);
2334 if (env
->singlestep_enabled
) {
2335 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
2336 gen_exception(&dc
, EXCP_DEBUG
);
2339 } while (dc
.is_jmp
== DISAS_NEXT
&&
2340 insn_count
< max_insns
&&
2341 dc
.pc
< next_page_start
&&
2342 gen_opc_ptr
< gen_opc_end
);
2345 reset_sar_tracker(&dc
);
2347 if (tb
->cflags
& CF_LAST_IO
) {
2351 if (dc
.is_jmp
== DISAS_NEXT
) {
2352 gen_jumpi(&dc
, dc
.pc
, 0);
2354 gen_icount_end(tb
, insn_count
);
2355 *gen_opc_ptr
= INDEX_op_end
;
2358 tb
->size
= dc
.pc
- pc_start
;
2359 tb
->icount
= insn_count
;
2363 void gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
2365 gen_intermediate_code_internal(env
, tb
, 0);
2368 void gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
2370 gen_intermediate_code_internal(env
, tb
, 1);
2373 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
2378 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
2380 for (i
= j
= 0; i
< 256; ++i
) {
2382 cpu_fprintf(f
, "%s=%08x%c", sregnames
[i
], env
->sregs
[i
],
2383 (j
++ % 4) == 3 ? '\n' : ' ');
2387 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
2389 for (i
= j
= 0; i
< 256; ++i
) {
2391 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
], env
->uregs
[i
],
2392 (j
++ % 4) == 3 ? '\n' : ' ');
2396 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
2398 for (i
= 0; i
< 16; ++i
) {
2399 cpu_fprintf(f
, "A%02d=%08x%c", i
, env
->regs
[i
],
2400 (i
% 4) == 3 ? '\n' : ' ');
2403 cpu_fprintf(f
, "\n");
2405 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
2406 cpu_fprintf(f
, "AR%02d=%08x%c", i
, env
->phys_regs
[i
],
2407 (i
% 4) == 3 ? '\n' : ' ');
2411 void restore_state_to_opc(CPUState
*env
, TranslationBlock
*tb
, int pc_pos
)
2413 env
->pc
= gen_opc_pc
[pc_pos
];