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trace: allow trace events with string arguments
[qemu/ar7.git] / hw / ac97.c
blobbc69d4e3452480fe6d6c42002224306143a8287a
1 /*
2 * Copyright (C) 2006 InnoTek Systemberatung GmbH
3 *
4 * This file is part of VirtualBox Open Source Edition (OSE), as
5 * available from http://www.virtualbox.org. This file is free software;
6 * you can redistribute it and/or modify it under the terms of the GNU
7 * General Public License as published by the Free Software Foundation,
8 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
9 * distribution. VirtualBox OSE is distributed in the hope that it will
10 * be useful, but WITHOUT ANY WARRANTY of any kind.
11 *
12 * If you received this file as part of a commercial VirtualBox
13 * distribution, then only the terms of your commercial VirtualBox
14 * license agreement apply instead of the previous paragraph.
15 */
16
17 #include "hw.h"
18 #include "audiodev.h"
19 #include "audio/audio.h"
20 #include "pci.h"
21
22 enum {
23 AC97_Reset = 0x00,
24 AC97_Master_Volume_Mute = 0x02,
25 AC97_Headphone_Volume_Mute = 0x04,
26 AC97_Master_Volume_Mono_Mute = 0x06,
27 AC97_Master_Tone_RL = 0x08,
28 AC97_PC_BEEP_Volume_Mute = 0x0A,
29 AC97_Phone_Volume_Mute = 0x0C,
30 AC97_Mic_Volume_Mute = 0x0E,
31 AC97_Line_In_Volume_Mute = 0x10,
32 AC97_CD_Volume_Mute = 0x12,
33 AC97_Video_Volume_Mute = 0x14,
34 AC97_Aux_Volume_Mute = 0x16,
35 AC97_PCM_Out_Volume_Mute = 0x18,
36 AC97_Record_Select = 0x1A,
37 AC97_Record_Gain_Mute = 0x1C,
38 AC97_Record_Gain_Mic_Mute = 0x1E,
39 AC97_General_Purpose = 0x20,
40 AC97_3D_Control = 0x22,
41 AC97_AC_97_RESERVED = 0x24,
42 AC97_Powerdown_Ctrl_Stat = 0x26,
43 AC97_Extended_Audio_ID = 0x28,
44 AC97_Extended_Audio_Ctrl_Stat = 0x2A,
45 AC97_PCM_Front_DAC_Rate = 0x2C,
46 AC97_PCM_Surround_DAC_Rate = 0x2E,
47 AC97_PCM_LFE_DAC_Rate = 0x30,
48 AC97_PCM_LR_ADC_Rate = 0x32,
49 AC97_MIC_ADC_Rate = 0x34,
50 AC97_6Ch_Vol_C_LFE_Mute = 0x36,
51 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
52 AC97_Vendor_Reserved = 0x58,
53 AC97_Vendor_ID1 = 0x7c,
54 AC97_Vendor_ID2 = 0x7e
55 };
56
57 #define SOFT_VOLUME
58 #define SR_FIFOE 16 /* rwc */
59 #define SR_BCIS 8 /* rwc */
60 #define SR_LVBCI 4 /* rwc */
61 #define SR_CELV 2 /* ro */
62 #define SR_DCH 1 /* ro */
63 #define SR_VALID_MASK ((1 << 5) - 1)
64 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
65 #define SR_RO_MASK (SR_DCH | SR_CELV)
66 #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
67
68 #define CR_IOCE 16 /* rw */
69 #define CR_FEIE 8 /* rw */
70 #define CR_LVBIE 4 /* rw */
71 #define CR_RR 2 /* rw */
72 #define CR_RPBM 1 /* rw */
73 #define CR_VALID_MASK ((1 << 5) - 1)
74 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
75
76 #define GC_WR 4 /* rw */
77 #define GC_CR 2 /* rw */
78 #define GC_VALID_MASK ((1 << 6) - 1)
79
80 #define GS_MD3 (1<<17) /* rw */
81 #define GS_AD3 (1<<16) /* rw */
82 #define GS_RCS (1<<15) /* rwc */
83 #define GS_B3S12 (1<<14) /* ro */
84 #define GS_B2S12 (1<<13) /* ro */
85 #define GS_B1S12 (1<<12) /* ro */
86 #define GS_S1R1 (1<<11) /* rwc */
87 #define GS_S0R1 (1<<10) /* rwc */
88 #define GS_S1CR (1<<9) /* ro */
89 #define GS_S0CR (1<<8) /* ro */
90 #define GS_MINT (1<<7) /* ro */
91 #define GS_POINT (1<<6) /* ro */
92 #define GS_PIINT (1<<5) /* ro */
93 #define GS_RSRVD ((1<<4)|(1<<3))
94 #define GS_MOINT (1<<2) /* ro */
95 #define GS_MIINT (1<<1) /* ro */
96 #define GS_GSCI 1 /* rwc */
97 #define GS_RO_MASK (GS_B3S12| \
98 GS_B2S12| \
99 GS_B1S12| \
100 GS_S1CR| \
101 GS_S0CR| \
102 GS_MINT| \
103 GS_POINT| \
104 GS_PIINT| \
105 GS_RSRVD| \
106 GS_MOINT| \
107 GS_MIINT)
108 #define GS_VALID_MASK ((1 << 18) - 1)
109 #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)
110
111 #define BD_IOC (1<<31)
112 #define BD_BUP (1<<30)
113
114 #define EACS_VRA 1
115 #define EACS_VRM 8
116
117 #define VOL_MASK 0x1f
118 #define MUTE_SHIFT 15
119
120 #define REC_MASK 7
121 enum {
122 REC_MIC = 0,
123 REC_CD,
124 REC_VIDEO,
125 REC_AUX,
126 REC_LINE_IN,
127 REC_STEREO_MIX,
128 REC_MONO_MIX,
129 REC_PHONE
130 };
131
132 typedef struct BD {
133 uint32_t addr;
134 uint32_t ctl_len;
135 } BD;
136
137 typedef struct AC97BusMasterRegs {
138 uint32_t bdbar; /* rw 0 */
139 uint8_t civ; /* ro 0 */
140 uint8_t lvi; /* rw 0 */
141 uint16_t sr; /* rw 1 */
142 uint16_t picb; /* ro 0 */
143 uint8_t piv; /* ro 0 */
144 uint8_t cr; /* rw 0 */
145 unsigned int bd_valid;
146 BD bd;
147 } AC97BusMasterRegs;
148
149 typedef struct AC97LinkState {
150 PCIDevice dev;
151 QEMUSoundCard card;
152 uint32_t glob_cnt;
153 uint32_t glob_sta;
154 uint32_t cas;
155 uint32_t last_samp;
156 AC97BusMasterRegs bm_regs[3];
157 uint8_t mixer_data[256];
158 SWVoiceIn *voice_pi;
159 SWVoiceOut *voice_po;
160 SWVoiceIn *voice_mc;
161 int invalid_freq[3];
162 uint8_t silence[128];
163 int bup_flag;
164 MemoryRegion io_nam;
165 MemoryRegion io_nabm;
166 } AC97LinkState;
167
168 enum {
169 BUP_SET = 1,
170 BUP_LAST = 2
171 };
172
173 #ifdef DEBUG_AC97
174 #define dolog(...) AUD_log ("ac97", __VA_ARGS__)
175 #else
176 #define dolog(...)
177 #endif
178
179 #define MKREGS(prefix, start) \
180 enum { \
181 prefix ## _BDBAR = start, \
182 prefix ## _CIV = start + 4, \
183 prefix ## _LVI = start + 5, \
184 prefix ## _SR = start + 6, \
185 prefix ## _PICB = start + 8, \
186 prefix ## _PIV = start + 10, \
187 prefix ## _CR = start + 11 \
188 }
189
190 enum {
191 PI_INDEX = 0,
192 PO_INDEX,
193 MC_INDEX,
194 LAST_INDEX
195 };
196
197 MKREGS (PI, PI_INDEX * 16);
198 MKREGS (PO, PO_INDEX * 16);
199 MKREGS (MC, MC_INDEX * 16);
200
201 enum {
202 GLOB_CNT = 0x2c,
203 GLOB_STA = 0x30,
204 CAS = 0x34
205 };
206
207 #define GET_BM(index) (((index) >> 4) & 3)
208
209 static void po_callback (void *opaque, int free);
210 static void pi_callback (void *opaque, int avail);
211 static void mc_callback (void *opaque, int avail);
212
213 static void warm_reset (AC97LinkState *s)
214 {
215 (void) s;
216 }
217
218 static void cold_reset (AC97LinkState * s)
219 {
220 (void) s;
221 }
222
223 static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r)
224 {
225 uint8_t b[8];
226
227 cpu_physical_memory_read (r->bdbar + r->civ * 8, b, 8);
228 r->bd_valid = 1;
229 r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3;
230 r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]);
231 r->picb = r->bd.ctl_len & 0xffff;
232 dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
233 r->civ, r->bd.addr, r->bd.ctl_len >> 16,
234 r->bd.ctl_len & 0xffff,
235 (r->bd.ctl_len & 0xffff) << 1);
236 }
237
238 static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)
239 {
240 int event = 0;
241 int level = 0;
242 uint32_t new_mask = new_sr & SR_INT_MASK;
243 uint32_t old_mask = r->sr & SR_INT_MASK;
244 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT};
245
246 if (new_mask ^ old_mask) {
247 /** @todo is IRQ deasserted when only one of status bits is cleared? */
248 if (!new_mask) {
249 event = 1;
250 level = 0;
251 }
252 else {
253 if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) {
254 event = 1;
255 level = 1;
256 }
257 if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) {
258 event = 1;
259 level = 1;
260 }
261 }
262 }
263
264 r->sr = new_sr;
265
266 dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n",
267 r->sr & SR_BCIS, r->sr & SR_LVBCI,
268 r->sr,
269 event, level);
270
271 if (!event)
272 return;
273
274 if (level) {
275 s->glob_sta |= masks[r - s->bm_regs];
276 dolog ("set irq level=1\n");
277 qemu_set_irq (s->dev.irq[0], 1);
278 }
279 else {
280 s->glob_sta &= ~masks[r - s->bm_regs];
281 dolog ("set irq level=0\n");
282 qemu_set_irq (s->dev.irq[0], 0);
283 }
284 }
285
286 static void voice_set_active (AC97LinkState *s, int bm_index, int on)
287 {
288 switch (bm_index) {
289 case PI_INDEX:
290 AUD_set_active_in (s->voice_pi, on);
291 break;
292
293 case PO_INDEX:
294 AUD_set_active_out (s->voice_po, on);
295 break;
296
297 case MC_INDEX:
298 AUD_set_active_in (s->voice_mc, on);
299 break;
300
301 default:
302 AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index);
303 break;
304 }
305 }
306
307 static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r)
308 {
309 dolog ("reset_bm_regs\n");
310 r->bdbar = 0;
311 r->civ = 0;
312 r->lvi = 0;
313 /** todo do we need to do that? */
314 update_sr (s, r, SR_DCH);
315 r->picb = 0;
316 r->piv = 0;
317 r->cr = r->cr & CR_DONT_CLEAR_MASK;
318 r->bd_valid = 0;
319
320 voice_set_active (s, r - s->bm_regs, 0);
321 memset (s->silence, 0, sizeof (s->silence));
322 }
323
324 static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v)
325 {
326 if (i + 2 > sizeof (s->mixer_data)) {
327 dolog ("mixer_store: index %d out of bounds %zd\n",
328 i, sizeof (s->mixer_data));
329 return;
330 }
331
332 s->mixer_data[i + 0] = v & 0xff;
333 s->mixer_data[i + 1] = v >> 8;
334 }
335
336 static uint16_t mixer_load (AC97LinkState *s, uint32_t i)
337 {
338 uint16_t val = 0xffff;
339
340 if (i + 2 > sizeof (s->mixer_data)) {
341 dolog ("mixer_store: index %d out of bounds %zd\n",
342 i, sizeof (s->mixer_data));
343 }
344 else {
345 val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8);
346 }
347
348 return val;
349 }
350
351 static void open_voice (AC97LinkState *s, int index, int freq)
352 {
353 struct audsettings as;
354
355 as.freq = freq;
356 as.nchannels = 2;
357 as.fmt = AUD_FMT_S16;
358 as.endianness = 0;
359
360 if (freq > 0) {
361 s->invalid_freq[index] = 0;
362 switch (index) {
363 case PI_INDEX:
364 s->voice_pi = AUD_open_in (
365 &s->card,
366 s->voice_pi,
367 "ac97.pi",
368 s,
369 pi_callback,
370 &as
371 );
372 break;
373
374 case PO_INDEX:
375 s->voice_po = AUD_open_out (
376 &s->card,
377 s->voice_po,
378 "ac97.po",
379 s,
380 po_callback,
381 &as
382 );
383 break;
384
385 case MC_INDEX:
386 s->voice_mc = AUD_open_in (
387 &s->card,
388 s->voice_mc,
389 "ac97.mc",
390 s,
391 mc_callback,
392 &as
393 );
394 break;
395 }
396 }
397 else {
398 s->invalid_freq[index] = freq;
399 switch (index) {
400 case PI_INDEX:
401 AUD_close_in (&s->card, s->voice_pi);
402 s->voice_pi = NULL;
403 break;
404
405 case PO_INDEX:
406 AUD_close_out (&s->card, s->voice_po);
407 s->voice_po = NULL;
408 break;
409
410 case MC_INDEX:
411 AUD_close_in (&s->card, s->voice_mc);
412 s->voice_mc = NULL;
413 break;
414 }
415 }
416 }
417
418 static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX])
419 {
420 uint16_t freq;
421
422 freq = mixer_load (s, AC97_PCM_LR_ADC_Rate);
423 open_voice (s, PI_INDEX, freq);
424 AUD_set_active_in (s->voice_pi, active[PI_INDEX]);
425
426 freq = mixer_load (s, AC97_PCM_Front_DAC_Rate);
427 open_voice (s, PO_INDEX, freq);
428 AUD_set_active_out (s->voice_po, active[PO_INDEX]);
429
430 freq = mixer_load (s, AC97_MIC_ADC_Rate);
431 open_voice (s, MC_INDEX, freq);
432 AUD_set_active_in (s->voice_mc, active[MC_INDEX]);
433 }
434
435 #ifdef USE_MIXER
436 static void set_volume (AC97LinkState *s, int index,
437 audmixerctl_t mt, uint32_t val)
438 {
439 int mute = (val >> MUTE_SHIFT) & 1;
440 uint8_t rvol = VOL_MASK - (val & VOL_MASK);
441 uint8_t lvol = VOL_MASK - ((val >> 8) & VOL_MASK);
442 rvol = 255 * rvol / VOL_MASK;
443 lvol = 255 * lvol / VOL_MASK;
444
445 #ifdef SOFT_VOLUME
446 if (index == AC97_Master_Volume_Mute) {
447 AUD_set_volume_out (s->voice_po, mute, lvol, rvol);
448 }
449 else {
450 AUD_set_volume (mt, &mute, &lvol, &rvol);
451 }
452 #else
453 AUD_set_volume (mt, &mute, &lvol, &rvol);
454 #endif
455
456 rvol = VOL_MASK - ((VOL_MASK * rvol) / 255);
457 lvol = VOL_MASK - ((VOL_MASK * lvol) / 255);
458 mixer_store (s, index, val);
459 }
460
461 static audrecsource_t ac97_to_aud_record_source (uint8_t i)
462 {
463 switch (i) {
464 case REC_MIC:
465 return AUD_REC_MIC;
466
467 case REC_CD:
468 return AUD_REC_CD;
469
470 case REC_VIDEO:
471 return AUD_REC_VIDEO;
472
473 case REC_AUX:
474 return AUD_REC_AUX;
475
476 case REC_LINE_IN:
477 return AUD_REC_LINE_IN;
478
479 case REC_PHONE:
480 return AUD_REC_PHONE;
481
482 default:
483 dolog ("Unknown record source %d, using MIC\n", i);
484 return AUD_REC_MIC;
485 }
486 }
487
488 static uint8_t aud_to_ac97_record_source (audrecsource_t rs)
489 {
490 switch (rs) {
491 case AUD_REC_MIC:
492 return REC_MIC;
493
494 case AUD_REC_CD:
495 return REC_CD;
496
497 case AUD_REC_VIDEO:
498 return REC_VIDEO;
499
500 case AUD_REC_AUX:
501 return REC_AUX;
502
503 case AUD_REC_LINE_IN:
504 return REC_LINE_IN;
505
506 case AUD_REC_PHONE:
507 return REC_PHONE;
508
509 default:
510 dolog ("Unknown audio recording source %d using MIC\n", rs);
511 return REC_MIC;
512 }
513 }
514
515 static void record_select (AC97LinkState *s, uint32_t val)
516 {
517 uint8_t rs = val & REC_MASK;
518 uint8_t ls = (val >> 8) & REC_MASK;
519 audrecsource_t ars = ac97_to_aud_record_source (rs);
520 audrecsource_t als = ac97_to_aud_record_source (ls);
521 AUD_set_record_source (&als, &ars);
522 rs = aud_to_ac97_record_source (ars);
523 ls = aud_to_ac97_record_source (als);
524 mixer_store (s, AC97_Record_Select, rs | (ls << 8));
525 }
526 #endif
527
528 static void mixer_reset (AC97LinkState *s)
529 {
530 uint8_t active[LAST_INDEX];
531
532 dolog ("mixer_reset\n");
533 memset (s->mixer_data, 0, sizeof (s->mixer_data));
534 memset (active, 0, sizeof (active));
535 mixer_store (s, AC97_Reset , 0x0000); /* 6940 */
536 mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x8000);
537 mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000);
538
539 mixer_store (s, AC97_Phone_Volume_Mute , 0x8008);
540 mixer_store (s, AC97_Mic_Volume_Mute , 0x8008);
541 mixer_store (s, AC97_CD_Volume_Mute , 0x8808);
542 mixer_store (s, AC97_Aux_Volume_Mute , 0x8808);
543 mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x8000);
544 mixer_store (s, AC97_General_Purpose , 0x0000);
545 mixer_store (s, AC97_3D_Control , 0x0000);
546 mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f);
547
548 /*
549 * Sigmatel 9700 (STAC9700)
550 */
551 mixer_store (s, AC97_Vendor_ID1 , 0x8384);
552 mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */
553
554 mixer_store (s, AC97_Extended_Audio_ID , 0x0809);
555 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
556 mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80);
557 mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80);
558 mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80);
559 mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80);
560 mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80);
561
562 #ifdef USE_MIXER
563 record_select (s, 0);
564 set_volume (s, AC97_Master_Volume_Mute, AUD_MIXER_VOLUME , 0x8000);
565 set_volume (s, AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM , 0x8808);
566 set_volume (s, AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN, 0x8808);
567 #endif
568 reset_voices (s, active);
569 }
570
571 /**
572 * Native audio mixer
573 * I/O Reads
574 */
575 static uint32_t nam_readb (void *opaque, uint32_t addr)
576 {
577 AC97LinkState *s = opaque;
578 dolog ("U nam readb %#x\n", addr);
579 s->cas = 0;
580 return ~0U;
581 }
582
583 static uint32_t nam_readw (void *opaque, uint32_t addr)
584 {
585 AC97LinkState *s = opaque;
586 uint32_t val = ~0U;
587 uint32_t index = addr;
588 s->cas = 0;
589 val = mixer_load (s, index);
590 return val;
591 }
592
593 static uint32_t nam_readl (void *opaque, uint32_t addr)
594 {
595 AC97LinkState *s = opaque;
596 dolog ("U nam readl %#x\n", addr);
597 s->cas = 0;
598 return ~0U;
599 }
600
601 /**
602 * Native audio mixer
603 * I/O Writes
604 */
605 static void nam_writeb (void *opaque, uint32_t addr, uint32_t val)
606 {
607 AC97LinkState *s = opaque;
608 dolog ("U nam writeb %#x <- %#x\n", addr, val);
609 s->cas = 0;
610 }
611
612 static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
613 {
614 AC97LinkState *s = opaque;
615 uint32_t index = addr;
616 s->cas = 0;
617 switch (index) {
618 case AC97_Reset:
619 mixer_reset (s);
620 break;
621 case AC97_Powerdown_Ctrl_Stat:
622 val &= ~0xf;
623 val |= mixer_load (s, index) & 0xf;
624 mixer_store (s, index, val);
625 break;
626 #ifdef USE_MIXER
627 case AC97_Master_Volume_Mute:
628 set_volume (s, index, AUD_MIXER_VOLUME, val);
629 break;
630 case AC97_PCM_Out_Volume_Mute:
631 set_volume (s, index, AUD_MIXER_PCM, val);
632 break;
633 case AC97_Line_In_Volume_Mute:
634 set_volume (s, index, AUD_MIXER_LINE_IN, val);
635 break;
636 case AC97_Record_Select:
637 record_select (s, val);
638 break;
639 #endif
640 case AC97_Vendor_ID1:
641 case AC97_Vendor_ID2:
642 dolog ("Attempt to write vendor ID to %#x\n", val);
643 break;
644 case AC97_Extended_Audio_ID:
645 dolog ("Attempt to write extended audio ID to %#x\n", val);
646 break;
647 case AC97_Extended_Audio_Ctrl_Stat:
648 if (!(val & EACS_VRA)) {
649 mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80);
650 mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80);
651 open_voice (s, PI_INDEX, 48000);
652 open_voice (s, PO_INDEX, 48000);
653 }
654 if (!(val & EACS_VRM)) {
655 mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80);
656 open_voice (s, MC_INDEX, 48000);
657 }
658 dolog ("Setting extended audio control to %#x\n", val);
659 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val);
660 break;
661 case AC97_PCM_Front_DAC_Rate:
662 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
663 mixer_store (s, index, val);
664 dolog ("Set front DAC rate to %d\n", val);
665 open_voice (s, PO_INDEX, val);
666 }
667 else {
668 dolog ("Attempt to set front DAC rate to %d, "
669 "but VRA is not set\n",
670 val);
671 }
672 break;
673 case AC97_MIC_ADC_Rate:
674 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) {
675 mixer_store (s, index, val);
676 dolog ("Set MIC ADC rate to %d\n", val);
677 open_voice (s, MC_INDEX, val);
678 }
679 else {
680 dolog ("Attempt to set MIC ADC rate to %d, "
681 "but VRM is not set\n",
682 val);
683 }
684 break;
685 case AC97_PCM_LR_ADC_Rate:
686 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
687 mixer_store (s, index, val);
688 dolog ("Set front LR ADC rate to %d\n", val);
689 open_voice (s, PI_INDEX, val);
690 }
691 else {
692 dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n",
693 val);
694 }
695 break;
696 default:
697 dolog ("U nam writew %#x <- %#x\n", addr, val);
698 mixer_store (s, index, val);
699 break;
700 }
701 }
702
703 static void nam_writel (void *opaque, uint32_t addr, uint32_t val)
704 {
705 AC97LinkState *s = opaque;
706 dolog ("U nam writel %#x <- %#x\n", addr, val);
707 s->cas = 0;
708 }
709
710 /**
711 * Native audio bus master
712 * I/O Reads
713 */
714 static uint32_t nabm_readb (void *opaque, uint32_t addr)
715 {
716 AC97LinkState *s = opaque;
717 AC97BusMasterRegs *r = NULL;
718 uint32_t index = addr;
719 uint32_t val = ~0U;
720
721 switch (index) {
722 case CAS:
723 dolog ("CAS %d\n", s->cas);
724 val = s->cas;
725 s->cas = 1;
726 break;
727 case PI_CIV:
728 case PO_CIV:
729 case MC_CIV:
730 r = &s->bm_regs[GET_BM (index)];
731 val = r->civ;
732 dolog ("CIV[%d] -> %#x\n", GET_BM (index), val);
733 break;
734 case PI_LVI:
735 case PO_LVI:
736 case MC_LVI:
737 r = &s->bm_regs[GET_BM (index)];
738 val = r->lvi;
739 dolog ("LVI[%d] -> %#x\n", GET_BM (index), val);
740 break;
741 case PI_PIV:
742 case PO_PIV:
743 case MC_PIV:
744 r = &s->bm_regs[GET_BM (index)];
745 val = r->piv;
746 dolog ("PIV[%d] -> %#x\n", GET_BM (index), val);
747 break;
748 case PI_CR:
749 case PO_CR:
750 case MC_CR:
751 r = &s->bm_regs[GET_BM (index)];
752 val = r->cr;
753 dolog ("CR[%d] -> %#x\n", GET_BM (index), val);
754 break;
755 case PI_SR:
756 case PO_SR:
757 case MC_SR:
758 r = &s->bm_regs[GET_BM (index)];
759 val = r->sr & 0xff;
760 dolog ("SRb[%d] -> %#x\n", GET_BM (index), val);
761 break;
762 default:
763 dolog ("U nabm readb %#x -> %#x\n", addr, val);
764 break;
765 }
766 return val;
767 }
768
769 static uint32_t nabm_readw (void *opaque, uint32_t addr)
770 {
771 AC97LinkState *s = opaque;
772 AC97BusMasterRegs *r = NULL;
773 uint32_t index = addr;
774 uint32_t val = ~0U;
775
776 switch (index) {
777 case PI_SR:
778 case PO_SR:
779 case MC_SR:
780 r = &s->bm_regs[GET_BM (index)];
781 val = r->sr;
782 dolog ("SR[%d] -> %#x\n", GET_BM (index), val);
783 break;
784 case PI_PICB:
785 case PO_PICB:
786 case MC_PICB:
787 r = &s->bm_regs[GET_BM (index)];
788 val = r->picb;
789 dolog ("PICB[%d] -> %#x\n", GET_BM (index), val);
790 break;
791 default:
792 dolog ("U nabm readw %#x -> %#x\n", addr, val);
793 break;
794 }
795 return val;
796 }
797
798 static uint32_t nabm_readl (void *opaque, uint32_t addr)
799 {
800 AC97LinkState *s = opaque;
801 AC97BusMasterRegs *r = NULL;
802 uint32_t index = addr;
803 uint32_t val = ~0U;
804
805 switch (index) {
806 case PI_BDBAR:
807 case PO_BDBAR:
808 case MC_BDBAR:
809 r = &s->bm_regs[GET_BM (index)];
810 val = r->bdbar;
811 dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val);
812 break;
813 case PI_CIV:
814 case PO_CIV:
815 case MC_CIV:
816 r = &s->bm_regs[GET_BM (index)];
817 val = r->civ | (r->lvi << 8) | (r->sr << 16);
818 dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index),
819 r->civ, r->lvi, r->sr);
820 break;
821 case PI_PICB:
822 case PO_PICB:
823 case MC_PICB:
824 r = &s->bm_regs[GET_BM (index)];
825 val = r->picb | (r->piv << 16) | (r->cr << 24);
826 dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index),
827 val, r->picb, r->piv, r->cr);
828 break;
829 case GLOB_CNT:
830 val = s->glob_cnt;
831 dolog ("glob_cnt -> %#x\n", val);
832 break;
833 case GLOB_STA:
834 val = s->glob_sta | GS_S0CR;
835 dolog ("glob_sta -> %#x\n", val);
836 break;
837 default:
838 dolog ("U nabm readl %#x -> %#x\n", addr, val);
839 break;
840 }
841 return val;
842 }
843
844 /**
845 * Native audio bus master
846 * I/O Writes
847 */
848 static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val)
849 {
850 AC97LinkState *s = opaque;
851 AC97BusMasterRegs *r = NULL;
852 uint32_t index = addr;
853 switch (index) {
854 case PI_LVI:
855 case PO_LVI:
856 case MC_LVI:
857 r = &s->bm_regs[GET_BM (index)];
858 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) {
859 r->sr &= ~(SR_DCH | SR_CELV);
860 r->civ = r->piv;
861 r->piv = (r->piv + 1) % 32;
862 fetch_bd (s, r);
863 }
864 r->lvi = val % 32;
865 dolog ("LVI[%d] <- %#x\n", GET_BM (index), val);
866 break;
867 case PI_CR:
868 case PO_CR:
869 case MC_CR:
870 r = &s->bm_regs[GET_BM (index)];
871 if (val & CR_RR) {
872 reset_bm_regs (s, r);
873 }
874 else {
875 r->cr = val & CR_VALID_MASK;
876 if (!(r->cr & CR_RPBM)) {
877 voice_set_active (s, r - s->bm_regs, 0);
878 r->sr |= SR_DCH;
879 }
880 else {
881 r->civ = r->piv;
882 r->piv = (r->piv + 1) % 32;
883 fetch_bd (s, r);
884 r->sr &= ~SR_DCH;
885 voice_set_active (s, r - s->bm_regs, 1);
886 }
887 }
888 dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr);
889 break;
890 case PI_SR:
891 case PO_SR:
892 case MC_SR:
893 r = &s->bm_regs[GET_BM (index)];
894 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
895 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
896 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
897 break;
898 default:
899 dolog ("U nabm writeb %#x <- %#x\n", addr, val);
900 break;
901 }
902 }
903
904 static void nabm_writew (void *opaque, uint32_t addr, uint32_t val)
905 {
906 AC97LinkState *s = opaque;
907 AC97BusMasterRegs *r = NULL;
908 uint32_t index = addr;
909 switch (index) {
910 case PI_SR:
911 case PO_SR:
912 case MC_SR:
913 r = &s->bm_regs[GET_BM (index)];
914 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
915 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
916 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
917 break;
918 default:
919 dolog ("U nabm writew %#x <- %#x\n", addr, val);
920 break;
921 }
922 }
923
924 static void nabm_writel (void *opaque, uint32_t addr, uint32_t val)
925 {
926 AC97LinkState *s = opaque;
927 AC97BusMasterRegs *r = NULL;
928 uint32_t index = addr;
929 switch (index) {
930 case PI_BDBAR:
931 case PO_BDBAR:
932 case MC_BDBAR:
933 r = &s->bm_regs[GET_BM (index)];
934 r->bdbar = val & ~3;
935 dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n",
936 GET_BM (index), val, r->bdbar);
937 break;
938 case GLOB_CNT:
939 if (val & GC_WR)
940 warm_reset (s);
941 if (val & GC_CR)
942 cold_reset (s);
943 if (!(val & (GC_WR | GC_CR)))
944 s->glob_cnt = val & GC_VALID_MASK;
945 dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt);
946 break;
947 case GLOB_STA:
948 s->glob_sta &= ~(val & GS_WCLEAR_MASK);
949 s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;
950 dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta);
951 break;
952 default:
953 dolog ("U nabm writel %#x <- %#x\n", addr, val);
954 break;
955 }
956 }
957
958 static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r,
959 int max, int *stop)
960 {
961 uint8_t tmpbuf[4096];
962 uint32_t addr = r->bd.addr;
963 uint32_t temp = r->picb << 1;
964 uint32_t written = 0;
965 int to_copy = 0;
966 temp = audio_MIN (temp, max);
967
968 if (!temp) {
969 *stop = 1;
970 return 0;
971 }
972
973 while (temp) {
974 int copied;
975 to_copy = audio_MIN (temp, sizeof (tmpbuf));
976 cpu_physical_memory_read (addr, tmpbuf, to_copy);
977 copied = AUD_write (s->voice_po, tmpbuf, to_copy);
978 dolog ("write_audio max=%x to_copy=%x copied=%x\n",
979 max, to_copy, copied);
980 if (!copied) {
981 *stop = 1;
982 break;
983 }
984 temp -= copied;
985 addr += copied;
986 written += copied;
987 }
988
989 if (!temp) {
990 if (to_copy < 4) {
991 dolog ("whoops\n");
992 s->last_samp = 0;
993 }
994 else {
995 s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4];
996 }
997 }
998
999 r->bd.addr = addr;
1000 return written;
1001 }
1002
1003 static void write_bup (AC97LinkState *s, int elapsed)
1004 {
1005 dolog ("write_bup\n");
1006 if (!(s->bup_flag & BUP_SET)) {
1007 if (s->bup_flag & BUP_LAST) {
1008 int i;
1009 uint8_t *p = s->silence;
1010 for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) {
1011 *(uint32_t *) p = s->last_samp;
1012 }
1013 }
1014 else {
1015 memset (s->silence, 0, sizeof (s->silence));
1016 }
1017 s->bup_flag |= BUP_SET;
1018 }
1019
1020 while (elapsed) {
1021 int temp = audio_MIN (elapsed, sizeof (s->silence));
1022 while (temp) {
1023 int copied = AUD_write (s->voice_po, s->silence, temp);
1024 if (!copied)
1025 return;
1026 temp -= copied;
1027 elapsed -= copied;
1028 }
1029 }
1030 }
1031
1032 static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r,
1033 int max, int *stop)
1034 {
1035 uint8_t tmpbuf[4096];
1036 uint32_t addr = r->bd.addr;
1037 uint32_t temp = r->picb << 1;
1038 uint32_t nread = 0;
1039 int to_copy = 0;
1040 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi;
1041
1042 temp = audio_MIN (temp, max);
1043
1044 if (!temp) {
1045 *stop = 1;
1046 return 0;
1047 }
1048
1049 while (temp) {
1050 int acquired;
1051 to_copy = audio_MIN (temp, sizeof (tmpbuf));
1052 acquired = AUD_read (voice, tmpbuf, to_copy);
1053 if (!acquired) {
1054 *stop = 1;
1055 break;
1056 }
1057 cpu_physical_memory_write (addr, tmpbuf, acquired);
1058 temp -= acquired;
1059 addr += acquired;
1060 nread += acquired;
1061 }
1062
1063 r->bd.addr = addr;
1064 return nread;
1065 }
1066
1067 static void transfer_audio (AC97LinkState *s, int index, int elapsed)
1068 {
1069 AC97BusMasterRegs *r = &s->bm_regs[index];
1070 int stop = 0;
1071
1072 if (s->invalid_freq[index]) {
1073 AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n",
1074 index, s->invalid_freq[index]);
1075 return;
1076 }
1077
1078 if (r->sr & SR_DCH) {
1079 if (r->cr & CR_RPBM) {
1080 switch (index) {
1081 case PO_INDEX:
1082 write_bup (s, elapsed);
1083 break;
1084 }
1085 }
1086 return;
1087 }
1088
1089 while ((elapsed >> 1) && !stop) {
1090 int temp;
1091
1092 if (!r->bd_valid) {
1093 dolog ("invalid bd\n");
1094 fetch_bd (s, r);
1095 }
1096
1097 if (!r->picb) {
1098 dolog ("fresh bd %d is empty %#x %#x\n",
1099 r->civ, r->bd.addr, r->bd.ctl_len);
1100 if (r->civ == r->lvi) {
1101 r->sr |= SR_DCH; /* CELV? */
1102 s->bup_flag = 0;
1103 break;
1104 }
1105 r->sr &= ~SR_CELV;
1106 r->civ = r->piv;
1107 r->piv = (r->piv + 1) % 32;
1108 fetch_bd (s, r);
1109 return;
1110 }
1111
1112 switch (index) {
1113 case PO_INDEX:
1114 temp = write_audio (s, r, elapsed, &stop);
1115 elapsed -= temp;
1116 r->picb -= (temp >> 1);
1117 break;
1118
1119 case PI_INDEX:
1120 case MC_INDEX:
1121 temp = read_audio (s, r, elapsed, &stop);
1122 elapsed -= temp;
1123 r->picb -= (temp >> 1);
1124 break;
1125 }
1126
1127 if (!r->picb) {
1128 uint32_t new_sr = r->sr & ~SR_CELV;
1129
1130 if (r->bd.ctl_len & BD_IOC) {
1131 new_sr |= SR_BCIS;
1132 }
1133
1134 if (r->civ == r->lvi) {
1135 dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi);
1136
1137 new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
1138 stop = 1;
1139 s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
1140 }
1141 else {
1142 r->civ = r->piv;
1143 r->piv = (r->piv + 1) % 32;
1144 fetch_bd (s, r);
1145 }
1146
1147 update_sr (s, r, new_sr);
1148 }
1149 }
1150 }
1151
1152 static void pi_callback (void *opaque, int avail)
1153 {
1154 transfer_audio (opaque, PI_INDEX, avail);
1155 }
1156
1157 static void mc_callback (void *opaque, int avail)
1158 {
1159 transfer_audio (opaque, MC_INDEX, avail);
1160 }
1161
1162 static void po_callback (void *opaque, int free)
1163 {
1164 transfer_audio (opaque, PO_INDEX, free);
1165 }
1166
1167 static const VMStateDescription vmstate_ac97_bm_regs = {
1168 .name = "ac97_bm_regs",
1169 .version_id = 1,
1170 .minimum_version_id = 1,
1171 .minimum_version_id_old = 1,
1172 .fields = (VMStateField []) {
1173 VMSTATE_UINT32(bdbar, AC97BusMasterRegs),
1174 VMSTATE_UINT8(civ, AC97BusMasterRegs),
1175 VMSTATE_UINT8(lvi, AC97BusMasterRegs),
1176 VMSTATE_UINT16(sr, AC97BusMasterRegs),
1177 VMSTATE_UINT16(picb, AC97BusMasterRegs),
1178 VMSTATE_UINT8(piv, AC97BusMasterRegs),
1179 VMSTATE_UINT8(cr, AC97BusMasterRegs),
1180 VMSTATE_UINT32(bd_valid, AC97BusMasterRegs),
1181 VMSTATE_UINT32(bd.addr, AC97BusMasterRegs),
1182 VMSTATE_UINT32(bd.ctl_len, AC97BusMasterRegs),
1183 VMSTATE_END_OF_LIST()
1184 }
1185 };
1186
1187 static int ac97_post_load (void *opaque, int version_id)
1188 {
1189 uint8_t active[LAST_INDEX];
1190 AC97LinkState *s = opaque;
1191
1192 #ifdef USE_MIXER
1193 record_select (s, mixer_load (s, AC97_Record_Select));
1194 #define V_(a, b) set_volume (s, a, b, mixer_load (s, a))
1195 V_ (AC97_Master_Volume_Mute, AUD_MIXER_VOLUME);
1196 V_ (AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM);
1197 V_ (AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN);
1198 #undef V_
1199 #endif
1200 active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM);
1201 active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM);
1202 active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM);
1203 reset_voices (s, active);
1204
1205 s->bup_flag = 0;
1206 s->last_samp = 0;
1207 return 0;
1208 }
1209
1210 static bool is_version_2 (void *opaque, int version_id)
1211 {
1212 return version_id == 2;
1213 }
1214
1215 static const VMStateDescription vmstate_ac97 = {
1216 .name = "ac97",
1217 .version_id = 3,
1218 .minimum_version_id = 2,
1219 .minimum_version_id_old = 2,
1220 .post_load = ac97_post_load,
1221 .fields = (VMStateField []) {
1222 VMSTATE_PCI_DEVICE(dev, AC97LinkState),
1223 VMSTATE_UINT32(glob_cnt, AC97LinkState),
1224 VMSTATE_UINT32(glob_sta, AC97LinkState),
1225 VMSTATE_UINT32(cas, AC97LinkState),
1226 VMSTATE_STRUCT_ARRAY(bm_regs, AC97LinkState, 3, 1,
1227 vmstate_ac97_bm_regs, AC97BusMasterRegs),
1228 VMSTATE_BUFFER(mixer_data, AC97LinkState),
1229 VMSTATE_UNUSED_TEST(is_version_2, 3),
1230 VMSTATE_END_OF_LIST()
1231 }
1232 };
1233
1234 static const MemoryRegionPortio nam_portio[] = {
1235 { 0, 256 * 1, 1, .read = nam_readb, },
1236 { 0, 256 * 2, 2, .read = nam_readw, },
1237 { 0, 256 * 4, 4, .read = nam_readl, },
1238 { 0, 256 * 1, 1, .write = nam_writeb, },
1239 { 0, 256 * 2, 2, .write = nam_writew, },
1240 { 0, 256 * 4, 4, .write = nam_writel, },
1241 PORTIO_END_OF_LIST(),
1242 };
1243
1244 static const MemoryRegionOps ac97_io_nam_ops = {
1245 .old_portio = nam_portio,
1246 };
1247
1248 static const MemoryRegionPortio nabm_portio[] = {
1249 { 0, 64 * 1, 1, .read = nabm_readb, },
1250 { 0, 64 * 2, 2, .read = nabm_readw, },
1251 { 0, 64 * 4, 4, .read = nabm_readl, },
1252 { 0, 64 * 1, 1, .write = nabm_writeb, },
1253 { 0, 64 * 2, 2, .write = nabm_writew, },
1254 { 0, 64 * 4, 4, .write = nabm_writel, },
1255 PORTIO_END_OF_LIST()
1256 };
1257
1258 static const MemoryRegionOps ac97_io_nabm_ops = {
1259 .old_portio = nabm_portio,
1260 };
1261
1262 static void ac97_on_reset (void *opaque)
1263 {
1264 AC97LinkState *s = opaque;
1265
1266 reset_bm_regs (s, &s->bm_regs[0]);
1267 reset_bm_regs (s, &s->bm_regs[1]);
1268 reset_bm_regs (s, &s->bm_regs[2]);
1269
1270 /*
1271 * Reset the mixer too. The Windows XP driver seems to rely on
1272 * this. At least it wants to read the vendor id before it resets
1273 * the codec manually.
1274 */
1275 mixer_reset (s);
1276 }
1277
1278 static int ac97_initfn (PCIDevice *dev)
1279 {
1280 AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
1281 uint8_t *c = s->dev.config;
1282
1283 /* TODO: no need to override */
1284 c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */
1285 c[PCI_COMMAND + 1] = 0x00;
1286
1287 /* TODO: */
1288 c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
1289 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
1290
1291 c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
1292
1293 /* TODO set when bar is registered. no need to override. */
1294 /* nabmar native audio mixer base address rw */
1295 c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
1296 c[PCI_BASE_ADDRESS_0 + 1] = 0x00;
1297 c[PCI_BASE_ADDRESS_0 + 2] = 0x00;
1298 c[PCI_BASE_ADDRESS_0 + 3] = 0x00;
1299
1300 /* TODO set when bar is registered. no need to override. */
1301 /* nabmbar native audio bus mastering base address rw */
1302 c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO;
1303 c[PCI_BASE_ADDRESS_0 + 5] = 0x00;
1304 c[PCI_BASE_ADDRESS_0 + 6] = 0x00;
1305 c[PCI_BASE_ADDRESS_0 + 7] = 0x00;
1306
1307 c[PCI_SUBSYSTEM_VENDOR_ID] = 0x86; /* svid subsystem vendor id rwo */
1308 c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x80;
1309
1310 c[PCI_SUBSYSTEM_ID] = 0x00; /* sid subsystem id rwo */
1311 c[PCI_SUBSYSTEM_ID + 1] = 0x00;
1312
1313 c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */
1314 c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
1315
1316 memory_region_init_io (&s->io_nam, &ac97_io_nam_ops, s, "ac97-nam", 1024);
1317 memory_region_init_io (&s->io_nabm, &ac97_io_nabm_ops, s, "ac97-nabm", 256);
1318 pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
1319 pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
1320 qemu_register_reset (ac97_on_reset, s);
1321 AUD_register_card ("ac97", &s->card);
1322 ac97_on_reset (s);
1323 return 0;
1324 }
1325
1326 static int ac97_exitfn (PCIDevice *dev)
1327 {
1328 AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
1329
1330 memory_region_destroy (&s->io_nam);
1331 memory_region_destroy (&s->io_nabm);
1332 return 0;
1333 }
1334
1335 int ac97_init (PCIBus *bus)
1336 {
1337 pci_create_simple (bus, -1, "AC97");
1338 return 0;
1339 }
1340
1341 static PCIDeviceInfo ac97_info = {
1342 .qdev.name = "AC97",
1343 .qdev.desc = "Intel 82801AA AC97 Audio",
1344 .qdev.size = sizeof (AC97LinkState),
1345 .qdev.vmsd = &vmstate_ac97,
1346 .init = ac97_initfn,
1347 .exit = ac97_exitfn,
1348 .vendor_id = PCI_VENDOR_ID_INTEL,
1349 .device_id = PCI_DEVICE_ID_INTEL_82801AA_5,
1350 .revision = 0x01,
1351 .class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
1352 };
1353
1354 static void ac97_register (void)
1355 {
1356 pci_qdev_register (&ac97_info);
1357 }
1358 device_init (ac97_register);
1359
AR7 emulation for QEMU